Single-wire transmission method, device and equipment and computer readable storage medium

By converting parallel data into a serial bit stream and mapping it to a duty cycle level signal through a single-wire transmission method, the design difficulty and interference problems caused by the large number of signal lines on the hardware board are solved, and low-cost, high-reliability data transmission is achieved.

CN121935196APending Publication Date: 2026-04-28SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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Patent Information

Application Number
CN202610059841.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-01-15
Publication Date
2026-04-28

AI Technical Summary

Technical Problem

In existing technologies, the large number of signal lines on hardware boards leads to high PCB design difficulty, increased costs, and risks of signal interference and data errors.

Method used

The single-wire transmission method is adopted. Parallel data is encapsulated into parallel data packets through a register read/write message protocol and converted into a serial bit stream. The logic bits are mapped into level signals using duty cycle encoding rules. Data transmission is carried out by controlling the level change of a single signal line through a switching circuit and then decoded at the receiving end.

Benefits of technology

It reduces PCB routing difficulty and hardware costs, avoids the risk of interference between signal lines, improves the reliability of data transmission and decoding accuracy, and is suitable for complex PCB environments and long-distance transmission scenarios.

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Abstract

The invention discloses a single-line transmission method, device and equipment and a computer readable storage medium, which are applied to the technical field of computers, and comprise the following steps: packaging internal bus parallel data into a parallel data message according to a register read-write message protocol, and converting the parallel data message into a serial bit stream; mapping each logic bit of the serial bit stream into a level signal of a corresponding duty ratio according to a duty ratio coding rule; the duty ratio coding rule is that a logic bit 0 represents that a single high level exists in a clock period, and the duty ratio of the single high level does not reach half, and a logic bit 1 represents that a plurality of discontinuous high levels exist in the clock period, and the duty ratios of the plurality of discontinuous high levels reach half; and controlling the level conversion of the single signal line through a switching circuit according to the level signal, and transmitting the coded bit stream to the slave device bit by bit. According to the invention, the problems of high PCB design difficulty, high cost, signal interference and data error risk caused by a large number of signal lines are solved.
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