Dynamic timing traffic signal control method and system based on finite state machine

Abstract

The application discloses a dynamic timing traffic signal lamp control method and system based on a finite state machine. A vehicle flow detection module acquires crossroad vehicle flow information in real time. A traffic control module embedded with a finite state machine receives the vehicle flow information. Different traffic states are defined in the finite state machine. Each state is preset with corresponding direction time. The direction time of the next state is dynamically updated according to the current vehicle flow information. When the direction time of the current state decreases to 1, the finite state machine switches the state. A signal lamp driving module controls the display state of the crossroad traffic signal lamp according to the current state of the finite state machine. A countdown display module controls the countdown value display of the crossroad traffic signal lamp according to the real-time direction time value of the current state of the finite state machine. The application can dynamically adjust the passing timing according to the vehicle flow change of each direction of the crossroad, greatly reduces the time waste of vehicle waiting, and improves the overall passing efficiency of vehicles.

Description

Technical Field

[0001] This invention belongs to the field of intelligent traffic control technology, and in particular relates to a dynamic timing traffic signal control method and system based on finite state machines. Background Technology

[0002] Traditional time-based traffic signal systems are an indispensable part of modern urban traffic management, playing a significant role in ensuring road safety and maintaining good traffic order over the past few decades. However, due to urbanization and the increase in the number of vehicles, traditional time-based traffic signal systems can no longer adequately meet the increasingly complex traffic demands. Faced with enormous and ever-increasing traffic pressure, the drawbacks of traditional time-based traffic signal systems are becoming increasingly apparent. These drawbacks mainly include the simplistic timing schemes, inability to respond promptly to traffic conditions, waste of time resources, and low overall traffic efficiency. These issues have become major obstacles to the intelligent development of urban transportation. In particular, the use of preset, fixed timing schemes, which cannot flexibly adjust the duration of traffic lights according to actual traffic flow, often results in vehicles waiting for extended periods in one direction while other directions remain deserted, causing significant waste, especially when traffic flow is unevenly distributed.

[0003] Intelligent transportation systems are one of the effective methods to solve the above problems. In recent years, they have received more and more attention and development. Intelligent transportation control systems based on field-programmable gate arrays (FPGAs) have broad application prospects in intelligent transportation due to their powerful concurrent processing capabilities, fast response speed and good reconfigurability. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] As can be seen from the above, the purpose of this invention is to provide a dynamic timing traffic signal control method and system based on a finite state machine. Its core purpose is to dynamically adjust the traffic timing according to the changes in traffic flow in each direction at an intersection, so as to reduce the waste of time resources and improve the overall traffic efficiency of vehicles.

[0006] (II) Technical Solution

[0007] This invention discloses a dynamic timing traffic light control method based on a finite state machine:

[0008] A traffic flow detection module is used to obtain real-time traffic flow information in the four directions of the intersection (east, west, south, and north).

[0009] The traffic control module with an embedded finite state machine receives the traffic flow information. The finite state machine defines multiple states, which are used to represent different display states of traffic lights at the intersection. Each state is preset with a direction time that represents the passage time in the corresponding direction under this state. The direction time under the current state is updated by countdown. At the same time, the direction time of the next state is dynamically adjusted according to the currently received traffic flow information. When the direction time under the current state decreases to 1, the finite state machine switches from the current state to the next state.

[0010] A traffic light driver module is used to control the display status of traffic lights at an intersection based on the current state of a finite state machine.

[0011] A countdown display module is used to control the countdown display of traffic lights at intersections based on the real-time value of the direction and time under the current state of the finite state machine.

[0012] Preferably, further detailed description of the present invention can be found in the following detailed embodiments.

[0013] In another aspect, the present invention discloses a dynamic timing traffic signal control system based on a finite state machine, including a traffic control module and a traffic flow detection module, a traffic light driving module and a countdown display module connected thereto. The control system adopts the above-mentioned dynamic timing traffic signal control method based on a finite state machine to realize the control of traffic lights at intersections.

[0014] In another aspect, the present invention discloses a computer-readable storage medium storing a computer program that, when executed by a traffic control module, implements the aforementioned dynamic timing traffic signal control method based on a finite state machine.

[0015] In another aspect, the present invention discloses a computer program product, including a computer program that, when executed by a traffic control module, implements the above-described dynamic timing traffic signal control method based on a finite state machine.

[0016] (III) Beneficial Effects

[0017] The proposed dynamic timing traffic light control method and system based on finite state machines adopts a hierarchical and modular architecture, dividing the entire system into three parts: a perception layer, a control layer, and an execution layer. The perception layer uses a traffic flow detection module to acquire traffic flow information in the four directions (east, west, south, and north), providing accurate and effective traffic flow information to the upper layers. The control layer is the core of the entire system, using a finite state machine within the traffic control module to switch between different traffic light states. This traffic control module, with its embedded finite state machine, can adjust the duration of each state according to the current traffic flow, overcoming the problems of traditional fixed timing and providing an accurate time for each traffic state to ensure the correctness of traffic light changes. The execution layer consists of a traffic light driving module and a countdown display module, transforming the logic of the control layer into traffic lights that pedestrians can see. By combining the collaborative work of these three layers, this invention can dynamically adjust the traffic timing according to changes in traffic flow in each direction at an intersection, significantly reducing wasted vehicle waiting time and improving overall traffic efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the embodiments will be briefly described below:

[0019] Figure 1 This is a flowchart of the dynamic timing traffic signal control method based on a finite state machine according to the present invention.

[0020] Figure 2 This is a block diagram of the dynamic timing traffic signal control system based on a finite state machine according to the present invention.

[0021] Figure 3 This is a simulation diagram of the traffic flow detection module in an embodiment of the present invention;

[0022] Figure 4 This is a simulation diagram of a traffic control module with an embedded finite state machine in an embodiment of the present invention;

[0023] Figure 5 This is a simulation diagram of the countdown display module in an embodiment of the present invention;

[0024] Figure 6 This is a simulation diagram of the traffic light driving module in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the code for defining different states of a finite state machine and assigning direction and time values ​​to different states in an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of the code for calculating the current traffic flow deviation by the traffic flow detection module in this embodiment of the invention;

[0027] Figure 9 This is a schematic diagram of the code for the finite state machine to dynamically adjust the direction and time of the next state based on the real-time traffic flow deviation in an embodiment of the present invention;

[0028] Figure 10 This is a schematic diagram of the code for the traffic flow detection module to perform anti-shake processing on the traffic flow signal in an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] See Figure 1 This invention discloses a dynamic timing traffic light control method based on a finite state machine, comprising the following steps:

[0031] Step 1: Use a traffic flow detection module to obtain real-time traffic flow information in the four directions of the intersection (east, west, south, and north).

[0032] The choice of sensor significantly impacts the accuracy and real-time performance of traffic flow detection. To improve economy and stability, this embodiment selects an infrared sensor for traffic flow detection. Infrared sensors are non-contact, have a rapid response, and are inexpensive, making them suitable for small and medium-sized cities or rural areas. Infrared sensors operate using infrared light; when a vehicle passes by, it blocks the infrared light, causing a change in the sensor's output level. By counting these changes and analyzing the time frame, the number of vehicles can be determined. Because real-world road conditions are complex, the requirements for infrared sensors are also high, requiring resistance to external interference and adaptability to various environments. The infrared sensor used in this embodiment operates at 3.3V~5V, has a detection distance of 3m~80m, and a response time of less than 100μs, which fully meets the requirements for vehicle detection.

[0033] The infrared sensor transmits the detected traffic flow information to the traffic flow detection module, which outputs a digital signal for easy connection to the traffic control module. This greatly reduces the difficulty of designing subsequent signal processing circuits.

[0034] Step 2: The traffic control module with an embedded finite state machine receives and processes the traffic flow information in the four directions of the intersection (east, west, south, and north) obtained in Step 1.

[0035] In this embodiment, as Figure 7As shown, the finite state machine in the traffic control module defines four states S0, S1, S2, and S3: east-west red light, north-south green light, east-west red light, north-south yellow light, east-west green light, north-south red light, and east-west yellow light, north-south red light. Each state corresponds to a different red, green, or yellow light. Combined with a one-second timer within the traffic control module, each state is preset with a directional time representing the travel time in the corresponding direction. Specifically, the east-west green light and north-south red light state is preset with a directional time t_g_ew representing the travel time in the east-west direction, and the east-west red light and north-south red light state is preset with a directional time t_g_ew representing the travel time in the east-west direction. The north-south green light status has a preset directional time t_g_sn indicating the duration of north-south travel in this status. The east-west yellow light status has a preset directional time t_y indicating the duration of east-west travel in this status. The east-west red light status has a preset directional time t_y indicating the duration of north-south travel in this status, also denoted by t_y. It is worth mentioning that the east-west yellow light and north-south red light status, as well as the east-west red light and north-south yellow light status, are both transition periods for vehicle passage. In these two statuses, the yellow light flashes for 3 seconds to warn drivers to prepare to slow down in advance.

[0036] In the current state, the traffic control module uses an internal one-second timer to incrementally update the direction time, and generates a real-time direction time signal (e.g., ...). Figure 2 The real-time time signals (ew_time) in the east-west direction and sn_time in the north-south direction are transmitted to the countdown display module. At the same time, the direction time of the next state is dynamically adjusted according to the current traffic flow information obtained by the traffic flow detection module. When the direction time in the current state decreases to 1, the finite state machine will switch from the current state to the next state and generate a state control signal state to send to the traffic light drive module, thereby achieving intelligent timing and maximizing road utilization.

[0037] The switching conditions of the finite state machine are determined based on the real-time values ​​of the direction time and the results of traffic flow detection. Specifically, firstly, the difference between the current traffic flow in the north-south direction and the east-west direction is calculated, and the direction time of the next state is dynamically updated according to this traffic flow difference. The larger the traffic flow difference between the north-south and east-west directions, the larger the difference in green light duration between the north-south and east-west directions, and vice versa. Secondly, it is determined whether the direction time in the current state has decreased to 1. If not, the current state is maintained; if so, the state is switched to the next state. Generally, the shortest green light time is selected as the initial direction time for each state. If there are many vehicles in a certain direction, the green light time for that direction can be appropriately increased, but it cannot exceed the longest green light time. Therefore, this invention can change the initial direction time of each state as needed to adapt to different intersection conditions, making this method more practical and scalable.

[0038] Step 3: Use a traffic light driver module to control the display status of the traffic lights at the intersection based on the current state of the finite state machine.

[0039] In this embodiment, the traffic light driver module uses an LED driver display. Its main function is to convert the digital signals emitted by the traffic control module into red, green, and yellow lights that people can see, that is, to transform the abstract traffic situation into observable traffic light display signals. The LED of this traffic light driver module has a total of six bits, which control the north-south yellow light, north-south green light, north-south red light, east-west yellow light, east-west green light, and east-west red light respectively, from the least significant bit to the most significant bit. A blink value of 0.5 seconds is first set as the blinking frequency of the yellow light.

[0040] The traffic light driver module receives the state control signal `state` from the finite state machine (FSM). Based on different `state` values, it generates corresponding red, yellow, and green light drive signals to ensure accurate display of traffic lights in each direction. For example, when the FSM transitions from the current state to the next state (north-south green light, east-west red light), it generates a state control signal `state` of 4'b0001. The traffic light driver module receives this `state` and generates the corresponding LED drive signal `6'b100010`, thus illuminating the north-south green light and the east-west red light. The traffic light driver module uses a one-hot encoding method, assigning each light color an independent control bit, allowing for accurate and independent display of each light's state and avoiding erroneous displays.

[0041] Step 4: Use a countdown display module to control the countdown display of the traffic lights at the intersection based on the real-time value of the direction time under the current state of the finite state machine.

[0042] The countdown display module receives real-time direction time signals from a finite state machine and uses these signals to drive the traffic lights at the intersection to synchronously display the corresponding real-time direction time. This allows pedestrians and vehicles to understand the remaining travel time in the corresponding direction. For example, if the current state of the finite state machine is north-south green light and east-west red light, and the real-time direction time in this state is 8 seconds, the finite state machine will generate the corresponding north-south direction real-time time signal sn_time and send it to the countdown display module. The countdown display module then uses this sn_time signal to drive the traffic lights at the intersection to synchronously display the north-south direction time, indicating that the remaining travel time in the north-south direction is 8 seconds. This countdown display module uses a dynamic scanning method, employing time-division multiplexing to control the content displayed on multiple digital tubes. The countdown display module contains a BCD decoder that converts the binary timing data into driving signals for the seven-segment digital tubes, capable of displaying 0-9 and some letters. To ensure display stability, the scanning frequency is 1kHz, making the display more continuous and eliminating flickering. The displayed information changes according to the current traffic light status: remaining waiting time for a red light, remaining passage time for a green light, and a warning message for a yellow light. The countdown display module also features brightness adjustment, automatically adjusting the brightness based on ambient light conditions. It reduces brightness at night to avoid light pollution and increases brightness in strong sunlight for better visibility. Furthermore, the size of the digital tube can be changed parametrically, offering excellent versatility and scalability.

[0043] In another embodiment, in step 2: a traffic control module, a traffic flow detection module, a traffic light driving module, and a countdown display module are selected to be built on an FPGA.

[0044] In this invention, the design of the hardware platform is crucial, involving data processing, logic control, and signal conversion. Its selection has a significant impact on system performance and cost. Based on requirements for real-time performance, parallelism, cost, and ease of development, and after thorough research, this invention selects Altera's Cyclone IV series FPGAs to build the traffic control module, traffic flow detection module, traffic light driving module, and countdown display module. The Cyclone IV EP4CE10F17C8 is used as the main controller. This series of chips has 10320 logic elements (LEs) and 414Kb of embedded memory, which can meet the requirements of multiple state machines, timers, and sensor interfaces operating simultaneously. The minimum system hardware components include a power management module, a direction timing distribution network, a configuration interface, and basic I / O interfaces. Signal integrity and electromagnetic compatibility are ensured based on reasonable PCB layout. Furthermore, the power management module uses an LDO regulator to provide 1.2V to the FPGA core and to the I / O... The bank provides a 3.3V voltage, enabling the system to operate normally under heavy traffic conditions. Furthermore, the internal PLL direction timing management of this chip series provides a stable direction timing for the entire system, ensuring time synchronization between modules. Abundant I / O resources can meet the connection requirements of multiple signals, including traffic flow sensor input, traffic light drive output, and countdown display. Therefore, this chip series meets the hardware platform design requirements of the present invention in terms of logic resources, direction timing management, and I / O quantity, offering excellent cost-effectiveness.

[0045] It's worth noting that before building the traffic control module, traffic flow detection module, traffic light driver module, and countdown display module on the FPGA, a top-level module needs to be designed. This top-level module coordinates the data exchange and control signal transmission between the various functional modules. The top-level module defines the system's main input / output interfaces, including clock signals, reset signals, infrared sensor inputs, and traffic light display outputs. Internally, the top-level module adopts a layered design, instantiating the traffic flow detection module, traffic control module, traffic light driver module, and a digital tube display and decoding module (i.e., the countdown display module), and connecting them with internal signal lines. Furthermore, the top-level module implements a global reset logic to ensure the system functions correctly and can be reset promptly in case of a fault. Through well-defined signal naming and port mapping, the top-level module provides a robust structural framework for the entire system, facilitating subsequent simulation testing and hardware debugging.

[0046] In another embodiment, in step 2: the traffic control module uses a Moore-type finite state machine to implement the state switching of traffic lights. This finite state machine is written in three stages, separating the current state transition, state transition conditions and rules, and output control to accurately control the traffic signals and smoothly switch states. Specifically, the first stage is the state register update, which updates the current state when the rising edge of the FPGA internal clock arrives; the second stage is the state switching logic, which determines the next state change based on the current state and preset change conditions. The switching conditions are determined by the real-time value of the direction time under the current state and the current traffic flow detection result; the third stage is the output control, including the change rules of each state and the corresponding direction time. The state switching condition of this finite state machine changes when the direction time decreases to 1, and when it decreases to 1, the direction time is reassigned, with the reassigned data determined by the traffic flow deviation. After receiving the traffic flow signal processed by the traffic flow detection module, the traffic control module adds the traffic flow in the same direction and compares it with the traffic flow in the other direction. Based on the magnitude of the comparison, it determines the flag value, and then determines the different times required for the two directions. In the third stage of the finite state machine, it assigns the corresponding state direction time. At the same time, the traffic control module outputs the corresponding state control signal "state" to the traffic light driver module, allowing the traffic light driver module to select and drive different lights to turn on or off or flash according to the changes in "state". It also outputs the corresponding real-time value signal of the time in the corresponding direction to the countdown display module, which then drives and displays the countdown value of different lights according to the real-time value signal of the time in the direction.

[0047] In another embodiment, in step 2: To address the uncertainty and complexity of traffic flow and thus optimize signal timing, this invention employs a fuzzy control algorithm to classify traffic flow information into levels. This fuzzy control algorithm uses traffic flow information as input variables, defining three fuzzy sets—small, medium, and large—to represent different traffic flow levels. Each fuzzy set is represented by triangular and trapezoidal membership functions. Specifically, when the infrared sensor output signal remains 0 for 0-3 seconds, 3-5 seconds, and 5 seconds or more, respectively, it indicates that the traffic flow is small, medium, and large, respectively. These three traffic flow levels are represented by binary values ​​00, 01, and 10, respectively. There is a certain degree of overlap between different levels to facilitate smooth handling of boundary conditions. The output variable of this fuzzy control algorithm is direction-time. Based on a sliding window method, the traffic flow detection module continuously monitors the traffic flow over the past 5 minutes. Figure 8As shown, the traffic flow levels flow_e, flow_s, flow_w, and flow_n in the east, south, west, and north directions of the intersection are calculated. The sum of the traffic flow levels in the north-south direction, flow_sn, and the sum of the traffic flow levels in the east-west direction, flow_ew, are calculated. The difference between flow_sn and flow_ew is then used to obtain the real-time traffic flow deviation flow. Figure 9 As shown, the traffic control module then dynamically adjusts the direction time of the next state based on the real-time traffic flow deviation, with the adjustment range not exceeding 50% of the initial direction time of the same state. At the same time, the corresponding state direction time is assigned in the third stage of the finite state machine, and the traffic control module outputs the corresponding state control signal to the traffic light drive module.

[0048] The fuzzy control algorithm is implemented on an FPGA using a lookup table approach. Fuzzification, rule reasoning, and defuzzification are performed on the FPGA, significantly improving real-time performance. To adapt to different intersection conditions, the system has a parameter adjustment interface, allowing for minor adjustments to membership function parameters and rule weights. It also features a learning function, continuously optimizing these parameters by learning from historical data, thereby improving control effectiveness. Experimental results show that compared to traditional timed control, fuzzy control can reduce average waiting time by 25%-35%, significantly improving traffic conditions.

[0049] In another embodiment, in step 2, the FPGA employs a dynamic timing strategy, automatically adjusting the direction time for each state based on continuous observation of traffic flow changes. This dynamic timing strategy is based on a sliding window method, continuously monitoring traffic flow over the past 5 minutes to calculate the sum of traffic flow in each direction and the traffic flow deviation in different directions, thereby discovering the temporal and spatial distribution patterns of traffic flow. In this embodiment, a day is divided into three periods: morning peak, evening peak, and off-peak. The finite state machine presets corresponding initial direction times for each state in each period. During the morning and evening peak periods, the initial value of the main direction travel time at the intersection is maximized, while during the off-peak period, the initial values ​​of the main and secondary direction travel times at the intersection are equal. During vehicle passage, dynamic adjustment is based on the initial direction time and fine-tuned according to the real-time traffic flow deviation, with the adjustment range not exceeding 50%, thus ensuring system stability while also possessing good adaptability. In addition, this dynamic timing strategy also considers the coordination between adjacent intersections, using a simple green wave control method to reduce the number of times vehicles stop at multiple intersections and improve overall traffic efficiency. In practical applications, dynamic timing strategies can effectively solve sudden traffic congestion problems, with a system response time of less than 30 seconds, providing strong support for intelligent traffic management.

[0050] In another embodiment, in step 1: infrared sensors are installed in the four directions of the intersection (north, south, east, and west). Each infrared sensor uses infrared beams to obtain traffic flow information in the corresponding direction. The traffic flow detection module uses a two-level register to de-jitter the traffic flow information, then uses a counter to count the number of vehicles passing in each direction, and classifies the traffic flow level according to the counting results. Finally, the traffic flow level signal is transmitted to the traffic control module.

[0051] Considering that the raw signals output by infrared sensors generally contain some noise and level fluctuations, a dedicated signal conditioning circuit is used to process them, ensuring that the signals entering the traffic control module meet the requirements of digital logic. Therefore, in this embodiment, the traffic flow detection module uses a level conversion circuit to transform the signals output by the infrared sensors into standard logic levels that the traffic control module can recognize, thus ensuring reliable signal transmission. Furthermore, since signal jitter may occur when vehicles pass by, hardware debouncing is incorporated into the level conversion circuit. This involves using a two-level register in the code to prevent mechanical jitter from affecting the detection. See [link to relevant documentation]. Figure 10 .

[0052] The data acquisition interface is a crucial link between the traffic control module and the traffic flow detection module, and its quality determines the accuracy of traffic flow data acquisition and the reliability of transmission. In this embodiment, the traffic control module's data acquisition interface adopts UART serial data transmission. The traffic control module assigns a separate digital input pin to each of the four directions of traffic flow detection, enabling simultaneous traffic flow detection in multiple directions. Each input channel has an individual pull-up resistor to keep the signal high when there are no vehicles. Furthermore, the traffic control module uses edge-triggered acquisition of traffic flow data, determining vehicle passage by detecting the rising or falling edge of the signal to prevent double counting. The traffic control module's interface circuit also includes expansion interfaces for future connection of more traffic flow detection modules. Notably, all input signals undergo the aforementioned anti-jitter processing before entering the traffic control module, eliminating signal jitter without affecting normal vehicle detection.

[0053] In another embodiment, in step 3: Since the current drive capability of the FPGA output port is relatively small, typically only 8-16mA, but high-brightness LEDs require a working current of 20-30mA to achieve sufficient brightness, a transistor amplifier circuit is selected as the signal light driver module in this embodiment. The transistor amplifier circuit uses an NPN transistor 8050 as the switch, whose maximum collector current can reach 500mA, fully meeting the requirements for LED driving. When the FPGA's GPIO port outputs a high level, a bias current is provided to the base of the transistor through a current-limiting resistor, causing the transistor to conduct and the LED to light up. When the FPGA's GPIO port outputs a low level, the transistor is cut off, and the LED turns off. To prevent reverse current from damaging the FPGA, a protection resistor with a resistance of 220Ω is connected in series in each LED circuit, ensuring both normal LED operating current and overcurrent protection. The entire transistor amplifier circuit uses a 5V power supply, matching the FPGA's 3.3V logic level, enabling good level conversion and power amplification.

[0054] On the other hand, the present invention also provides a dynamic timing traffic signal control system based on a finite state machine, such as... Figure 2 As shown, the control system includes a traffic control module and connected to it a traffic flow detection module, a traffic light driving module, and a countdown display module. The traffic flow detection module collects real-time traffic flow information from the four directions (east, west, south, and north) of the intersection and sends this information to the traffic control module. The traffic control module uses a finite state machine to switch the state of the traffic lights. The finite state machine defines multiple states, each representing a different display state of the traffic lights at the intersection. Each state has a preset direction time representing the passage time in that direction. The traffic control module updates the direction time in the current state with a countdown and dynamically adjusts the direction time for the next state based on the received traffic flow information. When the direction time in the current state decreases to 1, the finite state machine switches from the current state to the next state. The traffic light driving module controls the display state of the traffic lights at the intersection based on the current state of the finite state machine. The countdown display module controls the display of the countdown value of the traffic lights at the intersection based on the real-time value of the direction time in the current state of the finite state machine.

[0055] In another embodiment, the present invention provides a dynamic timing traffic signal control system based on a finite state machine, which uses the dynamic timing traffic signal control method based on a finite state machine described in any of the above embodiments to control the traffic signals at intersections.

[0056] In another embodiment, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a traffic control module, implements the dynamic timing traffic light control method based on a finite state machine as described in any of the above embodiments. Specifically, the computer-readable storage medium may be RAM, ROM, EEPROM, SSD, CDROM, DVD, USB flash drive, or any other medium capable of carrying or storing a computer program and capable of being read by a computer.

[0057] In another embodiment, the present invention also provides a computer program product, including a computer program that, when executed by a traffic control module, implements the dynamic timing traffic signal control method based on a finite state machine as described in any of the above embodiments.

[0058] To verify the functionality and performance of the proposed finite state machine-based dynamic timing traffic light control system in a real hardware environment, ModelSim simulation was used to test the system. During the simulation, a complete test environment was built, including:

[0059] 1. See Figure 3 The traffic flow detection part of the test is performed by writing a testbench file to simulate the traffic flow input signal under different traffic flow conditions.

[0060] 2. Testing of the traffic control module with an embedded finite state machine, see... Figure 4 .

[0061] 3. For testing the countdown display module, see... Figure 5 .

[0062] 4. For testing the traffic light driver module, see... Figure 6 .

[0063] This simulation utilizes the SignalTap II logic analyzer built into Quartus II to perform hardware-in-the-loop testing on the target FPGA-implemented system. The test platform is built on the EP4CE10F17C8 development board, and the system's state transitions, signal outputs, and real-time response characteristics are captured and analyzed online.

[0064] During the test, SignalTap II was used to sample and observe the waveforms of the core control signals (including finite state machine states, traffic flow counts in each direction, traffic light control outputs, timing parameters, etc.) in real time.

[0065] Test Results: The system's finite state machine can stably jump according to the preset logic; the traffic light drive signal level conversion timing is accurate; the LED display module has uniform brightness, with no signal glitches or abnormal levels. During a continuous 2-hour power-on test, the system did not experience unexpected resets, state jumps, or logic malfunctions, demonstrating good operational stability. The traffic flow detection module's response delay is less than 50 ms, and the state machine switching and traffic light timing adjustment response time is less than 100 ms, fully meeting the real-time requirements of traffic control scenarios. In simulated peak-hour traffic flow impact tests, the system can dynamically adjust the traffic timing according to changes in traffic flow in each direction, achieving adaptive control logic of "allowing more vehicles when there are many and restricting traffic when there are few," effectively alleviating the bottleneck of traffic efficiency under fixed timing schemes. Compared with traditional fixed-timing traffic light systems, this simulation improved the intersection's throughput capacity by approximately 18% in the simulated test scenario, verifying the effectiveness and practicality of the adaptive timing strategy of this invention.

[0066] The system parameters used in this simulation and the relevant test results are shown in Table 1 below.

[0067] Table 1 Simulation parameters and results

[0068]

[0069] As shown in Table 1, in terms of timing performance, the longest combinational logic delay occurs between the traffic flow data processing module and the state decision module, with a path delay of 12.8 ns, which is much smaller than the 20 ns direction time period, indicating sufficient timing margin. The setup and hold time checks both showed zero violations, indicating that the data input to all registers can be stably established before the valid edge of the direction time and meet the hold time requirements after the direction time transition, demonstrating stable and reliable system timing performance.

[0070] As shown in Table 1, in terms of resource utilization, the target FPGA's logic element (LE) utilization rate is 15% (1573 / 10320), register resources are used in 1133 locations, pin resources are used in 13% (24 / 180), and embedded memory resources are used in 21% (90112 / 423936). Multipliers and PLL resources are not used. The overall resource utilization rate is low, reserving sufficient hardware space for subsequent functional expansion (such as adding pedestrian detection, emergency mode, etc.). In addition, through two simulations of slow and fast timing models, the timing reliability of the system under different process corners, voltages, and temperatures was ensured, laying a solid foundation for subsequent hardware implementation and board-level debugging.

[0071] As shown in Table 1, in terms of power consumption performance, the system's static power consumption is approximately 85mW, and the dynamic power consumption is controlled below 150mW, meeting the low-power design requirements.

[0072] Therefore, the system proposed in this invention can correctly respond to the input of the traffic flow detection module, the switching between the states of the finite state machine is reasonable, and the state timer can provide the correct time under different timing methods. Especially in the simulation of dynamic timing strategies, the system can automatically adjust the passage time in each direction according to the actual changes in traffic flow.

[0073] In summary, the innovation of this invention lies in:

[0074] The proposed dynamic timing traffic light control method and system based on finite state machines adopts a hierarchical and modular architecture design, using an FPGA as the core processing unit. The entire system is divided into three parts: a perception layer, a control layer, and an execution layer. The perception layer mainly consists of a traffic flow detection module, used to acquire the number of vehicles in the four directions (east, west, south, and north). Infrared beams are used to determine the number and frequency of vehicle passages, providing accurate and effective traffic flow information to the upper layer. The control layer is the core of the entire system, implementing multiple state machines within the traffic control module, with four states: east-west green light, north-south red light, east-west red light, north-south green light, east-west yellow light, north-south red light, and east-west red light, north-south yellow light. Furthermore, the traffic control module can intelligently time the traffic, adjusting the duration of each state according to the current traffic flow, overcoming the problems of traditional fixed timing. It also includes a timer module group to assign an accurate time to each traffic state, ensuring accurate traffic light changes. The execution layer consists of a traffic light driver module and a countdown display module, transforming the logic of the control layer into traffic lights that are visible to pedestrians.

[0075] The system proposed in this invention features a closed-loop feedback data flow. Traffic flow detection signals, after filtering and jitter reduction, are sent to the traffic control module. The traffic control module makes judgments based on current traffic conditions and past experience, then provides corresponding traffic light signals and countdown information. To ensure the system's real-time performance and accuracy, the various components operate asynchronously and in parallel. Utilizing the parallel computing capabilities of FPGAs, traffic lights in multiple directions can be updated synchronously and individually simultaneously. The overall system design emphasizes low coupling between modules, with each module possessing a degree of independence for easy individual testing and maintenance. Standard interface protocols ensure good cooperation between modules. This design significantly simplifies system complexity, improves development efficiency and maintainability, and facilitates the engineering application of intelligent traffic control systems.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dynamic timing traffic signal control method based on finite state machines, characterized in that: A traffic flow detection module is used to obtain real-time traffic flow information in the four directions of the intersection (east, west, south, and north). The traffic control module with an embedded finite state machine receives the traffic flow information. The finite state machine defines multiple states, which are used to represent different display states of traffic lights at the intersection. Each state is preset with a direction time that represents the passage time in the corresponding direction under this state. The direction time under the current state is updated by countdown. At the same time, the direction time of the next state is dynamically adjusted according to the currently received traffic flow information. When the direction time under the current state decreases to 1, the finite state machine switches from the current state to the next state. A traffic light driver module is used to control the display status of traffic lights at an intersection based on the current state of a finite state machine. A countdown display module is used to control the countdown display of traffic lights at intersections based on the real-time value of the direction and time under the current state of the finite state machine.

2. The dynamic timing traffic signal control method based on a finite state machine according to claim 1, characterized in that, The traffic control module, traffic flow detection module, traffic light driver module, and countdown display module were built on an FPGA.

3. The dynamic timing traffic signal control method based on a finite state machine according to claim 2, characterized in that, The finite state machine is written in three stages: the first stage is the state register update, which updates the current state when the rising edge of the FPGA internal clock arrives; The second stage is the state switching logic, which determines the change of the next state based on the current state and the preset switching conditions. The switching conditions are determined based on the real-time value of the direction time in the current state and the current traffic flow detection result. The third stage is the output control, which includes the change law of each state and the corresponding direction time.

4. The dynamic timing traffic signal control method based on a finite state machine according to claim 3, characterized in that, The finite state machine defines four states: east-west green light, north-south red light, east-west red light, north-south green light, east-west yellow light, north-south red light, and east-west red light, north-south yellow light. The direction time in both the east-west yellow light, north-south red light, and east-west red light, north-south yellow light states is 3 seconds.

5. The dynamic timing traffic signal control method based on a finite state machine according to claim 4, characterized in that, An infrared sensor is installed in each of the east, south, west, and north directions of the intersection. Each infrared sensor uses infrared beams to detect traffic flow information in the corresponding direction and transmits it to the traffic flow detection module. The traffic flow detection module uses a two-level register to de-jitter the traffic flow information, then uses a counter to count the number of vehicles passing in each direction, and classifies the traffic flow level according to the counting results. Finally, the traffic flow level signal is transmitted to the traffic control module.

6. The dynamic timing traffic signal control method based on a finite state machine according to claim 5, characterized in that, A fuzzy control algorithm is used to classify traffic flow levels. The algorithm defines three fuzzy sets, namely, small, medium, and large, to represent different traffic flow levels. Triangular and trapezoidal membership functions are used to represent each fuzzy set. When the infrared sensor output signal remains at 0 for 0-3 seconds, 3-5 seconds, and 5 seconds or more, respectively, it indicates that the traffic flow is small, medium, and large. These three traffic flow levels are represented by binary values ​​00, 01, and 10, respectively.

7. The dynamic timing traffic signal control method based on a finite state machine according to claim 6, characterized in that, In the traffic control module, a day is divided into three periods: morning peak, evening peak, and off-peak. An initial direction time is preset for each state in each period. During vehicle passage, based on the sliding window method, the traffic flow detection module continuously monitors the traffic flow over the past 5 minutes, calculates the sum of the traffic flow levels in the north-south direction and the sum of the traffic flow levels in the east-west direction at the intersection, and calculates the difference between the two values ​​to obtain the real-time traffic flow deviation. The traffic control module then dynamically adjusts the direction time of the next state based on the real-time traffic flow deviation, with the adjustment range not exceeding 50% of the initial direction time of the same state.

8. A dynamic timing traffic signal control system based on a finite state machine, comprising a traffic control module and a traffic flow detection module, a traffic light driving module, and a countdown display module connected thereto, characterized in that: The control system employs the dynamic timing traffic signal control method based on finite state machines as described in any one of claims 1-7 to achieve control of traffic signals at intersections.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When executed by the traffic control module, the computer program implements the dynamic timing traffic signal control method based on a finite state machine as described in any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that: When executed by the traffic control module, the computer program implements the dynamic timing traffic signal control method based on a finite state machine as described in any one of claims 1-7.

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