Power semiconductor device
Patent Information
- Application Number
- CN202510337274.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2026-09-29
AI Technical Summary
[0003]SiC平面DMOSFET(Double-diffused MOSFET，双扩散金属氧化物半导体场效应管)工艺相对简单、可靠性强，但由于JFET(Junction Field Effect Transistor，结型场效应晶体管)区的影响，二维电流路径受限，JFET区电阻贡献占比高达30％-50％，使得器件功耗较大，影响器件性能
[0007]本发明上述实施例可以具有如下有益效果：通过在相邻两个第二导电类型阱区之间的区域形成沟槽、并使每个所述第一导电类型掺杂区通过所述对应的第二导电类型阱区的所述间隔部与所述沟槽间隔开，其使得所述功率半导体器件可以同时形成平面沟道(planar channel)和沟槽沟道(trench channel)、且JFET区对导通电阻的影响得以减小甚至消除，从而可以减小导电电阻以增大FOM(Figure of Merit，优值系数)值、提高沟道迁移率、以及缓解短沟道效应以增强栅控能力，藉此提升器件性能。再者，通过将所述沟槽的开口尺寸设计为自所述顶表面沿所述第一方向呈缩小趋势、或者通过使所述沟槽的第一侧壁和第二侧壁均相对于其底面倾斜设置，一方面可以获得较长的沟槽沟道，从而可以减少短沟道效应以提高器件稳定性和可靠性以及具有更高耐压能力，另一方面使得刻蚀负载(etch loading)大大降低，工艺难度得以降低、可靠性也会提升。此外，由于栅控能力增强，栅氧化层厚度可以增大，栅氧可靠性得以改善，适合制作更高耐压的功率半导体器件。另外，由于栅控能力增大，沟道利用率大大提升、功耗低、甚至单位面积元胞密度可以增大以使得集成度高。
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Figure CN122846773A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronic device technology, and more particularly to a power semiconductor device. Background Technology
[0002] Power semiconductor devices are the heart of power electronics technology, playing a crucial role in the development towards high frequency and high power density. Wide bandgap semiconductor materials, such as silicon carbide (SiC), have become ideal choices for high-voltage, high-temperature, high-frequency, high-power, and low-switching-loss power electronic devices due to their advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity. SiC MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are unipolar devices with ideal gate insulation characteristics.
[0003] The SiC planar DMOSFET (Double-diffused MOSFET) process is relatively simple and reliable, but due to the influence of the JFET (Junction Field Effect Transistor) region, the two-dimensional current path is limited, and the resistance contribution of the JFET region is as high as 30%-50%, resulting in high power consumption and affecting device performance. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a power semiconductor device to reduce the influence of the JFET region on the on-resistance, thereby improving device performance.
[0005] Specifically, an embodiment of the present invention provides a power semiconductor device, including, for example, a substrate, a first conductivity type epitaxial layer, a plurality of second conductivity type well regions, a plurality of first conductivity type doped regions, and a gate; the first conductivity type epitaxial layer is disposed on the substrate, the first conductivity type epitaxial layer is configured with trenches, and the trenches are recessed along a first direction on the top surface of the first conductivity type epitaxial layer away from the substrate, the first direction being the direction from the first conductivity type epitaxial layer to the substrate, and the opening size of the trenches decreases from the top surface along the first direction; the plurality of second conductivity type well regions are disposed within the first conductivity type epitaxial layer and extend from the top surface toward the substrate, the trenches are located between two adjacent second conductivity type well regions, the adjacent Each of the two second conductivity type well regions has a spacer exposed to the trench; each first conductivity type doped region is disposed within a corresponding second conductivity type well region and located on the side of the corresponding second conductivity type well region away from the substrate and spaced from the trench by the spacer of the corresponding second conductivity type well region in a second direction perpendicular to the first direction; and the gate is disposed on the side of the first conductivity type epitaxial layer away from the substrate, the gate portion extending into the trench and crossing the spacer of each of the two adjacent second conductivity type well regions and extending to cover a portion of the first conductivity type doped region located on the side of the spacer away from the trench.
[0006] Furthermore, another embodiment of the present invention provides a power semiconductor device, for example including: a substrate, a first conductivity type epitaxial layer, a plurality of second conductivity type well regions, a plurality of first conductivity type doped regions, and a gate; the first conductivity type epitaxial layer is disposed on the substrate, the first conductivity type epitaxial layer is configured with trenches, and the trenches are recessed along a first direction on the top surface of the first conductivity type epitaxial layer away from the substrate, the first direction being the direction from the first conductivity type epitaxial layer to the substrate, the trenches include opposing first sidewalls and second sidewalls and a bottom surface connected between the first sidewalls and the second sidewalls, each of the first sidewalls and the second sidewalls is inclined relative to the bottom surface, and the angle between them and the bottom surface is an obtuse angle; the plurality of second conductivity type well regions are disposed within the first conductivity type epitaxial layer and extend toward the substrate in the first direction, the trenches being located between two adjacent well regions. Between the second conductivity type well regions, each of the two adjacent second conductivity type well regions has a spacer portion exposed to the trench; each first conductivity type doped region is disposed within a corresponding second conductivity type well region and located on the side of the corresponding second conductivity type well region away from the substrate and spaced from the trench by the spacer portion of the corresponding second conductivity type well region in a second direction perpendicular to the first direction; and the gate is disposed on the side of the first conductivity type epitaxial layer away from the substrate, the gate covering the first sidewall, the second sidewall and the bottom surface in the trench, and extending outward from the trench to cover the end face of the spacer portion of each of the two adjacent second conductivity type well regions away from the substrate and a portion of the first conductivity type doped region located on the side of the spacer portion away from the trench.
[0007] The above embodiments of the present invention can have the following beneficial effects: By forming a trench in the region between two adjacent second conductivity type well regions and separating each first conductivity type doped region from the trench through the spacer portion of the corresponding second conductivity type well region, the power semiconductor device can simultaneously form a planar channel and a trench channel, and the influence of the JFET region on the on-resistance is reduced or even eliminated. This reduces the conductivity resistance to increase the FOM (Figure of Merit) value, improves the channel mobility, and alleviates the short-channel effect to enhance gate control capability, thereby improving device performance. Furthermore, by designing the opening size of the trench to decrease from the top surface along the first direction, or by making the first and second sidewalls of the trench inclined relative to its bottom surface, a longer trench channel can be obtained, thereby reducing the short-channel effect to improve device stability and reliability and have higher withstand voltage capability. On the other hand, the etching load is greatly reduced, the process difficulty is reduced, and the reliability is improved. Furthermore, the enhanced gate control capability allows for a greater gate oxide thickness, improving gate oxide reliability and making it suitable for fabricating higher voltage-rated power semiconductor devices. Additionally, the increased gate control capability significantly improves channel utilization, reduces power consumption, and even allows for increased cell density per unit area, resulting in higher integration density. Attached Figure Description
[0008] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0009] Figure 1 This is a partial structural cross-sectional schematic diagram of a power semiconductor device provided in an embodiment of the present invention.
[0010] Figure 2 for Figure 1 An enlarged schematic diagram of the trench of the power semiconductor device shown.
[0011] Figure 3 This is a partial structural cross-sectional schematic diagram of another power semiconductor device provided in an embodiment of the present invention.
[0012] Figures 4A to 4C This is a partial structural cross-sectional view of a method for fabricating a power semiconductor device according to an embodiment of the present invention.
[0013] [Explanation of Key Figure Markings]
[0014] 10 - Power semiconductor device; 11 - Substrate; 13 - Epitaxial layer of first conductivity type; 13T - Top surface; 130 - Well region of second conductivity type; 130S - Lower end face; 1300 - Doped region of first conductivity type; 1302 - Heavily doped region of second conductivity type; 131 - Spacer portion; 131E - End face; W1, W2 - Width of spacer portion; 133 - Trench; WS - Opening size of trench; 133L - First sidewall; 133R - Second sidewall; 133B - Bottom surface; 133A - Transition arc surface; 15 - Gate; 151 - Gate oxide layer; 153 - Polysilicon layer; θ1 - Tilt angle; θ2 - Angle; CH - Contact hole; 17 - Interlayer insulating layer; 19a - First electrode layer; 19b - Second electrode layer; 200 - Protective layer; 300 - Patterned photoresist layer; B1 - First direction; B2 - Second direction. Detailed Implementation
[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0016] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0018] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.
[0019] See Figure 1 , Figure 2 and Figure 3The present invention provides a power semiconductor device 10, which includes, for example, a substrate 11, a first conductivity type epitaxial layer 13, a plurality of second conductivity type well regions 130, a plurality of first conductivity type doped regions 1300, and a gate 15.
[0020] The first conductivity type epitaxial layer 13 is disposed on the substrate 11. The first conductivity type epitaxial layer 13 has a trench 133, which is recessed along a first direction B1 on the top surface 13T of the first conductivity type epitaxial layer 13 away from the substrate 11. The first direction B1 is the direction from the first conductivity type epitaxial layer 13 to the substrate 11. The opening size WS of the trench 133 decreases from the top surface 13T along the first direction B1. For example, the substrate 11 is an N-type SiC substrate, and its doping concentration is, for example, in the range 1E19 cm⁻¹. -3 -1E20cm -3 The first conductivity type epitaxial layer 13 is an N-type SiC epitaxial layer, and its doping concentration is, for example, in the range of 1E16cm. -3 -1E17cm -3 It is worth mentioning that the statement that "the opening size WS of the groove 133 decreases from the top surface 13T along the first direction B1" should be understood as meaning that the opening size at the groove opening of the groove 133 is larger than the opening size at the bottom of the groove 133, and not limited to the case where the opening size WS of the groove 133 gradually decreases from the groove opening to the groove bottom along the first direction B1.
[0021] The plurality of second conductivity type well regions 130 are disposed within the first conductivity type epitaxial layer 13 and extend from the top surface 13T toward the substrate 11. The trench 133 is located between two adjacent second conductivity type well regions 130, and each of the two adjacent second conductivity type well regions 130 has a spacer portion 131 exposed to the trench 133. For example, Figure 1 The diagram shows two adjacent well regions 130 of the second conductivity type, which are, for example, P-type doped regions, and whose doping concentration is, for example, in the range of 1E16 cm⁻¹. -3 -1E18cm -3 Furthermore, it is worth noting that the fact that the spacer 131 is exposed to the groove 133 can be understood as: the spacer 131 can be seen on the sidewall of the groove 133, or in other words, the surface of the spacer 131 facing the groove 130 constitutes part of the sidewall of the groove 130.
[0022] As described above, each first conductivity type doped region 1300 is disposed within a corresponding second conductivity type well region 130, located on the side of the corresponding second conductivity type well region 130 facing away from the substrate 11, and spaced apart from the trench 133 by the spacer portion 131 of the corresponding second conductivity type well region 130 in a second direction B2 perpendicular to the first direction B1. For example, each first conductivity type doped region 1300 is an N-type heavily doped region, and its doping concentration is, for example, in the range of 1E19 cm⁻¹. -3 -1E20cm -3 .
[0023] The gate 15 is disposed on the side of the first conductivity type epitaxial layer 13 facing away from the substrate 11. The gate 15 partially extends into the trench 133 and crosses the spacer portion 131 of each of the two adjacent second conductivity type well regions 130, extending to cover a portion of the first conductivity type doped region 1300 located on the side of the spacer portion 131 away from the trench 133. For example, the gate 15 includes a stacked gate oxide layer 151 and a polysilicon layer 153, with the gate oxide layer 151 located on the side of the polysilicon layer 153 facing the substrate 11; furthermore, the thickness of the gate oxide layer 151 is, for example, in the range of 30 nm to 100 nm, and the thickness of the polysilicon layer 153 is, for example, in the range of 300 nm to 800 nm.
[0024] As can be seen from the above, the embodiments of the present invention form a trench 133 in the region between two adjacent second conductivity type well regions 130, and space each first conductivity type doped region 1300 apart from the trench 133 by the spacer portion 131 of the corresponding second conductivity type well region 130, which enables the power semiconductor device 10 to simultaneously form planar channels and trench channels (see...). Figure 3 Furthermore, the influence of the JFET region on the on-resistance is reduced or even eliminated, thereby reducing the conductivity resistance to increase the FOM value, improving channel mobility, and mitigating short-channel effects to enhance gate control capability, thereby improving device performance. Moreover, by designing the opening size WS of the trench 133 to decrease in size from the top surface 13T along the first direction B1, the etching load is significantly reduced, simplifying the process and improving reliability. In addition, due to the enhanced gate control capability, the thickness of the gate oxide layer 151 can be increased, improving gate oxide reliability and making it suitable for fabricating higher voltage-rated power semiconductor devices. Furthermore, the increased gate control capability significantly improves channel utilization, reduces power consumption, and even allows for increased cell density per unit area, resulting in higher integration density.
[0025] In some embodiments, see Figure 1 and Figure 2 , the trench 133 includes a first sidewall 133L and a second sidewall 133R that are oppositely arranged, and the first sidewall 133L and the second sidewall 133R extend obliquely toward the substrate 11 in a manner of approaching each other. For example, an inclination angle θ1 of each of the first sidewall 133L and the second sidewall 133R relative to the first direction B1 is in a range of 10°-60°. In this way, an opening size WS of the trench 133 gradually decreases from the notch to the trench bottom along the first direction B1. Compared with a situation where the first sidewall 133L and the second sidewall 133R are vertical, a longer trench channel can be obtained, thereby reducing the short channel effect to improve the stability and reliability of the device and providing a higher voltage withstand capability. Furthermore, the oblique arrangement of the sidewalls greatly reduces the etching load. Since a vertical trench structure is not required, the process difficulty is reduced and the reliability is also improved.
[0026] In some embodiments, referring to Figure 1 and Figure 2 , the trench 133 further includes a bottom surface 133B and transition arc surfaces 133A respectively connected between the bottom surface 133B and the first sidewall 133L and the second sidewall 133R, and the radian of each transition arc surface 133A is greater than π / 2. In this way, the trench 133 is a bowl-shaped trench structure, which can reduce the peak electric field at the bottom corner of the trench 133, thereby improving the reliability of gate oxide.
[0027] In some embodiments, referring to Figure 1 and Figure 2 , widths W1 and W2 of the spacer 131 gradually increase along the first direction B1, that is, W1<W2. This structural design of the spacer 131 facilitates the oblique arrangement of the first sidewall 133L and the second sidewall 133R of the trench 133.
[0028] In some embodiments, referring to Figure 1 and Figure 2 , in the first direction B1, a bottom surface 133B of the trench 133 is higher than or flush with a lower end surface 130S, facing the substrate 11, of each of the two adjacent second conductivity type well regions 130. This relative position design is beneficial for reducing or even eliminating the influence of the JFET region on the on-resistance of the device.
[0029] In some embodiments, referring to Figure 1The power semiconductor device 10 further includes a plurality of heavily doped regions 1302 of a second conductivity type. Each heavily doped region 1302 of the second conductivity type is disposed within a corresponding well region 130 of the second conductivity type and is spaced apart from the spacer portion 131 in the second direction B2 by a first conductivity type doped region 1300 of the corresponding well region 130. The doping concentration of each heavily doped region 1302 of the second conductivity type is higher than the doping concentration of the corresponding well region 130. For example, each heavily doped region 1302 of the second conductivity type is a p-type heavily doped region, and its doping concentration is, for example, in the range 1E18cm. -3 -1E20cm -3 The arrangement of the second conductivity type heavily doped region 1302 is beneficial for providing stable electrical connections, such as ohmic contacts, to ensure that current can flow into or out of the device efficiently.
[0030] In some embodiments, see Figure 1 and Figure 3 The power semiconductor device 10 further includes an interlayer insulating layer 17, a first electrode layer 19a, and a second electrode layer 19b. The interlayer insulating layer 17 is disposed on the side of the gate 15 facing away from the substrate 11 and has a contact hole CH formed therein to expose a portion of the first conductivity type doped region 1300 and at least a portion of the second conductivity type heavily doped region 1302 within each of the two adjacent second conductivity type well regions 130. The material of the interlayer insulating layer 17 is, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The first electrode layer 19a is disposed on the side of the interlayer insulating layer 17 away from the substrate 11 and extends into the contact hole CH to form an electrical contact, such as an ohmic contact, with the first conductivity type doped region 1300 and the second conductivity type heavily doped region 1302 in each of the two adjacent second conductivity type well regions 130. The first electrode layer 19a is, for example, composed of a titanium (Ti) layer, a nickel (Ni) layer and an aluminum (Al) layer stacked sequentially. The second electrode layer 19b is disposed on the side of the substrate 11 away from the first conductivity type epitaxial layer 13 and forms an electrical contact, such as an ohmic contact, with the substrate 11. The second electrode layer 19b is, for example, composed of a silver layer and Ti and Ni layers stacked alternately between the silver layer and the substrate 11.
[0031] Please see again. Figure 1 , Figure 2 and Figure 3Another embodiment of the present invention provides a power semiconductor device 10, which includes, for example, a substrate 11, a first conductivity type epitaxial layer 13, a plurality of second conductivity type well regions 130, a plurality of first conductivity type doped regions 1300, and a gate 15.
[0032] The first conductivity type epitaxial layer 13 is disposed on the substrate 11. The first conductivity type epitaxial layer 13 is provided with a trench 133, and the trench 133 is recessed along a first direction B1 on the top surface 13T of the first conductivity type epitaxial layer 13 away from the substrate 11. The first direction B1 is the direction from the first conductivity type epitaxial layer 13 to the substrate 11. The trench 133 includes a first sidewall 133L and a second sidewall 133R disposed opposite to each other, and a bottom surface 133B connecting the first sidewall 133L and the second sidewall 133R. Each of the first sidewall 133L and the second sidewall 133R is inclined relative to the bottom surface 133B, and the included angle θ2 between them is an obtuse angle. For example, the substrate 11 is an N-type SiC substrate, and its doping concentration is, for example, in the range 1E19cm. -3 -1E20cm -3 The first conductivity type epitaxial layer 13 is an N-type SiC epitaxial layer, and its doping concentration is, for example, in the range of 1E16cm. -3 -1E17cm -3 .
[0033] The plurality of second conductivity type well regions 130 are disposed within the first conductivity type epitaxial layer 13 and extend from the top surface 13T toward the substrate 11. The trench 133 is located between two adjacent second conductivity type well regions 130, and each of the two adjacent second conductivity type well regions 130 has a spacer portion 131 exposed to the trench 133. For example, Figure 1 The diagram shows two adjacent well regions 130 of the second conductivity type, which are, for example, P-type doped regions, and whose doping concentration is, for example, in the range of 1E16 cm⁻¹. -3 -1E18cm -3 .
[0034] Each first conductivity type doped region 1300 is disposed within a corresponding second conductivity type well region 130, and is located on the side of the corresponding second conductivity type well region 130 facing away from the substrate 11, and is spaced apart from the trench 133 by the spacer portion 131 of the corresponding second conductivity type well region 130 in a second direction B2 perpendicular to the first direction B1. For example, each first conductivity type doped region 1300 is an N-type heavily doped region, and its doping concentration is, for example, in the range of 1E19 cm⁻¹. -3 -1E20cm-3 .
[0035] The gate 15 is disposed on the side of the first conductivity type epitaxial layer 13 facing away from the substrate 11. The gate 15 covers the first sidewall 133L, the second sidewall 133R, and the bottom surface 133B within the trench 133, and extends outward from the trench 133 to cover the end face 131E of the spacer portion 131 of each of the two adjacent second conductivity type well regions 130 facing away from the substrate 11 and a portion of the first conductivity type doped region 1300 located on the side of the spacer portion 131 away from the trench 133. For example, the gate 15 includes a stacked gate oxide layer 151 and a polysilicon layer 153, with the gate oxide layer 151 located on the side of the polysilicon layer 153 facing the substrate 11; furthermore, the thickness of the gate oxide layer 151 is, for example, in the range of 30nm-100nm, and the thickness of the polysilicon layer 153 is, for example, in the range of 300nm-800nm.
[0036] As can be seen from the above, the embodiments of the present invention form a trench 133 in the region between two adjacent second conductivity type well regions 130, and space each first conductivity type doped region 1300 apart from the trench 133 by the spacer portion 131 of the corresponding second conductivity type well region 130, which enables the power semiconductor device 10 to simultaneously form planar channels and trench channels (see...). Figure 3 Furthermore, the influence of the JFET region on the on-resistance is reduced or even eliminated, thereby reducing the conductivity resistance to increase the FOM value, improving channel mobility, and mitigating short-channel effects to enhance gate control capability, thus improving device performance. Moreover, by tilting both the first and second sidewalls of the trench relative to its bottom surface, a longer trench channel can be obtained, reducing short-channel effects and improving device stability and reliability. Additionally, the etching load is significantly reduced, simplifying the manufacturing process and improving reliability. Furthermore, due to the enhanced gate control capability, the thickness of the gate oxide layer 151 can be increased, improving gate oxide reliability and making it suitable for fabricating higher voltage-rated power semiconductor devices. Additionally, the increased gate control capability significantly improves channel utilization, reduces power consumption, and even allows for increased cell density per unit area, resulting in higher integration density.
[0037] To facilitate a clearer understanding of the power semiconductor devices provided in the embodiments of the present invention, the following will be combined with... Figures 4A to 4C Brief description Figure 1 A method for manufacturing the power semiconductor device 10 shown may specifically include the following steps.
[0038] First, provide Figure 4AThe initial semiconductor structure shown includes: a substrate 11; a first conductivity type epitaxial layer 13 formed on one side of the substrate 11; a plurality of second conductivity type well regions 130 formed within the first conductivity type epitaxial layer 130 and extending from the top surface 13T of the first conductivity type epitaxial layer 130 along a first direction B1 toward the substrate 11; a first conductivity type doped region 1300 and a second conductivity type heavily doped region 1302 formed within each second conductivity type well region 130 and located on the side of the second conductivity type well region 130 opposite to the substrate 11; and a... A protective layer 200 is formed on the side of the first conductivity type epitaxial layer 13 facing away from the substrate 11; in a second direction B2 perpendicular to the first direction B1, the first conductivity type doped region 1300 is located between the corresponding second conductivity type well region 130 and the second conductivity type heavily doped region 1302; and the protective layer 200 covers the top surface 13T of the first conductivity type epitaxial layer 13, the plurality of second conductivity type well regions 130, and the first conductivity type doped region 1300 and the second conductivity type heavily doped region 1302 within each second conductivity type well region 130. The protective layer 200 may be a silicon dioxide layer formed by surface deposition or in-situ oxidation, with a thickness, for example, in the range of 30 nm to 100 nm. Figure 4A The specific implementation method of the initial semiconductor structure shown can refer to the relevant steps in the existing mature SiC planar DMOSFET fabrication process, so it will not be repeated here.
[0039] Next, a photoresist material is spin-coated, and an exposure window is created in the area to be used for subsequent gate formation to form a patterned photoresist layer 300, such as... Figure 4B As shown, the window area partially opens the planar channel to prevent the formation of a JFET region below this area, which would increase on-resistance. Instead, it is etched into a trench 133. This has advantages: firstly, it reduces on-resistance; secondly, it increases the cell density per unit area of the chip, thus reducing cost. Furthermore, by adjusting the exposure opening size D1 according to the planar channel size, the channel length can be flexibly adjusted.
[0040] Subsequently, trench-type structures are formed through dry or wet etching, for example, forming... Figure 4C The bowl-shaped trench 133 shown has a certain arc at the bottom with an arc greater than π / 2. The specific size is determined by the actual trench depth or channel length. The advantages of this structure are that it can reduce the peak electric field at the bottom corner of the trench 133, and the etching load is also greatly reduced. It does not require a vertical trench structure, which greatly reduces the process difficulty and improves reliability. Moreover, it reduces or even eliminates the influence of the JFET region on the on-resistance, and the channel density is greater.
[0041] Then, wet etching removes the remaining protective layer 200, and high-temperature (e.g., 1400℃-1500℃) oxidation is used to form in-situ gate oxide with a thickness, for example, in the range of 30nm-100nm. Simultaneously, polysilicon is deposited as the gate electrode material with a thickness, for example, in the range of 300nm-800nm. Finally, etching yields... Figure 1 The power semiconductor device 10 shown includes a gate oxide layer 151 and a polysilicon layer 153 stacked together. From... Figure 1 and Figure 2 As can be seen, this power semiconductor device 10 has two channels: a planar channel and a trench channel. This increases the process window and makes the threshold voltage more controllable because the size of the trench channel can be adjusted by adjusting the bowl tilt angle θ1 (a larger tilt angle θ1 results in a shallower trench, and a smaller tilt angle θ1 results in a deeper trench). It also reduces the peak electric field at the bottom of the trench, making the gate oxide more reliable and suitable for manufacturing power devices with higher withstand voltage. Furthermore, it reduces or even eliminates the influence of the JFET region on the on-resistance.
[0042] Furthermore, it is understandable that, Figure 1 Based on the structure shown, a series of mature process steps can be performed, such as the formation of interlayer insulating layer 17, the formation of first electrode layer 19a, and the formation of second electrode layer 19b, to obtain... Figure 3 The power semiconductor device structure shown is shown.
[0043] Finally, it is worth mentioning that the device material is not limited to SiC, but can also be Si, Ga2O3, GaN, diamond, etc.; the cell structure of the power semiconductor device in the embodiments of the present invention can be applied not only to strip distribution layouts, but also to layouts of square, circular, hexagonal, octagonal, dodecagonal, and other shapes.
[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A power semiconductor device, characterized in that, include: Substrate; A first conductivity type epitaxial layer is disposed on the substrate. The first conductivity type epitaxial layer is configured with trenches, and the trenches are recessed along a first direction on the top surface of the first conductivity type epitaxial layer away from the substrate. The first direction is the direction from the first conductivity type epitaxial layer to the substrate. The opening size of the trenches decreases from the top surface along the first direction. A plurality of second conductivity type well regions are disposed within the first conductivity type epitaxial layer and extend from the top surface toward the substrate, the trench is located between two adjacent second conductivity type well regions, and each of the two adjacent second conductivity type well regions has a spacer exposed to the trench; Multiple first conductivity type doped regions, each first conductivity type doped region is disposed in a corresponding second conductivity type well region and is located on the side of the corresponding second conductivity type well region away from the substrate and is separated from the trench by the spacer portion of the corresponding second conductivity type well region in a second direction perpendicular to the first direction; as well as A gate is disposed on the side of the first conductivity type epitaxial layer away from the substrate. The gate portion extends into the trench and crosses the spacer of each of the two adjacent second conductivity type well regions and extends to cover a portion of the first conductivity type doped region located on the side of the spacer away from the trench.
2. The power semiconductor device according to claim 1, characterized in that, The trench includes a first sidewall and a second sidewall disposed opposite to each other, the first sidewall and the second sidewall extending obliquely toward the substrate in a manner close to each other.
3. The power semiconductor device according to claim 2, characterized in that, The groove further includes a bottom surface and transition arc surfaces connecting the bottom surface to the first sidewall and the second sidewall respectively, wherein the curvature of each transition arc surface is greater than π / 2.
4. The power semiconductor device according to claim 2, characterized in that, The tilt angle of each of the first and second sidewalls relative to the first direction is in the range of 10°-60°.
5. The power semiconductor device according to claim 1, characterized in that, The width of the interval gradually increases along the first direction.
6. The power semiconductor device according to claim 1, characterized in that, In the first direction, the bottom surface of the trench is higher than or flush with the lower end surface of each of the two adjacent second conductivity type well regions facing the substrate.
7. The power semiconductor device according to claim 1, characterized in that, Also includes: Multiple heavily doped regions of the second conductivity type are provided, each of which is disposed within a corresponding second conductivity type well region and is separated from the spacer portion in the second direction by a first conductivity type doped region of the corresponding second conductivity type well region; the doping concentration of each heavily doped region of the second conductivity type is higher than the doping concentration of the corresponding second conductivity type well region.
8. The power semiconductor device according to claim 1, characterized in that, The gate includes a stacked gate oxide layer and a polysilicon layer, wherein the gate oxide layer is located on the side of the polysilicon layer facing the substrate; and The thickness of the gate oxide layer is in the range of 30nm-100nm, and / or the thickness of the polysilicon layer is in the range of 300nm-800nm.
9. The power semiconductor device according to claim 7, characterized in that, Also includes: An interlayer insulating layer is disposed on the side of the gate opposite to the substrate and has contact holes formed to expose a portion of the first conductivity type doped region and at least a portion of the second conductivity type heavily doped region in each of the two adjacent second conductivity type well regions; A first electrode layer is disposed on the side of the interlayer insulating layer away from the substrate and extends into the contact hole to form an electrical contact with the first conductivity type doped region and the second conductivity type heavily doped region in each of the two adjacent second conductivity type well regions. as well as The second electrode layer is disposed on the side of the substrate opposite to the first conductivity type epitaxial layer and forms an electrical contact with the substrate.
10. A power semiconductor device, characterized in that, include: Substrate; A first conductivity type epitaxial layer is disposed on the substrate. The first conductivity type epitaxial layer is configured with a trench, and the trench is recessed along a first direction on the top surface of the first conductivity type epitaxial layer away from the substrate. The first direction is the direction from the first conductivity type epitaxial layer to the substrate. The trench includes a first sidewall and a second sidewall disposed opposite to each other and a bottom surface connected between the first sidewall and the second sidewall. Each of the first sidewall and the second sidewall is inclined relative to the bottom surface and the angle between them is an obtuse angle. A plurality of second conductivity type well regions are disposed within the first conductivity type epitaxial layer and extend toward the substrate in the first direction, the trench is located between two adjacent second conductivity type well regions, and each of the two adjacent second conductivity type well regions has a spacer exposed to the trench; Multiple first conductivity type doped regions, each first conductivity type doped region is disposed in a corresponding second conductivity type well region and is located on the side of the corresponding second conductivity type well region away from the substrate and is separated from the trench by the spacer portion of the corresponding second conductivity type well region in a second direction perpendicular to the first direction; as well as A gate is disposed on the side of the first conductivity type epitaxial layer away from the substrate. The gate covers the first sidewall, the second sidewall, and the bottom surface within the trench, and extends outward from the trench to cover the end face of the spacer portion away from the substrate of each of the two adjacent second conductivity type well regions and a portion of the first conductivity type doped region located on the side of the spacer portion away from the trench.
11. The power semiconductor device according to claim 10, characterized in that, Each of the first sidewall and the second sidewall is connected to the bottom surface via a transition arc surface, and the arc of the transition arc surface is greater than π / 2.
12. The power semiconductor device according to claim 10, characterized in that, The tilt angle of each of the first sidewall and the second sidewall relative to the first direction is in the range of 10°-60°; And / or, in the first direction, the bottom surface of the trench is higher than or flush with the lower end surface of each of the two adjacent second conductivity type well regions facing the substrate.
13. The power semiconductor device according to claim 10, 11, or 12, characterized in that, The width of the interval gradually increases along the first direction; And / or, the power semiconductor device further includes: an interlayer insulating layer, a first electrode layer, and a second electrode layer, wherein the interlayer insulating layer is disposed on the side of the gate opposite to the substrate and has a contact hole formed therein to expose at least a portion of the first conductivity type doped region in each of the two adjacent second conductivity type well regions, the first electrode layer is disposed on the side of the interlayer insulating layer opposite to the substrate and extends into the contact hole to form an electrical contact with at least the first conductivity type doped region in each of the two adjacent second conductivity type well regions, and the second electrode layer is disposed on the side of the substrate opposite to the first conductivity type epitaxial layer and forms an electrical contact with the substrate.