Analog in-memory calculation circuit, processing device and electronic equipment

Abstract

The utility model discloses an analog in-memory calculation circuit, a processing device and electronic equipment, relates to the technical field of neural networks, and solves the technical problem that in-memory calculation is easy to cause reduction of reliability and throughput along with increase of the number of calculation lines. A storage and calculation module of the circuit comprises a storage and calculation sub-module, a selector and an analog-to-digital converter, the storage operator sub-module comprises a first group of calculation sub-modules and a second group of calculation sub-modules; the first group of calculation sub-modules is connected with input data, the other end of each row of summation capacitor is connected with a first signal line, and the first signal line is connected with an analog-to-digital converter through a selector; and in the second group of calculation sub-modules, the input end of each row of storage and calculation unit accesses input data through a delay unit, the other end of each row of summation capacitor is connected with a second signal line, and the second signal line is connected with the analog-to-digital converter through the selector. According to the utility model, the first group of calculation sub-modules and the second group of calculation sub-modules are respectively used for calculation, so that high throughput and reliability of calculation are guaranteed.

Description

Technical Field

[0001] The utility model relates to the technical field of neural network, and in particular to an analog in-memory computing circuit, a processing device and an electronic device. Background Art

[0002] As Moore's Law gradually approaches its limit, the "storage wall" and "power consumption wall" problems of artificial intelligence (AI) chips based on the von Neumann architecture are becoming increasingly prominent, and the growth rate of chip computing power is becoming slower and slower. Against this background, the emerging chip architecture of integrated storage and computing is gradually emerging to provide the next generation of artificial intelligence chips with greater computing power and better energy efficiency. The integrated storage and computing architecture can be understood as embedding computing power in the memory, performing two-dimensional and three-dimensional matrix multiplication / addition operations with a new computing architecture, rather than optimizing on traditional logic operation units or processes. This can essentially eliminate unnecessary data movement delays and power consumption, improve artificial intelligence computing efficiency by hundreds or thousands of times, reduce costs, and break the "storage wall" and "power consumption wall".

[0003] The Computing-in-Memory (CIM) architecture is an innovative chip architecture that aims to overcome the "memory wall" problem by integrating storage and computing functions on the same chip. The basic idea is to move data calculations to the memory units that store data, thereby achieving in-situ computing and eliminating bandwidth limitations and data movement costs. This technology embeds computing power in the memory and adopts a new computing architecture to implement matrix-vector multiplication and accumulation operations. The advantage of the integrated storage and computing technology is that it can reduce the additional energy consumption caused by data movement and improve the efficiency of parallel data processing. This technology is not only suitable for AI computing, but can also be applied to integrated sensing, storage and computing chips and brain-like chips, representing the mainstream big data computing chip architecture in the future.

[0004] Regarding the implementation of computing in the integrated storage and computing chip architecture, there are two main traditional implementation architectures: digital computing architecture and analog computing architecture. The digital computing architecture refers to the cumulative sum of the matrix-vector product obtained by cascading a multi-level addition tree to obtain the product of the stored data in the in-memory computing unit matrix and the input vector data. The analog computing architecture refers to the cumulative sum of the product of the stored data in the in-memory computing unit matrix and the input vector data, which is then converted into a digital signal by an analog-to-digital converter (ADC) through capacitor accumulation. Among them, the physical implementation of the analog in-memory computing circuit has a smaller chip area and lower power consumption than the physical implementation of the digital in-memory computing circuit.

[0005] However, the calculation in analog memory is usually easily affected by the surrounding voltage fluctuation, which causes errors in charge accumulation and thus calculation errors. In the specific calculation process, the power supply voltage of the storage unit matrix and the analog-to-digital converter around the capacitor is VDD, and the ground voltage is VSS. The ideal voltage of VSS is 0. The voltage change amplitude of the S end of each row of capacitors is one LSB (Least Significant Bit). LSB is equal to the voltage VDD divided by the number of rows X, that is, LSB = VDD / X. It can be seen from the formula that as the number of rows X increases, the voltage of LSB will also be smaller. For example, when VDD is 800mV, when the number of rows is 32, the LSB voltage is 25mV, and when the number of rows increases to 64, the LSB voltage is reduced to 12.5mV. The smaller the voltage of LSB, the higher the resolution requirement of the analog-to-digital converter, and the higher the probability of the analog-to-digital converter conversion error. Especially when the power supply voltage fluctuates due to external influences, if the fluctuation voltage △V exceeds the voltage of LSB, the conversion error of the analog-to-digital converter will occur, and then the calculation result will be wrong. Therefore, the reliability of analog charge calculation in existing in-memory computing schemes will decrease as the number of calculation rows increases. However, if the number of calculation rows is reduced, the calculation throughput will decrease, affecting the computing performance. There is an urgent need for an analog in-memory computing circuit with high reliability and high throughput. Utility Model Content

[0006] The purpose of the present invention is to provide an analog in-memory computing circuit, a processing device and an electronic device to at least solve the above technical problems. The preferred technical solutions among the many technical solutions provided by the present invention can produce many technical effects as described below.

[0007] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0008] The utility model provides an analog in-memory computing circuit, comprising M columns of memory computing modules, each column of memory computing modules comprising: N rows of memory computing submodules for computing N input data, a selector, and an analog-to-digital converter for converting an analog signal output by the selector into a digital signal; each row of the memory computing submodules comprises: a memory computing unit for storing and multiplying the stored data with the input data, and a summing capacitor for sensing the change of the product voltage output by the memory computing unit, one end of the summing capacitor of each row is connected to the output end of the memory computing unit of the row; the N rows of memory computing submodules at least comprise: a first group of computing submodules containing a plurality of rows of memory computing submodules, and a second group of computing submodules containing a plurality of rows of memory computing submodules; the total number of rows of the memory computing submodules of the first group of computing submodules is equal to the total number of rows of the memory computing submodules of the second group of computing submodules; the memory computing submodules of each row in the first group of computing submodules are equal to the total number of rows of the memory computing submodules of the second group of computing submodules; The input end of the unit is connected to the input data, and the other end of the summing capacitor of each row is connected to the first signal line to accumulate the signal on the summing capacitor, and the first signal line is connected to the analog-to-digital converter through the selector; in the second group of calculation sub-modules, the input end of the storage and calculation unit of each row is connected to the input data through the delay unit, so that the time when the input data is input into the storage and calculation unit in the second group of calculation sub-modules is later than the time when the input data is input into the storage and calculation unit in the first group of calculation sub-modules, and the other end of the summing capacitor of each row in the second group of calculation sub-modules is connected to the second signal line to accumulate the signal on the summing capacitor, and the second signal line is connected to the analog-to-digital converter through the selector; the selector is used to connect the signal of one of the first signal line and the second signal line to the analog-to-digital converter, so as to obtain the calculation result of the storage and calculation module of this column based on the digital signal output by the analog-to-digital converter.

[0009] Preferably, it also includes a delayed digital power supply connected to the delay unit, and the delayed digital power supply is used to supply power to the delay unit.

[0010] Preferably, the first group of computing submodules is formed by storage-operation submodules located in even-numbered rows, and the second group of computing submodules is formed by storage-operation submodules located in odd-numbered rows.

[0011] Preferably, the in-memory calculation process of the first group of calculation submodules includes: a first multiplication calculation and charge sampling process, and a first signal analog-to-digital conversion process; the in-memory calculation process of the second group of calculation submodules includes: a delay process, a second multiplication calculation and charge sampling process, and a second signal analog-to-digital conversion process; the first signal analog-to-digital conversion process of the first group of calculation submodules operates in parallel with the delay process, the second multiplication calculation and charge sampling process of the second group of calculation submodules, and the second signal analog-to-digital conversion process of the second group of calculation submodules operates in parallel with the first multiplication calculation and charge sampling process of the first group of calculation submodules.

[0012] Preferably, the delay time of the delay unit is set based on the time it takes for the analog signal on the first signal line to enter the analog-to-digital converter for analog-to-digital conversion.

[0013] Preferably, the delay time of the delay unit is equal to the time it takes for the analog signal on the first signal line to enter the analog-to-digital converter for analog-to-digital conversion.

[0014] Preferably, the signal accumulation on the summing capacitor is accumulation of charges on the summing capacitor or accumulation of current on the summing capacitor.

[0015] Preferably, after the first group of computing submodules performs multiplication calculation and charge sampling, the obtained product charge is accumulated to the first signal line, the selector is connected to the first signal line and is cut off from the second signal line, and the analog-to-digital converter starts to convert the product charge accumulated on the first signal line into a first digital signal.

[0016] Preferably, in the process of converting the product charge accumulated on the first signal line into the first digital signal, the delayed second group of calculation submodules accumulates the calculated product charge on the second signal line.

[0017] Preferably, after the product charge accumulated on the first signal line is converted into the first digital signal, the selector selects to be turned on with the second signal line and turned off with the first signal line, the first signal line is charged to the VDD potential or reset to the VSS potential, and the analog-to-digital converter starts to convert the product charge accumulated on the second signal line into a second digital signal.

[0018] Preferably, during the process of converting the product charge accumulated on the second signal line into the second digital signal, the input data corresponding to the first group of calculation submodules in the next calculation cycle begins to be connected to the storage and calculation unit, and multiplication calculation and charge sampling are performed.

[0019] Preferably, after the analog-to-digital converter converts the product charge accumulated on the second signal line into a second digital signal, the selector is connected to the first signal line and is cut off from the second signal line, the first signal line is charged to the VDD potential or reset to the VSS potential, and the analog-to-digital converter again converts the product charge accumulated on the first signal line into a first digital signal.

[0020] A processing device comprises the analog in-memory computing circuit described in any one of the above items.

[0021] An electronic device comprises the analog in-memory computing circuit described in any one of the above items.

[0022] Implementing one of the above technical solutions of the utility model has the following advantages or beneficial effects:

[0023] The utility model divides the storage and calculation modules of the same column into at least a first group of calculation submodules and a second group of calculation submodules, and performs the storage calculation operation in time-sharing manner on the first group of calculation submodules and the second group of calculation submodules through a delay unit. Since the voltage variation amplitude of each row of capacitor plates is a least significant bit LSB, and the LSB of the storage and calculation operation is equal to the voltage VDD on the signal line divided by the number of rows X, that is, LSB=VDD / X, when the storage and calculation modules of the same column are grouped, the number of rows X participating in the storage and calculation calculation each time decreases with the grouping of the storage and calculation modules, and the LSB naturally increases. With the increase of LSB, the resolution requirement of the analog-to-digital converter is reduced, and the probability of the analog-to-digital converter conversion error is also reduced, which naturally improves the reliability of the analog-to-digital converter. At the same time, the analog-to-digital converter performs time-sharing selection for the analog-to-digital conversion of the signals of the first group of computing submodules, the second group of computing submodules, etc. Since the data that needs to be converted at the same time is reduced, the number of bits of the analog-to-digital converter is reduced, thereby making the cycle of the analog-to-digital conversion shorter and the power consumption lower. At the same time, since the data converted at the same time is reduced, the fluctuation △V of the analog power supply is also reduced, thereby further improving the conversion reliability of the analog-to-digital converter. In terms of calculation throughput, since the first group of computing submodules, the second group of computing submodules, etc. can be calculated in parallel and will be added after calculation, the calculation input amount of the same calculation cycle is not affected, and the calculation throughput is also not affected, that is, the analog in-memory calculation circuit provided by the utility model can support the situation of large input amount, thereby achieving high throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0025] Figure 1 This is a circuit schematic diagram of an analog in-memory computing circuit according to a first embodiment of the utility model;

[0026] Figure 2 This is a schematic diagram of an analog in-memory computing circuit according to an embodiment of the present invention. Figure 1 ;

[0027] Figure 3 This is a schematic diagram of an analog in-memory computing circuit according to an embodiment of the present invention. Figure 2 ;

[0028] Figure 4It is a schematic diagram comparing the timing of calculation and analog-to-digital conversion of the analog in-memory calculation circuit in the prior art and the first embodiment of the utility model;

[0029] Figure 5 It is a schematic diagram of the neural network accelerator in the second embodiment of the present utility model. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the utility model clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, wherein various exemplary embodiments that may be used to implement the utility model are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods, and devices that are consistent with some aspects of the utility model disclosed as detailed in the attached claims, and other embodiments may also be used, or the embodiments listed herein may be modified in structure and function without departing from the scope and essence of the utility model.

[0031] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", etc. indicate the orientation or position relationship based on the drawings, which is only for the convenience of describing the utility model and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. The terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "multiple" means two or more. The terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to the specific circumstances.

[0032] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below, in which only the parts related to the embodiment of the present invention are shown.

[0033] Embodiment 1:

[0034] like Figure 1-Figure 3As shown, the utility model provides an analog in-memory computing circuit, including M column memory computing modules. Each column memory computing module includes: N row memory computing submodules for computing N input data, a selector (preferably a two-choice selector, Figure 1 MUX in the selector), and an analog-to-digital converter ( Figure 1 The N rows of storage and operation submodules and analog-to-digital converters are connected to the analog power domains AVDD and AVSS to facilitate in-memory calculations. Each row of storage and operation submodules includes: a storage and operation unit for storing and multiplying the stored data with the input data, and a summing capacitor for sensing the change in the product voltage output by the storage and operation unit. One end of the summing capacitor of each row ( Figure 2 The M end in the row is connected to the output end of the storage unit in the row. The N-row storage submodules at least include: a first group of computing submodules containing a number of rows of storage submodules, and a second group of computing submodules containing a number of rows of storage submodules; the total number of rows of storage submodules in the first group of computing submodules is equal to the total number of rows of storage submodules in the second group of computing submodules. The input end of each row of storage units in the first group of computing submodules is connected to the input data, and the other end of the summing capacitor of each row ( Figure 2 The S end in the first group of calculation submodules) are connected to the first signal line to accumulate the signal on the summing capacitor (such as a voltage signal, a current signal, etc.), and the first signal line is connected to the analog-to-digital converter through a selector. In the second group of calculation submodules, the input end of the storage unit in each row is connected to the input data through a delay unit, so that the time when the input data is input into the storage unit in the second group of calculation submodules is later than the time when the input data is input into the storage unit in the first group of calculation submodules, that is, the input data of the first group of calculation submodules and the second group of calculation submodules are different in the storage unit time, and the two are calculated in time sharing, and the other end of the summing capacitor in each row of the second group of calculation submodules is connected to the second signal line to accumulate the signal on the summing capacitor, and the second signal line is connected to the analog-to-digital converter through a selector. The selector is used to connect the first signal line ( Figure 1 SL in), the second signal line ( Figure 1The signal of one of the SR) in the analog-to-digital converter is connected, that is, the first signal line and the second signal line cannot be connected at the same time, so as to obtain the calculation result of the storage and calculation module of the column based on the digital signal output by the analog-to-digital converter. Specifically, the first group of calculation submodules and the second group of calculation submodules will be added together after calculation respectively to obtain the final calculation result of the in-memory calculation, so that the calculation input amount of the same calculation cycle remains unchanged, and the calculation throughput remains unchanged. Since the reliability of the charge domain calculation of the analog in-memory calculation is proportional to the LSB size and inversely proportional to the related power supply fluctuation △V, the calculation throughput is proportional to the amount of input data. The utility model divides the storage and calculation modules of the same column into at least a first group of calculation submodules and a second group of calculation submodules, and uses a delay unit to divide the first group of calculation submodules and the second group of calculation submodules into time-sharing in-memory calculation operations. Since the voltage variation amplitude of each row of capacitor plates is a least significant bit LSB, and the LSB of the in-memory operation is equal to the voltage VDD on the signal line divided by the number of rows X, that is, LSB = VDD / X, when the storage and calculation modules in the same column are grouped, the number of rows X participating in the in-memory calculation each time decreases with the grouping of the storage and calculation modules, and the LSB naturally increases. If the storage and calculation modules in the same column are divided into only the above two groups of calculation submodules, the number of rows participating in the in-memory calculation each time is X / 2, then the calculated LSB is equal to AVDD divided by X divided by 2, that is, LSB = AVDD / X / 2 = 2*AVDD / X, and the LSB becomes twice that of the prior art solution. With the increase of LSB, the resolution requirements for the analog-to-digital converter are reduced, and the probability of the analog-to-digital converter conversion error is also reduced, which naturally improves the reliability of the analog-to-digital converter, and here the conversion reliability of the analog-to-digital converter is improved by 2 times. At the same time, the analog-to-digital converter selects the analog-to-digital conversion of the signals of the first group of computing submodules, the second group of computing submodules, etc. in a time-sharing manner. Since the data that needs to be converted at the same time is reduced, the number of bits of the analog-to-digital converter is reduced, thereby making the cycle of the analog-to-digital conversion shorter and the power consumption lower. At the same time, since the conversion data is reduced at the same time, the fluctuation △V of the analog power supply is also reduced, thereby further improving the conversion reliability of the analog-to-digital converter. Specifically, when the storage and calculation module is divided into only the first group of computing submodules and the second group of computing submodules, since the data that needs to be converted at the same time is halved, the number of bits of the analog-to-digital converter is reduced by one, thereby making the cycle of the analog-to-digital conversion shorter and the power consumption lower. At the same time, since the conversion data is halved at the same time, the fluctuation △V of the analog power supply is also approximately halved, which is equivalent to increasing the conversion reliability of the analog-to-digital converter by 2 times. In terms of calculation throughput, since the first group of computing submodules, the second group of computing submodules, etc. can be calculated in parallel and will be added after calculation, the calculation input amount of the same calculation cycle remains unchanged, and the calculation throughput remains unchanged.

[0035] As an optional implementation, Figure 1 As shown, it also includes a delayed digital power supply connected to the delay unit, the delayed digital power supply ( Figure 1DVDD and DVSS in the delay unit are used to power the delay unit. Powering the delay unit with the delayed digital power supply facilitates turning the delay unit on or off. Turning the delay unit on or off can stagger the time when the storage and calculation units in each row of the storage and calculation submodules in the second group of calculation submodules access input data with the time when the storage and calculation units in the first calculation submodule access input data. Based on the power supply of the delayed digital power supply to the delay unit, the calculations of the first group of calculation submodules and the second group of calculation submodules are staggered and performed alternately, thereby realizing parallel operation of the two calculations.

[0036] As an optional implementation, Figure 1 As shown, the first group of computing submodules is formed by storage and computing submodules located in even-numbered rows, and the number is at least one, that is, Figure 1 In the IN[0], IN[2], ... IN[x-2] rows, they correspond to even-numbered rows. The second group of computing submodules is formed by the storage submodules located in odd-numbered rows, and the number is also at least one, that is, Figure 1 The IN[1], IN[3], ... IN[x-1] rows in the structure correspond to odd-numbered rows. The total number of rows of storage submodules of the first group of computing submodules and the second group of computing submodules are the same, that is, both are X / 2 rows. Therefore, the calculation time of the first group of computing submodules and the second group of computing submodules is basically the same, which facilitates parallel calculation of the first group of computing submodules and the second group of computing submodules, thereby improving the calculation efficiency.

[0037] As an optional implementation, the in-memory calculation process of the first group of calculation submodules includes: a first multiplication calculation and charge sampling process (the first group of calculation submodules perform multiplication calculation and charge sampling process), a first signal analog-to-digital conversion process (the analog signal of the first signal line performs an analog-to-digital conversion process); the in-memory calculation process of the second group of calculation submodules includes: a delay process, a second multiplication calculation and charge sampling process (the second group of calculation submodules perform multiplication calculation and charge sampling process), a second signal analog-to-digital conversion process (the analog signal of the second signal line performs an analog-to-digital conversion process). The multiplication calculation and charge sampling process specifically includes: multiplying the input data with the stored data in the corresponding row storage unit, and reflecting the product to the first plate of the corresponding summing capacitor; after the voltage of the first plate of the summing capacitor is reached, the sampling of the corresponding row charge begins, and the sampled charge is fed back to the second plate of the summing capacitor; the second plate of the summing capacitor accumulates the product charge to the first signal line or the second signal line. Figure 4As shown, the first signal analog-to-digital conversion process of the first group of computing submodules and the delay process, second multiplication calculation and charge sampling process of the second group of computing submodules are operated in parallel (i.e., calculation clock 1 and calculation clock 3), and the second signal analog-to-digital conversion process of the second group of computing submodules and the first multiplication calculation and charge sampling process of the first group of computing submodules are operated in parallel (i.e., calculation clock 2 and calculation clock 4). Parallel operation means that both are executed independently at the same time without any sequence, thereby saving the entire in-memory computing time. The delay time of the delay unit is set based on the time when the analog signal on the first signal line enters the analog-to-digital converter for analog-to-digital conversion, such as being equal to or approximately equal to (the delay time is slightly longer or shorter than the time when the analog signal on the first signal line enters the analog-to-digital converter for analog-to-digital conversion, which is set according to actual usage) the time when the analog signal on the first signal line enters the analog-to-digital converter for analog-to-digital conversion. Through parallel execution, it is ensured that the calculation cycle of the group calculation remains basically unchanged, and the calculation throughput remains high after the calculation reliability is greatly improved. Highly parallel operations greatly improve computing efficiency, make up for the delay caused by performing separate calculations on odd and even row groups, and ensure that the computing clock and computing throughput remain unchanged.

[0038] As an optional implementation, the signal accumulation on the summing capacitor is to accumulate the charge on the summing capacitor or to accumulate the current on the summing capacitor. Charge accumulation and current accumulation can be performed through the first signal line and the second signal line. Of course, voltage accumulation can also be selected, thereby improving the adaptability of the utility model.

[0039] As an optional implementation, in the storage and calculation module, the power supply for the storage and calculation module to perform calculations, the power supply for the summing capacitor to perform sampling, and the power supply for the first signal line and the second signal line to perform charge accumulation are all digital power supplies. Since the flip fluctuation of the digital power supply will not affect the fluctuation of the analog power supply domain of the storage and calculation module and the analog-to-digital converter, the voltage fluctuation of the analog power supply related to the charge calculation can be reduced, further improving the reliability of the charge calculation of the utility model.

[0040] As an optional implementation, Figure 1 As shown, it also includes a charging reset circuit; the charging reset circuit is connected to the first signal line and the second signal line, and is used to charge the first signal line and the second signal line to the VDD potential or reset them to the VSS potential, and prepare the charges on the first signal line and the second signal line before calculation, so that the charge accumulation on the first signal line and the second signal line will not be wrong. The charging reset circuit can prevent the residual charges on the first signal line and the second signal line from affecting the accuracy of the calculation results in the memory.

[0041] As an optional implementation, Figure 4As shown, the parallel execution process of the utility model is mainly described as follows. After the first group of calculation submodules performs multiplication calculation and charge sampling, the obtained product charge is accumulated to the first signal line, the selector is connected to the first signal line and cut off from the second signal line, and the analog-to-digital converter begins to convert the accumulated product charge on the first signal line into a first digital signal. In the process of converting the accumulated product charge on the first signal line into the first digital signal, the delayed second group of calculation submodules accumulates the calculated product charge on the second signal line. After the accumulated product charge on the first signal line is converted into the first digital signal, the selector selects to be connected to the second signal line and cut off from the first signal line, the first signal line is charged to the VDD potential or reset to the VSS potential, and the analog-to-digital converter begins to convert the accumulated product charge on the second signal line into a second digital signal. In the process of converting the accumulated product charge on the second signal line into the second digital signal, the input data corresponding to the first group of calculation submodules in the next calculation cycle begins to be connected to the storage unit, and multiplication calculation and charge sampling are performed. After the analog-to-digital converter converts the product charge accumulated on the second signal line into a second digital signal, the selector is turned on with the first signal line and turned off with the second signal line, the first signal line is charged to the VDD potential or reset to the VSS potential, and the analog-to-digital converter converts the product charge accumulated on the first signal line into the first digital signal again. By analogy, the operation logic of the circuit of the utility model is obtained by repeating the cycle. Therefore, the utility model divides the analog memory calculation process into 4 parallel and alternating timings: the first multiplication calculation and charge sampling process, the first signal analog-to-digital conversion process, the second multiplication calculation and charge sampling process, and the second signal analog-to-digital conversion process. Among them, the first multiplication calculation and charge sampling process and the second multiplication calculation and charge sampling process are parallel, and the first signal analog-to-digital conversion process and the second signal analog-to-digital conversion process are performed alternately. The calculation effect of this innovative timing of the utility model is higher, which makes up for the calculation time increment of the alternating conversion in the first signal analog-to-digital conversion process and the second signal analog-to-digital conversion process. Furthermore, since the array time-sharing calculation reduces the amount of calculation, the calculation speed of the multi-bit analog-to-digital converter is improved, and the calculation power consumption is reduced.

[0042] The embodiment is only a special case and does not indicate that the present invention is implemented in such a way.

[0043] Embodiment 2:

[0044] A processing device includes the simulated in-memory calculation circuit in embodiment 1. Through the simulated in-memory calculation circuit in embodiment 1, the utility model divides the storage and calculation modules of the same column into at least a first group of calculation submodules and a second group of calculation submodules, and performs in-memory calculation operations on the first group of calculation submodules and the second group of calculation submodules in time-sharing through a delay unit. Since the voltage variation amplitude of each row of capacitor plates is a least significant bit LSB, and the LSB of the in-memory operation is equal to the voltage VDD on the signal line divided by the number of rows X, that is, LSB=VDD / X, when the storage and calculation modules of the same column are grouped, the number of rows X participating in the in-memory calculation each time decreases with the grouping of the storage and calculation modules, and the LSB naturally increases. With the increase of LSB, the resolution requirement of the analog-to-digital converter is reduced, and the probability of the analog-to-digital converter conversion error is also reduced, which naturally improves the reliability of the analog-to-digital converter. At the same time, the analog-to-digital converter performs time-sharing selection for the analog-to-digital conversion of the signals of the first group of computing submodules, the second group of computing submodules, etc. Since the data that needs to be converted at the same time is reduced, the number of bits of the analog-to-digital converter is reduced, thereby making the cycle of the analog-to-digital conversion shorter and the power consumption lower. At the same time, since the data converted at the same time is reduced, the fluctuation △V of the analog power supply is also reduced, thereby further improving the conversion reliability of the analog-to-digital converter. In terms of calculation throughput, since the first group of computing submodules, the second group of computing submodules, etc. can be calculated in parallel and will be added after calculation, the calculation input amount of the same calculation cycle is not affected, and the calculation throughput is also not affected, that is, the analog in-memory calculation circuit provided by the utility model can support the situation of large input amount, thereby achieving high throughput.

[0045] The processing device of the present invention may be a chip, or an IP core (a circuit module with independent functions, which may be applied to other chip design projects including the circuit module).

[0046] The processing device provided by the present invention may be, for example, a neural network accelerator (i.e., NPU, such as Figure 5

[0047] As shown, the NPU includes functional modules such as an in-memory computing matrix, a vector processor, a compiler, etc., which are used to perform neural network calculations), or various devices such as a speech recognition device including a neural network accelerator, a video processing device including a neural network accelerator, and a large model processing device. When the processing device is a chip, each module in the chip can be implemented in whole or in part by software, hardware, and a combination thereof. The above modules can be embedded in or independent of the processor in the computing device in the form of hardware, or can be stored in the memory of the computing device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0048] The utility model can be applied to fields requiring high-precision, high-reliability, low-power consumption, and low-area-cost computing power, such as artificial intelligence and metaverse that are suitable for analog in-memory computing chips, artificial intelligence training or reasoning chip products, autonomous driving chips, VR chips, robot built-in chips, wearable smart chips, and deep learning applications of parallel computing.

[0049] Embodiment three:

[0050] An electronic device includes the analog in-memory computing circuit in the first embodiment. The utility model can be applied to electronic devices related to computing centers, computing devices, edge computing, autonomous driving, AR, VR, laser radar, etc., as well as a series of electronic devices such as smart phones, tablet computers, wearable electronic equipment, smart home electronic products, industrial or medical or battery-powered devices.

[0051] The above description is only the preferred embodiment of the present invention. Those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the guidance of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present invention.

Claims

1. An analog in-memory computing circuit, comprising M columns of memory computing modules, characterized in that: Each column storage and calculation module includes: N row storage and calculation submodules for calculating N input data, a selector, and an analog-to-digital converter for converting an analog signal output by the selector into a digital signal; Each row of storage and calculation submodules includes: a storage and calculation unit for storing and performing multiplication operation on the stored data and the input data, and a summing capacitor for sensing the change of the product voltage output by the storage and calculation unit, and one end of the summing capacitor of each row is connected to the output end of the storage and calculation unit of the row; The N row storage operator modules at least include: a first group of computing submodules including a plurality of row storage operator modules, and a second group of computing submodules including a plurality of row storage operator modules, wherein the total number of rows of the storage operator modules of the first group of computing submodules is equal to the total number of rows of the storage operator modules of the second group of computing submodules; The input end of each row of the storage and calculation units in the first group of calculation submodules is connected to the input data, and the other end of the summing capacitor in each row is connected to the first signal line to accumulate the signal on the summing capacitor, and the first signal line is connected to the analog-to-digital converter through the selector; in the second group of calculation submodules, the input end of each row of the storage and calculation units is connected to the input data through the delay unit, so that the time when the input data is input into the storage and calculation units in the second group of calculation submodules is later than the time when the input data is input into the storage and calculation units in the first group of calculation submodules, and the other end of the summing capacitor in each row of the second group of calculation submodules is connected to the second signal line to accumulate the signal on the summing capacitor, and the second signal line is connected to the analog-to-digital converter through the selector; The selector is used to connect the signal of one of the first signal line and the second signal line to the analog-to-digital converter, so as to obtain the calculation result of the column storage and calculation module based on the digital signal output by the analog-to-digital converter.

2. The analog in-memory computing circuit according to claim 1, characterized in that: It also includes a delayed digital power supply connected to the delay unit, and the delayed digital power supply is used to supply power to the delay unit.

3. The analog in-memory computing circuit according to claim 1 or 2, characterized in that: The first group of computing submodules is formed by storage-operation submodules located in even-numbered rows, and the second group of computing submodules is formed by storage-operation submodules located in odd-numbered rows.

4. The analog in-memory computing circuit according to claim 1, characterized in that: The in-memory calculation process of the first group of calculation submodules includes: a first multiplication calculation and charge sampling process, and a first signal analog-to-digital conversion process; the in-memory calculation process of the second group of calculation submodules includes: a delay process, a second multiplication calculation and charge sampling process, and a second signal analog-to-digital conversion process; the first signal analog-to-digital conversion process of the first group of calculation submodules is operated in parallel with the delay process, the second multiplication calculation and charge sampling process of the second group of calculation submodules, and the second signal analog-to-digital conversion process of the second group of calculation submodules is operated in parallel with the first multiplication calculation and charge sampling process of the first group of calculation submodules.

5. The analog in-memory computing circuit according to claim 4, characterized in that: The delay time of the delay unit is set based on the time when the analog signal on the first signal line enters the analog-to-digital converter for analog-to-digital conversion.

6. The analog in-memory computing circuit according to claim 5, characterized in that: The delay time of the delay unit is equal to the time it takes for the analog signal on the first signal line to enter the analog-to-digital converter for analog-to-digital conversion.

7. The analog in-memory computing circuit according to claim 1, characterized in that: The signal accumulation on the summing capacitor is accumulation of charges on the summing capacitor or accumulation of current on the summing capacitor.

8. The analog in-memory computing circuit according to claim 1, characterized in that: After the first group of computing submodules performs multiplication calculation and charge sampling, the obtained product charge is accumulated to the first signal line, the selector is connected to the first signal line and is cut off from the second signal line, and the analog-to-digital converter converts the accumulated product charge on the first signal line into a first digital signal.

9. The analog in-memory computing circuit according to claim 8, characterized in that: In the process of converting the product charge accumulated on the first signal line into the first digital signal, the delayed second group of calculation submodules accumulates the calculated product charge on the second signal line.

10. The analog in-memory computing circuit according to claim 9, characterized in that: After the product charge accumulated on the first signal line is converted into the first digital signal, the selector selects to be connected to the second signal line and to be cut off from the first signal line, the first signal line is charged to the VDD potential or reset to the VSS potential, and the analog-to-digital converter starts to convert the product charge accumulated on the second signal line into the second digital signal.

11. The analog in-memory computing circuit according to claim 10, characterized in that: During the process of converting the accumulated product charge on the second signal line into a second digital signal, the input data corresponding to the first group of calculation submodules in the next calculation cycle begins to be connected to the storage and calculation unit, and multiplication calculation and charge sampling are performed.

12. The analog in-memory computing circuit according to claim 11, characterized in that: After the analog-to-digital converter converts the product charge accumulated on the second signal line into a second digital signal, the selector is connected to the first signal line and is cut off from the second signal line, the first signal line is charged to the VDD potential or reset to the VSS potential, and the analog-to-digital converter again converts the product charge accumulated on the first signal line into a first digital signal.

13. A processing device, characterized in that: The analog in-memory computing circuit comprises any one of claims 1-12.

14. An electronic device, characterized in that: The analog in-memory computing circuit comprises any one of claims 1-12.

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