Quantum dot light-emitting device on silicon substrate with high electro-optical coupling efficiency

Abstract

The utility model discloses a high electro-optical coupling efficiency quantum dot light-emitting device on a silicon substrate. The device comprises a silicon substrate, a first transparent insulating layer, a silicon nitride waveguide layer, a first electrode layer, a hole transport layer, a quantum dot layer, an electron transport layer and a second electrode layer which are connected in sequence. The second transparent insulating layer surrounds the silicon nitride waveguide layer, the first electrode layer, the hole transport layer, the quantum dot layer and the electron transport layer; a part of the first electrode layer is exposed through a first groove in the second transparent insulating layer; the thickness of the first electrode layer is 100-200 nm; the thickness of the second electrode layer is 100 to 200 nm; the thickness of the hole transport layer is 40-100 nm; the thickness of the electron transport layer is 20-80 nm, and the thickness of the quantum dot layer is 10-30 nm. The first electrode layer, the hole transport layer, the electron transport layer and the second electrode layer are arranged on the two sides of the quantum dot layer respectively, the thickness of each layer of the device is optimized, more light energy can enter the silicon nitride waveguide layer, the light emitting rate is increased, and therefore the efficient silicon substrate light source is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of light sources on silicon substrates, in particular to a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency. Background Art

[0002] With the development of photonic integration technology, how to achieve an effective light source has become the key to breaking through the technical bottleneck. As the core component of silicon photonic chips, light sources can be divided into on-chip light sources and off-chip light sources. On-chip light sources avoid off-chip coupling losses, achieve high-density integration, and perform better in terms of energy efficiency. However, since silicon is an indirect semiconductor and has low luminous efficiency, it is difficult to directly use silicon materials to prepare on-chip light sources. Therefore, efficient light emission directly on silicon wafers is the key to breaking through the bottleneck of light sources on silicon wafers. Quantum dot light-emitting diodes (QLED) devices emit light through electrical drive, which can meet the application requirements of ultra-thin, flexible, high color gamut, and high contrast. However, existing QLEDs usually emit light from a transparent glass substrate, and the average coupling efficiency is low. According to the relevant data reported, the average coupling efficiency of the device can only reach 0.8% at most, and the output power of QLED can only reach about 2nW. Utility Model Content

[0003] The technical problem to be solved by the present invention is to provide a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency in view of at least one defect of the above-mentioned background technology.

[0004] The technical solution adopted by the utility model to solve the technical problem is: to provide a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency, which includes a silicon substrate, a first transparent insulating layer, a silicon nitride waveguide layer, a first electrode layer, a hole transport layer, a quantum dot layer, an electron transport layer, a second electrode layer, and a second transparent insulating layer;

[0005] The silicon substrate, the first transparent insulating layer, the silicon nitride waveguide layer, the first electrode layer, the hole transport layer, the quantum dot layer, the electron transport layer, and the second electrode layer are connected in sequence; the second transparent insulating layer is connected to the first transparent insulating layer and surrounds the silicon nitride waveguide layer, the first electrode layer, the hole transport layer, the quantum dot layer, and the electron transport layer;

[0006] At least one first groove is provided on the second transparent insulating layer, and a portion of the first electrode layer is exposed through the first groove;

[0007] Among them, the thickness of the first electrode layer is 100-200nm; the thickness of the second electrode layer is 100-200nm; the thickness of the hole transport layer is 40-100nm; the thickness of the electron transport layer is 20-80nm, and the thickness of the quantum dot layer is 10-30nm.

[0008] Preferably, a cross-sectional area of ​​the silicon nitride waveguide layer is smaller than a cross-sectional area of ​​the first transparent insulating layer.

[0009] Preferably, the cross-sectional area of ​​the first electrode layer is smaller than the cross-sectional area of ​​the silicon nitride waveguide layer.

[0010] Preferably, the cross-sectional areas of the hole transport layer, the quantum dot layer, the electron transport layer and the second electrode layer are equal, and the cross-sectional area of ​​the hole transport layer is smaller than the cross-sectional area of ​​the first electrode layer.

[0011] Preferably, a long axis of the first electrode layer is perpendicular to a long axis of the silicon nitride waveguide layer.

[0012] Preferably, the thickness of the first electrode layer is 100 nm.

[0013] Preferably, the thickness of the second electrode layer is 100 nm.

[0014] Preferably, the hole transport layer includes a first transport layer and a second transport layer, the first transport layer is connected to the first electrode layer, the second transport layer is connected to the quantum dot layer, the thickness of the first transport layer is 90 nm, and the thickness of the second transport layer is 30 nm.

[0015] Preferably, the thickness of the electron transport layer is 50 nm.

[0016] Preferably, the thickness of the quantum dot layer is 20 nm.

[0017] The utility model has at least the following beneficial effects: the quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency of the utility model arranges the first electrode layer, the hole transport layer, the electron transport layer, and the second electrode layer on both sides of the quantum dot layer, respectively, couples the light source generated at the quantum dot layer with the silicon nitride waveguide layer, and optimizes the thickness of each layer of the device, so that more light energy can enter the silicon nitride waveguide layer, increasing the light output rate, thereby realizing an efficient silicon substrate light source. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution of the utility model, the utility model will be further described below in conjunction with the accompanying drawings and embodiments, in which:

[0019] Figure 1 It is a schematic diagram of the three-dimensional structure of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to an embodiment of the utility model;

[0020] Figure 2 yes Figure 1 A schematic diagram of the vertical cross-sectional structure of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency is shown;

[0021] Figure 3 This is an energy band diagram of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to an embodiment of the utility model;

[0022] Figure 4 This is a curve diagram showing the relationship between the quantum dot layer thickness and the coupling efficiency of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to an embodiment of the utility model;

[0023] Figure 5 This is a curve diagram showing the relationship between the thickness of the first transport layer of the hole transport layer of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency and the coupling efficiency of an embodiment of the utility model;

[0024] Figure 6 This is a curve diagram showing the relationship between the thickness of the second transport layer of the hole transport layer of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency and the coupling efficiency of an embodiment of the utility model;

[0025] Figure 7 This is a curve diagram showing the relationship between the thickness of the electron transport layer and the coupling efficiency of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to an embodiment of the utility model;

[0026] Figure 8 This is an EL spectrum diagram of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to an embodiment of the utility model;

[0027] Fig. 9 This is a schematic diagram of the position distribution of some structural layers along the thickness direction of a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to an embodiment of the utility model;

[0028] Fig.10 yes Fig. 9 A graph showing the relationship between the recombination rate of the device of the corresponding embodiment and the position of the device;

[0029] Fig.11 yes Fig. 9 A curve diagram showing the relationship between the charge density of the device and the position of the device of the corresponding embodiment;

[0030] Fig.12 yes Fig. 9 A curve diagram showing the relationship between the coupling efficiency of the device of the corresponding embodiment and the current density of the device;

[0031] Fig.13 yes Fig. 9 A curve diagram showing the relationship between the current density of the device of the corresponding embodiment and the operating voltage of the device;

[0032] Fig.14It is a schematic diagram of the process of a method for preparing a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to an embodiment of the utility model. DETAILED DESCRIPTION

[0033] In order to have a clearer understanding of the technical features, purposes and effects of the present utility model, the specific implementation methods of the present utility model are now described in detail with reference to the accompanying drawings.

[0034] In the following description, it is to be understood that when an element is referred to as being "on" or "under" another element, the element can be "directly" or "indirectly" located on the other element, or there may be one or more intervening elements. The terms "first", "second", "third", etc. are only used to facilitate the description of the present technical solution, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", "third", etc. may explicitly or implicitly include one or more of the features. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to the specific circumstances.

[0035] like Figure 1 to Figure 2 As shown, in a naturally placed state, a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency (hereinafter referred to as the device for ease of explanation) of an embodiment of the utility model includes a silicon (Si) substrate, a silicon nitride (SiN) waveguide layer, a first electrode layer 31, a hole transport layer 41, a quantum dot layer 5, an electron transport layer 42, and a second electrode layer 32 connected in sequence from bottom to top. That is, the first electrode layer 31, the hole transport layer 41 and the electron transport layer 42, and the second electrode layer 32 are respectively located on both sides of the quantum dot layer 5. The device also includes a second transparent insulating layer 62, which is connected to the first transparent insulating layer 61 and surrounds the silicon nitride waveguide layer 2, the first electrode layer 31, the hole transport layer 41, the quantum dot layer 5, and the electron transport layer 42. The second electrode layer 32 is exposed above the second transparent insulating layer 62. At least one first groove 621 is provided on the second transparent insulating layer 62, and a portion of the upper surface of the first electrode layer 31 is exposed through the first groove 621. Thus. The first electrode layer 31 and the second electrode layer 32 are respectively exposed to the outside to form electrical interconnection. The number of the first grooves 621 can be one or two or more. Figures 1 to 3 As shown, in some embodiments, the hole transport layer 41 may be a double hole transport layer, which includes a first transport layer 411 and a second transport layer 412, and the materials of the first transport layer 411 and the second transport layer 412 are different. The use of two transport layers of different materials can increase the hole transport efficiency. In some other embodiments, the hole transport layer 41 may also be a single hole transport layer.

[0036] Further, the materials of each structural layer can be set as follows: the material of the electron transport layer 42 includes at least one of magnesium-doped zinc oxide nanoparticles (ZnMgO), tin oxide (SnO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), and zinc oxide (ZnO). That is, the material of the electron transport layer 42 can include one or more of the above materials. The material of the hole transport layer 41 includes at least one of poly[(9,9-dioctylfluorene-2,7-diyl)-co-(4,4′-(N-(4-sec-butylphenyl)diphenylamine)] (TFB), poly(3,4-ethylenedioxythiophene)-polystyrenesulfonic acid (PEDOT:PSS), poly[bis(4-phenyl)(4-butylphenyl)amine] (Poly-TPD), 4,4-di(9-carbazole)biphenyl (CBP), 4,4′,4′-tri(carbazole-9-yl)triphenylamine (TCTA), and polyvinylcarbazole (PVK). The material of the first electrode layer 31 includes metals Al, Ag, Au, and I The material of the second electrode layer 32 includes one of metal Al, Ag, Au and ITO transparent electrodes. The material of the quantum dot layer 5 includes one of lead sulfide (PbS), cadmium sulfide (CdS), zinc telluride (ZnTe), gallium arsenide (GaAs), perovskite materials (including CsPbI3, MAPbI3, MAPbBr3, etc.). The material of the first transparent insulating layer 61 and the second transparent insulating layer 62 may include one of silicon dioxide, polymethyl methacrylate (PMMA), polydimethylsiloxane (PDMS), polystyrene (PS), and polycarbonate (PC).

[0037] See also Figure 3 , Figure 3 The energy band diagram of the device of an embodiment of the utility model is shown, which includes, from left to right, the first electrode layer 31, the hole transport layer 41, the quantum dot layer 5, the electron transport layer 42, and the second electrode layer 32. In this embodiment, the first electrode layer 31 is an ITO transparent electrode. The hole transport layer 41 is a double hole transport layer, which includes a first transport layer 411 and a second transport layer 412. The quantum dot layer 5 is referred to as QDs, the electron transport layer 42 is zinc oxide (ZnO), and the second electrode layer 32 is metal Al. Under the condition of power on, electrons and holes converge in the quantum dot layer 5, and after radiation recombination, photons are generated and transmitted toward the silicon nitride waveguide layer 2, increasing the light extraction rate, thereby realizing an efficient silicon-based on-chip light source.

[0038] See also Figures 4 to 7 , Figures 4 to 7The effect of the thickness of several different structural layers in the devices of some embodiments of the utility model on the coupling efficiency of the device is shown. In this embodiment, poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid (PEDOT:PSS) is used as the first transport layer 411 of the hole transport layer 41, poly[(9,9-dioctylfluorene-2,7-diyl)-co-(4,4′-(N-(4-sec-butylphenyl)diphenylamine)] (TFB) is used as the second transport layer 412 of the hole transport layer 41, and zinc oxide (ZnO) is used as the electron transport layer 42. Figure 4 It shows that when the thickness of the quantum dot layer 5 (QDs) is 10-50 nm, the coupling efficiency of the device can reach a minimum of 6.58%. In order to obtain a greater coupling efficiency, the thickness of the quantum dot layer 5 can be selected to be 10-30 nm. Figure 5 It shows that when the thickness of the first transport layer 411 (PEDOT:PSS) of the hole transport layer 41 is 20-120 nm, the coupling efficiency of the device can reach 8.10% at the minimum. In order to obtain a higher coupling efficiency, the thickness of the first transport layer 411 of the hole transport layer 41 can be selected to be 40-100 nm. Figure 6 It shows that when the thickness of the second transport layer 412 of the hole transport layer (TFB) is 20-100 nm, the coupling efficiency of the device can reach a minimum of 7.89%. In order to obtain a higher coupling efficiency, the thickness of the second transport layer 412 of the hole transport layer can be selected to be 20-80 nm. Figure 7 It shows that when the thickness of the electron transport layer 42 (ZnO) is 10-80 nm, the coupling efficiency of the device can reach a minimum of 3.74%. In order to obtain a greater coupling efficiency, the thickness of the electron transport layer 42 can be selected to be 20-80 nm.

[0039] Therefore, in some embodiments of the present invention, the thickness of some of the structural layers is set to: the thickness of the first electrode layer 31 is 100 to 200 nm. The thickness of the second electrode layer 32 is 100 to 200 nm. The thickness of the first transport layer 411 of the hole transport layer 41 is 40 to 100 nm. The thickness of the second transport layer 412 of the hole transport layer 41 is 20 to 80 nm. The thickness of the electron transport layer 42 is 20 to 80 nm. The thickness of the quantum dot layer 5 is 10 to 30 nm. Within this thickness range, the device can obtain a larger electro-optical coupling efficiency and realize an efficient light source on a silicon substrate.

[0040] See also Figures 4 to 7, the thickness of several different structural layers in the device shows the effect on the coupling efficiency of the device, among which the minimum electro-optical coupling efficiency can reach 3.74%. Compared with the reported relevant data (average coupling efficiency 0.8%), the coupling efficiency of the device of the utility model has been significantly improved by at least one order of magnitude, which shows that coupling the light source with the silicon nitride waveguide can achieve more efficient output of light energy, effectively increase the light output rate, and thus realize an efficient silicon-based on-chip light source.

[0041] In summary, the quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency of the utility model arranges the first electrode layer 31, the hole transport layer 41, the electron transport layer 42, and the second electrode layer 32 on both sides of the quantum dot layer 5, respectively, couples the light source generated at the quantum dot layer 5 with the silicon nitride waveguide layer 2, and optimizes the thickness of each layer of the device, so that more light energy can enter the silicon nitride waveguide layer 2, increase the light output rate, and thus realize a high-efficiency silicon-based light source.

[0042] See also Figures 4 to 7 , Figure 4 In the figure, when the thickness of quantum dot layer 5 (QDs) is 20 nm, the coupling efficiency of the device reaches a maximum value of 8.76%; Figure 5 In the embodiment, when the thickness of the first transport layer 411 (PEDOT:PSS) of the hole transport layer 41 is 90 nm, the coupling efficiency of the device can reach a maximum value of 9.00%; Figure 6 In the embodiment, when the thickness of the second transport layer 412 (TFB) of the hole transport layer 41 is 30 nm, the coupling efficiency of the device can reach a maximum value of 8.76%; Figure 7 In the embodiment, ZnO is used as the electron transport layer 42, and when its thickness is 50 nm, the coupling efficiency of the device can reach a maximum value of 8.85%. Therefore, after the electro-optical coupling optimization, the maximum coupling efficiency of the device is improved, and the light extraction rate is effectively increased, thereby realizing an efficient light source on a silicon wafer.

[0043] See also Figure 8 , Figure 8 This is an EL spectrum diagram of a device of an embodiment of the utility model. The horizontal axis represents the wavelength of the emitted light, and the vertical axis represents the electroluminescent intensity of the device. There are 11 lines from bottom to top corresponding to 11 different operating voltages (0V to 10V). Figure 8 It can be seen that the EL spectrum of the exciton after the recombination of the present invention shows that the wavelength of the light emitted by the device is basically maintained at 639nm, and the electroluminescence intensity gradually increases with the increase of the operating voltage.

[0044] See also Fig. 9 and Fig.10 , Fig. 9 It is a schematic diagram of the position distribution of each structural layer along the thickness direction of the device in one embodiment of the utility model. Fig.10 yes Fig. 9 The relationship curve of the recombination rate of the device of the embodiment shown changes with the position of the device. In this embodiment, the structural layers of the device from bottom to top are: silicon substrate 1, silicon nitride (SiN) waveguide layer (thickness 300nm), first electrode layer 31 (material is ITO, thickness is 100nm), hole transport layer 41 (composed of 30nm thick PEDOT:PSS layer superimposed with 30nm thick TFB layer), quantum dot layer 5 (thickness is 20nm), electron transport layer 42 (material is ZnO, thickness is 35nm), second electrode layer 32 (material is Al, thickness is 100nm). In this embodiment, the lower surface of the PEDOT:PSS layer is taken as the origin, Fig. 9 The vertical coordinate x-axis corresponds to Fig.10 The horizontal axis in (the position of the device, that is, the position of each structural layer along its thickness direction). That is, Fig.10 The interval of 50 to 60 nm of the abscissa corresponds to the second transport layer 412 (made of TFB) of the hole transport layer 41. Fig.10 The interval between 60 and 80 nm of the horizontal axis corresponds to the quantum dot layer 5 (thickness is 20 nm). Fig.10 The interval of 80 to 115 nm on the abscissa corresponds to the electron transport layer 42 (the material is ZnO and the thickness is 35 nm). Fig.10 The ordinate in the figure is the recombination rate of the device. According to the distribution of the recombination rate, there is a peak value of 1.84×10 25 cm 3 / s recombination peak, after recombination, the generated photons are transmitted toward the silicon nitride waveguide layer 2 at the bottom.

[0045] See also Fig.11 , Fig.11 yes Fig. 9 and Fig.10 A graph showing the relationship between the charge density of the device of the embodiment shown and the position of the device, Fig.11 The meaning of the horizontal axis "device position" can be referred to above. Fig.10 Meaning of the horizontal axis. According to the distribution of the charge density, holes are injected from the hole transport layer 41 (TFB layer) side, and electrons are injected from the electron transport layer 42 (ZnO layer) side. The peak value of the electron density is located at the junction of the TFB layer and the quantum dot layer 5, which is closer to the underlying silicon nitride waveguide layer 2 than other positions on the quantum dot layer 5.

[0046] At the same time, by Fig.12 It can be seen that the coupling efficiency of the device is affected by the current density. When the current density is close to 0, the coupling efficiency reaches a maximum value of 8.23%, and decreases as the current density continues to increase. Fig.13It can be seen that when the applied voltage is 8V, the current density of the device is 409mA / cm 2 .

[0047] like Figure 1 and Figure 2 In the illustrated embodiment, the cross section of the silicon nitride waveguide layer 2 is rectangular, the cross section area of ​​the silicon nitride waveguide layer 2 is smaller than the cross section area of ​​the first transparent insulating layer, and the silicon nitride waveguide layer 2 is substantially strip-shaped and has a length direction. The cross section area of ​​the component described below refers to the area of ​​its cross section in the horizontal direction. The horizontal direction may refer to a direction parallel to the device placement surface, which refers to the placement surface where the device is placed in a natural placement state. The vertical direction is parallel to the horizontal direction.

[0048] like Figure 1 and Figure 2 In the illustrated embodiment, the first electrode layer 31 is roughly in the shape of a long strip. The cross section of the first electrode layer 31 is also rectangular. The first electrode layer 31 is arranged above the silicon nitride waveguide layer 2 and corresponds to the middle area of ​​the silicon nitride waveguide layer 2. The cross-sectional area of ​​the first electrode layer 31 is smaller than the cross-sectional area of ​​the silicon nitride waveguide layer 2. In other embodiments not shown in the figure, the first electrode layer 31 may also be in other shapes, and the utility model is not limited to this. From bottom to top, the cross-sectional areas of the hole transport layer 41, the quantum dot layer 5, the electron transport layer 42 and the second electrode layer 32 are equal, and the cross sections of the hole transport layer 41, the quantum dot layer 5, the electron transport layer 42 and the second electrode layer 32 are all square. The cross-sectional area of ​​the hole transport layer 41 is smaller than the cross-sectional area of ​​the first electrode layer 31, and the hole transport layer 41 is arranged above the first electrode layer 31 at a position corresponding to the middle area of ​​the first electrode layer 31. In addition, the hole transport layer 41 is flush with the two side edges of the first electrode layer 31 in the horizontal direction, that is, the side length of the hole transport layer 41 is equal to the width of the first electrode layer 31. In other embodiments not shown in the figure, the cross-sectional shape and area of ​​the hole transport layer 41, the quantum dot layer 5, the electron transport layer 42 and the second electrode layer 32 can be adjusted and changed, and the utility model does not limit this. The cross-sectional area of ​​the hole transport layer 41, the quantum dot layer 5, the electron transport layer 42 and the second electrode layer 32 needs to be smaller than the cross-sectional area of ​​the silicon nitride waveguide layer 2.

[0049] like Figure 1 and Figure 2 In the illustrated embodiment, the long axis (the axis along the length direction) of the first electrode layer 31 is perpendicular to the long axis (the axis along the length direction) of the silicon nitride waveguide layer 2 .

[0050] like Figure 1 and Figure 2In the illustrated embodiment, the number of the first groove 621 is one. However, in other embodiments, the number of the first groove 621 may also be two, and the two first grooves 621 may be symmetrically arranged on opposite sides of the second electrode layer 32 .

[0051] Please also read Fig.14 The following is a method for preparing a quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to a specific embodiment of the utility model. In this embodiment, the structural layers of the device from bottom to top are: silicon substrate 1, silicon nitride waveguide layer (SiN, thickness 300nm), ITO electrode layer (thickness 100nm), hole transport layer 41 (composed of a 30nm thick PEDOT:PSS layer superimposed with a 30nm thick TFB layer), quantum dot layer 5 (thickness 20nm), electron transport layer 42 (material is ZnO, thickness 35nm), and metal Al electrode layer (thickness 100nm).

[0052] S1, when the high energy electron beam acceleration voltage is 10 kV, the electron beam current is about 10-100 mA, the beam spot diameter is about 3 mm, and the background vacuum of the evaporation chamber is 8×10 -4 Under the condition that the distance between the substrate and the crucible is 8 cm, a SiO2 film with a thickness of 300 nm is evaporated on the silicon substrate 1. The SiO2 film is used as the first transparent insulating layer 61.

[0053] S21, under the conditions of pressure of 170 Pa, temperature of 450° C., total gas flow of 4320 sccm, volume ratio V(NH3):V(SiH4)=10:1, and deposition rate of 6.25 nm / min, a 300 nm thick silicon nitride film is deposited on the first transparent insulating layer 61. The silicon nitride film serves as the silicon nitride waveguide base layer 21.

[0054] S22, wet etching is performed on the silicon nitride waveguide substrate 21 using photoresist AZ4620 as a mask. Specifically, a layer of AZ4620 photoresist with a thickness of 5.6 μm is spin-coated on the silicon nitride waveguide substrate 21 at a low speed of 500 r / min, a time of 6 seconds, a high speed of 4000 r / min, a time of 30 seconds, a pre-baking temperature of 95°C, and a time of 3 minutes, and the thickness uniformity is tested with a step profiler. The exposure dose is about 60 mJ, the volume ratio of the developer is V(AZ400K):V(H2O)=1:3, the development is performed at room temperature for 60 seconds, the post-baking temperature is 115°C, the time is 10 minutes, and the exposure and development are terminated. A saturated solution of NH4F is prepared at room temperature, and the etching solution with a volume ratio of V(HF):V(NH4F):V(CH3COOH)=1:5:1 is prepared and placed in a plastic container. During the etching process, a constant temperature magnetic stirrer was used to heat the plastic container at a rotation speed of 650 r / min; a partial edge area of ​​the silicon nitride waveguide base layer 21 was etched at an etching temperature of 60°C and an etching rate of 109.5 nm / min, and finally a long strip of silicon nitride waveguide layer 2 with a cross-sectional size of 300×1000 nm was obtained.

[0055] S3, when the high energy electron beam acceleration voltage is 6 kV and the background vacuum of the evaporation chamber is 8 × 10 -4 Pa, the cavity temperature is 300°C, the volume ratio V(ln2O3):V(SnO2)=9:1, the flow rate of oxygen is 2.2sccm, and the deposition rate is 0.15nm / s. An ITO electrode with a thickness of 100nm is deposited on the upper surface of the silicon nitride waveguide layer 2, and the ITO electrode serves as the first electrode layer 31.

[0056] S4, when the high energy electron beam acceleration voltage is 10 kV, the electron beam current is about 10-100 mA, the beam spot diameter is about 3 mm, and the background vacuum of the evaporation chamber is 8×10 -4 Pa, and the distance between the substrate and the crucible is 8 cm. A SiO2 film with a thickness of 115 nm is evaporated on the first transparent insulating layer 61. The SiO2 film serves as the second transparent insulating layer 62. The second transparent insulating layer 62 covers the silicon nitride waveguide layer 2 on the first transparent insulating layer 61 and the first electrode layer 31 on the silicon nitride waveguide layer 2. Moreover, after being deposited by electron beam evaporation technology, the second transparent insulating layer 62 is formed with a convex area 623 convex upward at a position corresponding to the silicon nitride waveguide layer 2. At this time, the upper surface of the second transparent insulating layer 62 is an uneven surface.

[0057] S45, patterned etching is performed on the upper surface of the second transparent insulating layer 62 using ICPE with positive photoresist (Shipley, S1818, USA) as a mask. Specifically, a layer of positive photoresist is plated on the second transparent insulating layer 62, and then the pattern is transferred from the mask to the photoresist by development, and then developed and dried. Finally, the device with the corresponding pattern photoresist on the surface is placed in the vacuum chamber of the etcher for etching, and the gas ratio and gas flow rate are CHF3 (200sccm), Ar (20sccm), O2 (5sccm), and under the conditions of 700W upper radio frequency power RF1 and 200W lower radio frequency power RF2, the second transparent insulating layer 62 is patterned, and the raised area 623 on the second transparent insulating layer 62 is etched away, so that the upper surface of the second transparent insulating layer 62 forms a smooth surface.

[0058] S5 , etching a second groove 622 with a depth of 115 nm on the second transparent insulating layer 62 at an etching temperature of 60° C. and an etching rate of 110 nm / min. The second groove 622 penetrates to the upper surface of the first electrode layer 31 .

[0059] S61, the PEDOT:PSS solution is filtered with a nylon filter head with a pore size of 0.2 μm, and then the filtered PEDOT:PSS solution is printed in the second groove 622 under the conditions of a droplet spacing of 40 μm, a printing voltage of 25 V, and a substrate temperature and a nozzle temperature of room temperature. The device is then dried on a hot stage at 150° C. for 20 minutes by evaporating the gel, and a PEDOT:PSS film with a thickness of 30 nm is obtained in the second groove 622 and on the first electrode layer 31, and the PEDOT:PSS film is used as the first transmission layer 411.

[0060] S62, inkjet print the TFB solution (8 mg / mL chlorobenzene solution) into the second groove 622 and on the first transport layer 411, and after drying, form a 30 nm thick TFB layer on the upper surface of the first transport layer 411, and the TFB layer serves as the second transport layer 412. The first transport layer 411 and the second transport layer 412 together serve as the hole transport layer 41.

[0061] S7, disperse the quantum dots in a toluene solution to form a 2 mg / mL quantum dot ink, then inkjet print the quantum dot ink into the second groove 622, and then anneal on a 100°C hot plate for 10 minutes, and finally form a quantum dot layer 5 with a thickness of 20 nm in the second groove 622 and on the second transmission layer 412.

[0062] S8. Place the pressed ZnO target in a high-temperature tube furnace and calcine it at 1200℃ for 2h. Place the calcined ZnO target in a crucible. When the high-energy electron beam acceleration voltage is 10kV, the electron beam current is 10mA, the distance between the substrate and the crucible is 8cm, the beam spot diameter is about 3mm, and the background vacuum of the evaporation chamber is 8×10 -4 Under the condition of Pa, a ZnO film with a thickness of 35 nm is evaporated in the second groove 622 and on the quantum dot layer 5 , and the ZnO film serves as the electron transport layer 42 .

[0063] S9, when the high-energy electron beam acceleration voltage is 9KV, the electron beam current is 0.2A, the distance between the substrate and the crucible is 8cm, the beam spot diameter is about 3mm, and the background vacuum of the evaporation chamber is 2.6×10 -4 Under the condition of Pa, a metal Al (aluminum) layer with a thickness of 100 nm is evaporated on the electron transport layer 42 outside the second groove 622. The metal Al layer serves as the second electrode layer 32 and protrudes above the second transparent insulating layer 62 to be exposed to the outside.

[0064] S10 , etching a first groove 621 with a depth of 115 nm on the second transparent insulating layer 62 at an etching temperature of 60° C. and an etching rate of 110 nm / min, and the first electrode layer 31 is exposed through the first groove 621 .

[0065] It can be understood that the above embodiments only express the preferred implementation methods of the utility model, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the patent scope of the utility model. It should be pointed out that, for ordinary technicians in this field, without departing from the concept of the utility model, the above-mentioned technical features can be freely combined, and several deformations and improvements can be made, which all belong to the protection scope of the utility model. Therefore, all equivalent changes and modifications made to the scope of the claims of the utility model should fall within the scope of the claims of the utility model.

Claims

1. A quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency, characterized in that: It comprises a silicon substrate (1), a first transparent insulating layer (61), a silicon nitride waveguide layer (2), a first electrode layer (31), a hole transport layer (41), a quantum dot layer (5), an electron transport layer (42), a second electrode layer (32), and a second transparent insulating layer (62); The silicon substrate (1), the first transparent insulating layer (61), the silicon nitride waveguide layer (2), the first electrode layer (31), the hole transport layer (41), the quantum dot layer (5), the electron transport layer (42), and the second electrode layer (32) are connected in sequence; the second transparent insulating layer (62) is connected to the first transparent insulating layer (61) and surrounds the silicon nitride waveguide layer (2), the first electrode layer (31), the hole transport layer (41), the quantum dot layer (5), and the electron transport layer (42); At least one first groove (621) is provided on the second transparent insulating layer (62), and a portion of the first electrode layer (31) is exposed through the first groove (621); The thickness of the first electrode layer (31) is 100-200 nm; the thickness of the second electrode layer (32) is 100-200 nm; the thickness of the hole transport layer is 40-100 nm; the thickness of the electron transport layer is 20-80 nm, and the thickness of the quantum dot layer (5) is 10-30 nm.

2. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The cross-sectional area of ​​the silicon nitride waveguide layer (2) is smaller than the cross-sectional area of ​​the first transparent insulating layer.

3. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The cross-sectional area of ​​the first electrode layer (31) is smaller than the cross-sectional area of ​​the silicon nitride waveguide layer (2).

4. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The cross-sectional areas of the hole transport layer (41), the quantum dot layer (5), the electron transport layer (42) and the second electrode layer (32) are equal, and the cross-sectional area of ​​the hole transport layer (41) is smaller than the cross-sectional area of ​​the first electrode layer (31).

5. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The long axis of the first electrode layer (31) is perpendicular to the long axis of the silicon nitride waveguide layer (2).

6. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The thickness of the first electrode layer (31) is 100 nm.

7. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The thickness of the second electrode layer (32) is 100 nm.

8. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The hole transport layer (41) comprises a first transport layer (411) and a second transport layer (412), the first transport layer (411) being connected to the first electrode layer (31), the second transport layer (412) being connected to the quantum dot layer (5), the first transport layer (411) having a thickness of 90 nm, and the second transport layer (412) having a thickness of 30 nm.

9. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The thickness of the electron transport layer (42) is 50 nm.

10. The quantum dot light-emitting device on a silicon substrate with high electro-optical coupling efficiency according to claim 1, characterized in that: The thickness of the quantum dot layer (5) is 20 nm.

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