Semiconductor process machine and semiconductor process equipment

Abstract

The utility model provides a semiconductor process machine table and semiconductor process equipment, a temperature control structure is arranged in a bearing table, and the upper surface of the bearing table is a flush surface; a first temperature control pipeline in the temperature control structure is located in a first area, and a second temperature control pipeline is located in a second area surrounding the first area. The first temperature control pipeline and the second temperature control pipeline are the same in pipe diameter and different in distance from the upper surface of the bearing table. According to the utility model, the temperature control structure is partitioned to respectively control the temperatures of the center and the edge of the bearing table, so that the reaction rate of the wafer on the bearing table is uniform; meanwhile, by setting the positions of the partitions, the temperature adjustment better conforms to the reaction rate distribution, and the reaction uniformity is improved; in addition, the temperature of the bearing table is adjusted by setting the heights of the first area and the second area to be different, and the improvement method is simple and convenient to apply; finally, the temperature of the machine table is adjusted by setting different fluid flow rates of the temperature control pipeline, the form of the temperature control structure does not need to be changed, and the method is simple and convenient and facilitates popularization.

Description

Technical Field

[0001] The utility model belongs to the field of semiconductor equipment, in particular to a semiconductor process machine and semiconductor process equipment. Background Art

[0002] ALC (Atomic Layer Cleaning) is an important step in the epitaxial process. The reaction results of ALC will affect the subsequent wafer defects. The ALC process uses hydrofluoric acid and ammonia as etching gases to react with silicon dioxide on the surface of the silicon wafer to generate white solid (NH4) 2 SiF6 is then heated to sublime to remove oxide from the surface of the silicon wafer.

[0003] However, during the etching process of the wafer in the ALC process chamber, there is a problem that the etching amount near the edge of the wafer and near the center of the wafer is quite different, which will affect the uniformity of the deposition surface obtained in the subsequent deposition process. Long-term uneven deposition surface will lead to global uniformity of the final product.

[0004] Therefore, there is an urgent need for a process equipment that can improve the uniformity of wafers after reaction.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Utility Model Content

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor process machine and a semiconductor process equipment to solve the problem of poor surface uniformity of wafers after reaction in the prior art.

[0007] In order to achieve the above purpose and other related purposes, the utility model provides the following technical solutions:

[0008] In a first aspect, the utility model provides a semiconductor process machine, the semiconductor process machine comprising: a carrier platform and a temperature control structure;

[0009] The temperature control structure is located in the carrier platform, the carrier platform is used to place wafers, and the upper surface of the carrier platform is a flush surface;

[0010] The temperature control structure includes a first temperature control pipeline and a second temperature control pipeline, the first temperature control pipeline is arranged in a first area to control the temperature of the upper surface of the carrier corresponding to the first area, the second temperature control pipeline is arranged in a second area to control the temperature of the upper surface of the carrier corresponding to the second area, and the second area surrounds the periphery of the first area;

[0011] The first temperature control pipeline and the second temperature control pipeline have the same pipe diameter, and the first temperature control pipeline and the second temperature control pipeline are at different distances from the upper surface of the supporting platform.

[0012] Optionally, the temperature control structure also includes a third temperature control pipeline, the first area and / or the second area includes a preset area, the third temperature control pipeline is arranged in the preset area to control the temperature of the upper surface of the support platform corresponding to the preset area, the third temperature control pipeline has the same diameter as the first temperature control pipeline, and the distance between the third temperature control pipeline and the upper surface of the support platform is a preset distance.

[0013] Optionally, the temperature control structure is a cooling structure, and the distance between the first temperature control pipeline and the upper surface of the supporting platform is smaller than the distance between the second temperature control pipeline and the upper surface of the supporting platform.

[0014] Optionally, the temperature control structure is a heating structure, and the distance between the first temperature control pipeline and the upper surface of the supporting platform is greater than the distance between the second temperature control pipeline and the upper surface of the supporting platform.

[0015] Optionally, the first region is circular, the second region is a ring concentric with the second region, and the diameter of the first region is 1 / 3-2 / 3 of the outer diameter of the second region.

[0016] In a second aspect, the utility model provides a semiconductor process machine, the semiconductor process machine comprising: a carrier platform and a temperature control structure;

[0017] The temperature control structure is located in the carrier platform, the carrier platform is used to place wafers, and the upper surface of the carrier platform is a flush surface;

[0018] The temperature control structure includes a first temperature control pipeline and a second temperature control pipeline, the first temperature control pipeline is arranged in a first area to control the temperature of the upper surface of the carrier corresponding to the first area, the second temperature control pipeline is arranged in a second area to control the temperature of the upper surface of the carrier corresponding to the second area, and the second area surrounds the periphery of the first area;

[0019] The first temperature control pipeline and the second temperature control pipeline have different or same distances from the upper surface of the support platform, and the flow rate of the fluid in the first temperature control pipeline is different from the flow rate of the fluid in the second temperature control pipeline.

[0020] Optionally, the temperature control structure also includes a third temperature control pipeline, the first area and / or the second area includes a preset area, the third temperature control pipeline is arranged in the preset area to control the temperature of the upper surface of the support platform corresponding to the preset area, the third temperature control pipeline and the first temperature control pipeline are at an equal distance from the upper surface of the support platform, and the fluid flow rate in the third temperature control pipeline is a preset flow rate.

[0021] Optionally, when the first temperature control pipeline and the second temperature control pipeline are at the same distance from the upper surface of the support platform, the temperature control structure is a cooling structure, and the fluid flow rate in the first temperature control pipeline is faster than the fluid flow rate in the second temperature control pipeline.

[0022] Optionally, when the first temperature control pipeline and the second temperature control pipeline are at an equal distance from the upper surface of the support platform, the temperature control structure is a heating structure, and the fluid flow rate in the first temperature control pipeline is slower than the fluid flow rate in the second temperature control pipeline.

[0023] Optionally, the first region is circular, the second region is a ring concentric with the second region, and the diameter of the first region is 1 / 3-2 / 3 of the outer diameter of the second region.

[0024] In a third aspect, the utility model provides a semiconductor process equipment, wherein the semiconductor process equipment comprises any one of the semiconductor process machines described above, and the semiconductor process equipment is an atomic layer cleaning equipment.

[0025] As described above, the semiconductor process machine and semiconductor process equipment of the present invention have the following beneficial effects:

[0026] The utility model sets the first temperature control pipeline and the second temperature control pipeline at different distances from the upper surface of the carrier, so that the temperature of the corresponding first area and the second area on the carrier can be controlled to be different. In the process of processing wafers, the reaction rate often changes with the temperature. By controlling the central area and the edge area of ​​the wafer surface to different temperatures to adjust the corresponding reaction rate, the reaction rate difference caused by the distribution of the position itself at different positions is compensated, so that the uniformity of the reaction rate of the wafer surface can be achieved, and the uniformity of the wafer surface after the process is improved;

[0027] The utility model sets a third temperature control pipeline in a preset area, so as to more accurately control the temperature of a specific position where a reaction rate abnormality may occur in certain areas of the carrier, thereby better improving the surface uniformity of the wafer after the process treatment;

[0028] The utility model sets the temperature control structure as a cooling structure, and sets the distance between the first temperature control pipeline located in the center area of ​​the wafer and the upper surface of the carrier platform to be smaller than the distance between the second temperature control pipeline located in the edge area of ​​the wafer and the upper surface of the carrier platform, so that the first temperature control pipeline is closer to the upper surface of the carrier platform, and it is easier to reduce the temperature of the position of the first temperature control pipeline corresponding to the upper surface of the carrier platform. Since the lower the temperature in the ALC reaction, the higher the etching rate, the etching rate of the central area of ​​the wafer can be increased, and the etching amount of the central area can be increased, so that the overall surface uniformity of the wafer after ALC is improved;

[0029] The utility model sets the temperature control structure as a heating structure, and sets the distance between the first temperature control pipeline located in the center area of ​​the wafer and the upper surface of the carrier platform to be greater than the distance between the second temperature control pipeline located in the edge area of ​​the wafer and the upper surface of the carrier platform, so that the second temperature control pipeline is closer to the upper surface of the carrier platform, and it is easier to increase the temperature of the position of the second temperature control pipeline corresponding to the upper surface of the carrier platform. In the ALC reaction, the higher the temperature, the lower the etching rate. Therefore, the etching rate of the edge area of ​​the wafer can be reduced, and the etching amount of the edge area can be reduced, so that the overall surface uniformity of the wafer after ALC is improved;

[0030] The utility model measures the etching amount at different positions of the wafer after the process is processed by the ALC semiconductor process equipment in the prior art, obtains the area range where the etching amount needs to be increased and reduced, determines that when the diameter of the first area is 1 / 3-2 / 3 of the outer diameter of the second area, the etching amount changes the most, and the wafer surface uniformity improvement effect achieved after temperature regulation is the best, thereby achieving the optimization of the wafer surface uniformity;

[0031] The utility model sets different fluid flow rates in the first temperature control pipeline and the second temperature control pipeline, so that the temperature of the corresponding first area and the second area on the carrier can be controlled to be different. In the process of processing wafers, the reaction rate often changes with the temperature. By controlling the central area and the edge area of ​​the wafer surface to different temperatures to adjust the corresponding reaction rate, the reaction rate difference caused by the distribution of the position itself at different positions is compensated, so that the uniformity of the reaction rate of the wafer surface can be achieved, and the uniformity of the wafer surface after the process is improved;

[0032] The utility model sets the first temperature control pipeline and the second temperature control pipeline at different distances from the upper surface of the carrier platform, and cooperates with the different fluid flow rates in the first temperature control pipeline and the second temperature control pipeline to jointly control the temperatures of different areas on the upper surface of the carrier platform, thereby achieving a more flexible and more precise control effect, and further improving the surface uniformity of the wafer after the process treatment;

[0033] The utility model sets the fluid flow rate of the third temperature control pipeline to a preset flow rate, thereby more accurately controlling the temperature of certain areas on the carrier where abnormal reaction rates may occur, thereby better improving the surface uniformity of the wafer after the process treatment;

[0034] The utility model sets the temperature control structure as a cooling structure, and sets the fluid flow rate in the first temperature control pipeline located in the center area of ​​the wafer to be faster than the fluid flow rate in the second temperature control pipeline located in the edge area of ​​the wafer, so that the cooling efficiency of the first temperature control pipeline is faster, and it is easier to reduce the temperature of the position corresponding to the first temperature control pipeline on the upper surface of the carrier platform. In the ALC reaction, the lower the temperature, the higher the etching rate. Therefore, the etching rate of the central area of ​​the wafer can be increased, and the etching amount of the central area can be increased, so that the overall surface uniformity of the wafer after ALC is improved;

[0035] The utility model sets the temperature control structure as a heating structure, and sets the fluid flow rate in the first temperature control pipeline located in the center area of ​​the wafer to be slower than the fluid flow rate in the second temperature control pipeline located in the edge area of ​​the wafer, thereby making the heating efficiency of the second temperature control pipeline higher and making it easier to increase the temperature of the position of the second temperature control pipeline corresponding to the upper surface of the carrier platform. In the ALC reaction, the higher the temperature, the lower the etching rate. Therefore, the etching rate in the edge area of ​​the wafer can be reduced, and the etching amount in the edge area can be reduced, so that the overall surface uniformity of the wafer after ALC is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The diagram is a cross-sectional view of a semiconductor process equipment in the prior art.

[0037] Figure 2 The diagram is a top view of a semiconductor process equipment in the prior art.

[0038] Figure 3 Shown is a schematic cross-sectional view of a carrier platform and the semiconductor process equipment in which it is located in an example of the utility model 1.

[0039] Figure 4 Shown is a schematic top view of a carrier platform and the semiconductor process equipment in which it is located in an example of the utility model 1.

[0040] Figure 5 Shown is a color heat map of the wafer etching amount of the ALC process in the prior art.

[0041] Figure 6 Shown is a grayscale diagram of a heat map of the wafer etching amount in the ALC process in the prior art.

[0042] Figure 7 The figure shows the variation of etching amount at different positions and different temperatures in the ALC process in the prior art.

[0043] Figure 8 The figure shows the variation of etching amount at different positions of the wafer after ALC processing in the prior art.

[0044] Fig. 9 Shown is a schematic cross-sectional view of a carrier platform and the semiconductor process equipment in which it is located in Example 2 of the present invention.

[0045] Fig.10 Shown is a schematic top view of a carrier platform and the semiconductor process equipment in which it is located in Example 2 of the present invention.

[0046] Fig.11 Shown is a schematic diagram of the temperature control pipeline structure in Example 2 of the present utility model.

[0047] Component number description

[0048] 11. Carrying platform; 12. Edge ring; 13. Pump ring; 131. Exhaust hole; 14. Jet channel; 15. Sapphire ball head; 16. Spray surface; 17. Reaction gas; 18. Reaction product gas; 19. Inert gas;

[0049] 21. Existing temperature control pipeline; 22. First temperature control pipeline; 23. Second temperature control pipeline; 24. First area; 25. Second area; 26. Wafer;

[0050] 31. Mass flow controller; 32. Water inlet pipeline; 33. Water return pipeline; 34. Cooling device. DETAILED DESCRIPTION

[0051] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0053] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0054] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0055] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0056] Embodiment 1:

[0057] This embodiment provides a semiconductor process machine, the semiconductor process machine comprising: a carrier 11 and a temperature control structure;

[0058] The temperature control structure is located in the carrier platform 11. The carrier platform 11 is used to place the wafer 26. The upper surface of the carrier platform 11 is a flush surface.

[0059] The temperature control structure includes a first temperature control pipeline 22 and a second temperature control pipeline 23. The first temperature control pipeline 22 is arranged in a first area 24 to control the temperature of the upper surface of the carrier 11 corresponding to the first area 24. The second temperature control pipeline 23 is arranged in a second area 25 to control the temperature of the upper surface of the carrier 11 corresponding to the second area 25. The second area 25 surrounds the periphery of the first area 24.

[0060] The first temperature control pipeline 22 and the second temperature control pipeline 23 have the same diameter, and the first temperature control pipeline 22 and the second temperature control pipeline 23 are at different distances from the upper surface of the supporting platform 11 .

[0061] In the prior art, such as Figure 1-Figure 2 As shown, the height of the existing temperature control pipeline 21 inside the carrier 11 is uniformly spaced from the upper surface of the carrier 11. Figure 1 is a cross-sectional view of the carrier 11 and the semiconductor process equipment where it is located, Figure 2 1 is a top view of the carrier 11 and the semiconductor process equipment in which it is located. When such semiconductor process equipment is used to perform an overall process on the surface of the wafer 26, the processing speeds of the center area and the edge area are often different, resulting in an uneven surface of the wafer 26 after the process, which can easily affect the subsequent process steps of the wafer 26, easily cause damage, or reduce the process accuracy, making it difficult to ensure the product yield.

[0062] The utility model sets the first temperature control pipeline 22 and the second temperature control pipeline 23 at different distances from the upper surface of the carrier 11, so that the temperatures of the corresponding first area 24 and the second area 25 on the carrier 11 can be controlled to be different. In the process of processing the wafer 26, its reaction rate often changes with temperature. By controlling the surface of the wafer 26 to have different temperatures in the central area and the edge area to adjust the corresponding reaction rate, the difference in reaction rate caused by the distribution of the positions themselves is compensated, so that the uniformity of the reaction rate on the surface of the wafer 26 can be achieved, and the surface uniformity of the wafer 26 after process processing is improved.

[0063] In one embodiment, the temperature control structure also includes a third temperature control pipeline, the first area 24 and / or the second area 25 includes a preset area, and the third temperature control pipeline is arranged in the preset area to control the temperature of the upper surface of the support platform 11 corresponding to the preset area. The third temperature control pipeline has the same diameter as the first temperature control pipeline 22, and the distance between the third temperature control pipeline and the upper surface of the support platform 11 is a preset distance.

[0064] Specifically, the preset area where the third temperature control pipeline is located is a hot spot area where the reaction rate of the corresponding wafer 26 on the carrier 11 is abnormal during the process treatment. The preset distance between the third temperature control pipeline and the upper surface of the carrier 11 is set accordingly by adjusting the temperature required for the reaction rate at the position of the wafer 26 corresponding to the preset area.

[0065] The utility model sets a third temperature control pipeline in a preset area, so as to more accurately control the temperature of certain areas on the carrier 11 where specific reaction rate abnormalities may occur, thereby better improving the surface uniformity of the wafer 26 after process treatment.

[0066] In one embodiment, Figure 3-Figure 4 As shown, Figure 3 is a cross-sectional view of the carrier 11 and the semiconductor process equipment where it is located, Figure 4 It is a top view of the carrier 11 and the semiconductor process equipment where it is located. The temperature control structure is a cooling structure. The distance between the first temperature control pipeline 22 and the upper surface of the carrier 11 is smaller than the distance between the second temperature control pipeline 23 and the upper surface of the carrier 11.

[0067] In the prior art, the etching amount of the wafer 26 surface processed in the ALC (atomic layer cleaning) reaction chamber is quite different between the edge area and the center area, and the etching amount of the center area is often less than that of the edge area. Figure 5 The figure shows a heat map of the etching amount of the wafer 26 in the ALC process in the prior art. Figure 6 The figure shows a heat map grayscale image of the etching amount of the wafer 26 in the ALC process in the prior art. The deeper the grayscale, the smaller the etching amount. It can be seen that the etching amount in the central area of ​​the wafer 26 is small, and the etching amount in the edge area is large, resulting in poor surface uniformity of the wafer 26 after the ALC process, and a low product yield. In the ALC reaction, the lower the temperature, the higher the etching rate. Figure 7 The figure shows the etching amount variation diagram at different positions and different temperatures of the ALC process in the prior art. The horizontal axis is the sampling point number on the radius from the center of the wafer 26 to the edge of the wafer 26, and the vertical axis is the normalized value of the etching amount after the ALC process. The line with triangles represents the etching amount at a temperature of 35°C, and the line with circles represents the etching amount at a temperature of 40°C. It can be seen that the etching amount increases rapidly at the positions of the 25th to 27th points, and the etching amount at a temperature of 35°C is always greater than the etching amount at a temperature of 40°C. It can be seen that lowering the temperature can increase the etching amount, that is, increase the etching rate.

[0068] The utility model sets the temperature control structure as a cooling structure, and sets the distance between the first temperature control pipeline 22 located in the central area of ​​the wafer 26 and the upper surface of the carrier 11 to be smaller than the distance between the second temperature control pipeline 23 located in the edge area of ​​the wafer 26 and the upper surface of the carrier 11, so that the first temperature control pipeline 22 is closer to the upper surface of the carrier 11, and it is easier to reduce the temperature of the position of the first temperature control pipeline 22 corresponding to the upper surface of the carrier 11. Since the lower the temperature in the ALC reaction, the higher the etching rate, the etching rate in the central area of ​​the wafer 26 can be increased, and the etching amount in the central area is increased, so that the overall surface uniformity of the wafer 26 after ALC is improved.

[0069] In one embodiment, the temperature control structure is a heating structure, and the distance between the first temperature control pipeline 22 and the upper surface of the carrier platform 11 is greater than the distance between the second temperature control pipeline 23 and the upper surface of the carrier platform 11 .

[0070] The utility model sets the temperature control structure as a heating structure, and sets the distance between the first temperature control pipeline 22 located in the center area of ​​the wafer 26 and the upper surface of the carrier 11 to be greater than the distance between the second temperature control pipeline 23 located in the edge area of ​​the wafer 26 and the upper surface of the carrier 11, so that the second temperature control pipeline 23 is closer to the upper surface of the carrier 11, and it is easier to increase the temperature of the position of the second temperature control pipeline 23 corresponding to the upper surface of the carrier 11. In the ALC reaction, the higher the temperature, the lower the etching rate. Therefore, the etching rate in the edge area of ​​the wafer 26 can be reduced, and the etching amount in the edge area can be reduced, so that the overall surface uniformity of the wafer 26 after ALC is improved.

[0071] In one embodiment, the first region 24 is circular, the second region 25 is a ring concentric with the second region 25 , and the diameter of the first region 24 is 1 / 3-2 / 3 of the outer diameter of the second region 25 .

[0072] The utility model measures the etching amount at different positions of the wafer 26 after the process by using the ALC semiconductor process equipment in the prior art, obtains the area range where the etching amount needs to be increased and reduced, and determines that when the diameter of the first area 24 is 1 / 3-2 / 3 of the outer diameter of the second area 25, the etching amount changes the most, and the surface uniformity of the wafer 26 is improved best after temperature control, thereby achieving the optimization of the surface uniformity of the wafer 26. Figure 8 The figure shows the etching amount variation at different positions of the wafer 26 after ALC treatment in the prior art, wherein the horizontal axis is the sampling point number on the diameter from one end to the other end of the wafer 26, and the vertical axis is the etching amount after ALC treatment, and it is found that the etching amount varies significantly within the range of 1 / 3-2 / 3 of the radius.

[0073] Embodiment 2:

[0074] This embodiment provides a semiconductor process machine, the semiconductor process machine comprising: a carrier 11 and a temperature control structure;

[0075] The temperature control structure is located in the carrier platform 11. The carrier platform 11 is used to place the wafer 26. The upper surface of the carrier platform 11 is a flush surface.

[0076] The temperature control structure includes a first temperature control pipeline 22 and a second temperature control pipeline 23. The first temperature control pipeline 22 is arranged in a first area 24 to control the temperature of the upper surface of the carrier 11 corresponding to the first area 24. The second temperature control pipeline 23 is arranged in a second area 25 to control the temperature of the upper surface of the carrier 11 corresponding to the second area 25. The second area 25 surrounds the periphery of the first area 24.

[0077] The first temperature control pipeline 22 and the second temperature control pipeline 23 are at different or same distances from the upper surface of the support platform 11 , and the flow rate of the fluid in the first temperature control pipeline 22 is different from the flow rate of the fluid in the second temperature control pipeline 23 .

[0078] The utility model sets different fluid flow rates in the first temperature control pipeline 22 and the second temperature control pipeline 23, so that the temperatures of the corresponding first area 24 and the second area 25 on the carrier 11 can be controlled to be different. In the process of processing the wafer 26, its reaction rate often changes with temperature. By controlling the surface of the wafer 26 to different temperatures in the central area and the edge area to adjust the corresponding reaction rate, the difference in reaction rate caused by the distribution of the positions themselves is compensated, so that the uniformity of the reaction rate on the surface of the wafer 26 can be achieved, and the surface uniformity of the wafer 26 after process processing is improved.

[0079] Specifically, when the first temperature control pipeline 22 and the second temperature control pipeline 23 are at the same distance from the upper surface of the carrier platform 11, the temperature of different areas on the upper surface of the carrier platform 11 can be regulated simply by controlling the fluid flow rate in the first temperature control pipeline 22 to be different from the fluid flow rate in the second temperature control pipeline 23; however, the utility model can also set the first temperature control pipeline 22 and the second temperature control pipeline 23 to be at different distances from the upper surface of the carrier platform 11, and cooperate with the fluid flow rate in the first temperature control pipeline 22 to be different from the fluid flow rate in the second temperature control pipeline 23, so as to jointly regulate the temperature of different areas on the upper surface of the carrier platform 11, thereby achieving a more flexible and more accurate regulation effect, and further improving the surface uniformity of the wafer 26 after process treatment.

[0080] In one embodiment, the temperature control structure also includes a third temperature control pipeline, the first area 24 and / or the second area 25 includes a preset area, the third temperature control pipeline is arranged in the preset area to control the temperature of the upper surface of the support platform 11 corresponding to the preset area, the third temperature control pipeline and the first temperature control pipeline 22 are at the same distance from the upper surface of the support platform 11, and the fluid flow rate in the third temperature control pipeline is a preset flow rate.

[0081] Specifically, the preset area where the third temperature control pipeline is located is the hot spot area where the reaction rate of the corresponding wafer 26 on the carrier 11 is abnormal during the process treatment. The preset flow rate of the third temperature control pipeline is set accordingly by adjusting the temperature required for the reaction rate at the position of the wafer 26 corresponding to the preset area.

[0082] The utility model sets the fluid flow rate of the third temperature control pipeline to a preset flow rate, thereby more accurately controlling the temperature of certain areas on the carrier 11 where specific reaction rate anomalies may occur, thereby better improving the surface uniformity of the wafer 26 after process treatment.

[0083] In one embodiment, the fluid flow rate can be controlled by setting the openings of the valves of the first temperature control pipeline 22 , the second temperature control pipeline 23 , and the third temperature control pipeline.

[0084] In one embodiment, the fluid flow rate can be controlled by setting the diameters of the first temperature control pipeline 22 , the second temperature control pipeline 23 , and the third temperature control pipeline.

[0085] Specifically, the fluid flow rates of the first temperature control pipeline 22 , the second temperature control pipeline 23 , and the third temperature control pipeline may also be controlled by other appropriate methods.

[0086] In one embodiment, Figure 9-10 As shown, Fig. 9 is a cross-sectional view of the carrier 11 and the semiconductor process equipment where it is located, Fig.10 It is a top view of the carrier platform 11 and the semiconductor process equipment where it is located. When the first temperature control pipeline 22 and the second temperature control pipeline 23 are at the same distance from the upper surface of the carrier platform 11, the temperature control structure is a cooling structure, and the fluid flow rate in the first temperature control pipeline 22 is faster than the fluid flow rate in the second temperature control pipeline 23.

[0087] Specifically, Fig.11 The figure shows the temperature control pipeline structure in the above-mentioned temperature control structure. The first temperature control pipeline 22 and the second temperature control pipeline 23 can be set to control the fluid flow rate through an MFC (mass flow controller 31) respectively, and then connected to the cooling device 34 through the water inlet pipeline 32 and the return water pipeline 33. The cooling device 34 is used to provide coolant of a preset temperature to the water inlet pipeline 32 and absorb the heat of the coolant in the return water pipeline 33 to restore it to the preset temperature.

[0088] In the prior art, the etching amount of the edge area and the center area of ​​the surface of the wafer 26 processed in the ALC (atomic layer cleaning) reaction chamber is quite different, and the etching amount in the center area is often smaller than that in the edge area, resulting in poor uniformity of the surface of the wafer 26 after the ALC process and a low product yield.

[0089] The utility model sets the temperature control structure as a cooling structure, and sets the fluid flow rate in the first temperature control pipeline 22 located in the central area of ​​the wafer 26 to be faster than the fluid flow rate in the second temperature control pipeline 23 located in the edge area of ​​the wafer 26, so that the cooling efficiency of the first temperature control pipeline 22 is faster, and it is easier to reduce the temperature of the position of the first temperature control pipeline 22 corresponding to the upper surface of the carrier 11. In the ALC reaction, the lower the temperature, the higher the etching rate. Therefore, the etching rate in the central area of ​​the wafer 26 can be increased, and the etching amount in the central area can be increased, so that the overall surface uniformity of the wafer 26 after ALC is improved.

[0090] In one embodiment, when the first temperature control pipeline 22 and the second temperature control pipeline 23 are at the same distance from the upper surface of the support platform 11 , the temperature control structure is a heating structure, and the fluid flow rate in the first temperature control pipeline 22 is slower than the fluid flow rate in the second temperature control pipeline 23 .

[0091] The utility model sets the temperature control structure as a heating structure, and sets the fluid flow rate in the first temperature control pipeline 22 located in the central area of ​​the wafer 26 to be slower than the fluid flow rate in the second temperature control pipeline 23 located in the edge area of ​​the wafer 26, thereby making the heating efficiency of the second temperature control pipeline 23 higher and making it easier to increase the temperature of the position of the second temperature control pipeline 23 corresponding to the upper surface of the carrier platform 11. In the ALC reaction, the higher the temperature, the lower the etching rate. Therefore, the etching rate in the edge area of ​​the wafer 26 can be reduced, and the etching amount in the edge area can be reduced, so that the overall surface uniformity of the wafer 26 after ALC is improved.

[0092] In one embodiment, the first region 24 is circular, the second region 25 is a ring concentric with the second region 25 , and the diameter of the first region 24 is 1 / 3-2 / 3 of the outer diameter of the second region 25 .

[0093] The utility model measures the etching amount at different positions of the wafer 26 after process treatment to obtain the area range where the etching amount needs to be increased and reduced, and determines that when the diameter of the first area 24 is 1 / 3-2 / 3 of the outer diameter of the second area 25, the change in etching amount is the largest, and the surface uniformity of the wafer 26 is improved best after temperature control, thereby achieving the optimization of the surface uniformity of the wafer 26.

[0094] In one embodiment, a sapphire ball head 15 is further disposed on the upper surface of the carrier platform 11 , and the sapphire ball head 15 is used to support the wafer 26 .

[0095] In one embodiment, the outer periphery of the carrier 11 is surrounded by an edge ring 12 , and the edge ring 12 is used to prevent the reaction gas 17 from entering the bottom of the wafer 26 and causing unnecessary etching to the bottom of the wafer 26 .

[0096] Embodiment 3:

[0097] This embodiment provides a semiconductor process equipment, which includes the semiconductor process machine described in any one of Embodiments 1-2, and the semiconductor process equipment is an atomic layer cleaning equipment.

[0098] Since the etching amount of the wafer 26 in the center area and the edge area in the atomic layer cleaning equipment is significantly different, and the reaction in the atomic layer cleaning equipment is that the higher the temperature, the lower the reaction rate, and the correlation is more obvious, the use of the semiconductor process machine in Examples 1-2 can significantly improve the uniformity of the surface of the wafer 26 after the ALC process. However, the semiconductor process machine in Examples 1-2 can also be applied to other similar surface uniformity problems caused by different reaction rates in different areas of the wafer 26. When the reaction rate is related to the reaction temperature, the semiconductor process machine in Examples 1-2 can be used to obtain a wafer 26 surface with higher uniformity after the process.

[0099] In one embodiment, Figure 3-Figure 4 and Figure 9-10 As shown in , the semiconductor process equipment also includes a spray surface 16 and a pump ring 13; the spray surface 16 is located above the carrier 11 for introducing reaction gas 17; the pump ring 13 surrounds the carrier 11 and discharges reaction product gas 18 through exhaust holes 131.

[0100] In one embodiment, Figure 3-Figure 4 and Figure 9-10 As shown in , an injection channel 14 is provided between the carrier platform 11 and the pump ring 13 , and the injection channel 14 is used to introduce an inert gas 19 upwards so that the gas does not enter under the carrier platform 11 to corrode the carrier platform 11 , thereby increasing the service life of the carrier platform 11 .

[0101] In summary, the semiconductor process machine and semiconductor process equipment of the utility model can control the temperature of the center and edge of the carrier platform by dividing the temperature control structure into zones, so that the reaction rate of the wafers on the carrier platform is uniform; at the same time, by setting the position of the partitions, the temperature adjustment is more in line with the reaction rate distribution, thereby improving the reaction uniformity; in addition, by setting the different heights of the first area and the second area, the temperature of the carrier platform can be adjusted, and the improved method is simple and easy to apply; finally, by setting the different fluid flow rates of the temperature control pipeline, the temperature of the machine can be adjusted without changing the shape of the temperature control structure, and the method is simple and convenient for promotion.

[0102] Therefore, the utility model effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor process machine, characterized in that: The semiconductor process machine comprises: a carrier platform and a temperature control structure; The temperature control structure is located in the carrier platform, the carrier platform is used to place wafers, and the upper surface of the carrier platform is a flush surface; The temperature control structure includes a first temperature control pipeline and a second temperature control pipeline, the first temperature control pipeline is arranged in a first area to control the temperature of the upper surface of the carrier corresponding to the first area, the second temperature control pipeline is arranged in a second area to control the temperature of the upper surface of the carrier corresponding to the second area, and the second area surrounds the periphery of the first area; The first temperature control pipeline and the second temperature control pipeline have the same pipe diameter, and the first temperature control pipeline and the second temperature control pipeline are at different distances from the upper surface of the supporting platform.

2. The semiconductor process machine according to claim 1, characterized in that: The temperature control structure also includes a third temperature control pipeline. The first area and / or the second area includes a preset area. The third temperature control pipeline is arranged in the preset area to control the temperature of the upper surface of the support platform corresponding to the preset area. The third temperature control pipeline has the same diameter as the first temperature control pipeline, and the distance between the third temperature control pipeline and the upper surface of the support platform is a preset distance.

3. The semiconductor process machine according to claim 1, characterized in that: The temperature control structure is a cooling structure, and the distance between the first temperature control pipeline and the upper surface of the supporting platform is smaller than the distance between the second temperature control pipeline and the upper surface of the supporting platform.

4. The semiconductor process machine according to claim 1, wherein: The temperature control structure is a heating structure, and the distance between the first temperature control pipeline and the upper surface of the supporting platform is greater than the distance between the second temperature control pipeline and the upper surface of the supporting platform.

5. A semiconductor process machine, characterized in that: The semiconductor process machine comprises: a carrier platform and a temperature control structure; The temperature control structure is located in the carrier platform, the carrier platform is used to place wafers, and the upper surface of the carrier platform is a flush surface; The temperature control structure includes a first temperature control pipeline and a second temperature control pipeline, the first temperature control pipeline is arranged in a first area to control the temperature of the upper surface of the carrier corresponding to the first area, the second temperature control pipeline is arranged in a second area to control the temperature of the upper surface of the carrier corresponding to the second area, and the second area surrounds the periphery of the first area; The first temperature control pipeline and the second temperature control pipeline have different or same distances from the upper surface of the support platform, and the flow rate of the fluid in the first temperature control pipeline is different from the flow rate of the fluid in the second temperature control pipeline.

6. The semiconductor process machine according to claim 5, characterized in that: The temperature control structure also includes a third temperature control pipeline. The first area and / or the second area includes a preset area. The third temperature control pipeline is arranged in the preset area to control the temperature of the upper surface of the support platform corresponding to the preset area. The third temperature control pipeline and the first temperature control pipeline are at the same distance from the upper surface of the support platform, and the fluid flow rate in the third temperature control pipeline is a preset flow rate.

7. The semiconductor process machine according to claim 5, characterized in that: When the first temperature control pipeline and the second temperature control pipeline are at the same distance from the upper surface of the support platform, the temperature control structure is a cooling structure, and the flow rate of the fluid in the first temperature control pipeline is faster than the flow rate of the fluid in the second temperature control pipeline.

8. The semiconductor process machine according to claim 5, characterized in that: When the first temperature control pipeline and the second temperature control pipeline are at the same distance from the upper surface of the support platform, the temperature control structure is a heating structure, and the flow rate of the fluid in the first temperature control pipeline is slower than the flow rate of the fluid in the second temperature control pipeline.

9. The semiconductor process machine according to any one of claims 1 to 8, characterized in that: The first region is circular, the second region is a ring concentric with the second region, and the diameter of the first region is 1 / 3-2 / 3 of the outer diameter of the second region.

10. A semiconductor process equipment, characterized in that: The semiconductor process equipment comprises the semiconductor process machine according to any one of claims 1 to 9, and the semiconductor process equipment is an atomic layer cleaning equipment.

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