Score indicator device based on 555 timer and counter

Abstract

The utility model relates to a score indicator device based on 555 timers and counters. The score indicator device comprises two 555 timer circuits, a logic OR gate, a logic NAND gate, a JK trigger 2-bit carry counter circuit and a seven-segment cathode nixie tube. The 555 timer circuit generates an unsteady waveform with controllable duration and generates a continuous square wave signal with controllable frequency and duty ratio, the square wave signal is input into the JK trigger 2-bit carry counter circuit after being operated by the logic AND gate, the signal is reset and carried by the logic circuit, the signal is input into the decoder chip, and the decoder chip is connected with the 555 timer circuit and the JK trigger 2-bit carry counter circuit. And finally, corresponding numbers are displayed by the seven sections of cathode nixie tubes. According to the utility model, two basic applications of the 555 timer, a simple chip and a nixie tube are utilized to complete the function of the score indicator, and the purpose of recording different scores by the score indicator is achieved by selecting the resistance values of the external parallel resistors of the monostable multivibrator circuit.

Description

Technical Field

[0001] The utility model relates to a scoring device based on a 555 timer and a counter, and belongs to the field of digital electronic technology. Background Art

[0002] Basketball is a popular sport, enjoyed by many in schools and communities, and scorers are essential equipment for basketball games. However, most commercially available scorers are expensive, making them unaffordable for some schools and communities. Therefore, a more affordable and practical basketball scorer is needed. Compared to microcontroller-based scorers, this device offers a more affordable and reliable basketball scorer, enabling more schools and communities to utilize a comprehensive basketball scorer while also improving the fairness and credibility of the game.

[0003] There have been many studies on basketball scorers at home and abroad, but most of them are based on high-performance hardware designs such as FPGAs and single-chip microcomputers, which are relatively expensive. Therefore, the scorer device based on the 555 timer and counter in this utility model is a more economical and affordable solution. Summary of the Invention

[0004] The technical problem to be solved by the utility model is: the utility model provides a scoring device based on a 555 timer and a counter, which adopts a digital circuit design and can realize the function of counting different scores. At the same time, it has the characteristics of low cost and easy maintenance, and is a very practical ball scoring solution.

[0005] The technical solution of the utility model is: a scorer device based on a 555 timer and counter, comprising a 555 monostable multivibrator circuit 1, a 555 astable multivibrator circuit 2, a JK trigger 2-bit carry counter circuit 3, a decoder circuit 4, and a seven-segment cathode ray tube 5; the output signals of the 555 monostable multivibrator circuit 1 and the 555 astable multivibrator circuit 2 are connected through a logic AND gate AND1, the calculated signals are input into the JK trigger 2-bit carry counter circuit 3, the signal output by the JK trigger 2-bit carry counter circuit 3 passes through a 74LS48 decoder circuit 4 and is displayed by the seven-segment cathode ray tube 5.

[0006] Furthermore, the 555 monostable multivibrator circuit 1 includes a 555 timer chip 555I, switches S2, S3, S4, resistors R1, R2, R3, R4, and capacitors C1 and C2; the VSS and RSI ports of the 555 timer chip 555I are connected to the positive pole of a 5V power supply, S2 is connected in series with R1, S3 is connected in series with R2, and S4 is connected in series with R3. The circuits after S2 and R1 are connected in series, the circuits after S3 and R2 are connected in series, and the circuits after S4 and R3 are connected in series are connected in parallel. One end of the parallel circuit is connected to the positive pole of the power supply, and the other end is connected to the DIS port of the 555 timer. DIS is connected to the THR port and then connected to the ground through the capacitor C1. The CON port is connected to the decoupling capacitor C2 and then connected to the ground. TRI is an input port connected to the output of the logic OR gate OR. OUT is an output port connected to the input end of the logic AND gate AND1. TRI is the input port, designed to receive a falling-edge trigger signal and connect to the output of the logic OR gate. Here, one end of the logic gate input is the positive terminal of a 5V power supply controlled by a switch, and the other end is the output of the 555 astable multivibrator circuit in the lower part. This allows the high level controlled by the switch to be ORed with the regular square wave signal. When the switch is turned on, the low level and the square wave signal are ORed together. The purpose is to capture the falling-edge trigger signal at the moment when the two are synchronized and output it to the 555 monostable multivibrator circuit, achieving synchronization with the regular square wave signal. OUT is the output port. When the trigger terminal receives a falling-edge trigger signal, the circuit reverses, and the circuit output remains high (in an unstable state) for a period of time before returning to a low level. The duration of the unstable process is determined by the parameters of the external resistor and capacitor. The formula is as follows. Connect the signal to the input of the logic AND gate AND1.

[0007] t=1.1×R×C

[0008] Furthermore, the 555 astable multivibrator circuit 2 includes a 555 timer chip 555Ⅱ, resistors R1, R5, R6, and a capacitor C3; the VSS and RSI ports of the 555 timer chip 555Ⅱ are connected to the positive electrode of the 5V power supply, and one end of the resistor R5 is connected to the positive electrode of the power supply; the other end is connected to the DIS port, DIS is connected to TRI through the resistor R6, THR is connected to TRI, and then connected to the capacitor C3 and the ground level. The OUT of the 555 timer chip 555Ⅱ is the output terminal, which is connected to the input terminal of the logic OR gate OR and the input terminal of the logic AND gate AND1. The frequency and duty cycle of the output signal of this part are determined by the parameters of the two external resistors and capacitors, as follows;

[0009]

[0010] Furthermore, the JK trigger 2-bit carry counter circuit 3 includes JK triggers JK1, JK2, JK3, JK4, JK5, JK6, JK7, JK8, a logic AND gate AND2, and NAND gates NAND1 and NAND2; the J and K ports of all JK triggers are connected to the positive pole of the power supply; wherein the JK triggers JK1, JK2, JK3, and JK4 form a group, and the triggers JK5, JK6, JK7, and JK8 form two groups;

[0011] The CP port of the JK flip-flop JK1 is the input port, connected to the output port of the logic AND gate AND1, the output port Q of JK1 is connected to the A port of the decoder 74LS84Ⅱ and the CP port of JK2 respectively; the output port Q of JK2 is connected to the B port of the decoder 74LS84Ⅱ and the CP port of JK3 respectively, the output port Q of JK3 is connected to the C port of the decoder 74LS84Ⅱ and the CP port of JK4 respectively, and the output port Q of JK4 is connected to the D port of the decoder 74LS84Ⅱ;

[0012] Next is the reset carry part. The two input ends of the logic NAND gate NAND1 are connected to the Q output of JK2 and JK4 respectively. That is, if the Q output signals of JK2 and JK4 are high at the same time, the overall four-way signal is 1010 (10 in decimal), generating a square wave signal representing reset. The output is connected to the CLR port of JK flip-flops JK1, JK2, JK3, and JK4. When the CLR port of the JK flip-flop is high, it means that the flip-flop is cleared. The two input ends of the logic NAND gate NAND2 are connected to JK6 and JK8 respectively. The Q-end output is connected, and the output is connected to the CLR port of JK flip-flops JK5, JK6, JK7, and JK8. A reset operation occurs in the same group. The input of logic AND gate AND2 is connected to the Q-end output of JK2 and JK4 respectively, and the output port is connected to the CP input port of JK5. At this time, if the Q-end output signals of JK2 and JK4 are high at the same time, the overall four-way signal is 1010 (10 in decimal), generating a square wave signal representing a carry, which is input to the CP input port of JK5 and acts as a clock signal.

[0013] Furthermore, the decoder circuit 4 includes 74LS84 decoder chips 74LS84Ⅰ and 74LS84Ⅱ; wherein the A, B, C, and D ports of 74LS84Ⅱ and 74LS84Ⅰ are respectively connected to the Q port outputs of the JK triggers JK1, JK2, JK3, JK4, JK5, JK6, JK7, and JK8 of the JK trigger 2-bit carry counter circuit 3, and the OA, OB, OC, OD, OE, OF, and OG ports are respectively connected to the A, B, C, D, E, F, and G ports of two seven-segment cathode ray tubes, and the LT, RBI, and BI / RBO ports of 74LS84Ⅰ and 74LS84Ⅱ are all connected to the positive pole of the power supply.

[0014] Furthermore, there are two seven-segment cathode ray tubes 5, and the CK ports of both seven-segment cathode ray tubes are grounded. The A, B, C, D, E, F, and G ports of the seven-segment cathode ray tubes 5 are respectively connected to the OA, OB, OC, OD, OE, OF, and OG ports of the 74LS84 decoder chip of the decoder circuit 4. By inputting a BCD code to the A, B, C, and D pins of the decoder, the corresponding digital display is obtained. For example, if the BCD code 0101 is input, the seven-segment digital display displays the number 5.

[0015] The beneficial effects of the utility model are:

[0016] The utility model provides a scoring device of a 555 timer and a counter, which can complete the scoring function with simple basic hardware and achieve the purpose of recording different scores by selecting the resistance value of an external parallel resistor connected to a monostable multivibrator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The utility model is a schematic diagram of the circuit principle of a 555 timer and a counter scorer device.

[0018] Figure 1 The numbers in the figure are: 1-555 monostable multivibrator circuit, 2-555 astable multivibrator circuit, 3-JK flip-flop 2-bit carry counter circuit, 4-decoder circuit, 5-seven-segment cathode ray tube, C1~C3-capacitors, R1~R6-resistors, S1~S4-switches, OR-logic OR gate, AND1~AND2-logic AND gates, NAND1~NAND2-logic NAND gates. DETAILED DESCRIPTION

[0019] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0020] Example 1: Figure 1 As shown, a 555 timer and counter scorer device includes a 555 monostable multivibrator circuit 1, a 555 astable multivibrator circuit 2, a JK trigger 2-bit carry counter circuit 3, a decoder circuit 4, and a seven-segment cathode ray tube 5;

[0021] The 555 monostable multivibrator circuit 1 includes a 555 timer chip 555I, switches S2, S3, S4, resistors R1, R2, R3, R4, and capacitors C1 and C2; the VSS and RSI ports of the 555 timer chip 555I are connected to the positive electrode of a 5V power supply, S2 is connected in series with R1, S3 is connected in series with R2, and S4 is connected in series with R3. The circuits after S2 and R1 are connected in series, the circuit after S3 and R2 are connected in series, and the circuit after S4 and R3 are connected in series are connected in parallel. One end of the parallel circuit is connected to the positive electrode of the power supply, and the other end is connected to the DIS port of the 555 timer. DIS is connected to the THR port and then to the ground through the capacitor C1. The CON port is connected to the decoupling capacitor C2 and then to the ground. TRI is an input port connected to the output of the logic OR gate OR. OUT is an output port connected to the input end of the logic AND gate AND1.

[0022] The 555 astable multivibrator circuit 2 includes a 555 timer chip 555Ⅱ, resistors R1, R5, R6, and a capacitor C3; the VSS and RSI ports of the 555 timer chip 555Ⅱ are connected to the positive electrode of the 5V power supply, one end of the resistor R5 is connected to the positive electrode of the power supply; the other end is connected to the DIS port, DIS is connected to TRI through the resistor R6, THR is connected to TRI, and then connected to the capacitor C3 and the ground level. The OUT of the 555 timer chip 555Ⅱ is the output terminal, the output terminal is connected to the input terminal of the logic OR gate OR, and the output terminal is also connected to the input terminal of the logic AND gate AND1.

[0023] The JK trigger 2-bit carry counter circuit 3 includes JK triggers JK1, JK2, JK3, JK4, JK5, JK6, JK7, JK8, a logic AND gate AND2, and NAND gates NAND1 and NAND2; the J and K ports of all JK triggers are connected to the positive pole of the power supply;

[0024] The CP port of the JK flip-flop JK1 is the input port, connected to the output port of the logic AND gate AND1, the output port Q of JK1 is connected to the A port of the decoder 74LS84Ⅱ and the CP port of JK2 respectively; the output port Q of JK2 is connected to the B port of the decoder 74LS84Ⅱ and the CP port of JK3 respectively, the output port Q of JK3 is connected to the C port of the decoder 74LS84Ⅱ and the CP port of JK4 respectively, and the output port Q of JK4 is connected to the D port of the decoder 74LS84Ⅱ;

[0025] Next is the reset carry part. The two input ends of the logic NAND gate NAND1 are connected to the Q-end output of JK2 and JK4 respectively, and the output is connected to the CLR port of JK flip-flops JK1, JK2, JK3, and JK4. The two input ends of the logic NAND gate NAND2 are connected to the Q-end output of JK6 and JK8 respectively, and the output is connected to the CLR port of JK flip-flops JK5, JK6, JK7, and JK8. The input ends of the logic AND gate AND2 are connected to the Q-end output of JK2 and JK4 respectively, and the output port is connected to the CP input port of JK5.

[0026] The decoder circuit 4 includes 74LS84 decoder chips 74LS84Ⅰ and 74LS84Ⅱ; wherein the A, B, C, and D ports of 74LS84Ⅱ and 74LS84Ⅰ are respectively connected to the Q port outputs of JK flip-flops JK1, JK2, JK3, JK4, JK5, JK6, JK7, and JK8 of the JK flip-flop 2-bit carry counter circuit 3, and the OA, OB, OC, OD, OE, OF, and OG ports are respectively connected to the A, B, C, D, E, F, and G ports of two seven-segment cathode ray tubes, and the LT, RBI, and BI / RBO ports of 74LS84Ⅰ and 74LS84Ⅱ are all connected to the positive pole of the power supply.

[0027] There are two seven-segment cathode ray tubes 5, and the CK ports of the two seven-segment cathode ray tubes are grounded. The A, B, C, D, E, F, and G ports of the seven-segment cathode ray tubes 5 are respectively connected to the OA, OB, OC, OD, OE, OF, and OG ports of the 74LS84 decoder chip of the decoder circuit 4.

[0028] In this embodiment, if the digital tube displays the number 02 at this time, the output end of the 555 astable multivibrator generates a regular square wave signal. Assume that the period is t (determined by the parameters of the external resistor and capacitor). In the 555 monostable multivibrator circuit, S4 is closed, S2 and S3 are opened, and then S1 is opened and closed again to generate a falling edge signal. After performing a logical AND operation with the regular square wave signal of the 555 astable multivibrator, the monostable multivibrator generates a rectangular wave signal synchronized with the square wave signal. The duration of the signal is calculated based on the capacitor C1 and the resistors R1, R2, and R3 controlled by the switches S2, S3, and S4. At this time, the duration of the rectangular wave is set to 3t. After the rectangular wave and square wave signals undergo logical OR operation, three square wave signals are output and connected to the counter circuit. The Q-end output of a group of JK1, JK2, JK3, and JK4 changes from 0, 1, 0, 0 to 1, 0, 1, 0. After inputting the A, B, C, and D of the decoder 74LS84Ⅱ, the output of the decoder 74LS84Ⅱ changes from 1101101 to 1011011, and the display of the digital tube II changes from 2 to 5, and finally displays 05.

[0029] Example 2: This example has the same structure as Example 1. When in use, if the digital tube displays the number 08 at this time, the output end of the 555 astable multivibrator generates a regular square wave signal. Assume that the period is t (determined by the parameters of the external resistor and capacitor). In the 555 monostable multivibrator circuit, close S3, open S2 and S4, and then open and close S1 to generate a falling edge signal. After performing a logical AND operation with the regular square wave signal of the 555 astable multivibrator, the monostable multivibrator generates a rectangular wave signal synchronized with the square wave signal. The duration of the signal is calculated based on the capacitor C1 and the resistors R1, R2, and R3 controlled by switches S2, S3, and S4. At this time, the duration of the rectangular wave is set to 2t. After the rectangular wave and square wave signals are logically ORed, two square wave signals are output and connected to the counter circuit. The Q-end outputs of a group of JK1, JK2, JK3, and JK4 change from 0, 0, 0, 1 to 0, 1, 0, 1. At this time, the two input pins of the logic AND gate are both high, and a square wave signal is output, which is connected to the CP port of the second group of JK5. The Q-end outputs of the two groups of triggers change from 0, 0, 0, 0 to 1, 0, 0, 0. After inputting the A, B, C, and D of the decoder 74LS84Ⅰ, the output of the decoder 74LS84Ⅰ changes from 1111110 to 0110000, and the display of the digital tube Ⅰ changes from 0 to 1. The two input pins of the logic NAND gate are both high, and the output is connected to the CLK terminal of JK1, JK2, JK3, and JK4, making them in a low state, clearing and resetting. The Q terminal of a group of flip-flops outputs 0, 0, 0, 0. After inputting the A, B, C, and D of the decoder 74LS84Ⅱ, the output of the decoder 74LS84Ⅱ changes from 1111111 to 1111110, and the digital tube II display changes from 8 to 0. The reset and carry function is completed, and the final display is 10.

[0030] The specific embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A scoring device based on a 555 timer and counter, characterized in that: The invention comprises a 555 monostable multivibrator circuit (1), a 555 astable multivibrator circuit (2), a JK trigger 2-bit carry counter circuit (3), a decoder circuit (4), and a seven-segment cathode ray tube (5); the output signals of the 555 monostable multivibrator circuit (1) and the 555 astable multivibrator circuit (2) are connected through a logic AND gate AND1, the calculated signals are input into the JK trigger 2-bit carry counter circuit (3), the signal output from the JK trigger 2-bit carry counter circuit (3) passes through a 74LS48 decoder circuit (4) and is displayed by the seven-segment cathode ray tube (5).

2. The scoring device based on 555 timer and counter according to claim 1, characterized in that: The 555 monostable multivibrator circuit (1) comprises a 555 timer chip 555I, switches S2, S3, S4, resistors R1, R2, R3, R4, and capacitors C1 and C2; the VSS and RSI ports of the 555 timer chip 555I are connected to the positive electrode of a 5V power supply, S2 is connected in series with R1, S3 is connected in series with R2, and S4 is connected in series with R3; the circuits after S2 and R1 are connected in series, the circuits after S3 and R2 are connected in series, and the circuits after S4 and R3 are connected in series are connected in parallel; one end of the parallel circuit is connected to the positive electrode of the power supply, and the other end is connected to the DIS port of the 555 timer; DIS is connected to the THR port, and then connected to the ground through the capacitor C1; the CON port is connected to the decoupling capacitor C2 and then connected to the ground; TRI is an input port, connected to the output of a logic OR gate OR; OUT is an output port, connected to the input end of a logic AND gate AND1.

3. The scoring device based on 555 timer and counter according to claim 2, characterized in that: The 555 astable multivibrator circuit (2) comprises a 555 timer chip 555Ⅱ, resistors R1, R5, R6, and a capacitor C3; the VSS and RSI ports of the 555 timer chip 555Ⅱ are connected to the positive electrode of a 5V power supply, one end of the resistor R5 is connected to the positive electrode of the power supply; the other end is connected to the DIS port, DIS is connected to TRI through the resistor R6, THR is connected to TRI, and then connected to the capacitor C3 and the ground level; the OUT of the 555 timer chip 555Ⅱ is the output terminal, the output terminal is connected to the input terminal of a logic OR gate OR, and the output terminal is also connected to the input terminal of a logic AND gate AND1.

4. The scoring device based on 555 timer and counter according to claim 1, characterized in that: The JK trigger 2-bit carry counter circuit (3) comprises JK triggers JK1, JK2, JK3, JK4, JK5, JK6, JK7, JK8, a logic AND gate AND2, and NAND gates NAND1 and NAND2; the J and K ports of all JK triggers are connected to the positive pole of the power supply; The CP port of the JK flip-flop JK1 is the input port, connected to the output port of the logic AND gate AND1, the output port Q of JK1 is connected to the A port of the decoder 74LS84Ⅱ and the CP port of JK2 respectively; the output port Q of JK2 is connected to the B port of the decoder 74LS84Ⅱ and the CP port of JK3 respectively, the output port Q of JK3 is connected to the C port of the decoder 74LS84Ⅱ and the CP port of JK4 respectively, and the output port Q of JK4 is connected to the D port of the decoder 74LS84Ⅱ; Next is the reset carry part. The two input ends of the logic NAND gate NAND1 are connected to the Q-end output of JK2 and JK4 respectively, and the output is connected to the CLR port of JK flip-flops JK1, JK2, JK3, and JK4. The two input ends of the logic NAND gate NAND2 are connected to the Q-end output of JK6 and JK8 respectively, and the output is connected to the CLR port of JK flip-flops JK5, JK6, JK7, and JK8. The input ends of the logic AND gate AND2 are connected to the Q-end output of JK2 and JK4 respectively, and the output port is connected to the CP input port of JK5.

5. The scoring device based on 555 timer and counter according to claim 1, characterized in that: The decoder circuit (4) includes 74LS84 decoder chips 74LS84Ⅰ and 74LS84Ⅱ; The A, B, C, and D ports of 74LS84Ⅱ and 74LS84Ⅰ are connected to the Q outputs of the JK flip-flops JK1, JK2, JK3, JK4, JK5, JK6, JK7, and JK8 of the JK flip-flop 2-bit carry counter circuit (3), respectively; the OA, OB, OC, OD, OE, OF, and OG ports are connected to the A, B, C, D, E, F, and G ports of the two seven-segment cathode ray tubes, respectively; and the LT, RBI, and BI / RBO ports of 74LS84Ⅰ and 74LS84Ⅱ are all connected to the positive pole of the power supply.

6. The scoring device based on 555 timer and counter according to claim 1, characterized in that: There are two seven-segment cathode ray tubes (5), the CK ports of the two seven-segment cathode ray tubes are both grounded, and the A, B, C, D, E, F, and G ports of the seven seven-segment cathode ray tubes (5) are respectively connected to the OA, OB, OC, OD, OE, OF, and OG ports of the 74LS84 decoder chip of the decoder circuit (4).

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