Vertical memory devices

Abstract

A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation application of U.S. Ser. No. 15 / 223,255, filed on Jul. 29, 2016, which claims priority under 35 USC § 119 to Korean Patent Application No. 10-2015-0150764, filed on Oct. 29, 2015, the disclosures of which are incorporated by reference herein in their entireties.TECHNICAL FIELD[0002]Exemplary embodiments of the inventive concept relate to vertical memory devices. More particularly, exemplary embodiments of the inventive concept relate to vertical memory devices including vertically stacked gate lines.DISCUSSION OF THE RELATED ART[0003]A vertical memory device including a plurality of memory cells stacked vertically with respect to a surface of a substrate has been developed for achieving a high degree of integration. In the vertical memory device, a channel having a pillar shape or a cylindrical shape may protrude vertically from the surface of the substrate, and gate lines and insulation layers surroundi...

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