A signal processor, radar system and signal processing method

Abstract

The present application discloses a signal processor, a radar system and a signal processing method for detecting foreign objects in a test area. The radar system includes a signal processor and a radio frequency system. The radio frequency system is used to send a radar detection signal to the test area, receive a radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor. The signal processor is used to process the radar echo signal to obtain a foreign object detection result in the test area. The radar system detects foreign objects in the test area without being affected by weather conditions and lighting conditions. Even if the weather is bad or the light is insufficient, it can still efficiently and accurately detect foreign objects in the test area. The detection reliability is very high, which effectively improves the safety of the test area. The signal processor uses a combination of FPGA and ARM processors to process the radar echo signal, which saves the cost of the signal processor and is conducive to the engineering realization and application of the signal processor and the radar system.

Description

Technical Field

[0001] The present application relates to the field of radar detection technology, and in particular to a signal processor, a radar system and a signal processing method. Background Art

[0002] Foreign object detection on airport runways is an important part of airport security construction. Foreign objects on airport runways often cause very serious harm. For example, foreign objects on the runway may be sucked into the aircraft engine, causing engine failure, accidents, or interfering with the pilot's vision. At present, airports in my country rely on manual inspections of runways and human eyes to search for foreign objects. This method is inefficient and unreliable, and it occupies more precious runway use time, resulting in a forced reduction in the number of flights.

[0003] Currently, there are methods of detecting foreign objects on the runway using optical equipment such as cameras, but this detection method is easily affected by weather conditions and lighting. The detection performance decreases at night or in bad weather conditions, and foreign objects with similar colors cannot be detected. Summary of the invention

[0004] Based on the above problems, the present application provides a signal processor, a radar system and a signal processing method to provide a radar system that is resistant to interference from weather conditions and lighting conditions, and to achieve efficient detection of foreign objects in the scene.

[0005] The embodiments of the present application disclose the following technical solutions:

[0006] In a first aspect of the present application, a signal processor is provided, which is applied to foreign body detection in a test area, and the signal processor comprises:

[0007] A field programmable gate array FPGA, wherein the FPGA is integrated with an ARM processor;

[0008] The FPGA is used to preprocess the radar echo signal from the radio frequency system to obtain the preprocessed signal; the radio frequency system is used to send the radar detection signal to the area to be measured, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor;

[0009] The ARM processor is used to perform constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map to obtain a foreign object detection result in the area to be tested; the clutter map is generated according to radar scanning data when the area to be tested does not contain foreign objects.

[0010] Optionally, the ARM processor is connected to a first memory and a second memory; the first memory communicates with the ARM processor via a first serial peripheral interface, and the second memory communicates with the ARM processor via a second serial peripheral interface;

[0011] The first memory is used to store the program of the FPGA and the program of the ARM processor; the FPGA is also used to read the program of the FPGA from the first memory and execute the program of the FPGA to realize the logic control of the signal processor and the preprocessing of the radar echo signal; the ARM processor is also used to read the program of the ARM processor from the first memory and execute the program of the ARM processor to perform constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be tested;

[0012] The second memory is used to store the clutter map.

[0013] Optionally, the signal processor further comprises: an analog-to-digital converter ADC and a direct digital frequency synthesizer DDS;

[0014] The ADC communicates with the FPGA via a third serial peripheral interface;

[0015] The DDS communicates with the FPGA via a fourth serial peripheral interface;

[0016] The FPGA is also used to control the selection of the working modes of the ADC and the DDS, and to configure working parameters for the ADC and the DDS;

[0017] The DDS is used to send a linear frequency modulation signal to the radio frequency system according to the control of the FPGA, so that the radio frequency system sends the radar detection signal to the area to be measured according to the linear frequency modulation signal;

[0018] The ADC is used to sample the radar echo signal to obtain a digital signal, and send the digital signal to the FPGA;

[0019] The FPGA is specifically used to perform logic control on the signal processor and preprocess the digital signal to obtain the preprocessed signal.

[0020] Optionally, the FPGA is connected to a third memory;

[0021] The FPGA is used to transmit the preprocessed signal to the third memory;

[0022] The third memory is used to store the preprocessed signal;

[0023] The ARM processor is specifically used to read the preprocessed signal from the third memory, perform constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map, obtain the foreign body detection result of the test area; and upload the foreign body detection result to the server.

[0024] Optionally, the signal processor further comprises: a first clock chip, a second clock chip and a crystal oscillator;

[0025] The first clock chip is used to provide a synchronous clock signal for the ADC, the DDS and the FPGA;

[0026] The second clock chip is used to provide a working clock signal for the ARM processor and the third memory;

[0027] The crystal oscillator is used to provide a working clock signal for the FPGA.

[0028] Optionally, the signal processor also includes: an FPGA power supply, an ADC power supply, a DDS power supply, a first clock chip power supply and a second clock chip power supply.

[0029] Optionally, the signal processor further includes: a reset chip and / or a reset button;

[0030] The reset chip is used to monitor the power-on status of the power supplies in the signal processor, and send a first power-on reset signal to the FPGA when all the power supplies are started;

[0031] The reset button is used to respond to a user's operation trigger and send a second power-on reset signal to the FPGA;

[0032] The FPGA is further used to control the reset of all chips according to the received first power-on reset signal or the second power-on reset signal.

[0033] Optionally, the ARM processor includes a first ARM and a second ARM; wherein the first ARM is used to run an Ethernet driver so that the signal processor uploads the foreign object detection result to the server via the Ethernet; the second ARM is used to perform logical operations, perform constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map, and obtain the foreign object detection result of the area to be tested.

[0034] In a second aspect of the present application, a radar system is provided, which is applied to foreign object detection in a detection area, and the system comprises: the signal processor provided in the first aspect, and further comprises: a radio frequency system;

[0035] The radio frequency system is used to send a radar detection signal to the area to be measured, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor;

[0036] The signal processor is used to process the radar echo signal to obtain the foreign body detection result of the area to be detected.

[0037] In a third aspect of the present application, a signal processing method is provided, which is applied to foreign body detection in a test area, and the method comprises:

[0038] The radar echo signal from the radio frequency system is preprocessed by using the FPGA of the signal processor to obtain the preprocessed signal; the radio frequency system is used to send a radar detection signal to the area to be measured, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor; the FPGA is integrated with an ARM processor;

[0039] The ARM processor is used to perform constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map to obtain a foreign object detection result in the area to be tested; the clutter map is generated according to radar scanning data when the area to be tested does not contain foreign objects.

[0040] Compared with the prior art, this application has the following beneficial effects:

[0041] The radar system provided in the embodiment of the present application is applied to the detection of foreign objects in the area to be tested, and the radar system includes a signal processor and a radio frequency system. Among them, the radio frequency system is used to send a radar detection signal to the area to be tested, receive a radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor. The signal processor is used to process the radar echo signal to obtain the foreign object detection result of the area to be tested. When the radar system detects foreign objects in the area to be tested, it is not affected by weather conditions and lighting conditions. Even if the weather is bad or the light is insufficient, it can still efficiently and accurately detect foreign objects in the area to be tested. Therefore, the detection reliability is very high, which effectively improves the safety of the area to be tested.

[0042] The signal processor specifically includes: a field programmable gate array FPGA, on which an ARM processor is integrated. Among them, the FPGA is responsible for the logic control of the signal processor, and preprocessing the radar echo signal from the radio frequency system to obtain the preprocessed signal; the ARM processor is responsible for constant false alarm rate processing of the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the test area. The signal processor uses a combination of FPGA and ARM processor to realize the processing of radar echo signals, which saves the cost of the signal processor, and is conducive to the engineering realization and application of the signal processor and the radar system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 A schematic diagram of the structure of a radar system provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of the structure of a signal processor provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of the structure of another signal processor provided in an embodiment of the present application;

[0047] Figure 4 A flowchart of a signal processing method provided in an embodiment of the present application;

[0048] Figure 5 A flowchart of another signal processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] As described above, some scenes with high safety requirements can usually use manual methods or optical equipment detection methods to achieve foreign object detection to ensure safety within the scene, but these two methods have their own defects. The manual method is inefficient and has poor reliability; the optical equipment detection method is easily affected by weather conditions and lighting conditions. Under the premise of bad weather conditions or lighting conditions, it is difficult to accurately detect foreign objects, so the reliability is volatile.

[0050] Based on this problem, the inventor has provided a radar system after research, which can overcome the interference of weather conditions and lighting conditions and achieve efficient detection of foreign objects on the scene.

[0051] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] See also Figure 1 , which is a schematic diagram of the structure of a radar system provided in an embodiment of the present application.

[0053] like Figure 1 As shown, the radar system provided in this embodiment includes: a radio frequency system 101 and a signal processor 102. The radar system is used to detect foreign objects in a detection area.

[0054] In this embodiment, interactive transmission of signals can occur between the radio frequency system 101 and the signal processor 102 .

[0055] The radio frequency system 101 is used to send a radar detection signal to the area to be detected, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor.

[0056] As an example, the RF system 101 may include: a transmitting antenna, a receiving antenna, a front-end subsystem, and an intermediate frequency subsystem. Among them, the transmitting antenna is used to send a radar detection signal to the area to be measured; the receiving antenna is used to receive a radar echo signal corresponding to the radar detection signal. During the rotation of the turntable controlled by the FPGA, a radar scan of the area to be measured is realized. The front-end subsystem performs preliminary processing on the radar echo signal received by the receiving antenna to obtain a first intermediate frequency signal. Since the intermediate frequency subsystem can receive the first intermediate frequency signal sent by the front-end subsystem for processing to generate a second intermediate frequency signal, as a possible implementation method, in this embodiment, the radar echo signal sent by the RF system 101 and received by the signal processor 102 may specifically refer to the second intermediate frequency signal sent by the intermediate frequency subsystem to the signal processor 102.

[0057] The signal processor 102 is used to process the radar echo signal to obtain the foreign body detection result of the detection area. Figure 2 The structural composition of the signal processor 102 is described.

[0058] See also Figure 2 , which is a structural schematic diagram of a signal processor provided in an embodiment of the present application.

[0059] like Figure 2As shown, the signal processor includes: a Field-Programmable Gate Array (FPGA), wherein the FPGA integrates an Advanced RISC Machine (ARM) processor. In this embodiment, as an example, the model of the FPGA may be FPGA Z7; the model of the ARM processor may be ARMcortex A9.

[0060] Of course, in practical applications, other types of FPGA and ARM processors may be integrated to realize the functions of the signal processor, so the specific types of FPGA and ARM are not limited here.

[0061] In the signal processor, FPGA is used to pre-process the radar echo signal from the radio frequency system to obtain the pre-processed signal;

[0062] The ARM processor is used to perform constant false alarm rate (CFAR) processing on the pre-processed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be tested.

[0063] In practical applications, as an example, the preprocessing operations of FPGA on radar echo signals may specifically include: digital down-conversion, filtering, extraction, coherent accumulation, windowed fast Fourier transform (FFT), complex modulus squaring, non-coherent accumulation, etc.

[0064] It should be noted that, in the present embodiment, the clutter map is generated by the radar system based on the radar scanning data of the current area to be tested without foreign objects in the pre-scanned state. It can be understood that the clutter map is a reference for detecting foreign objects, and the foreign object target in the area to be tested can be better determined based on the clutter map. The ARM processor performs constant false alarm rate processing on the pre-processed signal according to the pre-generated clutter map, specifically, using the CFAR algorithm to compare the pre-processed signal with the clutter map. For those skilled in the art, how to apply the CFAR algorithm is a relatively mature technology, so the specific process of ARM performing constant false alarm rate processing is not described in detail here.

[0065] ARM can extract relevant information about foreign objects in the area to be tested, such as the distance information and angle information of the foreign objects relative to the radar, by performing constant false alarm rate processing on the pre-processed signal according to the pre-generated clutter map, so that the foreign object detection result in the area to be tested can be obtained based on these relevant information about the foreign objects. When the user applies the radar system, based on the premise that the radar position is known, the foreign objects in the area to be tested can be efficiently and accurately located based on the distance information and angle information of the foreign objects relative to the radar contained in the foreign object detection result.

[0066] The above is the radar system provided in the embodiment of the present application. The system is applied to the detection of foreign objects in the area to be tested. When detecting foreign objects in the area to be tested, it is not affected by weather conditions and lighting conditions. Even if the weather is bad or the light is insufficient, it can still efficiently and accurately detect foreign objects in the area to be tested. Therefore, the detection reliability is very high, which effectively improves the safety of the area to be tested.

[0067] Although the signal processor can be implemented by using digital signal processing (DSP) technology, the versatility of the DSP external interface is poor, resulting in its inflexible control of the radar system. In addition, the signal processor based on DSP is often expensive. FPGA has a much better logic control capability than DSP, but the algorithm complexity of the signal processor function that completely relies on FPGA is very high, and the requirements for on-chip resources are very high, resulting in high cost and long development cycle, which is not suitable for engineering implementation and application. In the radar system provided in this embodiment, the signal processor uses a combination of FPGA and ARM processor to realize the processing of radar echo signals. FPGA has powerful logic control capabilities and high flexibility; ARM processor has high-speed signal processing capabilities and low power consumption. Compared with the signal processor based on DSP and the signal processor that completely relies on FPGA, the signal processor provided in this embodiment has a lower cost, which is conducive to the engineering implementation and application of the signal processor and the radar system.

[0068] On the basis of the signal processor provided in the aforementioned embodiment, the present application further provides another signal processor, which is described and introduced below in conjunction with the accompanying drawings.

[0069] See also Figure 3 , which is a schematic diagram of the structure of another signal processor provided in an embodiment of the present application.

[0070] like Figure 3 As shown, in the signal processor, the ARM processor is connected to a first memory and a second memory. The first memory communicates with the ARM processor via a first serial peripheral interface SPI-1, and the second memory communicates with the ARM processor via a second serial peripheral interface SPI-2.

[0071] As an example, both the first memory and the second memory may be non-volatile storage media. For example, the first memory may be a load SPI-FLASH; and the second memory may be a data SPI-FLASH.

[0072] The first memory is used to store the FPGA program and the ARM processor program; the FPGA is also used to read the FPGA program from the first memory and execute the FPGA program to realize the logic control of the signal processor and the preprocessing of the radar echo signal; the ARM processor is also used to read the ARM processor program from the first memory and execute the ARM processor program to perform constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be tested;

[0073] The second memory is used to store the pre-generated clutter map mentioned above.

[0074] In practical applications, since important chip operating programs are stored in the first memory, in order to ensure the safe and effective use of the programs, the internal space of the first memory can be divided into two parts, one part is used to store the FPGA program and the ARM processor program for normal working use; the other part is used to store the backup program, so that when facing problems such as program loading failure, the FPGA and ARM processor can automatically load the backup program to ensure the normal use of the signal processor function and the normal operation of the radar system.

[0075] In addition, the signal processor in this embodiment also includes a chip with analog functions, which is used to complete ADC data collection and data playback functions. Figure 3 The analog-to-digital converter ADC and the direct digital frequency synthesizer DDS shown in the figure communicate with the FPGA via a third serial peripheral interface SPI-3; and the DDS communicates with the FPGA via a fourth serial peripheral interface SPI-4.

[0076] In this embodiment, as an example, a high-performance ADC and a high-speed current-type output DDS from Analog Devices can be used, wherein the analog bandwidth of the ADC is 500MHz, and the maximum sampling rate of a single chip single channel is 65Msps. Each ADC includes 2 channels of 16-bit quantization, and has two analog inputs. The ADC is connected to the FPGA through 16 pairs of low voltage differential signaling (LVDS) data lines. The DDS board supports 1-channel data playback, supports 12-bit resolution, and the maximum playback speed of a single channel is 2.4Gsps.

[0077] The FPGA is also used to control the selection of the working modes of the ADC and the DDS, and to configure the working parameters for the ADC and the DDS. The DDS can support the following five working modes: single-tone modulation, contour modulation, digital slope modulation, parallel interface modulation, and programmable analog-to-digital mode. It should be noted that these working modes can be compatible at the same time. There is a certain priority protocol inside the DDS chip. When several functions are enabled at the same time, the mode selection is performed in the following order: programmable analog-to-digital mode, digital slope modulation, contour modulation, and parallel interface modulation. In this embodiment, the single-tone modulation mode can be set by default.

[0078] In practical applications, the signal processor can realize signal conversion and transmission between FPGA and RF system through a chip with analog function. Before the radar scans the area to be tested, the FPGA sends a control signal to the DDS, and the DDS is used to send a linear frequency modulation (LFM) signal to the RF system according to the control of the FPGA, so that the RF system sends the radar detection signal to the area to be tested according to the linear frequency modulation signal.

[0079] As an analog signal, the radar echo signal can be sampled by the ADC to obtain a digital signal, and the digital signal can be sent to the FPGA; the FPGA specifically preprocesses the digital signal to obtain the preprocessed signal.

[0080] In this embodiment, the FPGA can also be mounted with a third memory, and the FPGA is used to transmit the preprocessed signal (also known as: one-dimensional range image) to the third memory, and the third memory is used to store it. As an example, the third memory can use the third-generation double-data-rate dynamic random access memory (Double-Data-Rate Three SynchronousDynamic Random Access Memory, DDR3 SDRAM). When the ARM processor needs to process the preprocessed signal, the preprocessed signal is directly read from the third memory, the data of the clutter map is read from the second memory, and the preprocessed signal is processed at a constant false alarm rate according to the clutter map to obtain the foreign body detection result of the test area.

[0081] Optionally, in this embodiment, after the ARM processor obtains the foreign object detection result, it can also upload the foreign object detection result to the server, so that the user can promptly remove the foreign objects in the area to be tested according to the foreign object detection result in the server, thereby eliminating the safety hazards in the area to be tested.

[0082] The signal processor can be divided into two modules, namely, the processing system (PS) module and the programmable logic (PL) module. In this embodiment, the FPGA is the PL module and the ARM processor is the PS module. For example, the PS module controls the PL module to pre-process the radar echo signal from the RF system, and the pre-processed signal is stored in the third memory.

[0083] See also Figure 3 The signal processor also includes multiple parts that provide clock signals, which are used to provide synchronous clocks and working clocks for FPGA and analog chips, including: a first clock chip, a second clock chip and a crystal oscillator.

[0084] Wherein, the first clock chip is used to provide a synchronous clock signal for the ADC, the DDS and the PL module (i.e., FPGA);

[0085] The second clock chip is used to provide a working clock signal for the PS module (i.e., the ARM processor) and the third memory;

[0086] The crystal oscillator is used to provide a working clock signal for the PL module.

[0087] In this embodiment, the first clock chip can provide a 32 MHz clock signal for the ADC, a 2.048 GHz clock signal for the DDS, and a 32 MHz synchronous clock signal for the FPGA.

[0088] In addition, the signal processor may also include various power supplies for providing working power for each chip of the signal processor. Specifically, the signal processor includes: FPGA power supply, ADC power supply, DDS power supply, first clock chip power supply and second clock chip power supply. Among them, the FPGA power supply includes: power supplies for the PS module, PL module and GTX interface; the ADC power supply includes: ADC core voltage and digital I / O voltage; the DDS power supply includes: digital I / O voltage, digital voltage and analog voltage.

[0089] In addition, the signal processor in this embodiment can also realize a reset function. The signal processor can also include: a reset chip and / or a reset button. The specific functions of the reset chip and the reset button are described below.

[0090] The reset chip is used to monitor the power-on status of the power supplies in the signal processor, and when all the power supplies are started, a first power-on reset signal is sent to the FPGA. The first power-on reset signal is used to instruct the FPGA to control all chips to reset. As a possible implementation, the SM706T chip can be selected as the reset chip in this embodiment to implement the above function.

[0091] The reset button is used to respond to the user's operation trigger and send a second power-on reset signal to the FPGA. Similarly, the second power-on reset signal is also used to instruct the FPGA to control all chips to reset. In other words, the reset button can be used to achieve manual reset by the user.

[0092] Then, the FPGA can send a control signal to all chips of the signal processor to control the reset of each chip according to the received first power-on reset signal or the second power-on reset signal, so as to meet the reset use requirements of the user.

[0093] As mentioned above, an ARM processor is integrated on the FPGA in the signal processor. In practical applications, the specific number of ARM processors is not limited. As an example, the ARM processor may include: a first ARM and a second ARM. Among them, the first ARM is specifically used to run the Ethernet driver so that the signal processor uploads the foreign body detection result to the server through the Ethernet interface; the second ARM is specifically used to perform logical operations, that is, to perform constant false alarm rate processing on the pre-processed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be tested.

[0094] It is understandable that the signal processor includes multiple interfaces to respectively realize the external control, data transmission and communication functions of the signal processor. Specifically, it includes at least 5 analog interfaces, namely: 2 AD inputs, 1 DDS output, 1 reference clock input, and 1 direct clock input. The signal processor also includes multiple external control interfaces, such as RS422 interface and TTL interface. The external control interface can share a J30 connector. In addition, there are two CAN bus interfaces for the transmission of control signals. And a Gigabit Ethernet interface located in the ARM processor part for data transmission to the server.

[0095] The signal processors provided above can all be applied to the radar system described above, providing it with strong signal processing capabilities. The signal processor can complete the real-time processing of a large amount of data, and plays an important role in the research of radar systems that perform field foreign object detection. The radar system uses FPGA as the architecture core of the system and signal processor, and can integrate one or more ARMs to give full play to the powerful logic control capabilities and flexibility of FPGA and the high-speed signal processing capabilities and low power consumption characteristics of ARM. FPAG completes the logic and timing control, signal acquisition, communication, transmission and signal preprocessing of the radar system; ARM as the core completes the algorithm operation and specific processing of radar echo signals. The ARM core has more resources and the frequency can be as high as 2GHz, while still maintaining ultra-low power consumption, so it can process signals more efficiently and quickly, and significantly reduce power consumption. In addition, the entire signal processor can be integrated in a single board to miniaturize the digital signal machine and reduce space occupancy.

[0096] In addition, the third memory is connected to the FPGA to transfer the pre-processed signal to the third memory, so that the ARM processor can directly read the pre-processed signal for further processing, which makes data transmission faster and more efficient compared to the previously used bus. In addition, a program backup function is designed in the first memory. When a program fails to load, the backup program can be directly loaded to ensure the normal operation of the system.

[0097] In general, compared with the existing technology, the use of this signal processor can effectively reduce the cost of signal processing, and at the same time is conducive to the engineering realization of the signal processor and related radar systems, solving foreign object detection problems in more scenarios.

[0098] Based on the signal processor and radar system provided in the aforementioned embodiments, the present application also provides a signal processing method accordingly. The specific implementation of the method is described and illustrated below in conjunction with the embodiments and drawings.

[0099] See also Figure 4 , which is a flow chart of a signal processing method provided in an embodiment of the present application. The method is applied to foreign body detection in a detection area.

[0100] like Figure 4 As shown, the signal processing method provided in this embodiment includes:

[0101] Step 401: Preprocess the radar echo signal from the radio frequency system using the FPGA of the signal processor to obtain a preprocessed signal.

[0102] It should be noted that, in this embodiment, the radio frequency system refers to the radio frequency system in the radar system of the aforementioned embodiment. The radio frequency system is used to send a radar detection signal to the area to be detected, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor.

[0103] As described in the above embodiment, an ARM processor is integrated on the FPGA. The operation in step 402 can be completed using the ARM processor.

[0104] Step 402: using the ARM processor to perform constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be detected.

[0105] It should be noted that, in this embodiment, the clutter map is generated based on radar scanning data when the area to be measured does not contain foreign matter.

[0106] The above is the signal processing method for radar echo signals provided in the embodiment of the present application. The method can be specifically applied to the radar system to detect foreign objects in the test area. The method is not affected by weather conditions and lighting conditions during use. Even in bad weather or insufficient lighting, it can still efficiently and accurately obtain foreign object detection results and detect the position and angle of foreign objects in the test area relative to the radar. Therefore, the detection reliability is very high, which effectively improves the safety of the test area.

[0107] In addition, the method is based on the use of a signal processor in a radar system. The signal processor specifically includes a field programmable gate array FPGA, and an ARM processor is integrated on the FPGA. Among them, the FPGA is responsible for preprocessing the radar echo signal from the radio frequency system to obtain the preprocessed signal; the ARM processor is responsible for performing constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the test area. The signal processor uses a combination of FPGA and ARM processor to realize the processing of radar echo signals, so the use of this method for signal processing saves costs, which is conducive to the engineering realization and application of the signal processor and the radar system.

[0108] For ease of understanding, the following describes various possible implementations of the signal processor provided in the foregoing embodiments. Figure 5 Steps 501-509 in the figure describe in detail another signal processing method based on the signal processor.

[0109] like Figure 5 As shown, the signal processing method includes:

[0110] 501: After the signal processor board is powered on, the crystal oscillator and the second clock chip provide working clock signals respectively to start the FPGA and the ARM processor.

[0111] 502: The ARM processor reads the program from the first memory.

[0112] 503: The first clock chip multiplies the reference clock provided by the radio frequency system, and then divides the reference clock to the FPGA, ADC and DDS to provide a synchronous clock.

[0113] 504: FPGA sends control signals to the power supply and the turntable respectively, and the radar system starts to work.

[0114] 505: The FPGA controls the selection of the working mode of the ADC through the third serial peripheral interface SPI-3 and configures the working parameters for the ADC; the FPGA controls the selection of the working mode of the DDS through the fourth serial peripheral interface SPI-4 and configures the working parameters for the DDS.

[0115] 506: The ADC performs AD sampling on the radar echo signal provided by the radio frequency system to obtain a digital signal, and then pre-processes the digital signal on the FPGA to obtain a pre-processed signal.

[0116] 507: Store the preprocessed signal in a third memory.

[0117] 508: The ARM processor reads the preprocessed signal from the third memory, and performs constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be detected.

[0118] 509: The signal processor reports the foreign body detection result to the server.

[0119] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0120] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A signal processing machine, characterized in that: Applied to foreign body detection in the area to be tested, the signal processor comprises: A field programmable gate array FPGA, wherein the FPGA is integrated with an ARM processor; The FPGA is used to preprocess the radar echo signal from the radio frequency system to obtain the preprocessed signal; the radio frequency system is used to send the radar detection signal to the area to be measured, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor; The ARM processor is used to perform constant false alarm rate processing on the pre-processed signal according to a pre-generated clutter map to obtain a foreign object detection result of the area to be tested; the clutter map is generated according to radar scanning data when the area to be tested does not contain foreign objects; The ARM processor is connected to a first memory and a second memory; the first memory communicates with the ARM processor via a first serial peripheral interface, and the second memory communicates with the ARM processor via a second serial peripheral interface; The first memory is used to store the program of the FPGA and the program of the ARM processor; the FPGA is also used to read the program of the FPGA from the first memory and execute the program of the FPGA to realize the logic control of the signal processor and the preprocessing of the radar echo signal; the ARM processor is also used to read the program of the ARM processor from the first memory and execute the program of the ARM processor to perform constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be tested; The second memory is used to store the clutter map; The FPGA is connected to a third memory; The FPGA is used to transmit the preprocessed signal to the third memory; The third memory is used to store the preprocessed signal; The ARM processor is specifically used to read the preprocessed signal from the third memory, perform constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map, obtain the foreign body detection result of the test area; and upload the foreign body detection result to the server.

2. The signal processor according to claim 1, characterized in that Also includes: Analog-to-digital converter ADC and direct digital frequency synthesizer DDS; The ADC communicates with the FPGA via a third serial peripheral interface; The DDS communicates with the FPGA via a fourth serial peripheral interface; The FPGA is also used to control the selection of the working modes of the ADC and the DDS, and to configure working parameters for the ADC and the DDS; The DDS is used to send a linear frequency modulation signal to the radio frequency system according to the control of the FPGA, so that the radio frequency system sends the radar detection signal to the area to be measured according to the linear frequency modulation signal; The ADC is used to sample the radar echo signal to obtain a digital signal, and send the digital signal to the FPGA; The FPGA is specifically used to perform logic control on the signal processor and preprocess the digital signal to obtain the preprocessed signal.

3. The signal processor according to claim 1, characterized in that: The signal processor also includes: a first clock chip, a second clock chip and a crystal oscillator; The first clock chip is used to provide a synchronous clock signal for the ADC, the DDS and the FPGA; The second clock chip is used to provide a working clock signal for the ARM processor and the third memory; The crystal oscillator is used to provide a working clock signal for the FPGA.

4. The signal processing machine according to claim 3, characterized in that: Also includes: FPGA power supply, ADC power supply, DDS power supply, first clock chip power supply and second clock chip power supply.

5. The signal processor according to claim 4, characterized in that Also includes: Reset chip and / or reset button; The reset chip is used to monitor the power-on status of the power supplies in the signal processor, and when all the power supplies are started, sends a first power-on reset signal to the FPGA; The reset button is used to respond to a user's operation trigger and send a second power-on reset signal to the FPGA; The FPGA is further used to control all chips to reset according to the received first power-on reset signal or the second power-on reset signal.

6. The signal processor according to any one of claims 1 to 5, characterized in that: The ARM processor includes a first ARM and a second ARM; wherein the first ARM is used to run an Ethernet driver so that the signal processor uploads the foreign object detection result to the server via the Ethernet; the second ARM is used to perform logical operations, perform constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map, and obtain the foreign object detection result of the area to be tested.

7. A radar system, characterized in that: Applicable to foreign body detection in a test area, the system comprises: the signal processor according to any one of claims 1 to 6, and further comprising: a radio frequency system; The radio frequency system is used to send a radar detection signal to the area to be measured, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor; The signal processor is used to process the radar echo signal to obtain the foreign body detection result of the area to be detected.

8. A signal processing method, characterized in that: Applied to foreign body detection in a test area, the method comprises: The radar echo signal from the radio frequency system is preprocessed by using the FPGA of the signal processor to obtain the preprocessed signal; the radio frequency system is used to send a radar detection signal to the area to be measured, receive the radar echo signal corresponding to the radar detection signal, and send the radar echo signal to the signal processor; the FPGA is integrated with an ARM processor; Using the ARM processor to perform constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map, to obtain a foreign object detection result of the area to be tested; the clutter map is generated according to radar scanning data when the area to be tested does not contain foreign objects; The ARM processor is connected to a first memory and a second memory; the first memory communicates with the ARM processor via a first serial peripheral interface, and the second memory communicates with the ARM processor via a second serial peripheral interface; the first memory is used to store the program of the FPGA and the program of the ARM processor; the second memory is used to store the clutter map; The method of using the FPGA of the signal processor to preprocess the radar echo signal from the radio frequency system to obtain the preprocessed signal includes: Using the FPGA to read the FPGA program from the first memory, and executing the FPGA program to implement logic control of the signal processor and preprocessing of the radar echo signal to obtain a preprocessed signal; The method of using the ARM processor to perform constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be tested includes: Using the ARM processor, reading a program of the ARM processor from the first memory, and executing the program of the ARM processor to perform constant false alarm rate processing on the pre-processed signal according to a pre-generated clutter map stored in the second memory, to obtain a foreign body detection result of the area to be detected; When the FPGA is connected to a third memory, the FPGA of the signal processor is used to pre-process the radar echo signal from the radio frequency system, and after obtaining the pre-processed signal, the method further includes: Using the FPGA, transmitting the preprocessed signal to the third memory; the third memory is used to store the preprocessed signal; The method of using the ARM processor to perform constant false alarm rate processing on the preprocessed signal according to the pre-generated clutter map to obtain the foreign body detection result of the area to be tested includes: Using the ARM processor, reading the preprocessed signal from the third memory, performing constant false alarm rate processing on the preprocessed signal according to a pre-generated clutter map, and obtaining a foreign body detection result of the area to be detected; After the ARM processor is used to perform constant false alarm rate processing on the pre-processed signal according to the pre-generated clutter map to obtain the foreign body detection result of the test area, the method further includes: The foreign body detection result is uploaded to the server.

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