Semiconductor devices

Abstract

The present invention prevents erroneous detection of an overcurrent state when the power supply voltage decreases during normal operation and ensures operability. The semiconductor device (S) comprises: a power semiconductor switch element (1) for driving a load (2); a comparison circuit (3) for comparing the output voltage value of the power semiconductor switch element with a threshold value indicating an overcurrent state and outputting the comparison result as a judgment signal to a control circuit; a filter circuit (4) for outputting a judgment signal to the control circuit after a delay time from when the power semiconductor switch element is turned on to when the output voltage of the power semiconductor switch element rises to a predetermined voltage value judged as normal conduction; and a false detection prevention circuit (11, 21, 31, 41) for changing the turn-on time, delay time or voltage value of the judgment signal of the power semiconductor switch element when the voltage of the power supply VCC decreases when the power semiconductor switch element is normally turned on, thereby preventing the control circuit from erroneously detecting an overcurrent state.

Description

Technical Field

[0001] The present invention relates to a semiconductor device for driving a load, and more particularly to a semiconductor device that prevents erroneous detection of an overcurrent state and ensures operability when a power supply voltage drops during normal operation. Background Art

[0002] Regarding semiconductor devices that drive loads using power from a power supply through the switching action of power semiconductor switching elements, there are semiconductor devices with protection functions to prevent element damage caused by overcurrent flowing through the power semiconductor switching elements (for example, refer to patent documents 1 and 2).

[0003] In this semiconductor device, whether an overcurrent flows through the power semiconductor switch element is determined based on whether the output voltage value of the power semiconductor switch element is higher than a predetermined threshold or lower than a predetermined threshold. However, at the beginning of the power semiconductor switch element being turned on, since its output voltage is lower than the predetermined voltage value that will be judged as being normally turned on, if a judgment is made in this state, it may be mistakenly judged as not being normally turned on, that is, an overcurrent state may be mistakenly detected. Therefore, a filter for setting a delay time is applied, and after the delay time has passed since the power semiconductor switch element was turned on, that is, after it rises to the predetermined voltage value that will be judged as the output voltage being normally turned on, the comparison result between the output voltage value and the threshold is output to the control circuit side that makes the judgment.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-138521

[0007] Patent Document 2: International Publication No. 2016 / 143382 Summary of the invention

[0008] Technical issues

[0009] However, in normal operation, the power supply voltage itself may drop due to some reason. In this case, after the delay time set by the filter, the output voltage of the power semiconductor switch element will not rise to the predetermined voltage value that is judged to be normally turned on, so an overcurrent state may be falsely detected, and the semiconductor device as a whole cannot work normally.

[0010] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that prevents erroneous detection of an overcurrent state and ensures operability when a power supply voltage drops during normal operation.

[0011] Technical Solution

[0012] In order to achieve the above-mentioned object, a semiconductor device according to one aspect of the present invention includes a power semiconductor switching element that drives a load with power from a power supply by switching, and outputs a judgment signal for the detection to a control circuit that detects whether the power semiconductor switching element is normally turned on, the semiconductor device including:

[0013] a comparison circuit that compares the value of the output voltage of the power semiconductor switch element with a threshold value indicating an overcurrent state of the power semiconductor switch element and outputs the comparison result as the judgment signal;

[0014] a filter circuit provided on the output side of the comparison circuit, and outputting the judgment signal to the control circuit after a delay time, the delay time being a time from when the power semiconductor switch element is turned on until the output voltage of the power semiconductor switch element rises to a predetermined voltage value to be judged as normal conduction; and

[0015] A circuit for preventing false detection, which prevents false detection of an overcurrent state in the control circuit by changing the turn-on time of the power semiconductor switch element, the delay time or the voltage value of the judgment signal when the voltage of the power supply decreases when the power semiconductor switch element is normally turned on.

[0016] In a semiconductor device that drives a load by switching a power semiconductor switch element, by comparing the output voltage value of the power semiconductor switch element with a predetermined threshold value, it is detected whether an overcurrent is flowing in the power semiconductor switch element, thereby preventing the element damage of the power semiconductor switch element caused by the overcurrent. At the beginning of the power semiconductor switch element being turned on, its output voltage value is lower than the predetermined voltage value that will be judged as being normally turned on. If the output voltage value is compared with the threshold value in the comparison circuit in this state, it may be judged that it is not normally turned on. Therefore, a filter circuit is provided, and after a delay time set by the filter circuit, that is, after the output voltage value becomes the predetermined voltage value that will be judged as being normally turned on, the comparison result of the comparison circuit is output to the control circuit side, thereby preventing the false detection of the overcurrent state.

[0017] However, even if the semiconductor device operates normally, the power supply voltage may sometimes decrease for some reason. In this case, even after the delay time, the output voltage of the power semiconductor switch element does not rise to a predetermined voltage value to be judged as normally conducting. In such a case, in order to prevent the false detection of the overcurrent state, a false detection prevention circuit is provided to prevent the false detection of the overcurrent state.

[0018] As a method of preventing false detection, the delay time is extended until the output voltage value of the power semiconductor switch element becomes a predetermined voltage value that will be judged as normally conducting even if the power supply voltage decreases. In addition, as for the on time, even if the output voltage decreases, the time required to turn on the power semiconductor switch element within the delay time is not longer than the delay time. In addition, as for the output of the filter circuit, when the power supply voltage decreases, the voltage value of the signal representing the comparison result input from the comparison circuit to the filter circuit, that is, the judgment signal from the comparison circuit, is changed. Thus, even when the power supply voltage decreases during normal operation, false detection of the overcurrent state can be prevented, thereby ensuring operability.

[0019] Technical Effects

[0020] According to the present invention, it is possible to provide a semiconductor device that can prevent erroneous detection of an overcurrent state and ensure operability when a power supply voltage drops during normal operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a circuit diagram for explaining the basic principle of the present invention.

[0022] Figure 2 This is a diagram showing output voltage characteristics for explaining the basic principle of the present invention.

[0023] Figure 3 This is a graph showing the power supply voltage dependency of the delay time and the turn-on time caused by the filter circuit for explaining the basic principle of the present invention.

[0024] Figure 4 (a) is a circuit diagram showing a circuit configuration of a first embodiment of the present invention, Figure 4 (b) is a graph showing the characteristics of the circuit structure.

[0025] Figure 5 (a) is a circuit diagram showing a circuit configuration of a first embodiment of the present invention, Figure 5 (b) is a graph showing the characteristics of the circuit structure.

[0026] Figure 6 : is a circuit diagram showing a circuit configuration of a second embodiment of the present invention.

[0027] Figure 7 : is a circuit diagram showing a circuit configuration of a third embodiment of the present invention.

[0028] Figure 8 : is a circuit diagram showing a circuit configuration of a third embodiment of the present invention.

[0029] Fig. 9: is a circuit diagram showing a circuit configuration of a fourth embodiment of the present invention.

[0030] Fig.10 It is shown Fig. 9 A circuit diagram showing an example of the configuration of a power supply voltage drop detection circuit shown in FIG.

[0031] Explanation of symbols

[0032] 1Power MOSFET (power semiconductor switching element)

[0033] 2 Load

[0034] 3Comparator (comparison circuit)

[0035] 4 Filter circuit

[0036] 5 Output terminals

[0037] 6 Reference voltage source

[0038] 7. Shutdown MOSFET

[0039] 8Control circuit (ECU)

[0040] 9Gate drive circuit

[0041] 10 Ground terminal

[0042] 11 First False Detection Prevention Circuit

[0043] 21 Second erroneous detection prevention circuit (charge pump circuit)

[0044] 21a Charging unit

[0045] 21b Oscillation unit

[0046] 22~24 Inverter (NOT gate)

[0047] 25 Oscillators

[0048] 31 Third false detection prevention circuit (internal grounding circuit)

[0049] 41 Fourth False Detection Prevention Circuit

[0050] 111 constant current source

[0051] 112 Capacitor

[0052] 113 diode

[0053] 211-213 first series circuit to third series circuit

[0054] 211D~213D diode

[0055] 211C~213C capacitor

[0056] 214~215 diode

[0057] 411OR Gate

[0058] 412 Power supply voltage drop detection circuit

[0059] 413 Inverter (NOT Gate)

[0060] D Delay time

[0061] GND Internal ground

[0062] GND_EX External ground

[0063] R1, R2 resistors

[0064] VOUT output voltage

[0065] VOC reference voltage

[0066] L1, L2 line segments DETAILED DESCRIPTION

[0067] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 3 The basic principle of the present invention is explained in detail.

[0068] (Basic Principle)

[0069] First, in order to illustrate the principle of the present invention, refer to Figure 1 The basic circuit structure is described.

[0070] The semiconductor device of the present invention is, for example, an IPS (Intelligent Power Switch) applied to an electric system such as an engine, a transmission, and a brake of an electric vehicle.

[0071] like Figure 1 As shown, the semiconductor device S mainly comprises: an N-type power MOSFET 1 which is normally off from the viewpoint of fault protection, a power supply VCC, a comparator 3, a filter circuit 4, and a shutdown MOSFET 7. Figure 7 The gate drive circuit 9) supplies a drive signal to the gate to turn the power MOSFET 1 on and off, thereby driving the load 2 in the above-mentioned electrical system with the power of the power source VCC such as a battery. The gate drive circuit is based on the control circuit such as the ECU of the electric vehicle (in the third embodiment described later, it is Figure 7 The above-mentioned drive signal is generated by the on / off signal supplied by the control circuit 8). It should be noted that Figure 1The circuit configuration shown is an example of a circuit configuration in which the power MOSFET 1 is a high-side switch arranged closer to the power supply VCC side than the load 2 , that is, on the high potential side of the load 2 .

[0072] Furthermore, the comparator 3 compares the output voltage value of the power MOSFET 1 with a threshold value. If the output voltage value is higher than the threshold value, the control circuit determines that the power MOSFET 1 is normally turned on. The threshold value is appropriately set based on, for example, the rated current flowing in the power MOSFET 1 and / or the heating temperature of the power MOSFET 1. On the other hand, when the output voltage value is lower than the threshold value, it is determined to be an overcurrent state. That is, the comparator 3 is a comparison circuit used to determine whether the power MOSFET 1 is normally turned on on the control circuit side by comparing the output voltage value of the power MOSFET 1 with the threshold value. In this case, the power MOSFET 1 is turned off, for example, so that the element is not destroyed due to the overcurrent. Specifically, the on-signal from the control circuit is applied to the gate of the MOSFET 7 for shutoff to turn it on, so that the gate of the power MOSFET 1 is turned on and the internal ground GND is connected, and the charge of the gate of the power MOSFET 1 is drawn out to turn off the power MOSFET 1.

[0073] The connection relationship is explained. The drain of the power MOSFET 1 is connected to the power supply VCC, the source is connected to the load 2 via the output terminal 5, and the source is also connected to the non-inverting input terminal of the comparator 3. The other end of the load 2 is grounded. In addition, the gate of the power MOSFET 1 is connected to the control circuit via the gate drive circuit, etc., and is also connected to the drain of the shutdown MOSFET 7. The source of the shutdown MOSFET 7 is connected to the internal ground GND, and the gate is connected to the above-mentioned control circuit. The inverting input terminal of the comparator 3 is connected to the reference voltage source 6, and the output terminal is connected to the input terminal of the filter circuit 4. The reference voltage source 6 outputs a reference voltage VOC for generating a threshold voltage. The output terminal of the filter circuit 4 is connected to the above-mentioned control circuit via various circuits for controlling the semiconductor device S.

[0074] The above-mentioned gate drive circuit and / or control circuit are just examples, and any circuit structure may be appropriately adopted as long as the purpose of the present invention can be achieved.

[0075] Next, refer to Figure 2The operation of the semiconductor device S having the above structure is described. As described above, the comparator 3 compares whether the voltage value of the output voltage VOUT of the power MOSFET 1 is higher or lower than the voltage value of the reference voltage VOC (the above threshold value), thereby determining the overcurrent state of the power MOSFET 1 on the control circuit side. As a specific example, when the on-resistance of the power MOSFET 1 is 100mΩ and the set overcurrent detection value is 2A, if VOUT≥VOC (=power supply VCC voltage-100(mΩ)×2(A)), it is determined to be normally turned on, and if VOUT<VOC, it is determined to be an overcurrent state.

[0076] The power MOSFET 1 is based on Figure 2 Initially, when the output voltage VOUT is turned on by the conduction signal IN shown, it is low. That is, it does not rise to the predetermined voltage value that is judged to be normally turned on. When the comparison result of the voltage value of the output voltage VOUT and the voltage value of the reference voltage VOC is output to the control circuit side in this state, the appropriate state judgment is not performed. Therefore, by setting Figure 1 The filter circuit 4 shown is used to set a predetermined time, that is, a delay time D until the power MOSFET 1 is normally turned on and the output voltage VOUT rises to a predetermined voltage value that will be judged as being normally turned on, and after the delay time D, the comparison result of the comparator 3 is output to the above-mentioned control circuit side to prevent erroneous detection of the overcurrent state.

[0077] However, even if the operation is performed normally, the voltage of the power supply VCC may drop for some reason. In this case, the turning-on operation of the power MOSFET 1 is delayed. Figure 2 As shown by the dotted line, the output voltage VOUT does not rise to the predetermined voltage value to be judged as normally conducting after the delay time D. If the control circuit side judges the overcurrent state based on the output voltage VOUT in this state, even though only the voltage of the power supply VCC has dropped and the semiconductor device S is operating normally, an erroneous detection of the overcurrent state may occur.

[0078] Regarding this, see Figure 3 The graph of the voltage VCC is described in detail from another perspective. The vertical axis is time and the horizontal axis is the voltage of the power supply VCC. Figure 3The graph shows the power supply voltage dependency of the delay time and the on-time generated by the filter circuit 4. When the voltage of the power supply VCC is reduced as described above, the operability of the filter circuit 4 deteriorates and the delay time generated by the filter circuit 4 becomes longer. In addition, when the voltage of the power supply VCC is reduced, the on-time of the power MOSFET 1, that is, the time until the output voltage VOUT of the predetermined voltage value to be judged as normally turned on is obtained, becomes longer. Therefore, the line segment L1 representing the on-time dependent on the voltage of the power supply VCC and the line segment L2 representing the delay time generated by the filter circuit 4 dependent on the voltage of the power supply VCC overlap. If the positional relationship of these line segments can be changed and the overlap can be suppressed, the operability of the semiconductor device S can be ensured even when the voltage of the power supply VCC is reduced in normal operation. The present invention adopts a circuit structure that suppresses such overlap and can ensure the operability of the semiconductor device S. In other words, even when the voltage of the power supply VCC is reduced, the positional relationship between the line segment L1 representing the on-time of the power MOSFET 1 and the line segment L2 representing the delay time generated by the filter circuit 4 is changed so that the two line segments do not intersect. Furthermore, when the voltage of the power supply VCC decreases, the voltage value of the output signal of the comparator 3 indicating the comparison result is changed, thereby preventing erroneous detection of an overcurrent state on the control circuit side.

[0079] (First Embodiment)

[0080] Reference Figure 4 (a)~ Figure 5 The first embodiment relates to the case where the voltage of the power supply VCC decreases during normal operation. Figure 3 The line segment L2 indicating the delay time shown in the figure does not overlap with the line segment L1 indicating the on time. In other words, even when the voltage of the power supply VCC decreases, the delay time generated by the filter circuit 4 is extended until the output voltage of the power MOSFET 1 reaches a predetermined voltage value at which the power MOSFET 1 is judged to be normally turned on, thereby preventing the overcurrent state from being misdetected. Hereinafter, this circuit structure is referred to as the first misdetection prevention circuit 11. The first misdetection prevention circuit 11 is as shown in FIG. Figure 4 As shown in (a) of FIG. 1 , a constant current source 111 and a capacitor 112 are provided. The other components are the same as those described above, so the illustration and description are omitted below.

[0081] The constant current source 111 is a circuit including a MOSFET, for example, and its input end is connected to the power supply VCC, and its output end is connected to the drain of the power MOSFET 1. The capacitor 112 is an element for stabilizing the voltage of the power supply VCC, and one end of the capacitor 112 is connected between the other end of the constant current source 111 and the drain of the power MOSFET 1, and the other end of the capacitor 112 is grounded to the internal ground GND.

[0082] The first false detection prevention circuit 11 is as follows Figure 4 As shown in (b), it contributes to the stabilization of the delay time generated by the filter circuit 4. That is, it is possible to reduce the dependency of the delay time on the voltage level of the power supply VCC.

[0083] In addition, the first false detection prevention circuit 11 can also be as follows Figure 5 As shown in (a), a diode 113 is provided, the cathode of the diode 113 is connected to the power supply VCC and the input end of the constant current source 111, and the anode is grounded to the internal ground GND. In the case of this structure, the diode 113 clamps the voltage of the power supply VCC. Figure 4 In combination with the structure shown in (a) of FIG. 1 , the delay time generated by the filter circuit 4 is constant. In addition, when the voltage of the power supply VCC decreases, the voltage is clamped by the diode 113, as shown in FIG. Figure 5 As shown in (b), the delay time generated by the filter circuit 4 can be lengthened. Figure 3 In the graph of , the line segment L2 representing the delay time generated by the filter circuit 4 is moved to the right side of the graph relative to the line segment L1 representing the on time, thereby preventing the two line segments from overlapping. In other words, the first false detection prevention circuit 11 changes the delay time generated by the filter circuit 4 even when the voltage of the power supply VCC decreases, so that the delay time is always longer than the on time of the power MOSFET 1. Thus, in normal operation, even when the voltage of the power supply VCC decreases for some reason, the delay time of the filter circuit 4 can be extended and the output voltage VOUT of the power MOSFET 1 can be increased to a predetermined voltage value that will be judged as being normally turned on. Therefore, even when the voltage of the power supply VCC decreases in normal operation, false detection of the overcurrent state can be prevented and the operability of the semiconductor device S can be ensured.

[0084] Furthermore, since the first erroneous detection preventing circuit 11 has a relatively simple structure, there is also an advantage that the above-mentioned effects can be achieved without significantly changing the chip layout of the semiconductor device S, for example.

[0085] (Second Embodiment)

[0086] Next, refer to Figure 6The second embodiment is described in detail. The second embodiment relates to a second erroneous detection prevention circuit 21 which, when the voltage of the power supply VCC decreases during normal operation, Figure 3 The line segment L1 indicating the on time shown is moved to the left side in the figure to suppress the overlap with the line segment L2 indicating the delay time generated by the filter circuit 4. In other words, even when the voltage of the power supply VCC is reduced, the power MOSFET 1 is turned on within the delay time set by the filter circuit 4 without extending the on time of the power MOSFET 1, thereby preventing the erroneous detection of the overcurrent state. The second erroneous detection prevention circuit 21 is a so-called charge pump, and even when the voltage of the power supply VCC is reduced, the voltage is boosted and applied to the gate of the power MOSFET 1. Hereinafter, for the sake of convenience, the second erroneous detection prevention circuit 21 is referred to as a charge pump circuit 21.

[0087] For example, when the IPS as the semiconductor device S of the present invention is used as a high-voltage side IPS in the electrical system of an electric vehicle, in order to fully turn on the power MOSFET 1 as an N-type MOSFET, a voltage higher than the drain is required in the circuit structure. The voltage of the drain is the voltage of the power supply VCC, which is the highest voltage in the circuit. Therefore, in order to obtain a voltage higher than the voltage of the power supply VCC, a charge pump circuit 21 is used in this embodiment.

[0088] (structure)

[0089] The charge pump circuit 21 is further described. The charge pump circuit 21 is composed of a charging section 21a and an oscillating section 21b. The charging section 21a includes a first series circuit 211 to a third series circuit 213, each of which is a series circuit of a diode and a capacitor, diodes 214 and 215 that connect the adjacent series circuits 211 to 213, and a diode 216 that applies the voltage output by the charge pump circuit 21 to a gate drive circuit (not shown) according to a control signal from a control circuit such as an ECU of an electric vehicle, and the gate drive circuit turns the power MOSFET 1 on and off. Each series circuit 211 to 213 includes a diode 211D to 213D and a capacitor 211C to 213C. The anode of each diode 211D to 213D is connected to the power supply VCC, and the cathode is connected to one end of each capacitor 211C to 213C.

[0090] The anode of the diode 214 is connected between the cathode of the diode 211D and one end of the capacitor 211C, and the cathode of the diode 214 is connected between the cathode of the diode 212D and the capacitor 212C.

[0091] Similarly, the anode of the diode 215 is connected between the cathode of the diode 212D and one end of the capacitor 212C, and the cathode of the diode 215 is connected between the cathode of the diode 213D and the capacitor 213C.

[0092] The anode of the diode 216 is connected between the cathode of the diode 213D and one end of the capacitor 213C, and the cathode is connected to the gate of the power MOSFET 1 via a gate drive circuit or the like.

[0093] The oscillator 21b includes first to third inverters (NOT gates) 22 and an oscillator 25. The output terminal of the first inverter 22 is connected to the other end of the capacitor 211C in the first series circuit 211 and the other end of the capacitor 213C in the third series circuit 213, and the output terminal of the second inverter 23 is connected to the other end of the capacitor 212C in the second series circuit 212. The output terminal of the third inverter 24 is connected to the input terminal of the second inverter 23.

[0094] Input terminals of the first inverter 22 and the third inverter 24 are connected to output terminals of the oscillator 25 , respectively.

[0095] The oscillator 25 generates an H level or L level pulse signal, such as a PFM (Pulse Frequency Modulation) pulse, based on an on / off signal from a control circuit such as an ECU of the electric vehicle, and supplies the signal to the first inverter 22 and the third inverter 24 .

[0096] (Function, Effect)

[0097] The function and effect of the charge pump circuit 21 having such a structure will be described. In the oscillation unit 21b, when the pulse signal from the oscillator 25 is at an H level, the first inverter 22 outputs an L level signal. Therefore, the power supply VCC and the internal ground GND are connected via the capacitor 211C, and the capacitor 211C is charged by the current flowing from the power supply VCC via the first diode 211D. The same is true for the capacitor 213C.

[0098] Next, when the pulse signal from the oscillator 25 is at an L level, the third inverter 24 outputs an H level signal, and the second inverter 23 to which the signal is input outputs an L level signal. Therefore, the power supply VCC and the internal ground GND are connected via the capacitor 212C, so the capacitor 212C is charged by the current flowing from the power supply VCC via the diode 212D. On the other hand, the first inverter 22 outputs an H level signal. Therefore, the charge accumulated in the capacitor 211C is superimposed on the voltage of the power supply VCC and is supplied to the gate drive circuit (not shown) via the diodes 214 and 215. Similarly, the charge accumulated in the capacitor 213C is output to the gate drive circuit via the diode 216.

[0099] When the pulse signal from the oscillator 25 is at H level again, the charge accumulated in the capacitor 212C is superimposed on the voltage of the power supply VCC and supplied to the gate drive circuit via the diodes 215 and 216. As described above, the capacitor 211C and the capacitor 213C are charged again.

[0100] By repeatedly charging and discharging the capacitors 211C to 213C, the charge discharged by the capacitor 211C and the like is superimposed on the voltage of the power supply VCC and applied to the gate of the power MOSFET 1 via the gate drive circuit and the like. That is, the charge pump circuit 21 changes the on-time even when the voltage of the power supply VCC decreases so that the on-time of the power MOSFET 1 is always shorter than the delay time generated by the filter circuit 4. In other words, in the entire voltage range of the power supply VCC, the delay time is always longer than the on-time. Therefore, even when the voltage of the power supply VCC decreases, by improving the on-time operation of the power MOSFET 1, it is possible to prevent erroneous detection of the overcurrent state of the semiconductor device S, thereby ensuring operability.

[0101] Furthermore, since the only external components necessary as components of the charge pump circuit 21 are the capacitors 211C to 213C, there are advantages such as space saving and ease of design of the charge pump circuit 21 itself.

[0102] It should be noted that the number of capacitors 211C, etc. of the charge pump circuit 21 is arbitrary. For example, it is preferable to appropriately design the number and / or capacitance of capacitors 211C, etc. so as to make the output voltage of the charge pump circuit 21 a desired voltage value and not exceed the gate withstand voltage of the power MOSFET 1.

[0103] (Third Embodiment)

[0104] Next, refer to Figure 7 and Figure 8 The third embodiment is described in detail. The third embodiment relates to a third false detection prevention circuit 31, which improves the performance of the charge pump circuit (second false detection prevention circuit) 21 of the second embodiment and ensures the operability of the semiconductor device S even when the voltage of the power supply VCC is reduced. Hereinafter, the third false detection prevention circuit 31 is referred to as an internal grounding circuit 31. Figure 7 As shown, the internal grounding circuit 31 is connected to the charge pump circuit 21, more specifically Figure 6 The voltage boosting operation of the charge pump circuit 21 is enhanced by lowering the potential of the internal ground GND to approximately 0 V between the internal ground GND and the external ground of the first inverter 22 to the third inverter 24 shown in FIG. Figure 8 It should be noted that Figure 7 The circuit structure shown is intended to help understand the present invention. In actual use, in addition to the components shown in the figure, it also includes various circuits such as a level shift circuit for controlling the semiconductor device S. However, in order to make the present invention easier to understand, the illustration of various circuits is omitted.

[0105] (structure)

[0106] like Figure 8 As shown, the internal grounding circuit 31 includes a first MOSFET 311 , a first diode 312 to a fourth diode 315 , a second MOSFET 316 to a fifth MOSFET 319 , a sixth MOSFET 320 , and a seventh MOSFET 321 .

[0107] The first MOSFET 311 is, for example, an enhancement type (normally off) P-MOSFET. The second MOSFET 316 to the fifth MOSFET 319 are, for example, buck type (normally on) N-MOSFETs. The sixth MOSFET 320 and the seventh MOSFET 321 are, for example, enhancement type N-MOSFETs.

[0108] The connection relationship is described in detail.

[0109] The first MOSFET 311 has a connection relationship in which the internal ground GND is formed with the power supply VCC as a reference in terms of potential and operates as a source follower. Specifically, the source of the first MOSFET 311 is connected to Figure 6 The internal ground GND and the drain of the sixth MOSFET 320 are connected to the drain of the first MOSFET 311 via Figure 7 The ground terminal 10 is shown to be grounded to the external ground GND_EX, and the gate is connected to the anode of the first diode 312 and the drain of the second MOSFET 316. The cathode of the first diode 312 is connected to the power supply VCC.

[0110] The source of the second MOSFET 316 is connected via Figure 7 The ground terminal 10 of the third MOSFET 317 is grounded to the external ground GND_EX, and the gate is connected to its source. The drain of the third MOSFET 317 is connected to the power supply VCC, the source is connected to the cathode of the second diode 313, and the gate is connected to its source. The drain of the fourth MOSFET 318 is connected to the anode of the fifth diode 315, the source is connected to the drain of the fifth MOSFET 319, and the gate is connected to its source. The source of the fifth MOSFET 319 is connected to the Figure 7 The ground terminal 10 is grounded to the external ground GND_EX, and the gate is connected to its source.

[0111] The drain of the sixth MOSFET 320 is grounded to the internal ground GND together with the source of the first MOSFET 311, and the source is connected to the internal ground GND via Figure 7 The ground terminal 10 of the seventh MOSFET 321 is grounded to the external ground GND_EX, and the gate is connected between the source of the third MOSFET 317 and the cathode of the second diode 313. The drain of the seventh MOSFET 321 is connected to the gate of the sixth MOSFET 320, and the source is connected to the gate of the sixth MOSFET 320 via Figure 7 The ground terminal 10 is grounded to the external ground GND_EX, and the gate is connected between the source of the fourth MOSFET 318 and the drain of the fifth MOSFET 319 .

[0112] The anode of the second diode 313 is connected via Figure 7 The ground terminal 10 of the third diode 314 is grounded to the external ground GND_EX. Figure 7 The ground terminal 10 of the diode 315 is connected to the external ground GND_EX, and the cathode is connected to the gate of the seventh MOSFET 321. The cathode of the fourth diode 315 is connected to the power supply VCC.

[0113] (Function, Effect)

[0114] Next, the operation and effects of the internal ground circuit 31 of the present embodiment will be described.

[0115] In order to improve the capability of the charge pump circuit 21, an internal grounding circuit is sometimes provided. In this case, in the case of a structure in which the internal grounding circuit 31 is composed of, for example, only the first MOSFET 311, the first diode 312, and the second MOSFET 316, and the first diode 312 and the fourth diode 315 etc. clamp the voltage at 5V, even if the voltage of the power supply VCC decreases, the potential of the internal ground GND is unlikely to become approximately 0V. Specifically, since the first MOSFET 311 is a P-type MOSFET that is turned on when the potential of the gate is lower than the potential of the source, and the source is connected to the internal ground GND, when the potential of the internal ground is lower than the potential of the gate, the first MOSFET 311 is turned off, and the internal ground GND and the external ground GND_EX are not turned on via the first MOSFET 311. Therefore, the potential of the internal ground GND is unlikely to become less than the gate-source threshold voltage Vth of the first MOSFET 311. As a result, the input signal input to the charge pump circuit 21, for example, from Figure 6 The amplitude of the signal of the inverter 22 and the like shown becomes smaller, and further, there is a possibility that the voltage boosting operation of the charge pump circuit 21 may be delayed.

[0116] However, according to the circuit configuration of the present embodiment, when the voltage of the power supply VCC drops below 5 V, the sixth MOSFET 320 and the like extract the charge of the internal ground GND, so that the potential of the internal ground GND drops to approximately 0 V. Thus, even when the voltage of the power supply VCC drops during normal operation, the amplitude of the input signal input to the charge pump circuit 21 is improved, so that the turn-on operation of the power MOSFET 1 is improved, and thus even when the voltage of the power supply VCC drops during normal operation, erroneous detection of an overcurrent state can be prevented.

[0117] (Fourth Embodiment)

[0118] In the first to third embodiments described above, the erroneous detection of the overcurrent state is prevented by changing the delay time generated by the filter circuit 4 or the on-time of the power MOSFET 1, but the erroneous detection of the overcurrent state can also be prevented by changing the voltage value of the judgment signal, which is an input signal input from the comparator 3 to the filter circuit 4, that is, a signal indicating the comparison result of the comparator 3, and is input to the filter circuit 4 and is used to detect and judge whether the power MOSFET 1 is normally turned on on the control circuit side. Fig. 9 and Fig.10 The fourth erroneous detection preventing circuit for changing the voltage value of the determination signal according to the present embodiment will be described in detail.

[0119] like Fig. 9 As shown, the fourth erroneous detection preventing circuit 41 includes an OR gate 411 and a power supply voltage drop detecting circuit 412 .

[0120] The OR gate 411 is disposed between the filter circuit 4 and the comparator 3, and one input terminal thereof is connected to the output terminal of the power supply voltage drop detection circuit 412, and the other input terminal thereof is connected to the output terminal of the comparator 3. In addition, the output terminal of the OR gate 411 is connected to the input terminal of the filter circuit 4. The OR gate 411 outputs a signal of a level corresponding to the output signal of the power supply voltage drop detection circuit 412 and the output signal of the comparator 3 to the filter circuit 4.

[0121] The power supply voltage drop detection circuit 412 detects a drop in the voltage of the power supply VCC. Fig.10 An example of the power supply voltage drop detection circuit 412 is shown in FIG. Fig.10As shown, the power supply voltage reduction detection circuit 412 includes a group of resistors R1, R2 and a NOT gate (inverter) 413, wherein the group of resistors R1, R2 are a group of resistors R1, R2 connected in series and one end is connected to the power supply VCC, and the other end is connected to the internal ground GND, the input terminal of the NOT gate (inverter) 413 is connected between the resistor R1 and the resistor R2, and the output terminal is connected to the OR gate 411.

[0122] The voltage V1 at the midpoint of the resistors R1 and R2 obtained by the resistor voltage division, that is, the voltage V1 applied to the input terminal of the inverter 413 is V1 = VCC × (R2 / (R1 + R2)). A predetermined threshold value Vth2 is set in the inverter 413, and the threshold value Vth2 is appropriately set so as to be able to detect a decrease in the voltage of the power supply VCC. Specifically, the inverter 413 is set so that when the voltage V1 is greater than the threshold value Vth2, the inverter 413 outputs an L-level signal, and when the voltage V1 is less than the threshold value Vth2, the inverter 413 outputs an H-level signal.

[0123] Next, the operation of the fourth false detection prevention circuit 41 will be described. Here, the operation of the fourth false detection prevention circuit 41 when the voltage of the power supply VCC decreases, which is a feature of the present invention, will be described below. When the voltage of the power supply VCC decreases, an L-level signal (the above-mentioned judgment signal) is input from the comparator 3 to the other input terminal of the OR gate 411, and since the above-mentioned voltage V1 is less than the threshold value Vth2, an H-level signal is input from the inverter 413 to one input terminal of the OR gate 411.

[0124] The OR gate 411 outputs an H-level signal to the filter circuit 4 based on the L-level signal from the comparator 3 and the H-level signal from the inverter 413. Here, in the absence of the OR gate 411, an L-level signal is input from the comparator 3 to the filter circuit 4, but in this embodiment, an H-level signal is input to the filter circuit 4 through the OR gate 411 configured between the filter circuit 4 and the comparator 3. Thus, since the filter circuit 4 outputs an H-level signal, erroneous detection of an overcurrent state is prevented. That is, by changing the voltage value of the judgment signal representing the comparison result from the comparator 3, erroneous detection of an overcurrent state on the control circuit side is prevented.

[0125] In the case where the voltage of the power supply voltage VCC temporarily decreases but not in the actual overcurrent state, in the state where the L-level signal is input to the other input terminal of the OR gate 411 from the comparator 3, the L-level signal is input to one input terminal of the OR gate 411 from the inverter 413 due to the recovery of the voltage of the power supply VCC. In this case, the OR gate 411 outputs the L-level signal to the filter circuit 4. However, after the above-mentioned delay time generated by the filter circuit 4, the H-level signal is input to the other input terminal of the OR gate 411 from the comparator 3, and the L-level signal is input to one input terminal of the OR gate 411 from the inverter 413, so the OR gate 411 outputs the H-level signal to the filter circuit 4. Therefore, since it is possible to prevent the erroneous detection of the overcurrent state on the control circuit side, the operability of the semiconductor device S is ensured.

[0126] When the fourth erroneous detection preventing circuit 41 is used, it is preferable to adopt a circuit configuration in which, for example, a sense MOSFET (not shown) is provided separately from the power MOSFET 1 to detect an actual overcurrent state.

[0127] (Other embodiments)

[0128] The embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various applications and changes can be made as long as they do not deviate from the technical scope. For example, the circuit configurations shown in the first to third embodiments are merely examples, and other circuit configurations can be used as long as the positional relationship between the line segment representing the delay time of the filter circuit 4 depending on the voltage of the power supply VCC and the line segment representing the turn-on time of the power MOSFET 1 depending on the voltage of the power supply VCC can be changed so that they do not overlap.

[0129] In addition, in the above-mentioned embodiment, the case where the power semiconductor switching element is the power MOSFET 1 is described as an example. However, the present invention is not limited to this, and for example, in an application requiring a larger power capacity than the power MOSFET 1 and requiring a switching speed slower than the power MOSFET 1, an IGBT may be used instead of the power MOSFET 1.

[0130] Furthermore, as long as the object of the present invention can be achieved, in actual use, the first to fourth embodiments may be appropriately combined within a range that satisfies required specifications and the like.

Claims

1. A semiconductor device, characterized in that: A semiconductor device having a power semiconductor switching element that drives a load with power from a power supply by switching, and outputting a judgment signal for detecting whether the power semiconductor switching element is normally turned on to a control circuit, wherein the semiconductor device has: a comparison circuit that compares the value of the output voltage of the power semiconductor switch element with a threshold value indicating an overcurrent state of the power semiconductor switch element and outputs the comparison result as the judgment signal; a filter circuit provided on the output side of the comparison circuit, and outputting the judgment signal to the control circuit after a delay time, the delay time being the time from when the power semiconductor switch element is turned on until the output voltage of the power semiconductor switch element rises to a predetermined voltage value to be judged as normal conduction; as well as A circuit for preventing false detection prevents false detection of an overcurrent state in the control circuit by changing the on-time of the power semiconductor switch element or the voltage value of the judgment signal when the voltage of the power supply decreases when the power semiconductor switch element is normally turned on.

2. The semiconductor device according to claim 1, wherein: The false detection prevention circuit comprises: a power supply voltage reduction detection circuit connected to the power supply to detect a reduction in the power supply voltage; and An OR gate has an output terminal connected to the filter circuit, one input terminal connected to the power supply voltage drop detection circuit, and another input terminal connected to the output terminal of the comparison circuit.

3. The semiconductor device according to claim 1, wherein: The erroneous detection preventing circuit changes the on-time so that the delay time is always longer than the on-time.

4. The semiconductor device according to claim 1, wherein: The power semiconductor switch element is an N-type power MOSFET configured on the high potential side of the load, The erroneous detection prevention circuit includes a charge pump circuit configured to increase a voltage applied to a gate of the power semiconductor switch element so as to make the on time of the power semiconductor switch element shorter than the delay time.

5. The semiconductor device according to claim 4, wherein: The circuit for preventing false detection also has an internal grounding circuit, which is arranged between the internal ground of the charge pump circuit and the external ground of the semiconductor device. The internal grounding circuit is used to stabilize the output of the charge pump circuit by lowering the potential of the internal ground by drawing the charge of the internal ground to the external ground when the power supply voltage decreases.

6. The semiconductor device according to claim 5, wherein: The internal grounding circuit is composed of: a diode, a cathode of which is connected to the power supply; a P-type MOSFET having a source connected to the internal ground, a drain connected to the external ground, and a gate connected to the anode of the diode; a normally-on N-type MOSFET, whose drain is connected to the gate of the P-type MOSFET, whose source is connected to the external ground, and whose gate is connected to the source; and A normally-off N-type MOSFET has a drain connected to the source of the P-type MOSFET and the internal ground, and a source connected to the external ground.

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