Semiconductor devices

Abstract

Embodiments of the present disclosure relate to semiconductor devices. In order to make a negative voltage level shifter operate stably even when the voltage value of a high level of an input signal is reduced, the negative voltage level shifter in the semiconductor device includes a first level shifter, a second level shifter, and a first medium voltage generating circuit. The first level shifter converts the high level of an input signal from a positive first power supply voltage to a first medium voltage. The second level shifter converts the low level of an output signal of the first level shifter from a third power supply voltage to a negative fourth power supply voltage lower than the third power supply voltage. The first medium voltage generating circuit generates the first medium voltage in such a way that the first medium voltage is higher than the first power supply voltage but lower than the second power supply voltage, and includes a source follower NMOS transistor and a clamp PMOS transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-028609 filed on February 12, 2018 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, for example, applicable to a semiconductor device including a level shifter for converting a lower potential side voltage level of an input signal into a negative high voltage. Background Art

[0004] For example, a nonvolatile memory circuit including logic circuits mixed therein uses a low voltage power supply (VDD, e.g., approximately 1.0 V), a medium voltage power supply (VCC, e.g., approximately 3 V), a positive high voltage power supply (VPP, e.g., up to approximately 11 V), and a negative high voltage power supply (VEE, e.g., up to approximately -8 V).

[0005] Specifically, a low power supply voltage VDD is used in the logic circuit portion. A medium power supply voltage VCC is used in the peripheral circuit of the nonvolatile memory. The positive high voltage VPP is used to provide data to the nonvolatile memory cell. The negative high voltage VEE is used to erase data from the nonvolatile memory cell. The positive high voltage VPP is generated by boosting the medium power supply voltage VCC. The negative high voltage VEE is generated by boosting the reference voltage (0V) to the negative direction.

[0006] In the peripheral circuit of the nonvolatile memory, a level shifter is provided. One level shifter converts a VDD / VSS level signal (i.e., a signal whose high level is a low power supply voltage VDD and whose low level is a reference voltage VSS) into a VPP / VSS level signal. Another level shifter converts a VDD / VSS level signal into a VDD / VEE level signal. Hereinafter, the former level shifter using the positive high voltage VPP is referred to as a positive voltage level shifter, and the latter level shifter using the negative high voltage VEE is referred to as a negative voltage level shifter.

[0007] Even when the negative high voltage power supply is invalid, that is, when the reference voltage VSS is supplied instead of the negative high voltage VEE, the negative high voltage level shifter must operate. As such a negative voltage level shifter that can operate both when the negative power supply is valid and when the negative power supply is invalid, there is known a negative voltage level shifter disclosed in Japanese Laid-Open Patent Application No. Hei 11 (1999)-308092.

[0008] Specifically, the negative voltage level shifter described in this document includes a pair of cross-coupled NMOS (N-channel metal oxide semiconductor) transistors coupled to a line for providing a negative power supply voltage VEE, a pair of input PMOS (P-channel MOS) transistors coupled to a line for providing a power supply voltage VDD, and a breakdown voltage relaxation circuit. The breakdown voltage relaxation circuit includes a pair of PMOS transistors and a pair of NMOS transistors for breakdown voltage relaxation. For the gates of the breakdown voltage relaxation NMOS transistors, a reference voltage VSS is provided when the negative power supply is valid, and the power supply voltage VDD is provided when the negative power supply is invalid. SUMMARY OF THE INVENTION

[0009] For the logic circuit part, scaling is performed such that its size decreases year by year. Associated with this, the value of the low power supply voltage VDD is reduced. At the same time, for high breakdown voltage MOS transistors used in non-volatile memories such as flash memories, it is difficult to reduce the size and the threshold voltage cannot be lowered. Therefore, the values of the medium power supply voltage VCC, the positive high voltage VPP, and the negative high voltage VEE do not change from the conventional values.

[0010] The above situation makes it difficult to implement a circuit configuration of a negative voltage level shifter using the negative power supply voltage VEE in the peripheral circuit of a non-volatile memory including a logic circuit incorporated therein. Specifically, for the positive voltage supplied to the negative voltage level shifter, from the perspective of breakdown voltage relaxation, VDD, which is the lowest positive power supply voltage, is used. At the same time, as described above, the negative high voltage level shifter must operate even when the negative high voltage power supply is invalid, that is, when the reference voltage VSS is provided instead of the negative high voltage VEE. Therefore, when the low power supply voltage VDD is excessively reduced due to size reduction, it is difficult for the negative voltage level shifter to operate in the case where the negative high voltage power supply is invalid.

[0011] For example, in the case where the central value of the low power supply voltage VDD is 1V, the lower limit value can be about 0.8 - 0.9V. At the same time, depending on the conditions, the threshold Vth of the high breakdown voltage MOS transistor used in the negative voltage level shifter can be 1V. Therefore, VDD < Vth can be established. In this case, the negative voltage level shifter will not operate properly.

[0012] In a negative voltage level shifter including breakdown voltage relaxation MOS transistors, this trend is more significant. The reason is as follows. The breakdown voltage relaxation MOS transistors must be coupled to the cross-coupled MOS transistors and the input MOS transistors connected in series therewith. Therefore, four high breakdown voltage MOS transistors having high threshold voltages are coupled in series, resulting in an increase in the resistance value of the current path and further reducing the margin for reducing the low power supply voltage VDD.

[0013] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0014] A semiconductor device according to an embodiment includes a negative voltage level shifter. The negative voltage level shifter includes a first level shifter that converts a high level of an input signal from a first power supply voltage to a first intermediate voltage, and a second level shifter that converts a low level of an output signal of the first level shifter to a negative high voltage. The intermediate voltage is between the first power supply voltage and a second power supply voltage higher than the first power supply voltage.

[0015] According to the above-described embodiments, the negative voltage level shifter is allowed to operate stably even when the voltage value of the high level of the input signal is lowered. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment.

[0017] Figure 2 It is a graphic Figure 1 A block diagram of the configuration of the flash memory module (FMDL) in FIG.

[0018] Figure 3 A- Figure 3 D illustrates, in a table format, an example of voltage applied to a memory cell at the time of data writing.

[0019] Figure 4 A- Figure 4 D illustrates, in a table format, an example of voltage applied to a memory cell at the time of data erasure.

[0020] Figure 5A-5D Diagram Figure 2 A specific configuration example of the high voltage switching circuit in.

[0021] Figure 6 is a block diagram illustrating a configuration of a negative voltage level shifter in the semiconductor device according to the first embodiment.

[0022] Figure 7 It is a graphic Figure 6 A circuit diagram of a configuration example of a negative voltage level shifter body in FIG.

[0023] Figure 8 is a circuit diagram illustrating another configuration example of the negative voltage level shifter body.

[0024] Fig. 9 It is a graphic Figure 6 Circuit diagram of a configuration example of the VDD-VBIAS level shifter.

[0025] Fig.10 It is a graphic Figure 6 A circuit diagram of a configuration example of a power supply control signal generating circuit in FIG.

[0026] Fig.11 Graphics based on Figure 6 Configuration example of a modified negative voltage level shifter.

[0027] Fig.12 The configuration of a negative voltage level shifter in the semiconductor device according to the second embodiment is shown.

[0028] Fig.13 A configuration of a negative voltage level shifter in a semiconductor device according to a third embodiment is illustrated.

[0029] Fig.14 A configuration of a negative voltage level shifter in a semiconductor device according to a fourth embodiment is shown.

[0030] Fig.15 It is a graphic Fig.14 Circuit diagram of a configuration example of the VDD-VBIAS level shifter.

[0031] Fig.16 It is a graphic Fig.14 A circuit diagram of a configuration example of a negative voltage level shifter body in FIG.

[0032] Fig.17 A configuration of a negative voltage level shifter in a semiconductor device according to a fifth embodiment is shown.

[0033] Fig.18 It is a graphic Fig.17 Circuit diagram of a configuration example of the VDD-VBIAS level shifter in FIG.

[0034] Fig.19 It is a graphic Fig.17 A circuit diagram of a configuration example of a power supply control signal generating circuit in FIG.

[0035] Fig. 20 It is used to illustrate Fig.17 2 is a timing diagram of the operation of the negative voltage level shifter.

[0036] Fig.21 A configuration of a negative voltage level shifter in a semiconductor device according to a sixth embodiment is shown.

[0037] Fig. 22 It is a graphic Fig.21 A circuit diagram of a configuration example of a negative voltage level shifter body in FIG.

[0038] Fig.23 It is used to illustrate Fig.21 Detailed operation timing diagram of the negative voltage level shifter. DETAILED DESCRIPTION

[0039] The embodiments will be described in detail below with reference to the accompanying drawings. The same or corresponding parts are denoted by the same reference numerals, and their description will not be repeated.

[0040] In the following description, a microcomputer including a flash memory is described as an example of a semiconductor device including a negative voltage level shifter. However, the semiconductor device is not limited to the following example. For example, the semiconductor device may be configured only by a flash memory. The technology disclosed in the present invention may be applied to any semiconductor device including a negative voltage level shifter.

[0041] First embodiment

[0042] [Microcomputer]

[0043] Figure 1 is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment. Figure 1 The configuration of a microcomputer or a microcontroller unit (MCU) as an example of a semiconductor device is illustrated.

[0044] Reference Figure 1 , for example, by using CMOS (Complementary Metal Oxide Semiconductor) integrated circuit manufacturing technology, for example, the microcomputer 31 is formed on a single semiconductor chip of single crystal silicon.

[0045] like Figure 1 As shown, the microcomputer 31 includes a central processing unit (CPU) 32, a random access memory (RAM) 35, and a flash memory module (FMDL) 36. The central processing unit 32 includes an instruction control unit and an execution unit, and executes instructions. For example, the random access memory 35 is used as a work area of ​​the central processing unit 32. The flash memory module 36 is provided as a non-volatile storage module for storing data, programs, etc.

[0046] The microcomputer 31 also includes a direct memory access controller (DMAC) 33, a bus interface circuit (BIF) 34, a flash sequencer (FSQC) 37, external input / output ports (PRT) 38 and 39, a timer (TMR) 40, a clock pulse generator (CPG) 41, a high-speed bus (HBUS) 42 and a peripheral bus (PBUS) 43.

[0047] The bus interface circuit 34 controls a bus interface or a bus bridge between the high-speed bus 42 and the peripheral bus 43. The flash sequencer 37 performs command access control for the flash memory module (FMDL) 36. The clock pulse generator 41 generates an internal clock CLK for controlling the microcomputer 31.

[0048] The bus configuration of the microcomputer 31 is not particularly limited. Figure 1In the case of a high-speed bus (HBUS) 42 and a peripheral bus (PBUS) 43, a high-speed bus (HBUS) 42 and a peripheral bus (PBUS) 43 are provided. Each of the high-speed bus 42 and the peripheral bus 43 is not particularly limited, but includes a data bus, an address bus, and a control bus. By providing two buses, the high-speed bus 42 and the peripheral bus 43, the load on the bus can be reduced compared to the case where all circuits are coupled to a single common bus, thereby ensuring a high-speed access operation.

[0049] The central processing unit 23, direct memory access controller 33, bus interface circuit 34, random access memory 35 and flash memory module 36 are coupled to a high-speed bus 42. The flash sequencer 37, external input / output ports 38 and 39, timer 40 and clock generator 41 are coupled to a peripheral bus 43.

[0050] The microcomputer 31 further includes a clock terminal XTAL coupled with an oscillator, a clock terminal EXTAL supplied with an external clock, an external hardware standby terminal STBY indicating a standby state, and an external reset terminal RES indicating a reset. The microcomputer 31 further includes terminals for receiving a power supply voltage VDD for a digital circuit, a power supply voltage VCC for an analog circuit, and a ground voltage VSS (also referred to as a reference voltage VSS), respectively.

[0051] Since the flash sequencer 37 and the flash memory module 36 configured as a logic circuit in an array form are designed by CAD tools separate from each other, for the sake of convenience, Figure 1 In the figure, they are shown as separate circuit blocks. However, they are configured together to form a flash memory 46.

[0052] The flash memory module 36 is coupled to the high-speed bus (HBUS) 42 via a read-only high-speed access port (HACSP) 45. The central processing unit 32 or the direct memory access controller 33 can read the flash memory module 36 from the high-speed bus 42 via the high-speed access port 45. When writing and initializing the flash memory module 36, the central processing unit 32 or the direct memory access controller 33 issues a command to the flash sequencer 37 via the bus interface circuit 34 by way of the peripheral bus (PBUS) 43. In response to the command, the flash sequencer 37 controls the initialization of the flash memory module and the write operation from the peripheral bus (PBUS) via the low-speed access port (LACSP) 44.

[0053] [Flash Module]

[0054] Figure 2 It is a graphic Figure 1 A block diagram of the configuration of the flash memory module (FMDL) in FIG.

[0055] The flash memory module 36 includes a memory cell array 51 , a CG driver circuit 52 , an MG driver circuit 53 , a high-voltage decoding circuit 54 , a high-voltage switching circuit 55 , a boost circuit 56 , and a sense amplifier / write control circuit 57 .

[0056] The memory cell array 51 includes a plurality of memory cells MC arranged in a matrix. Figure 2 Only a typical memory cell among the memory cells MC is illustrated. In the present disclosure, a MONOS (metal oxide nitride oxide silicon) type memory cell MC is described as follows Figure 2 , Figure 3 A- Figure 3 D and Figure 4 A- Figure 4 D. However, the technology of the present disclosure can also be applied to a memory cell MC having another configuration, for example, a floating gate type. Figure 3 A- Figure 3 D A specific configuration of the MONOS type memory cell MC is described.

[0057] The memory cell array 51 also includes a plurality of memory gate lines MGL, a plurality of control gate lines CGL and a plurality of source lines SL provided as control signal lines for the memory cells MC to correspond to respective rows of the memory cells MC, and a plurality of bit lines BL provided to correspond to respective columns of the memory cells MC. Figure 2 Typical control signal lines coupled to one memory cell MC are shown.

[0058] The CG driver circuit 52 includes a plurality of drivers 521 , each of which generates a control gate (CG) signal to drive a corresponding control gate line CGL.

[0059] The MG driver circuit 53 includes a plurality of drivers 531 , each of which generates a memory gate (MG) signal to drive a corresponding memory gate line MGL.

[0060] The boost circuit 56 includes a charge pump circuit therein, and generates a boosted voltage for each clock and provides the boosted voltage to the high-voltage decoding circuit 54. Specifically, the boost circuit 56 generates a positive voltage VPPA for writing MG, a positive voltage VPPC for writing unselected MG, a positive voltage VPPB for writing SL, a breakdown voltage relaxation positive voltage VPPR, and a negative voltage VEEM for erasing MG.

[0061] Hereinafter, the positive voltage VPPA for writing MG may be referred to as the high power supply voltage VPPA, the positive voltage VPPC for writing the unselected MG may be referred to as the medium voltage VPPC, and the breakdown voltage relaxation positive voltage VPPR may be referred to as the medium voltage VPPR. The medium voltage VPPC and the medium voltage VPPR are both between the high power supply voltage VPPA and the ground voltage VSS. In addition, in the following embodiments, the medium voltage VRRP is set to a voltage value between the high power supply voltage VPPA and the medium voltage VPPC.

[0062] The high-voltage switching circuit 55 selects various boosted voltages generated by the boosting circuit 56 to generate a voltage VMGPP for MG on the high potential side in the selected block, a voltage VMGPN for MG on the low potential side in the selected block, a voltage VMGNP for MG on the high potential side in the unselected block, a voltage VMGNN for MG on the low potential side in the unselected block, a selected SL voltage VSLP, and a voltage VSLN for unselected SL. The high-voltage switching circuit 55 supplies the generated voltages to the high-voltage decoding circuit 54 as decoder power supply voltages.

[0063] The high voltage decoding circuit 54 supplies a high voltage to the MG driver circuit 53 and the source line SL. More specifically, the high voltage decoding circuit 54 uses a decoder power supply voltage generated by the high voltage switching circuit 55 to supply a decoded signal to the MG driver circuit 53 and generates a source line signal to be supplied to the source line SL.

[0064] The sense amplifier / write control circuit 57 reads out the content stored in the selected memory cell via the bit line BL, and writes the content to be stored in the selected memory cell via the bit line BL.

[0065] [Supplying voltage to memory cell]

[0066] Next, an example of voltages supplied to selected / unselected memory cells in selected / unselected blocks from the above-mentioned CG driver circuit 52, MG driver circuit 53, high voltage decoding circuit 54, and sense amplifier / write control circuit 57 is described. Figure 3 A- Figure 3 D and Figure 4 A- Figure 4 The values ​​in D) are examples for illustration. The voltages are not limited to these values.

[0067] (Example of voltage applied to memory cell when data is written)

[0068] Figure 3 A- Figure 3 D illustrates, in a table format, an example of voltage applied to a memory cell at the time of data writing.

[0069] First, refer to Figure 3 A, briefly describes the configuration of the MONOS type non-volatile memory cell MC. The memory cell MC includes a control gate (CG) 61, a silicon nitride film 62, a memory gate (MG) 63, a source 64 and a drain 65. The control gate 61 is formed above the surface of the P-type silicon substrate 60 via an insulating layer (not shown). The silicon nitride film 62 is formed above the side wall of the control gate 61 as an ONO (oxide-nitride-oxide) film formed by a silicon oxide film (not shown), a silicon nitride film 62 and a silicon oxide film (not shown). A memory gate 63 with a sidewall substrate is formed above the ONO film. The source 64 and the drain 65 are formed by inserting N-type impurities on both sides of the gates 61 and 63, respectively. The source 64 is coupled to the corresponding source line SL, and the drain 65 is coupled to the corresponding bit line BL.

[0070] Next, a description will be given of a voltage applied to the memory cell MC at the time of data writing. The electrode to which a high voltage requiring breakdown voltage relaxation is applied is the memory gate MG. Therefore, the following description focuses on the voltage applied to the memory gate MG.

[0071] for Figure 3 In the selected memory cell in the selected block shown in A, the voltage applied to the selected memory gate MG is VMGPP, and VPPA is selected as VMGPP during writing. As an example, VPPA is a voltage of about 6.4 to 11 [V].

[0072] for Figure 3 In the unselected memory cells in the selected block shown in B, the voltage applied to the unselected memory gate MG is VMGPN, and VPPC is selected as VMGPN during writing. As an example, VPPC is a voltage of about 3.5 [V].

[0073] for Figure 3 In the selected memory cell in the unselected block shown in C, the voltage applied to the selected memory gate MG is VMGNP, and VPPC is selected as VMGNP during writing. As an example, VPPC is a voltage of about 3.5 [V].

[0074] for Figure 3 In the unselected memory cells in the unselected block shown in D, the voltage applied to the unselected memory gate MG is VMGNN, and VDD is selected as VMGNN during writing. As an example, VDD is a voltage of about 1.5 [V].

[0075] (Example of voltage applied to memory cell at the time of data erasure)

[0076] Figure 4 A- Figure 4 D illustrates an example of voltages applied to a memory cell at the time of data erasure in a table format. The electrode to which a negative high voltage requiring breakdown voltage relaxation is applied is the memory gate MG. Therefore, the following description focuses on the voltage applied to the memory gate MG.

[0077] for Figure 4 In the selected memory cell in the selected block shown in A, the voltage applied to the selected memory gate MG during erasure is VMGPN, and VEEM is selected as VMGPN during erasure. As an example, VEEM is a voltage of about -3.3 to -8 [V].

[0078] for Figure 4 In the unselected memory cells in the selected block shown in B, the voltage applied to the unselected memory gate MG during erasure is VMGPP, and VDD is selected as VMGPP during erasure. As an example, VDD is a voltage of about 1.5 [V].

[0079] Not present when erased Figure 4 C shows the state of the selected memory cell in the unselected block. Therefore, during erasing, a common voltage VMGNP is applied to all the memory gates GM in the unselected block, as shown in FIG. Figure 4 D. When erasing, VDD is selected as VMGNP. As an example, VDD is a voltage of about 1.5 [V].

[0080] [High voltage switching circuit]

[0081] Figure 5A-5D Pictured Figure 2 A specific configuration example of the high voltage switching circuit in.

[0082] Figure 5A A circuit generating voltage VMGPP is illustrated. Voltage VPPA is applied to output node 86 of voltage VMGPP via switch 71, and voltage VDD is applied to output node 86 of voltage VMGPP via switch 72. Either voltage VPPA or voltage VDD is selected according to an operation mode.

[0083] For each of switches 71 and 72, a single or multiple PMOS transistors are used. For simplicity, Figure 5AEach of the switches 71 and 72 is illustrated by a single-stage PMOS transistor. However, if necessary, due to the breakdown voltage, a multi-stage PMOS crystal may be used or a MOS transistor for relaxing the breakdown voltage may be input. Similarly, for each of the switches 73 to 78 described later, if necessary, due to the breakdown voltage, a multi-stage MOS transistor may be used or a MOS transistor for relaxing the breakdown voltage may be inserted.

[0084] The switches 71 and 72 are controlled to be turned on / off respectively by the selection signals selpp_a and selpp_c at the VDD level. No level shifter is required for the selection signal selpp_c. The selection signal selpp_c at the VDD level is directly input to the gate of the PMOS transistor configuring the switch 72.

[0085] At the same time, the VDD level selection signal selpp_a is converted into a VPPA level signal by the positive voltage level shifter 81. The VPPA level selection signal selpp_a is input to the gate of the PMOS transistor configuring the switch 71. The voltage VPPA is input to the terminal up of the positive voltage level shifter 81. Since the voltage VPPA is a high voltage, the positive voltage level shifter 81 requires breakdown voltage relaxation.

[0086] Figure 5B A circuit for generating voltage VMGPN is shown. Voltage VPPC is applied to output node 87 of voltage VMGPN via switch 73, and voltage VEEM is applied to output node 87 of voltage VMGPN via switch 74. Either voltage VPPC or voltage VEEM is selected according to the operation mode. For switch 73, a single-stage or multi-stage PMOS transistor is used. For switch 74, a single-stage or multi-stage NMOS transistor is used.

[0087] The on / off of the switch 73 is controlled by the selection signal selpn_c. The selection signal selpn_c at the VDD level is converted into a VPPC level signal by the positive voltage level shifter 83. The VPPC level selection signal selpp_c is input to the gate of the PMOS transistor configuring the switch 73. The voltage VPPC is input to the terminal up of the positive voltage level shifter 83. Since the voltage VPPC is not a high voltage, the positive voltage level shifter 83 does not require breakdown voltage relaxation.

[0088] The switch 74 is turned on / off controlled by the selection signal selpn_e at the VDD level. The VDD level selection signal selpn_e is converted into a VEEM level signal by the negative voltage level shifter 84. The VEEM level selection signal selpn_e is input to the gate of the NMOS transistor configuring the switch 74. The voltage VEEM is input to the terminal un of the negative voltage level shifter 84.

[0089] Figure 5C A circuit for generating voltage VMGPN is illustrated. Voltage VPPN is applied to output node 88 of voltage VMGNP via switch 75, and voltage VDD is applied to output node 88 of voltage VMGNP via switch 76. Either of voltage VPPC and voltage VDD is selected according to the operation mode. For each of switches 75 and 76, a single-stage or multi-stage PMOS transistor is used.

[0090] The switches 75 and 76 are controlled to be turned on / off by VDD level selection signals selnp_c and selpp_d, respectively. The selection signal selpp_d does not require a level shifter. The VDD level selection signal selpp_d is directly input to the gate of the PMOS transistor configuring the switch 76.

[0091] At the same time, the VDD level selection signal selnp_c is converted into a VPPC level signal by the positive voltage level shifter 85. The VPPC level selection signal selnp_c is input to the gate of the PMOS transistor of the configuration switch 75. The voltage VPPC is input to the terminal up of the positive voltage level shifter 85. Since the voltage VPPC is not a high voltage, the positive voltage level shifter 85 does not require breakdown voltage relaxation.

[0092] Figure 5D A circuit for generating voltage VMGNN is shown. Voltage VDD is applied to output node 89 of voltage VMGNN via switch 77, and voltage VSS is applied to output node 89 of voltage VMGNN via switch 78. Either voltage VDD or voltage VSS is selected according to the operation mode. For switch 77, a single-stage or multi-stage PMOS transistor is used. For switch 78, a single-stage or multi-stage NMOS transistor is used.

[0093] The switches 77 and 78 are turned on / off respectively by VDD level selection signals selnn_d and selnn_s. For the selection signals selnn_d and selnn_s, no level shifter is required. The selection signal selnn_d is directly input to the gate of the PMOS transistor of the configuration switch 77, and the selection signal selnn_s is directly input to the gate of the NMOS transistor of the configuration switch 78.

[0094] Table 1 shows the Figure 2 Example of a high voltage switching circuit in selecting a boosted voltage.

[0095] [Table 1]

[0096] Table 1: Examples of boosted voltages selected by the high voltage switching circuit

[0097] Write Status Erase Status VMGPP VPPA VDD VMGPN VPPC VEEN VMGNP VPPC VDD VMGNN VDD VSS

[0098] As shown in Table 1, the high-voltage switching circuit 55 selects VPPA as the output voltage VMGPP when writing, and selects VDD as the output voltage VMGPP when erasing. The high-voltage switching circuit 55 selects VPPC as the output voltage VMGPN when writing, and selects VEEM as the output voltage VMGPN when erasing. The high-voltage switching circuit 55 selects VPPC as the output voltage VMGNP when writing, and selects VDD as the output voltage VMGNP when erasing. The high-voltage switching circuit 55 selects VDD as the output voltage VMGNN when writing, and selects VSS as the output voltage VMGNN when erasing.

[0099] Additional switches may be provided in the high voltage switching circuit 55 to handle the verify mode and the test mode, which are operation modes in addition to writing and erasing.

[0100] like Figure 5A-5D As shown, for configuration Figure 2 The high voltage switching circuit 55 in the embodiment requires level shifters 81 and 83 to 85. Among these level shifters, breakdown voltage relaxation must be considered for the positive voltage level shifter 81. The reason is as follows. At the time of writing, for example, a high voltage of 11V class is used as the voltage VPPA applied to the storage gate MG. However, even if the transistor is used for a high breakdown voltage type, the breakdown voltage of the MOS transistor configuring the positive voltage level shifter 81 is as high as about 10V. Therefore, it is necessary to prevent the high power supply voltage VPPA from being applied to each MOS transistor configuring the positive voltage level 81 in this way by breakdown voltage relaxation.

[0101] Further, because voltage VEEM is a negative high voltage of about -8V, voltage VEEM must be applied to the gate of switching NMOS transistor 74 to allow a VDD / VEEM level signal to pass therethrough in order to turn off NMOS transistor 74. Therefore, negative voltage level shifter 84 must handle negative high voltage VEEM.

[0102] [Overall configuration of negative voltage level shifter]

[0103] Figure 6 is a block diagram illustrating a configuration of a negative voltage level shifter in the semiconductor device according to the first embodiment. Figure 6The negative voltage level shifter 130 can be applied to Figure 5B Negative voltage level shifter 84 in.

[0104] Reference Figure 6 The negative voltage level shifter 130 includes a VDD-VBIAS level shifter 132, a negative voltage level shifter body 131, a medium voltage generating circuit 133 generating a medium voltage VBIAS, a power control signal generating circuit 134, and an inverter 140 operating with a low power supply voltage VDD.

[0105] The VDD-VBIAS level shifter 132 receives complementary VDD / VSS level signals inp and inn, and converts the high levels of the input signals inp and inn into a medium voltage VBIAS that is higher than the low power supply voltage VDD and lower than the medium power supply voltage VCC. For example, the input signal inn corresponds to a signal obtained by inverting the logic level of the input signal inp through the inverter 140. The VDD-VBIAS level shifter 132 outputs VBIAS / VSS level output signals outp and outn as input signals intp and intn of the next stage.

[0106] The positive power supply node up of the VDD-VBIAS level shifter 132 is coupled to the power supply node bias of the medium voltage generating circuit 133, thereby receiving the medium voltage VBIAS from the medium voltage generating circuit 133. The negative power supply node un of the VDD-VBIAS level shifter 132 receives the ground voltage VSS.

[0107] The negative voltage level shifter body 131 converts the low level of the VBIAS / VDD level input signals intp and intn outputted from the VDD-VBIAS level shifter 132 into the negative high voltage VEE. The negative voltage level shifter body 131 outputs the VBIAS / VEE level output signals outp and outn to the circuit in the subsequent stage.

[0108] The positive power supply node up of the negative voltage level shifter body 131 is coupled to the node bias of the medium voltage generating circuit 133, thereby receiving the medium voltage VBIAS from the medium voltage generating circuit 133. The negative power supply node un of the negative voltage level shifter body 131 receives the negative high voltage VEE. When the negative high voltage power supply is invalid, the ground voltage VSS is input to the negative voltage node un. Figure 6 In the figure, "VEE (or VSS)" means that the voltage of the negative power supply node un is VEE when the negative high voltage power supply is valid, and is VSS when the negative high voltage power supply is invalid. The same is true in other figures.

[0109] The medium voltage generating circuit 133 includes an NMOS transistor MNP and a PMOS transistor MPC.

[0110] The NMOS transistor MNP is configured as a source follower. Specifically, the drain of the NMOS transistor MNP is coupled to a node provided with a medium power supply voltage VCC (hereinafter also referred to as a "VCC node"). The source and back gate of the NMOS transistor MNP are coupled to a power supply node bias. A control signal biasg is provided to the gate of the NMOS transistor MNP from a power supply control signal generation circuit 134.

[0111] The PMOS transistor MPC is coupled in a diode-connected manner and serves as a clamp circuit to prevent the potential at the power supply node bias from rising too high. The source and back gate of the PMOS transistor MPC are coupled to the power supply node bias. A control signal biasc is provided to the gate of the PMOS transistor MPC from the power supply control signal generation circuit 134.

[0112] The PMOS transistor MPC is used as a path for discharging the charge of the power supply node bias.

[0113] The power control signal generating circuit 134 generates control signals biasg and biasc. The specific configuration and operation of the power control signal generating circuit 134 will be described later.

[0114] [Configuration example of negative voltage level shifter main body and its operation]

[0115] Figure 7 It is a graphic Figure 6 A circuit diagram of a configuration example of a negative voltage level shifter body in FIG. In addition to providing a medium voltage VBIAS instead of a low power supply voltage VDD to the positive power supply node up, Figure 7 The configuration of the negative voltage level shifter body 131 in FIG. 1 is substantially the same as that of a conventional negative voltage level shifter without breakdown voltage relaxation.

[0116] Specifically, Figure 7 The negative voltage level shifter body 131 in FIG. 1 includes a cross-coupled level shifter stage 150 and a driver stage 170. The level shifter stage 150 includes an input circuit 151 to which complementary input signals intp and intn are input, and a latch circuit 152.

[0117] The input circuit 151 includes a pair of input PMOS transistors MPINP and MPINN. Sources and back gates of the input PMOS transistors MPINP and MPINN are coupled to a positive power supply node up.

[0118] The latch circuit 152 includes a pair of cross-coupled NMOS transistors MNCCP and MNCCN. The sources and back gates of the NMOS transistors MNCCP and MNCCN are coupled to the negative power supply node un. The gates and drains of the NMOS transistors MNCCP and MNCCN are cross-coupled. In other words, the gate of the NMOS transistor MNCCP and the drain of the NMOS transistor MNCCN are coupled to each other, and the drain of the NMOS transistor MNCCP and the gate of the NMOS transistor MNCCN are coupled to each other.

[0119] The drain of the input PMOS transistor MPINP and the drain of the cross-coupled NMOS transistor MNCCP are coupled to each other via an output node 154. The drain of the input PMOS transistor MPINN and the drain of the cross-coupled NMOS transistor MNCCN are coupled to each other via an output node 153.

[0120] The driver stage 170 includes driver PMOS transistors MPDRP and MPDRN and driver NMOS transistors MNDRP and MNDRN.

[0121] The sources of the driver PMOS transistors MPDRP and MPDRN are coupled to the positive power supply node up, and the gates are coupled to the output nodes 153 and 154, respectively. Complementary output signals outp and outn are output from the drains of the driver PMOS transistors MPDRP and MPDRN, respectively. The sources of the driver NMOS transistors MNDRP and MNDRN are coupled to the negative power supply node un, and the gates are coupled to the output nodes 153 and 154, respectively. The drains of the driver NMOS transistors MNDRP and MNDRN are coupled to the driver PMOS transistors MPDRP and MPDRN, respectively.

[0122] Next, the operation of the above-mentioned negative voltage level shifter body 131 will be briefly described. In response to the complementary input signals intp and intn at the VBIAS / VSS level, one of the input PMOS transistors MPINP and MPINN is turned on, while the other input PMOS transistor is turned off. For example, assuming that the input PMOS transistor MPINP is turned on, the potential at the gate of the cross-coupled NMOS transistor MNCCN is pulled up, thereby turning on the cross-coupled NMOS transistor MNCCN. Therefore, the voltage of the output node 153 becomes the negative high voltage VEE, and the voltage of the output node 154 becomes the medium voltage VBIAS. In this way, the driver PMOS transistor MPDRP and the driver NMOS transistor MNDRN are turned on, so that the output signal outp is at a high level (medium voltage VBIAS) and the output signal outn is at a low level (negative high voltage VEE).

[0123] [Another Configuration Example of Negative Voltage Level Shifter Main Body and Its Operation]

[0124] Figure 8 is a circuit diagram illustrating another configuration example of the negative voltage level shifter body. Figure 8 The level shifter stage 150 in Figure 7 The difference between the level shifter stage 150 in FIG. 1 is that a breakdown voltage relaxation circuit 155 is added between the input circuit 151 and the latch circuit 152 and a level shifter 160 is added.

[0125] The breakdown voltage relaxation circuit 155 includes breakdown voltage relaxation PMOS transistors MPE1P and MPE1N and breakdown voltage relaxation NMOS transistors MNE1P and MNE1N. The breakdown voltage relaxation PMOS transistor MPE1P and the breakdown voltage relaxation NMOS transistor MNE1P are sequentially coupled in series between the drain of the input PMOS transistor MPINN and the drain of the cross-coupled NMOS transistor MNCCN. Similarly, the breakdown voltage relaxation PMOS transistor MPE1N and the breakdown voltage relaxation NMOS transistor MNE1N are sequentially coupled in series between the drain of the input PMOS transistor MPINP and the drain of the cross-coupled NMOS transistor MNCCP.

[0126] The gates of the breakdown voltage relaxation PMOS transistors MPE1P and MPE1N are provided with a ground voltage VSS. Each of the back gates is coupled to a corresponding source. The gates of the breakdown voltage relaxation NMOS transistors MNE1P and MNE1N are provided with a signal obtained by inverting the logic level of the breakdown voltage relaxation control signal noemi by the level shifter 160. The back gates are coupled to the corresponding sources.

[0127] More specifically, the breakdown voltage relaxation control signal noemi is obtained by converting a VDD / VSS level signal into a VBIAS / VSS level signal by the level shifter 160. This is because when the input high level of the breakdown voltage relaxation control signal noemi is VDD, too low VDD prevents the operation of the breakdown voltage relaxation NMOS transistors MNE1P and MNE1N.

[0128] The breakdown voltage relaxation control signal noemi is at a high level (low power supply voltage VDD) when the negative high voltage power supply is valid (i.e., breakdown voltage relaxation is valid), and is at a low level (ground voltage VSS) when the negative high voltage power supply is invalid. Therefore, when the negative high voltage power supply is valid, the ground voltage VSS is applied to the gates of the breakdown voltage MNOS transistors MNE1P and MNE1N; and when the negative high voltage power supply is invalid, the medium voltage VBIAS is applied to the gates of the breakdown voltage MNOS transistors MNE1P and MNE1N.

[0129] Figure 8 The driver stage 170 in Figure 7 The difference between the driver stage 170 in FIG. 1 and FIG. 2 is that the former also includes breakdown voltage relaxation PMOS transistors MPE2P and MPE2N and breakdown voltage relaxation NMOS transistors MNE2P and MNE2N. The breakdown voltage relaxation PMOS transistor MPE2P and the breakdown voltage relaxation NMOS transistor MNE2P are sequentially coupled in series between the drain of the driver PMOS transistor MPDRP and the drain of the driver NMOS transistor MNDRP. Similarly, the breakdown voltage relaxation PMOS transistor MPE2N and the breakdown voltage relaxation NMOS transistor MNE2N are sequentially coupled in series between the drain of the driver PMOS transistor MPDRN and the drain of the driver NMOS transistor MNDRN.

[0130] The ground voltage VSS is provided to the gates of the breakdown voltage relaxation PMOS transistors MPE2P and MPE2N. The breakdown voltage relaxation control signal noemi is input to the gates of the breakdown voltage relaxation NMOS transistors MNE2P and MNE2N, the logic level of which has been inverted and which has been converted into a VBIAS / VSS level signal. The back gates of the breakdown voltage relaxation PMOS transistors MPE2P and MPE2N are coupled to the corresponding sources. The back gates of the breakdown voltage relaxation NMOS transistors MNE2P and MNE2N are coupled to the corresponding sources.

[0131] The output signal outp is output from a coupling node 171 between the drain of the breakdown voltage relaxation PMOS transistor MPE2P and the drain of the breakdown voltage relaxation NMOS transistor MNR2P. The output signal outn is output from a coupling node 172 between the drain of the breakdown voltage relaxation PMOS transistor MPE2P and the drain of the breakdown voltage relaxation NMOS transistor MNR2N.

[0132] In addition to adding the breakdown voltage relaxation function, Figure 8 The operation of the negative voltage level shifter body 131 is similar to Figure 7 The negative voltage level shifter body 131 in is basically the same.

[0133] Specifically, the voltage applied to the input PMOS transistors MPINP and MPINN and the driver PMOS transistors MPDRP and MPDRN is limited to VBIAS-VSS. The voltage applied to the cross-coupled NMOS transistors MNCCP and MNCCN and the driver NMOS transistors MNDRP and MNDRN is limited to VSS-VEE when the negative voltage level shifter body 131 is valid, and is limited to VBIAS-VSS when the negative voltage level shifter body 131 is invalid.

[0134] Through the above configuration, damage to the gate oxide film in each of the input PMOS transistors MPINP and MPINN, the cross-coupled NMOS transistors MNCCP and MNCCN, the driver PMOS transistors MPDRP and MPDRN, and the driver NMOS transistors MNDRP and MNDRN, for example, due to FN (Fowler-Nordheim) degradation, can be suppressed.

[0135] [Configuration example of VDD-VBIAS level shifter and its operation]

[0136] Fig. 9 It is a graphic Figure 6 1 is a circuit diagram of a configuration example of a VDD-VBIAS level shifter in FIG. When the medium voltage VBIAS to be applied to the positive power supply node up is too high, it is difficult to satisfy the breakdown voltage condition of the MOS transistor configuring the level shifter. Therefore, the potential difference between the low power supply voltage VDD and the medium voltage VBIAS is set relatively small. Thus, as Fig. 9 The cross-coupled level shifters shown may be used as the VDD-VBIAS level shifter 132 .

[0137] Reference Fig. 9 The VDD-VBIAS level shifter 132 includes a pair of input PMOS transistors MPINP and MPINN (190), a pair of input NMOS transistors MNINP and MNINN (191), and cross-coupled PMOS transistors MPCCP and MPCCN (192) provided therebetween.

[0138] The sources of the input PMOS transistors MPINP and MPINN are coupled to the positive power supply node up, as shown in FIG. Fig. 9 As shown. The drains of the input PMOS transistors MPINP and MPINN are coupled to the sources of the cross-coupled PMOS transistors MPCCP and MPCCN, respectively. The sources of the input NMOS transistors MNINP and MNINN are coupled to the negative power supply node un. The drains of the input NMOS transistors MNINP and MNINN are coupled to the drains of the cross-coupled PMOS transistors MPCCP and MPCCN, respectively. The back gates of the input PMOS transistors MPINP and MPINN and the cross-coupled PMOS transistors MPCCP and MPCCN are coupled to the positive power supply node up. The back gates of the input NMOS transistors MNINP and MNINN are coupled to the negative power supply node un.

[0139] The input signal inp is input to the gate of the input PMOS transistor MPINN and the gate of the input NMOS transistor MNINN. The input signal inn complementary to the input signal inp is input to the gate of the input PMOS transistor MPINP and the gate of the input NMOS transistor MNINP. The output signal outp is output from the coupling node 195 between the cross-coupled PMOS transistor MPCCP and the input NMOS transistor MNINP. The output signal outp complementary to the output signal outp is output from the coupling node 196 between the cross-coupled PMOS transistor MPCCN and the input NMOS transistor MNINN.

[0140] The operation of the negative voltage level shifter body 131 configured as above is briefly described. For example, it is assumed that the input signal inp is at a high level (low power supply voltage VDD) and the input signal inn is at a low level (ground voltage VSS). Thus, the input NMOS transistor MNINN is turned on, the input NMOS transistor MNINP is turned off, and the input PMOS transistor MPINP is turned on. If the low power supply voltage VDD is much lower than the medium voltage VBIAS, the input PMOS transistor MPINN is not completely turned off in some cases.

[0141] When the input NMOS transistor MNINN is turned on, the voltage of the coupling node 196 (output signal outn) becomes approximately equal to the ground voltage VSS. Thus, the charge in the gate of the PMOS transistor MPCCP is pulled out, so that the PMOS transistor MPCCP is turned on. Therefore, the voltage of the coupling node 195 (output signal outp) becomes approximately equal to the intermediate voltage VBIAS.

[0142] Further, when the voltage of the coupling node 195 becomes equal to the intermediate voltage VBIAS, the PMOS transistor MPCCN is turned off. As described above, by providing the cross-coupled PMOS transistors MPCCP and MPCCN, a through current between the positive power node up and the negative power node un can be blocked.

[0143] [Configuration Example of Power Supply Control Signal Generation Circuit]

[0144] Fig.10 It is a graphic Figure 6 A circuit diagram showing an example of a configuration of a power supply control signal generating circuit in FIG. Fig.10 The power control signal generating circuit 134 includes PMOS transistors MPM1A and MPM1B configuring a current mirror circuit 220, NMOS transistors MNM2A and MNM2B configuring a current mirror circuit 221, an NMOS transistor MNR, a PMOS transistor MPR, and current sources I1 and I2. First, coupling of these circuit components is described.

[0145] The sources of the PMOS transistors MPM1A and MPM1B configuring the current mirror circuit 220 are coupled to the VCC node. The gate of each of the PMOS transistors MPM1A and MPM1B is coupled to the drain of the PMOS transistor MPM1A. The back gates of the PMOS transistors MPM1A and MPM1B are coupled to the sources thereof, respectively.

[0146] The NMOS transistor MNR and the current source I1 are provided in series with each other on a current path 222, and the current path 222 couples the drain of the PMOS transistor MPM1A and a node provided with a ground voltage VSS (hereinafter also referred to as a "VSS node") to each other. The low power supply voltage VDD is applied to the gate of the NMOS transistor MNR. The back gate of the NMOS transistor MNR is coupled to its source. The NMOS transistor MNR is a replica of the input NMOS transistors MNINP and MNINN configuring the VDD-VBIAS level shifter 132.

[0147] NMOS transistor MNM2A and PMOS transistor MPR are provided in series with each other on a current path 223 that couples the drain of PMOS transistor MPM1B and the VSS node with each other. Low power supply voltage VDD is applied to the gate of PMOS transistor MPR. The back gate of PMOS transistor MPR is coupled to its source.

[0148] NMOS transistors MNM2A and MNM2B are Figure 6 The source follower NMOS transistor MNP is a replica of the source follower NMOS transistor MNP in the configuration. Further, the PMOS transistor MPR is Fig. 9 The input PMOS transistors MPINP and MPINN of the VDD-VBIAS level shifter 132 in the current mirror circuit 220 are duplicated. However, as described below, the size (gate width) of the PMOS transistor MPR is formed to be several times to about 10 times the size of the input PMOS transistors MPINP and MPINN (when the mirror ratio of the current mirror circuit 220 is 1:1).

[0149] The NMOS transistor MNM2B and the NMOS transistor MNM2A together configure a current mirror circuit 221. The gate of the NMOS transistor MNM2B is coupled to the gate and drain of the NMOS transistor MNM2A. The drain of the MOS transistor MNM2B is coupled to the VCC node. The back gates of the NMOS transistors MNM1A and MNM1B are coupled to their sources, respectively. The current source I2 is provided on a current path 224 that couples the source of the NMOS transistor MNM2B and the VSS node to each other.

[0150] The coupling node 210 between the PMOS transistor MPM1B and the NMOS transistor MNM2A is coupled to the signal line 225 provided at Figure 6 The control signal biasg is thus provided to the gate of the NMOS transistor MNP in the medium voltage generating circuit 133 in the circuit. The coupling node 211 between the NMOS transistor MNM2B and the current source I2 is coupled to the gate of the NMOS transistor MNP via the signal line 226. Figure 6 The control signal biasc is provided to the gate of the PMOS transistor MPC in the medium voltage generating circuit 133. Thus, the control signal biasc is provided to the gate of the PMOS transistor MPC.

[0151] [Operation of the power supply control signal generating circuit]

[0152] The following will describe Fig.10 Operation of the power supply control signal generating circuit 134 in FIG. First, an outline of the operation is described.

[0153] When a low power supply voltage VDD is applied to the gate of each transistor MNR or MPR by using a current mirror circuit, the power supply control signal generating circuit 134 adjusts the current value of the replica NMOS transistor MNR and the current value of the replica PMOS transistor MPR. The current value in this case is determined as a value at which the VDD-VBIAS level shifter 132 operates stably with respect to the VDD / VSS level input signal. In this state, the power supply control signal generating circuit 134 outputs the gate voltage of the replica PMOS transistor MNM2A as the control signal biasg, and outputs the source voltage of the replica NMOS transistor MNM2A as the control signal biasc.

[0154] Next, refer to Figure 6 , Fig. 9 and Fig.10 , combined with Figure 6 The operation of the power control signal generating circuit 134 will be described in more detail with reference to the medium voltage generating circuit 133 in FIG.

[0155] ( Figure 6 Function of the PMOS transistor MPC in the medium voltage generating circuit)

[0156] Reference Figure 6, the power supply node bias of the medium voltage generating circuit 133 is coupled to the positive power supply node up of the VDD-VBIAS level shifter 132 and the positive power supply node up of the negative voltage level shifter body 131. Here, each of the VDD-VBIAS level shifter 132 and the negative voltage level shifter body 131 does not substantially cause current consumption as long as an inverting operation is performed. Therefore, in order to prevent leakage in the NMOS transistor MNP from causing an excessive rise in the medium voltage VBIAS of the power supply node bias, when VBIAS>biasc, current flows in a direction from the power supply node bias to the power supply control signal generating circuit 134 via the clamp PMOS transistor MPC. Therefore, the medium voltage VBIAS of the power supply node bias is not allowed to rise to a predetermined value or more.

[0157] (How to set medium voltage VBIAS)

[0158] The medium voltage VBIAS is set to allow the VDD-VBIAS level shifter 132 to operate stably. Fig. 9 In the example of the VDD-VBIAS level shifter 132 shown, when the current value when the low power supply voltage VDD is applied to the input NMOS transistors MNINP and MNINN is much greater than the current value when the low power supply voltage VDD is applied to the input PMOS transistors MPINP and MPINN, for example, when the former current value is several times to ten times or more than the latter current value, the VDD-VBIAS level shifter 132 operates stably. As shown above, considering that the input signals inp and inn are VDD / VSS level signals, the voltage applied to the positive power supply node up is the middle voltage VBIAS and is higher than the low power supply voltage VDD. Therefore, the input PMOS transistors MPINP and MPINN are not completely disconnected.

[0159] Here, the drain current increases according to the gate-source voltage. Therefore, the above conditions can be replaced by the conditions of the gate-source voltage. When the low power supply voltage VDD is applied to the gates of the input NMOS transistors MNINP and MNINN, the gate-source voltage Vgs is VDD. At the same time, when the low power supply voltage VDD is applied to the gates of the input NMOS transistors MNINP and MNINN, the absolute value of the gate-source voltage |Vgs| is VBIAS-VDD. Therefore, the medium voltage VBIAS is selected to satisfy:

[0160] VDD>>VBIAS-VDD...(1).

[0161] (How to set the control signal biasg)

[0162] Fig.10The power control signal generating circuit 134 shown in the figure is characterized by using an NMOS transistor MNP. Fig. 9 The input NMOS transistors MNINP and MNINN of the VDD-VBIAS level shifter 132 in FIG. 1 are duplicates, and a PMOS transistor MPR is used, which is a duplicate of the input PMOS transistors MPINP and MPINN.

[0163] Although the low power supply voltage VDD is applied to the gate of the replica NMOS transistor MNR and the gate of the replica PMOS transistor MPR, a current equal to the current flowing into the replica NMOS transistor MNR flows into the replica PMOS transistor MPR by using the current mirror circuit 220. Therefore, the voltage of the node 212 which is the source terminal of the PMOS transistor MPR is converged to a value equal to the intermediate voltage VBIAS (hereinafter also referred to as virtual VBIAS).

[0164] Fig.10 The diode-connected NMOS transistor MNM2A is configured Figure 6 Therefore, the gate voltage of the replica NMOS transistor MNM2A (i.e., a voltage (virtual VBIAS+Vth_N) higher than the virtual VBIAS as the voltage of the node 212 by the threshold voltage Vth_N of the replica NMOS transistor MNM2A) is input to the gate of the NMOS transistor MNP as the control signal biasg.

[0165] Here, for Fig. 9 The stable operating condition of the VDD-VBIAS level shifter 132 shown, assumes that the on-current of the input NMOS transistor MNINP or MNINN when the low power supply voltage VDD is applied to its gate is 10 times the on-current of the input PMOS transistor MPINP or MPINN when the low power supply voltage VDD is applied to its gate. In this case, the size of the replica NMOS transistor MNP is formed to be equal to the size of the input NMOS transistors MNINP and MNINN. At the same time, the size of the replica PMOS transistor MPR is formed to be 10 times the size of the input PMOS transistors MPINP and MPINN. The mirror ratio of the current mirror circuit 220 is set to 1:1.

[0166] Alternatively, the replica PMOS transistor MPR may be sized equal to the input PMOS transistors MPINP and MPINN. In this case, the mirror ratio 220 of the current mirror circuit is set to 10:1 (in other words, the PMOS transistor MPM1A is sized 10 times the size of the PMOS transistor MPM1B).

[0167] The current source I1 coupled between the source of the replica NMOS transistor MNR and the VSS node is used to limit the current to achieve low power consumption. In other words, under the operating condition that the low power supply voltage VDD is high and / or the operating condition that the threshold voltage of the NMOS transistor MNR is low, the current source I1 is provided to prevent a substantial increase in the on-current of the NMOS transistor MNR. The virtual VBIAS converges to a voltage value corresponding to the current value of the current source I1.

[0168] (How to set the control signal biasc)

[0169] The control signal biasc is set as Figure 6 The control signal bias is provided to the gate of the NMOS transistor MN2B.

[0170] Further, the current source I2 is coupled between the source of the NMOS transistor MNM2B and the VSS node. Figure 6 The bias current flows from the power supply node to the VSS node, even if the leakage current flows into Figure 6 The NMOS transistor MNP in Figure 6 The voltage of the power supply node bias in the circuit will not rise excessively. Figure 6 The VDD-VBIAS level shifter 132 has a positive power supply node up and a negative power supply node up of the level shifter body 131 has a medium voltage VBIAS.

[0171] [Advantageous Effects of the First Embodiment]

[0172] As described above, according to the first embodiment, the VDD-VBIAS level shifter 132 for converting the VDD / VSS level input signals inp and inn into the VBIAS / VSS level signals is added in the previous stage of the negative voltage level shifter body 131. Since the high level of the input signals intp and intn of the negative voltage level shifter 131 is pulled up from the low power supply voltage VDD to the medium voltage VBIAS by the VDD-VBIAS level shifter 132 in the previous stage, the negative power supply level shifter 130 can be allowed to operate stably even in the case where the low power supply voltage VDD is low.

[0173] Further, the power supply voltage applied to the positive power supply node up of the negative voltage level shifter body 131 also changes from the low power supply voltage VDD to the medium voltage VBIAS. Therefore, the high level of the output signals outp and outn also rises to the medium voltage VBIAS. Thus, the switching NMOS transistor receiving the output signal outp or outn at its gate can be reliably controlled and turned on / off.

[0174] In order to generate a medium voltage VBIAS satisfying VBIAS>VDD, a medium voltage generating circuit 133 is provided. Further, a power control signal generating circuit 134 is provided for generating control signals biasg and biasc to be provided to the medium voltage generating circuit 133.

[0175] The power control signal generating circuit 134 includes a PMOS transistor MPR, which is a replica of the input PMOS transistors MPINP and MPINN of the VDD-VBIAS level shifter 132, and an NMOS transistor MNR, which is a replica of the input NMOS transistors MNINP and MNINN. By using the current mirror circuit 220, an appropriate bias current is made to flow into these replica MOS transistors MPR and MNR. In this case, the bias current value is set to allow the VDD-VBIAS shifter 132 to operate stably. Therefore, the medium voltage VBIAS is automatically determined, and the control signal biasg is determined according to the value of the medium voltage VBIAS.

[0176] Further, a PMOS transistor MPC is provided to prevent the negative voltage level shifter body 131 and the VDD-VBIAS level shifter 132 from performing an inversion operation. Figure 6 In order to prevent the voltage of the power supply node bias from excessively rising due to leakage of the NMOS transistor MNP in the medium voltage generating circuit 133, an NMOS transistor MNM2B is provided as a replica of the PMOS transistor MPR in the power control signal generating circuit 134. The excessive increase of the voltage of the power supply node bias is prevented by the current source I2 coupled to the source of the NMOS transistor MNM2B. The control signal biasc provided to the medium voltage generating circuit 133 is pulled out from the source of the NMOS transistor MNM2B.

[0177] [Modification of First Embodiment]

[0178] exist Figure 6In the medium voltage generating circuit 133, the drain of the clamping PMOS transistor MPC is coupled to its gate, and the drain is provided with the control signal bias as the gate. However, the clamped potential at the power supply node bias is determined by the gate potential of the PMOS transistor MPC. Therefore, the drain potential is lower than the gate potential. Fig.11 A modification that takes this into account is illustrated in FIG.

[0179] Fig.11 The diagram shows Figure 6 A modified negative voltage level shifter configuration. Fig.11 The negative voltage level shifter 130A in Figure 6 The negative voltage level shifter 130 in FIG. 1 is different in that the drain of the PMOS transistor MPC provided in the medium voltage generating circuit 133 is coupled to the VSS node. Fig.11 The other points in Figure 6 Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0180] Although in Fig.11 The drain voltage of the PMOS transistor MPC is the ground voltage VSS, but the drain voltage can be any voltage as long as it is lower than the voltage value of the control signal biasc and is stable. For example, the drain voltage of the PMOS transistor MPC can be set to the low power supply voltage VDD.

[0181] Further, Fig.11 The changes in can also be applied to the second to sixth embodiments described later.

[0182] Second embodiment

[0183] In the first embodiment, the common medium voltage VBIAS is supplied from the common medium voltage generating circuit 133 to the positive power supply node up of the negative voltage level shifter body 131 in the previous stage and the positive power supply node up of the VDD-VBIAS level shifter 132. This is because it is necessary to make the high level of the input signals intp and intn of the negative voltage level shifter body 131 and the medium voltage VBIAS supplied to the positive power supply node up the same.

[0184] However, since the two level shifters 131 and 132 are different in operation timing and current consumption, by sharing the power supply, fluctuation of the power supply voltage of one level shifter may affect the operation of the other level shifter. The second embodiment presents a configuration for solving this problem.

[0185] [Configuration of negative voltage level shifter]

[0186] Fig.12A configuration of a negative voltage level shifter in a semiconductor device according to a second embodiment is illustrated.

[0187] Reference Fig.12 , Fig.12 The negative voltage level shifter 130B in Figure 6 The difference between the negative voltage level shifter 130 in FIG. 1 is that the medium voltage generating circuit 133 is divided into a medium voltage generating circuit 133A for the VDD-VBIAS level shifter 132 in the previous stage and a medium voltage generating circuit 133B for the negative voltage level shifter body 131 in the next stage.

[0188] The configuration of each of the medium voltage generating circuits 133A and 133B is similar to Figure 6 Specifically, the medium voltage generating circuit 133A includes a power supply node bias0, an NMOS transistor MNP0, and a PMOS transistor MPC0. The power supply node bias0, the NMOS transistor MNP0, and the PMOS transistor MPC0 correspond to Figure 6 The power supply node bias, the NMOS transistor MNP and the PMOS transistor MPC in the medium voltage generating circuit 133 in FIG. Similarly, the medium voltage generating circuit 133B includes a power supply node bias1, an NMOS transistor MNP1 and a PMOS transistor MPC1. The power supply node bias1, the NMOS transistor MNP1 and the PMOS transistor MPC1 correspond to Figure 6 The power supply node bias, the NMOS transistor MNP and the PMOS transistor MPC in the medium voltage generating circuit 133.

[0189] exist Fig.12 In the embodiment, a power control signal generating circuit 134 is provided, which is shared by the medium voltage generating circuits 133A and 133B. Specifically, the power control signal generating circuit 134 provides a common control signal biasg to the gate of the NMOS transistor MNP0 of the medium voltage generating circuit 133A and the gate of the NMOS transistor MNP1 of the medium voltage generating circuit 133B. The power control signal generating circuit 134 provides a common control signal biasc to the gate of the PMOS transistor MPC0 of the medium voltage generating circuit 133A and the gate of the PMOS transistor MPC1 of the medium voltage generating circuit 133B.

[0190] Fig.12 The other points in Figure 6 Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0191] [Operation of negative voltage level shifter]

[0192] The medium voltage generating circuit 133A and the medium voltage generating circuit 133B differ from each other only in the size of the internal MOS transistors, but are identical in circuit configuration. Therefore, the voltage of the power supply node bias0 of the medium voltage generating circuit 133A and the voltage of the power supply node bias1 of the medium voltage generating circuit 133B are identical in terms of DC voltage. However, there is a difference between the voltage drop of the power supply node bias0 when the VDD-VBIAS level shifter 132 performs an inversion operation and the voltage drop of the power supply node bias1 when the negative voltage level shifter 131 performs an inversion operation.

[0193] Generally, the negative voltage level shifter body 131 in the subsequent stage consumes much more current than the VDD-VBIAS level shifter 132 in the previous stage. Therefore, when the level shifters 131 and 132 share a common power supply, a voltage drop of a power supply node bias1 associated with the operation of the negative voltage level shifter body 131 in the subsequent stage may reach a power supply node bais0 of the VDD-VBIAS level shifter 132 in the previous stage, thereby affecting the operation of the VDD-VBIAS level shifter 132 in the previous stage.

[0194] In the case of the second embodiment, the power supply node bias0 and the power supply node 1 are separated from each other, so the above-mentioned phenomenon of reaching the voltage drop does not occur.

[0195] [Advantageous Effects of the Second Embodiment]

[0196] As described above, according to the second embodiment, the medium voltage generating circuit 133A for the VDD-VBIAS level shifter 132 in the previous stage and the medium voltage generating circuit 133B for the negative voltage level shifter main body 131 are provided separately from each other. Therefore, the power supply node bias0 for the VDD-VBIAS level shifter 132 and the power supply node bias1 for the negative voltage level shifter main body 131 are separated from each other. In this way, the power supply noise caused by the inversion operation of one of the level shifters does not reach the power supply node of the other level shifter, thereby enabling the stable inversion operation of the level shifter.

[0197] Further, since the current consumption difference between the VDD-VBIAS level shifter 132 and the negative voltage level shifter body 131 is large, the appropriate size of the MOS transistor can be set according to the current consumption of the corresponding level shifter in the corresponding medium voltage generating circuit 133A and 133B.

[0198] Third embodiment

[0199] The first and second embodiments are based on the voltage of the positive power supply node up of the negative voltage level shifter body 131 and the voltage of the positive power supply node up of the VDD-VBIAS level shifter 132 in the previous stage being at the same level. However, these two voltages are not necessarily at the same level. This is because, for the negative voltage level shifter body 131, the input PMOS transistors MPINP and MPINN can be completely disconnected when the high level of the input signals intp and intn is higher than the voltage level of the positive power supply node up. The third embodiment describes an example in which the power supply voltage for the negative voltage level shifter body 131 and the power supply voltage for the VDD-VBIAS level shifter in the previous stage are set to be at different levels.

[0200] [Configuration of negative voltage level shifter]

[0201] Fig.13 A configuration of a negative voltage level shifter in a semiconductor device according to a third embodiment is illustrated.

[0202] Reference Fig.13 , Fig.13 The negative voltage level shifter 130C in Fig.12 The difference between the negative voltage level shifter 130B in the embodiment is that the power control signal generating circuit 134 is divided into the power control signal generating circuit 0 (134A) for the VDD-VBIAS level shifter 132 in the previous stage and the power control signal generating circuit 1 (134B) for the negative voltage level shifter body 131 in the next stage. Therefore, the power control signal generating circuit 0 (134A) provides the control signals biasc0 and biasg0 to the medium voltage generating circuit 133A. The power control signal generating circuit 1 (134B) provides the control signals biasc1 and biasg1 to the medium voltage generating circuit 133B independently of the power control signal generating circuit 0 (134A).

[0203] By the above configuration, the values ​​of the control signals biasc0 and biasg0 can be made different from the values ​​of the control signals biasc1 and biasg1. Therefore, the intermediate voltage VBIAS0 supplied to the positive power supply node up of the VDD-VBIAS level shifter 132 in the previous stage and the intermediate voltage VBIAS1 supplied to the positive power supply node up of the negative voltage level shifter body 131 can be made different from each other. However, VBIAS0>VBIAS1 must be satisfied.

[0204] Fig.13 The other points in Fig.12 Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0205] [Advantageous Effects of the Third Embodiment]

[0206] By adopting Fig.13 the configuration in Fig.13 , when viewed from the breakdown voltage angle of the negative voltage level shifter main body 131, if the middle voltage VBIAS0 determined from the stable operation angle of the VDD-VBIAS level shifter 132 in the previous stage is too high, the middle voltage VBIAS1 supplied to the negative voltage level shifter main body 131 can be set to satisfy VBIAS1 < VBIAS0. Thus, the maximum voltage VBIAS1 - VEE applied to the MOS transistors in the negative voltage level shifter main body 131 can be reduced.

[0207] Fourth Embodiment

[0208] In the first to third embodiments, the voltage of the positive power supply node up applied to the negative voltage level shifter main body 131 is the middle voltage VBIAS that is higher than the low power supply voltage VDD. However, when the load driven by the negative voltage level shifter is large, it is necessary to increase the size of the MOS transistors used in the middle voltage generation circuit 131 that generates the middle voltage VBIAS, which is disadvantageous in terms of area.

[0209] The fourth embodiment describes that by restricting the usage conditions of the negative voltage level shifter, the voltage of the positive power supply node up applied to the negative voltage level shifter main body 131 can be returned to the low power supply voltage VDD supplied from the outside.

[0210] [Overall Configuration of Negative Voltage Level Shifter]

[0211] Fig.14 The figure illustrates the configuration of the negative voltage level shifter in the semiconductor device according to the fourth embodiment.

[0212] Referring to Fig.14 , Fig.14 the negative voltage level shifter 130D in Fig.14 is different from the negative voltage level shifter 130B in Fig.12 in that: the middle voltage generation circuit 133B for the negative voltage level shifter main body 131 is removed, and instead, the low power supply voltage VDD is supplied to the positive power supply node up of the negative voltage level shifter main body 131.

[0213] Furthermore, in the case of the fourth embodiment, a part of the configuration of the VDD-VBIAS level shifter 132 is changed. The reasons for the disadvantages of the configuration of the VDD-VBIAS level shifter 132 described in the first to third embodiments are as follows.

[0214] The PMOS transistors (for example, Figure 7 ​​The driving capability of the input PMOS transistors MPINP and MPINN in FIG. 1 depends on the absolute value |Vgs| of the gate-source voltage Vgs. Specifically,

[0215] |Vgs|=voltage of positive power supply node up-lower limit voltage of input signal intp or intn...(2).

[0216] In the case of the first to third embodiments, the lower limit voltage (i.e., low level) of the input signals intp and inpn is the ground voltage VSS. Therefore, when the voltage of the positive power supply node up is set to the low power supply voltage VDD, the absolute value of the gate-source voltage |Vgs| is VDD-VSS. Therefore, when the low power supply voltage VDD is low, the driving capability of the input PMOS transistor cannot be fully obtained, so that the input PMOS transistor may not operate normally. In order to solve this problem, in the first to third embodiments, the gate-source voltage |Vgs| of the input PMOS transistor is increased by setting the applied voltage of the positive power supply voltage node up to the medium voltage VBIAS (>VDD).

[0217] In the fourth embodiment, the voltage of the positive power supply node up cannot be changed to a voltage other than the low power supply voltage VDD. Therefore, the lower limit voltage of the input signals intp and intn is changed to VBB lower than the ground voltage VSS to solve the above problem. Here, VBB is regarded as being at a negative voltage level shallower than -1V. Therefore, the VDD-VBIAS level shifter 132 in the previous stage converts the VDD / VSS level input signals inp and inn into VBIAS / VBB level signals. A medium voltage VBIAS is applied to the positive power supply node up of the VDD / VBIAS level shifter 132. A shallow negative voltage VBB is applied to its negative power supply node un. When the power supply generating the shallow negative voltage VBB is invalid, the voltage of the negative power supply node un is the ground voltage VSS.

[0218] Thus, the input signals intp and intn of the negative voltage level shifter body 131 are VBIAS / VBB level signals. Therefore, even if the voltage applied to the positive power supply node up is the low power supply voltage VDD, the negative voltage level shifter body 131 can be allowed to operate stably.

[0219] [Configuration example of VDD-VBIAS level shifter]

[0220] Fig.15 It is a graphic Fig.14 Circuit diagram of a configuration example of the VDD-VBIAS level shifter. Fig.15 The VDD-VBIAS level shifter 132 in Fig. 9The difference between the VDD-VBIAS level shifter 132 in FIG. 1 is that the former also includes cross-coupled NMOS transistors MNCCP and MNCCN (193) located between the cross-coupled PMOS transistors MPCCP and MPCCN (192) and the input NMOS transistors MNINP and MNINN (191).

[0221] Specifically, the cross-coupled NMOS transistor MNCCP is coupled between the PMOS transistor MPCCP and the input NMOS transistor MNINP connected in series therewith. The cross-coupled NMOS transistor MNCCN is coupled between the PMOS transistor MPCCN and the input NMOS transistor MNINN connected in series therewith. The gates and drains of the cross-coupled NMOS transistors MNCCP and MNCCN are cross-coupled. The back gates of the cross-coupled NMOS transistors MNCCP and MNCCN are coupled to the negative power supply node un.

[0222] The output signal outp is output from a coupling node 195 between the PMOS transistor MPCCP and the cross-coupled NMOS transistor MNCCP. The output signal outn is output from a coupling node 196 between the PMOS transistor MPCCN and the cross-coupled NMOS transistor MNCCN.

[0223] In the above configuration, the cross-coupled NMOS transistors MNCCP and MNCCN are necessary to prevent the through current from flowing between the positive power node up and the negative power node un. Because the voltage applied to the negative power node un is set to a negative voltage VBB shallower than the ground voltage VSS, the voltage of VSS-VBB is applied across the gate and source of each input NMOS transistor MNINP or MNINN even when the input signal inp or inn is at a low level (ground voltage VSS). Therefore, the input NMOS transistor MNINP or MNINN may not be completely disconnected. On the other hand, the voltage across the gate and source of one of the cross-coupled NMOS transistors MNCCP and MNCCN becomes 0V. Therefore, the through current can be avoided.

[0224] [Configuration example of negative voltage level shifter main body]

[0225] Without making any changes, Figure 7 The negative voltage level shifter body 131 shown without breakdown voltage relaxation can be used for Fig.14 The negative voltage level shifter 130D in the Figure 8 The negative voltage level shifter body 131 with breakdown voltage relaxation is shown partially modified to be used for Fig.14The required changes will be described below with reference to the accompanying drawings.

[0226] Fig.16 It is a graphic Fig.14 A circuit diagram of a configuration example of a negative voltage level shifter body in FIG. Fig.16 The negative voltage level shifter body 131 in Figure 8 The negative voltage level shifter body 131 in FIG. 1 is different in that a shallow negative voltage VBB is applied to the gates of the breakdown voltage relaxation PMOS transistors MPE1P, MPE1N, MPE2P, and MPE2N instead of the ground voltage VSS. Fig.16 The other points in Figure 8 Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0227] Assume that the ground voltage VSS is applied to the gates of the breakdown voltage relaxation PMOS transistors MPE1P and MPE1N. In this case, the breakdown voltage relaxation PMOS transistors MPE1P and MPE1N interfere with the operation of the negative voltage level shifter body 131, thereby losing the effect provided by lowering the low level of the input signals inp and inn to the shallow low negative voltage VBB. In order to prevent this, it is necessary to change the gate voltages of the breakdown voltage relaxation PMOS transistors MPE1P, MPE1N, MPE2P, and MPE2N from the ground voltage VSS to the shallow negative voltage VBB.

[0228] [Usage conditions of negative voltage level shifter]

[0229] In the fourth embodiment, the output signals outp and outn of the negative voltage level shifter body 131 are at the VDD / VEE level. Therefore, the above-mentioned negative voltage level shifter 130 cannot be used to control the switching NMOS transistor for allowing the VSS level signal to pass therethrough. This is because the gate-source voltage Vgs in this case is VDD-VSS, and therefore a sufficient gate-source voltage Vgs cannot be obtained when VDD is low.

[0230] However, the negative voltage level shifter 130D can be used to control the switching NMOS transistor while allowing a signal at a negative voltage level to pass, i.e., closing the switch when the voltage level of the signal is the ground voltage VSS and opening the switch when the voltage level is a negative voltage.

[0231] Specifically, when the negative high voltage is invalid (VEE = VSS), the output signal of the negative voltage level shifter 130D is set to a low level (VSS), thereby turning off the NMOS transistor switch. When the negative high voltage power supply is valid (VEE < VSS), the output signal of the negative voltage level shifter 130D is set to a high level (VDD), so that the gate-source voltage of the switching NMOS transistor is VDD - VEE. When VEE deepens to a certain extent, the gate-source voltage Vgs is fully ensured. Therefore, the NMOS transistor can be turned on.

[0232] When the negative voltage level shifter 130D is inverted, the input signals inp and inn of the negative voltage level shifter 130D are switched when the negative high voltage power supply is invalid. In this state, the gate-source voltage Vgs of the switching NMOS transistor is VDD - VSS. Therefore, the switching NMOS transistor does not allow signals to pass through it stably. Subsequently, when the negative high voltage power supply is started, the negative voltage level shifter main body 131 is inverted when the negative high voltage VEE deepens to a certain extent. In this state, the gate-source voltage Vgs of the switching NMOS transistor is VDD - VEE. Therefore, the switching NMOS transistor can allow signals to pass through it stably.

[0233] [Advantages of the Fourth Embodiment]

[0234] As described above, the fourth embodiment has described that if the usage conditions of the negative voltage level shifter are restricted, the voltage of the positive power supply node up of the negative voltage level shifter can be returned from the intermediate voltage VBIAS to the low power supply voltage VDD. Accordingly, there is no longer a need for an intermediate voltage generation circuit for the level shifter main body, so the layout area of the negative voltage level shifter can be greatly reduced.

[0235] Fifth Embodiment

[0236] In the first to fourth embodiments, the constant current sources I1 and I2 in the power supply control signal generation circuit 134 have been operating all the time. Therefore, a constant DC current power consumption is generated. However, in a state where no negative voltage is generated, when it is not necessary to operate the negative voltage level shifter, this constant current is an unnecessary current. The fifth embodiment describes the configuration of the negative voltage level shifter 130E having a function of stopping the constant current sources I1 and I2 in the power supply control signal generation circuit 134.

[0237] [Overall Configuration of the Negative Voltage Level Shifter]

[0238] Fig.17 The configuration of the negative voltage level shifter in the semiconductor device according to the fifth embodiment is illustrated. Fig.17 The negative voltage level shifter 130E in Figure 6The difference between the negative voltage level shifter 130 in FIG. 1 is that an enable signal en and a discharge signal disc are added, and the previous level shifter 130E further includes VDD-VCC level shifters 135A and 135B.

[0239] The enable signal en is a control signal for determining an operation time period of the negative voltage level shifter 130E. The discharge signal disc is a signal for determining a timing for discharging the charge of the power supply node bias by the control signal biasc.

[0240] Each of the VDD-VCC level shifters 135A and 135B converts a VDD / VSS level signal into a VCC / VSS level. Specifically, the VDD-VCC level shifter 135A converts a VDD / VSS level discharge signal disc into a VCC / VSS level discharge signal discp, and outputs the discharge signal discp to the power control signal generation circuit 134. The VDD-VCC level shifter 135B converts a VDD / VSS level enable signal en into complementary VCC / VSS level enable signals enp and enn, outputs the enable signal enp to the power control signal generation circuit 134 and the VDD-VBIAS level shifter 132, and outputs the enable signal enn to the VDD-VBIAS level shifter 132.

[0241] Further, the power supply control signal generating circuit 134 is additionally provided with a function of cutting off the constant current source, and the VDD-VBIAS level shifter 132 in the previous stage is additionally provided with a function of fixing the output when stopped. An example of a specific configuration of these circuit components will be described below.

[0242] Fig.17 The other points of the negative voltage level shifter 130E are Figure 6 Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0243] [Configuration example of VDD-VBIAS level shifter]

[0244] Fig.18 It is a graphic Fig.17 Circuit diagram of a configuration example of the VDD-VBIAS level shifter. Fig.18 The VDD-VBIAS level shifter 132 in Fig. 9The difference between the VDD-VBIAS level shifter 132 in FIG. 1 is that the former also includes a pull-up PMOS transistor MPPU and a pull-down NMOS transistor MNPD, which fix the output when the level shifter 132 stops, and cut-off NMOS transistors MNSWP and MNSWN that prevent direct current when the output is fixed.

[0245] The pull-up PMOS transistor MPPU is coupled between the VCC node and a coupling node 196 for outputting an output signal outn. An enable signal enp is input to a gate of the pull-up PMOS transistor MPPU. A back gate of the pull-up PMOS transistor PMOS is coupled to the VCC node.

[0246] The pull-down NMOS transistor MNPD is coupled between a coupling node 195 for outputting an output signal outp and a VSS node. An enable signal enn is input to a gate of the pull-down PMOS transistor MNPD. A back gate of the pull-down NMOS transistor PMOS is coupled to the VSS node.

[0247] The cut-off NMOS transistors MNSWP and MNSWN (194) are respectively coupled to the input NMOS transistors MNINP and MNINN (191) and the negative voltage node un. The gates of the input NMOS transistors MNINP and MNINN are input with an enable signal enp. The back gates of the cut-off NMOS transistors MNSWP and MNSWN are coupled to the negative power supply node un.

[0248] Fig.18 The other points in Fig. 9 Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0249] [Configuration Example of Power Supply Control Signal Generation Circuit]

[0250] Fig.19 It is a graphic Fig.17 A circuit diagram of a configuration example of a power supply control signal generating circuit in FIG. Fig.19 The power control signal generating circuit 134 and Fig.10 The power control signal generating circuit 134 in FIG. 1 is different in that the former further includes switching NMOS transistors MNSW1, MNSW2 and MNSW3, switching PMOS transistor MPSW3 and NMOS transistor MNDIS.

[0251] Switching NMOS transistors MNSW1 , MNSW2 , and MNSW3 are provided for cutting off current paths 222 , 223 , and 224 , respectively, when the negative voltage level shifter 130E stops.

[0252] Specifically, the switching NMOS transistor MNSW1 is coupled to a current path 222 between the NMOS transistor MNR and the current source I1 connected in series therewith. The switching NMOS transistor MNSW2 is coupled to a current path 223 between the PMOS transistor MPR and the VSS node connected in series therewith. The switching NMOS transistor MNSW3 is coupled to a current path 224 between the NMOS transistor MNM2B and the current source I2 connected in series therewith. An enable signal enp is input to the gates of the switching NMOS transistors MNSW1, MNSW2 and MNSW3. The back gates of the switching NMOS transistors MNSW1, MNSW2 and MNSW3 are coupled to the corresponding sources.

[0253] The PMOS transistor MPSW3 is provided for fixing the value of the control signal biasg to the mid-power supply voltage VCC when the negative voltage level shifter 130E stops. Specifically, the switching PMOS transistor MPSW3 is coupled between the coupling node 210 for outputting the control signal biasg and the VCC node. An enable signal enp is input to the gate of the PMOS transistor MPSW3. The back gate of the PMOS transistor MPSW3 is coupled to the VCC node.

[0254] The NMOS transistor MNDIS is provided for pulling out charge via the signal line 266 for providing the control signal biasc when the negative voltage level shifter 130E stops. Specifically, the NMOS transistor MNDIS is coupled between the signal line 226 and the VSS node. A discharge signal discp is input to the gate of the NMOS transistor MNDIS. The back gate of the NMOS transistor MNDIS is coupled to the VSS node.

[0255] [Operation of negative voltage level shifter]

[0256] Fig. 20 It is used to illustrate Fig.17 2 is a timing diagram of the operation of the negative voltage level shifter.

[0257] Reference Figures 17 to 20 The operation of the negative voltage level shifter 130E is described. In the following description, a high level is referred to as "H" and a low level is referred to as "L".

[0258] First, in the state where the negative voltage level shifter is not operating before time T1, en = "L", and disc = "L". Therefore, Fig.19 The current paths 222, 223 and 224 in the circuit are cut off by switching NMOS transistors MNSW1, MNSW2 and MNSW3. Similarly, the values ​​of control signals biasg and biasc are both controlled by Fig.19The PMOS transistor MPSW3 and the NMOS transistor MNDIS in are fixed to the power supply voltage VCC.

[0259] Further, in Fig.18 In the VDD-VBIAS level shifter 132, the enable signal enp is "L", and the enable signal enp is "H". Therefore, the coupling node 195 is fixed to the ground voltage VSS, and the coupling node 196 is fixed to the power supply voltage VCC. Accordingly, the output signals outp and outn of the VDD-VBIAS level shifter 132 are fixed to VSS and VCC, respectively, the input signals intp and intn of the negative voltage level shifter 131 are fixed to VSS and VCC, respectively, and the output signals outp and outn are fixed to VSS and VCC, respectively.

[0260] At time T1, en is set to "H" to operate the negative voltage level shifter 130E. Fig.19 All current paths in the negative voltage level shifter 130E are disconnected and the output is fixed. Therefore, the high level of the input signals intp and intn and the high level of the output signals outp and outn are reduced from the medium power supply voltage VCC to the medium voltage VBIAS. Thus, the inversion operation of the negative voltage level shifter 130E is possible.

[0261] The discharge signal disc and the enable signal en are limited to the "H" level at time T1, but are limited to the "L" level at time T2 after a predetermined time has passed. The reason is as follows. Since the value of the control signal biasc is VCC in the initial state, it is necessary to pull out the charge from the signal line 226 for providing the control signal biasc when starting the normal state. However, in Fig.10 In the power control signal generating circuit 134, the only path for pulling the charge out of the signal line 226 is the current path 224. In addition, there is a constant current source I2 in the current path 224. Therefore, it takes too much time before the value of the control signal biasc stabilizes to become the medium voltage VBIAS. Therefore, the charge of the signal line 226 is released once to approximately VSS via the NMOS transistor MNDIS, and then the discharge signal disc is placed in "L", and the signal line 226 is charged in such a way that the value of the control signal biasc becomes approximately VBIAS. This method can quickly stabilize the value of the control signal biasc. Fig. 20 In the embodiment, the discharge signal disc is limited to the “H” level only during the period from time T1 to time T2.

[0262] Thereafter, the negative voltage level shifter can be inverted in both cases where the voltage of the negative power supply node un is VSS and VEE. Fig. 20In this case, a negative high voltage VEE is generated by activating the negative high voltage power supply at time T3, and the voltage of the negative power supply node un becomes VEE (< VSS); subsequently, the input signal inp is inverted at times T4 and T5.

[0263] Subsequently, the operation of the negative high voltage power supply is stopped at time T6. Therefore, the voltage of the negative power supply node un returns to the ground voltage VSS.

[0264] At time T7, in order to complete the operation, while stopping the negative high voltage power supply, the value of the enable signal is set to the "L" level. Therefore, the negative high voltage shifter enters the standby state. In other words, Fig.19 the current paths 222, 223, and 224 in are disconnected, and both the output signals baisg and baisc are fixed to VCC. At the same time, Fig.18 the voltages of the internal coupling nodes 195 and 196 in are fixed on the unselected side. The high levels of the input signals intp and intn and the high levels of the output signals outp and outn change from the middle power supply voltage VCC (> VBIAS) to the middle voltage VBIAS.

[0265] [Advantages of the Fifth Embodiment]

[0266] As described above, according to the fifth embodiment, when the negative high voltage shifter is not used, the power consumption can be stopped by the power supply control signal generation circuit 134. Therefore, unnecessary power consumption can be reduced in a state where the negative high voltage power supply does not generate a negative voltage.

[0267] Sixth Embodiment

[0268] The first to fifth embodiments illustrate that Figure 8 or Fig.16 the breakdown voltage relaxation shifters in can be used to relax the breakdown voltage of the negative voltage shifter main body 131. The problem with these breakdown voltage relaxation shifters is that since the breakdown voltage relaxation circuit in the driver stage 170 has a two-stage configuration of PMOS transistors and NMOS transistors, the area becomes large. Specifically, for the NMOS transistors in the breakdown voltage relaxation circuit, the breakdown voltage relaxation of the substrate also needs to be considered. Therefore, a separate well is required, and the increase in area becomes very large. The sixth embodiment illustrates a negative voltage shifter that has solved this problem.

[0269] [Overall Configuration of Negative Voltage Shifter]

[0270] Fig.21 The figure illustrates the configuration of the negative voltage shifter in the semiconductor device according to the sixth embodiment. Fig.21 The negative voltage shifter 130F in is the same as Fig.17The negative voltage level shifter 130E in FIG. 1 is different in that a function of making the input signals intp and intn of the negative voltage level shifter body 131 at the “H” level is added.

[0271] Specifically, in Fig.21 In the case of the negative high power supply voltage being effective, the VDD-VBIAS level shifter 312 in the previous stage is divided into a VDD-VBIAS level shifter 132A for converting the input signal intp and a VDD-VBIAS level shifter 132B for converting the input signal intn. These level shifters can be controlled independently of each other. Further, a logic circuit 145 is added, which controls the input signals inpp, inpn, innp, and innn in such a way that the input signals intp and intn are at the "H" level when the breakdown voltage relaxation control signal noemi = "H" (in other words, when the negative high power supply voltage is effective, the breakdown voltage relaxation is effective).

[0272] exist Fig.21 In the example of FIG. 1 , the logic circuit 145 includes inverters 140 , 142 , and 143 that operate at the low power supply voltage VDD, and NAND gates 141 and 147 that operate at the low power supply voltage VDD.

[0273] More specifically, the logical AND of the input signal inp and the breakdown voltage relaxation control signal noemi is input to the VDD-VBIAS level shifter 132A as the input signal innp through the NAND gate 147 and the inverter 142. A signal obtained by inverting the logical AND of the input signal inp and the breakdown voltage relaxation control signal noemi is input to the VDD-VBIAS level shifter 132A as the input signal inpn.

[0274] Similarly, a signal obtained by inverting the logical AND of the input signal inp and the breakdown voltage relaxation control signal noemi through the NAND gate 141 and the inverters 140 and 143 is input to the VDD-VBIAS level shifter 132B as the input signal innp. A logical AND of the input signal inp and the breakdown voltage relaxation control signal noemi is input to the VDD-VBIAS level shifter 132B as the input signal innn.

[0275] because Fig.21 The configuration of each of the VDD-VBIAS level shifters 132A and 132B is similar to that of the reference Fig.18 The VDD-VBIAS level shifter described is the same, so its description will not be repeated.

[0276] [Configuration example of negative voltage level shifter main body]

[0277] Fig. 22It is a graphic Fig.21 A circuit diagram of a configuration example of a negative voltage level shifter body in FIG. Fig. 22 The negative voltage level shifter body 131 in the embodiment is additionally provided with a function capable of making the positive power supply nodes upp and upn of the driver stage 170 the ground voltage VSS when the breakdown voltage relaxation control signal noemi is at a high level (i.e., breakdown voltage relaxation is valid). Therefore, even in the configuration of the driver stage 170 that does not include a breakdown voltage relaxation circuit, breakdown voltage relaxation of the driver MOS transistor can be achieved.

[0278] Reference Fig. 22 , the negative voltage level shifter 131 includes a level shifter stage 150 and a driver stage 170. The level shifter stage 150 includes input circuits 181 and 182, a latch circuit 180, and pull-up PMOS transistors MPPUP and MPPUN.

[0279] The input circuit 181 includes an input PMOS transistor MPINP and an input NMOS transistor MNINP. The input PMOS transistor MPINP and the input NMOS transistor MNINP are sequentially coupled in series between a positive power supply node up and a VSS node. An input signal intp is input to the gate of the input PMOS transistor MPINP and the gate of the input NMOS transistor MNINP. The back gates of the input PMOS transistor MPINP and the input NMOS transistor MNINP are coupled to corresponding sources. A coupling node upn between the input PMOS transistor MPINP and the input NMOS transistor MNINP is used as a first power supply node upn for the latch circuit 180 and the driver stage 170.

[0280] Similarly, the input circuit 182 includes an input PMOS transistor MPINN and an input NMOS transistor MNINN. The input PMOS transistor MPINN and the input NMOS transistor MNINN are sequentially coupled in series between the positive power supply node up and the VSS node. The input signal intn is input to the gate of the input PMOS transistor MPINN and the gate of the input NMOS transistor MNINN. The back gates of the input PMOS transistor MPINN and the input NMOS transistor MNINN are coupled to the corresponding sources. The coupling node upp between the input PMOS transistor MPINN and the input NMOS transistor MNINN is used as a second power supply node upp for the latch circuit 180 and the driver stage 170.

[0281] The latch circuit 180 includes cross-coupled PMOS transistors MPCCP and MPCCN, cross-coupled NMOS transistors MNCCP and MNCCN, and pull-down NMOS transistors MNPDP and MNPDN.

[0282] The PMOS transistor MPCCP, the cross-coupled NMOS transistor MNCCP, and the pull-down NMOS transistor MNPDP are sequentially coupled in series between the positive power node upn and the negative power node un. Similarly, the PMOS transistor MPCCN, the cross-coupled NMOS transistor MNCCN, and the pull-down NMOS transistor MNPDN are sequentially coupled in series between the positive power node upp and the negative power node un. In the following description, the coupling node between the PMOS transistor MPCCP and the cross-coupled NMOS transistor MNCCP is referred to as cnn, and the coupling node between the PMOS transistor MPCCN and the cross-coupled NMOS transistor MNCCN is referred to as ccp.

[0283] The gates and sources of the cross-coupled PMOS transistors MPCCP and MPCCN are cross-coupled. The back gate of the cross-coupled PMOS transistor MPCCP is coupled to the positive power supply node upn. The back gate of the PMOS transistor MPCCN is coupled to the positive power supply node upp.

[0284] The gates and sources of the cross-coupled NMOS transistors MNCCP and MNCCN are cross-coupled. The back gates of the cross-coupled NMOS transistors MNCCP and MNCCN are coupled to a negative power supply node un.

[0285] The gate of the pull-down NMOS transistor MNPDP is coupled to the positive power supply node upp, and its back gate is coupled to the negative power supply node un. The gate of the pull-down NMOS transistor MNPDN is coupled to the positive power supply node upn, and its back gate is coupled to the negative power supply node un.

[0286] The pull-up PMOS transistor MPPUP is coupled between the coupling node ccn and the positive power node upn. The gate of the pull-up PMOS transistor MPPUP is coupled to the VSS node, and its back gate is coupled to the positive power node upn. The pull-up PMOS transistor MPPUN is coupled between the coupling node ccp and the positive power node upp. The gate of the pull-up PMOS transistor MPPU is coupled to the VSS node, and its back gate is coupled to the positive power node upp.

[0287] The driver stage 170 is configured with Figure 7 The same as the driver stage 170 in which the breakdown voltage relaxation circuit is not included. The gate of each of the driver PMOS transistor MPDRP and the driver NMOS transistor MNDRP is coupled to the coupling node ccn. The gate of each of the driver PMOS transistor MPDRN and the driver NMOS transistor MNDRN is coupled to the coupling node ccp.

[0288] [Operation of negative voltage level shifter]

[0289] The following will refer to Fig.21 and Fig. 22 The operation of the negative voltage level shifter 130F is described.

[0290] First, in the case where the breakdown voltage is invalid (i.e., the breakdown voltage relaxation control signal noemi = "L"), when the "H" level is input as the input signal inp of the negative voltage level shifter 130F, intp = "H" and intn = "L". Through the operation of the input circuits 181 and 182, the voltage of the positive power supply node upp becomes equal to the voltage of the positive power supply node up, and the voltage of the positive power supply node upn becomes the ground voltage VSS. Therefore, the voltage of the coupling node ccp is pulled up to the voltage of the positive power supply node up through the pull-up PMOS transistor MPPUN. The voltage of the coupling node ccn is pulled down to the voltage of the negative power supply node un through the pull-down NMOS transistor MNPDP. When the voltages of the coupling nodes ccp and ccn change to a certain extent, the through current is cut off by the latch circuit 180 configured by the cross-coupling MOS transistors MPCCP, MNCP, MPCCN and MNCCN.

[0291] The driver stage 170 outputs an "H" level as the output signal outp. Since the voltage of the positive power supply node upp is equal to the voltage of the positive power supply node up, the voltage level of the output signal outp is equal to the voltage of the positive power supply node up. Further, the driver stage 170 outputs an "L" level as the output signal outn. Although the voltage of the positive power supply node upn is equal to the ground voltage VSS, the voltage level of the output signal outn is equal to the voltage of the negative power supply node un.

[0292] Next, when the input signal inp of the negative voltage level shifter 130F changes from the "H" level to the "L" level, the input signals intp and intn change to the "L" level and the "H" level, respectively. Therefore, the voltage of the coupling node ccp is pulled down to the voltage of the negative power supply node un through the pull-down NMOS transistor MNPDN. The voltage of the coupling node ccn is pulled up to the voltage of the positive power supply node up through the pull-up PMOS transistor MPPUP. When the voltages of the coupling nodes ccp and ccn change to a certain extent, the latch circuit 180 is inverted to enter a stable state. In this case, the voltage of the positive power supply node upp becomes equal to the ground voltage VSS, and the voltage of the positive power supply node upn becomes equal to the voltage of the positive power supply node up. At the same time, the voltage level of the output signal outp is equal to the voltage of the negative power supply node un, and the voltage level of the output signal outn is equal to the positive power supply node up.

[0293] Next, in the case where the voltage of the negative power supply node un is lower than the ground voltage VSS, when the breakdown voltage relaxation becomes effective (i.e., the breakdown voltage relaxation control signal noemi = "H"), the input signals intp and intn become "H" level. Therefore, the voltages of the positive power supply nodes upp and upn become equal to the ground voltage VSS. In this case, the input signal cannot be received. However, since the data is held in the latch circuit 180, the output becomes outp / outn = VSS / un or un / VSS according to the data held in the latch circuit 180.

[0294] Fig.23 It is used to illustrate Fig.21 The timing diagram of the specific operation of the negative voltage level shifter in FIG. Fig.19 and Figure 21 to Figure 23 The operation of the negative voltage level shifter 130F is described.

[0295] First, at time T1, the enable signal en becomes the "H" level, thereby releasing the fixation of the output of the negative voltage level shifter 130F, and the negative voltage level shifter 130F becomes operable. Therefore, the output of the input signals intp and intn and the output signals outp and outn are reduced from the intermediate power supply voltage VCC to the intermediate voltage VBIAS.

[0296] Further, at time T1, the discharge signal disc becomes the "H" level, thereby discharging the signal line 226 for supplying the control signal biasc, until the discharge signal becomes the "L" level at time T2.

[0297] Subsequently, at time T3, a negative high voltage is generated by activating the negative high voltage power supply, and the voltage of the negative power supply node un is reduced to VEE (a level that does not require breakdown voltage relaxation).

[0298] At time T4, the input signal inp is inverted, thereby inverting the input signals intp and intn and the output signals outp and outn.

[0299] At time T5 before the negative high voltage becomes deeper, breakdown voltage relaxation is enabled by making the breakdown voltage relaxation control signal noemi at the "H" level. Therefore, the input signals intp and intn become VSS, and the high levels of the output signals outp and outn change from the medium voltage VBIAS to the ground voltage VSS. Subsequently, at time T6, the voltage of the negative power supply node un is further reduced to VEE2 (a level requiring breakdown voltage relaxation).

[0300] At time T7, the voltage of the negative power supply node un returns from VEE2 to VEE. Then, at time T8 after the voltage of the negative power supply node un returns to VEE, the breakdown voltage relaxation control signal noemi is at the "L" level to release the breakdown voltage relaxation. As a result, the "H" level of the input signals intp and intn returns from the ground voltage VSS to the medium voltage VBIAS. Similarly, the "H" level of the output signals outp and outn returns from the ground voltage VSS to the medium voltage VBIAS. In this case, the input signal inp can be inverted.

[0301] At time T9, when the input signal inp is inverted, the input signals intp and intn and the output signals outp and outn are also inverted in association with the inversion.

[0302] At time T10, the operation of the negative high voltage power supply is stopped. Therefore, the voltage of the negative power supply node un returns from the negative high voltage VEE to the ground voltage VSS.

[0303] After stopping the negative high voltage power supply, when the enable signal en is at the "L" level at time T11, the output of the negative voltage level shifter 130F is fixed, and the "H" level of each of the input signals intp and intn and the output signals outp and outn returns from the medium voltage VBIAS to the medium power supply voltage VCC.

[0304] [Advantageous Effects of the Sixth Embodiment]

[0305] According to the configuration of the negative voltage level shifter 130F described above, the voltage levels of the input signals intp and intn of the negative voltage level shifter body 131 are at the "H" level, thereby lowering the positive power supply nodes upp and upn of the driver stage 170 of the negative power supply level shifter body 131 to the ground voltage VSS. Therefore, the breakdown voltage of the driver MOS transistor can be relaxed without inserting the breakdown voltage relaxation MOS transistor into the driver stage 170. Accordingly, the breakdown voltage relaxation MOS transistor occupying a large area can be omitted, so that the negative voltage level shifter can be configured to be relatively small.

[0306] In the above, the invention made by the inventor of the present application has been specifically described by way of embodiments. However, it is of course understood that the present invention is not limited to the above embodiments and can be modified in various ways within the scope not departing from the gist thereof.

Claims

1. A semiconductor device comprising a negative voltage level shifter, wherein the negative voltage level shifter comprises a first level shifter, the first level shifter converts a high level of an input signal from a positive first power supply voltage to a first intermediate voltage, the first intermediate voltage being higher than the first power supply voltage and lower than a second power supply voltage, The negative voltage level shifter further comprises: a second level shifter that converts a low level of an output signal of the first level shifter from a third power supply voltage to a fourth power supply voltage lower than the third power supply voltage, and a first medium voltage generating circuit, the first medium voltage generating circuit generating the first medium voltage, and The first medium voltage generating circuit comprises: a first NMOS (N-channel metal oxide semiconductor) transistor coupled between a first medium voltage node outputting the first medium voltage and a first power supply node supplied with the second power supply voltage, and a first PMOS (P-channel MOS) transistor coupled to the first medium voltage node to serve as a path for discharging charges of the first medium voltage node, The negative voltage level shifter further comprises a first control signal generating circuit that generates a first control signal and a second control signal, wherein the first control signal controls a gate voltage of the first NMOS transistor, and the second control signal controls a gate voltage of the first PMOS transistor. wherein the first level shifter comprises a third PMOS transistor and a third NMOS transistor, the input signal is input to the third PMOS transistor and the third NMOS transistor, and The first control signal generating circuit comprises: a fourth PMOS transistor, the fourth PMOS transistor being a replica of the third PMOS transistor, a fourth NMOS transistor, the fourth NMOS transistor being a replica of the third NMOS transistor, and The current mirror circuit is used for providing currents having a predetermined current ratio to the fourth PMOS transistor and the fourth NMOS transistor.

2. The semiconductor device according to claim 1, wherein the second level shifter converts the high level of the output signal of the first level shifter from the first medium voltage to a second medium voltage, the second medium voltage being higher than the first power supply voltage and equal to or lower than the first medium voltage, wherein the negative voltage level shifter further comprises a second medium voltage generating circuit for generating the second medium voltage, and The second medium voltage generating circuit comprises: a second NMOS transistor coupled between a second medium voltage node outputting the second medium voltage and the first power supply node, and The second PMOS transistor is capable of releasing the charge of the second medium voltage node by being coupled to the second medium voltage node. 3 . The semiconductor device according to claim 2 , wherein the first control signal generating circuit supplies the first control signal to a gate of the second NMOS transistor, and supplies the second control signal to a gate of the second PMOS transistor.

4. The semiconductor device according to claim 2, wherein the negative voltage level shifter further comprises a second control signal generating circuit generating a third control signal and a fourth control signal, the third control signal controlling a gate voltage of the second NMOS transistor, the fourth control signal controlling a gate voltage of the second PMOS transistor.

5. The semiconductor device according to claim 1, wherein the third power supply voltage is a negative voltage whose absolute value is smaller than that of the fourth power supply voltage, and The second level shifter converts a high level of the output signal of the first level shifter from the first medium voltage to the first power supply voltage. 6 . The semiconductor device according to claim 1 , wherein a gate and a drain of the first PMOS transistor are coupled to each other. 7 . The semiconductor device according to claim 1 , wherein the first PMOS transistor is coupled between a node supplied with a constant voltage lower than a control voltage supplied to a gate of the first PMOS transistor and the first medium voltage node.

8. The semiconductor device according to claim 1, wherein the first control signal generating circuit further comprises: A first constant current power source is provided on a current path of the third NMOS transistor. 9 . The semiconductor device according to claim 1 , wherein the first power supply voltage is supplied to a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor.

10. The semiconductor device according to claim 9, wherein the current mirror circuit is configured to make a current flowing through the fourth PMOS transistor and a current flowing through the fourth NMOS transistor equal to each other, and The size ratio of the fourth PMOS transistor to the third PMOS transistor is greater than the size ratio of the fourth NMOS transistor to the third NMOS transistor.

11. The semiconductor device according to claim 1, The first control signal generating circuit further includes a diode-coupled fifth NMOS transistor, the fifth NMOS transistor being a replica of the first NMOS transistor, wherein the fifth NMOS transistor is coupled on the high potential side of the fourth PMOS transistor and on the current path of the fourth PMOS transistor, and The first control signal is the gate voltage of the fifth NMOS transistor.

12. The semiconductor device according to claim 11, The first control signal generating circuit further includes a sixth NMOS transistor, and the sixth NMOS transistor is a copy of the first NMOS transistor. wherein the gate of the sixth NMOS transistor is coupled to the gate of the fifth NMOS transistor, and The second control signal is a source voltage of the sixth NMOS transistor.

13. The semiconductor device according to claim 1, The first control signal generating circuit further includes a plurality of switches, wherein the plurality of switches cut off a plurality of current paths leaving or entering the current mirror circuit in response to an enable signal, and The first level shifter includes a pull-up circuit and a pull-down circuit for fixing a voltage level of an output signal in response to the enable signal.

14. The semiconductor device according to claim 1, wherein the second level shifter is configured to operate based on a voltage of a positive power supply node, and The second level shifter is configured to switch the input of the positive power supply node to the first medium voltage or the third power supply voltage.

15. The semiconductor device according to claim 14, wherein the second level shifter performs conversion in response to a complementary output signal output from the first level shifter, and The second level shifter is configured to switch the input of the positive power supply node to the third power supply voltage when both of the complementary output signals are at a high level.

16. A semiconductor device comprising a negative voltage level shifter, wherein a first power supply voltage and a second power supply voltage higher than the first power supply voltage are input to the semiconductor device, wherein an input signal having a high level equal to the first power supply voltage is input to the negative voltage level shifter, and The negative voltage level shifter comprises: a first level shifter, comprising a first positive power node and a first negative power node, wherein the first level shifter converts the high level of the input signal into a voltage of the first positive power node and converts the low level of the input signal into a voltage of the first negative power node, a second level shifter having a second positive power supply node and a second negative power supply node coupled to a negative power supply, the second level shifter converting a high level of an output signal of the first level shifter into a voltage of the second positive power supply node, and converting a low level of the output signal into a voltage of the second negative power supply node, a first NMOS transistor having a source coupled to the first positive power supply node and the second positive power supply node, and a drain to which the second power supply voltage is applied, a first PMOS transistor having a source coupled to the first positive power supply node and the second positive power supply node, and a drain coupled to a gate or provided with a constant voltage that is lower than a control voltage provided to the gate, a first control signal generating circuit generating a first control signal and a second control signal, wherein the first control signal controls a gate voltage of the first NMOS transistor, and the second control signal controls a gate voltage of the first PMOS transistor, wherein the first level shifter comprises a third PMOS transistor and a third NMOS transistor, the input signal is input to the third PMOS transistor and the third NMOS transistor, and The first control signal generating circuit comprises: a fourth PMOS transistor, the fourth PMOS transistor being a replica of the third PMOS transistor, a fourth NMOS transistor, the fourth NMOS transistor being a replica of the third NMOS transistor, and The current mirror circuit is used for providing currents having a predetermined current ratio to the fourth PMOS transistor and the fourth NMOS transistor.

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