A control chip for LED display screen drive system

Abstract

The embodiment of the present invention discloses a control chip of an LED display screen driving system, belonging to the field of LED driving technology. The control chip is provided with a combined shift register, which includes a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin: the 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin and a first control signal output pin and a second control signal output pin, and the DIR pins of each 2-bit shift register are connected in parallel and connected to the level input pin, and the level signal input pin is used to control whether the control signals output by the first control signal output pin and the second control signal output pin are the same by receiving a high level or a low level signal, thereby realizing the selection of the working mode of the control chip. By adopting the embodiment of the present invention, the purpose of a control chip supporting different working modes is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of LED driving technology, and in particular to a control chip of an LED display screen driving system. Background Art

[0002] LED (light emitting diode) is a new type of solid-state semiconductor light source, which is widely used in lighting circuits, backlight modules or display panels. LED driver chip is a power adjustment electronic device that drives LED to emit light or LED module components to work normally. According to different application requirements, different versions of control chips of LED drive systems are required, such as the commonly used 4-channel control chip and 8-channel control chip. In the prior art, a specific version of the control chip can only support one working mode, for example, it can only support 4-channel mode or 8-channel mode, which makes the design cost and production cost of the control chip high. Summary of the invention

[0003] In view of this, the purpose of an embodiment of the present invention is to provide a control chip for an LED display driving system to solve the problem that a specific version of the control chip in the prior art can only support one working mode, resulting in high design cost and production cost of the control chip for the LED display driving system.

[0004] The technical solution adopted by the embodiment of the present invention to solve the above technical problems is as follows:

[0005] A control chip of an LED display screen driving system is provided. The control chip is provided with a combined shift register, and the combined shift register includes a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin:

[0006] The 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and connected to the level input pin, the CLK pin of each 2-bit shift register is connected in parallel and connected to the clock signal input pin, and the DIN pin of each 2-bit shift register is connected in series and connected to the data input pin;

[0007] Among them, the level signal input pin is used to control whether the control signals output by the first control signal output pin and the second control signal output pin are the same by receiving a high level or a low level signal, thereby realizing the selection of the working mode of the control chip.

[0008] Preferably, the 2-bit shift register comprises a first D flip-flop and a second D flip-flop, each D flip-flop is provided with a D pin, a ck pin, a Q pin and a set pin:

[0009] The set pin of the first D flip-flop 201 and the set pin of the second D flip-flop 202 are connected in parallel and then connected to the DIR pin of the 2-bit shift register;

[0010] The ck pin of the first D flip-flop 201 and the ck pin of the second D flip-flop 202 are connected in parallel and then connected to the CLK pin of the 2-bit shift register;

[0011] The D pin of the first D flip-flop 201 is connected to the DIN pin of the 2-bit shift register;

[0012] The Q pin of the first D flip-flop 201 is connected to the D pin of the second D flip-flop 202 and the first control signal output pin of the 2-bit shift register respectively;

[0013] The Q pin of the second D flip-flop 202 is connected to the second control signal output pin and the data output pin of the 2-bit shift register respectively.

[0014] Preferably, the combined shift register is provided with four 2-bit shift registers.

[0015] Preferably, the level signal input pin receives a high level signal, the control signals output by the first control signal output pin and the second control signal output pin of each 2-bit shift register are different, and the control chip operating mode is an 8-channel operating mode.

[0016] 5. The control chip of the LED display screen driving system according to claim 4, characterized in that the level signal input pin receives a high level signal by connecting to a power supply voltage.

[0017] Preferably, the level signal input pin receives a low level signal, the control signal output by the first control signal output pin and the second control signal output pin of each 2-bit shift register is the same, and the control chip operating mode is a 4-channel operating mode.

[0018] Preferably, the level signal input pin receives a low level signal through grounding.

[0019] Preferably, the control chip further includes a buffer, a multi-channel timing generation and control unit and a gate control unit:

[0020] The shift register is connected to the buffer and the multi-channel timing generation and control unit through a bit line;

[0021] The multi-channel timing generation and control unit is connected to the gate control unit via a bit line;

[0022] The multi-channel timing generation and control unit is provided with a chip selection function multiplexing pin, and the chip selection function multiplexing pin is used to receive a high level or a low level signal, so as to select the working mode of the control chip.

[0023] Preferably, the LED display screen driving circuit is further provided with a protection circuit, and the protection circuit is respectively connected to the buffer, the multi-channel timing generation and control unit and the gate control unit.

[0024] The control chip of the LED display screen driving system of the embodiment of the present invention is provided with a combined shift register that can support channel selection. The shift register is provided with a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin. The level signal received by the level signal input pin and the clock signal received by the clock signal input pin are input in parallel to each 2-bit shift register, and the data signal received by the data input pin is input in series to each 2-bit shift register. The first control signal output pin and the second control signal output pin of each 2-bit shift register output a control signal in parallel according to the level signal, clock signal and data signal received by each 2-bit shift register. When the level signal input pin receives a high level signal, the control signals output by the first control signal output pin and the second control signal output pin are different. When a low level signal is received, the control signals output by the first control signal output pin and the second control signal output pin are the same, thereby achieving the purpose that one control chip can support different working modes and reducing design costs and production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the module structure of a control chip of an LED display screen driving system provided in Embodiment 1 of the present invention;

[0026] Figure 2 for Figure 1 The module structure of the combined shift register in FIG.

[0027] Figure 3 for Figure 2 Schematic diagram of the module structure of the 2-bit shift register in.

[0028] The realization of the purpose, functional features and advantages of the embodiments of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention clearer and more understandable, the embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.

[0030] Embodiment 1 of the present invention provides a control chip suitable for an LED display screen driving system. Figure 1 The control chip includes a combined shift register 101, a buffer 102, a multi-channel timing generation and control unit 103, a gate control unit 104 and a protection circuit 105.

[0031] The combined shift register 101 includes a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin:

[0032] The 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and connected to the level input pin, the CLK pin of each 2-bit shift register is connected in parallel and connected to the clock signal input pin, and the DIN pin of each 2-bit shift register is connected in series and connected to the data input pin;

[0033] Among them, the level signal input pin is used to control whether the control signals output by the first control signal output pin and the second control signal output pin are the same by receiving a high level or a low level signal, thereby realizing the selection of the working mode of the control chip.

[0034] In actual applications, the data transmission of each 2-bit shift register is realized by the clock signal input pin receiving the CLOCK signal and transmitting it to each 2-bit shift register in parallel. When a clock signal (CLK) of a certain frequency is input sequentially, the data is sent to the register sequentially through the DIN pin.

[0035] See also Figure 2 , which is a feasible solution of a combined shift register in this embodiment. The combined shift register 200 in the solution includes four 2-bit shift registers. Each 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin CTRL0 and a second control signal output pin CTRL1, wherein:

[0036] The DIR pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are all connected to the level signal input pin, thereby realizing the parallel input of the level signal;

[0037] The CLK pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are all connected to the clock signal input pin to realize the parallel input of the clock signal;

[0038] The DIN pins of the 2-bit shift register 201 , the 2-bit shift register 202 , the 2-bit shift register 203 and the 2-bit shift register 204 are connected in series and connected to the data input pin to achieve serial input of data.

[0039] The DIN pins of the 2-bit shift register 201, 2-bit shift register 202, 2-bit shift register 203 and 2-bit shift register 204 are connected in series and connected to the data input pin, which means:

[0040] The DIN pin of the 2-bit shift register 201 is connected to the data input pin of the shift register 200 , the data output pin is connected to the DIN pin of the 2-bit shift register 202 , the data output pin of the 2-bit shift register 202 is connected to the DIN pin of the 2-bit shift register 203 , and the data output pin of the 2-bit shift register 203 is connected to the DIN pin of the 2-bit shift register 204 .

[0041] See also Figure 3 ,for Figure 2 Schematic diagram of the module structure of each 2-bit shift register.

[0042] The 2-bit shift register 300 includes a first D flip-flop 301 and a second D flip-flop 302, each of which is provided with a D pin, a ck pin, a Q pin and a set pin:

[0043] The set pin of the first D flip-flop 301 and the set pin of the second D flip-flop 302 are connected in parallel and then connected to the DIR pin of the 2-bit shift register;

[0044] The ck pin of the first D flip-flop 301 and the ck pin of the second D flip-flop 302 are connected in parallel and then connected to the CLK pin of the 2-bit shift register;

[0045] The D pin of the first D flip-flop 301 is connected to the DIN pin of the 2-bit shift register;

[0046] The Q pin of the first D flip-flop 301 is connected to the D pin of the second D flip-flop 302 and the first control signal output pin of the 2-bit shift register respectively;

[0047] The Q pin of the second D flip-flop 302 is connected to the second control signal output pin and the data output pin of the 2-bit shift register respectively.

[0048] In this way, when the D pin of the first trigger 301 receives a high-level signal, the control signal CTRL0 output by the Q pin of the first trigger 301 is different from the control signal CTRL1 output by the Q pin of the second trigger 302, that is, the control signals output by the first control signal output pin and the second control signal output pin of the 2-bit shift register are different.

[0049] When the D pin of the first trigger 301 receives a low level signal, the control signal CTRL0 output by the Q pin of the first trigger 301 is the same as the control signal CTRL1 output by the Q pin of the second trigger 302, that is, the control signal output by the first control signal output pin and the second control signal output pin of the 2-bit shift register are the same.

[0050] by Figure 2 Taking the combined shift register as an example, it has 4 2-bit shift registers. When its level signal input pin receives a high level signal, the control signal output pin of each 2-bit shift register is different from the control signal output pin of the second control signal output pin, then the control chip working mode is 8-channel working mode; when its level signal input pin receives a low level signal, the control signal output pin of the first control signal output pin of each 2-bit shift register is the same as the control signal output pin of the second control signal output pin, then the control chip working mode is 4-channel working mode.

[0051] In practical applications, the level signal input pin of the control chip can receive a high level signal by connecting to the power supply voltage, and receive a low level signal by connecting to the ground.

[0052] Continue reading Figure 1 , the combined shift register 101 is connected to the buffer 102 and the multi-channel timing generation and control unit 103 through a bit line;

[0053] The multi-channel timing generation and control unit 103 is connected to the gate control unit 104 via a bit line;

[0054] The multi-channel timing generation and control unit 103 is provided with a chip selection function multiplexing pin, and the chip selection function multiplexing pin is used to receive a high level or a low level signal, so as to select the working mode of the driving circuit;

[0055] The protection circuit 105 is connected to the buffer 102 , the multi-channel timing generation and control unit 103 , and the gate control unit 102 respectively.

[0056] The protection circuit 105 of this embodiment may include:

[0057] Abnormal detection subcircuit, used for output channel voltage short circuit protection and chip over-temperature protection;

[0058] The output channel voltage short-circuit protection subcircuit is used to detect the voltage of the output channel (OUT0~OUT7) in real time. When the voltage is lower than 0.1V, the channel is considered to be in a short-circuit state, and the channel is immediately shut down and locked. The power supply needs to be restarted to release it.

[0059] The chip over-temperature protection sub-circuit is used to trigger the over-temperature protection module when the chip temperature exceeds 135°C, output a high level (maintain a low level during normal operation), shut down the output channel, and reduce the temperature. When the temperature drops to 115°C, the output channel is reopened;

[0060] The delay protection subcircuit is used to implement the delay protection mechanism. Its function is to shield the instantaneous voltage overshoot when the 8 (or 4) output channels are turned on and off to prevent the protection circuit from making a wrong judgment. Usually, a cascaded director is used to achieve a delay judgment of about 50nm. In other words, the state detected by the protection module is considered to be a valid state only after the output channel is turned on or off for 50nm.

[0061] In this embodiment, the abnormality detection subcircuit and the delay protection subcircuit are combined to output an enable signal after internal logic operation, which is used to control both the output channel and the cascade signal (DOUT).

[0062] The specific circuit of the protection circuit 105 of this embodiment can be designed according to actual needs, or an existing protection circuit can be used, which will not be described in detail here.

[0063] Please continue reading Figure 1 , explain the main pins of the control chip:

[0064] DIN receives external input data and is connected to the data input pin of the combined shift register 101; BK is the enable terminal, which is valid at a high level and shuts down the output channel at a low level; the CLK pin receives an external clock signal and the clock signal input pin of the combined shift register 101 to realize shifting and generating timing; the DIR pin is the mode selection (chip select) pin, which is connected to the level signal input pin of the combined shift register 101 to select 8-channel or 4-channel output mode.

[0065] The control chip of this embodiment is provided with a combined shift register that can support channel selection. The shift register is provided with a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin. The level signal received by the level signal input pin and the clock signal received by the clock signal input pin are input in parallel to each 2-bit shift register, and the data signal received by the data input pin is input in series to each 2-bit shift register. The first control signal output pin and the second control signal output pin of each 2-bit shift register output a control signal in parallel according to the level signal, clock signal and data signal received by each 2-bit shift register. When the level signal input pin receives a high level signal, the control signals output by the first control signal output pin and the second control signal output pin are different. When receiving a low level signal, the control signals output by the first control signal output pin and the second control signal output pin are the same, thereby achieving the purpose of one control chip supporting different working modes and reducing design costs and production costs.

[0066] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the embodiments of the present invention is not limited thereby. Any modification, equivalent substitution and improvement made by those skilled in the art without departing from the scope and essence of the embodiments of the present invention shall be within the scope of the rights of the embodiments of the present invention.

Claims

1. A control chip for an LED display screen driving system, characterized in that: The control chip is provided with a combined shift register, and the combined shift register includes a level signal input pin, four 2-bit shift registers, a clock signal input pin and a data input pin: The 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin and a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and connected to the level input pin, the CLK pin of each 2-bit shift register is connected in parallel and connected to the clock signal input pin, and the DIN pin of each 2-bit shift register is connected in series and connected to the data input pin; wherein the level signal input pin is used to control the control signals output by the first control signal output pin and the second control signal output pin to be the same or different by receiving a high level or low level signal, thereby realizing the selection of the working mode of the control chip; The control chip includes a DIN pin, a CLK pin and a DIR pin, wherein the DIN pin is connected to the data input pin of the combined shift register, the CLK pin is connected to the clock signal input pin of the combined shift register, and the DIR pin is connected to the level signal input pin of the combined shift register; The level signal input pin is used to control the control signals output by the first control signal output pin and the second control signal output pin to be the same or different by receiving a high level or low level signal, thereby realizing the selection of the working mode of the control chip, including: The level signal input pin receives a high level signal, the control signals output by the first control signal output pin and the second control signal output pin of each 2-bit shift register are different, and the control chip operating mode is an 8-channel operating mode; or The level signal input pin receives a low level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register output the same control signal, and the control chip operating mode is a 4-channel operating mode.

2. The control chip of the LED display screen driving system according to claim 1, characterized in that: The 2-bit shift register includes a first D flip-flop and a second D flip-flop, each of which is provided with a D pin, a ck pin, a Q pin and a set pin: the set pin of the first D flip-flop is connected in parallel with the set pin of the second D flip-flop and then connected to the DIR pin of the 2-bit shift register; the ck pin of the first D flip-flop is connected in parallel with the ck pin of the second D flip-flop and then connected to the CLK pin of the 2-bit shift register; the D pin of the first D flip-flop is connected to the DIN pin of the 2-bit shift register; the Q pin of the first D flip-flop is respectively connected to the D pin of the second D flip-flop and the first control signal output pin of the 2-bit shift register; the Q pin of the second D flip-flop is respectively connected to the second control signal output pin and the data output pin of the 2-bit shift register.

3. The control chip of the LED display screen driving system according to claim 1, characterized in that: The level signal input pin receives a high level signal by connecting a power supply voltage.

4. The control chip of the LED display screen driving system according to claim 1, characterized in that: The level signal input pin receives a low level signal through grounding.

5. The control chip of the LED display screen driving system according to claim 1, characterized in that: The control chip also includes a buffer, a multi-channel timing generation and control unit, a gate control unit and a protection circuit: the combined shift register is connected to the buffer and the multi-channel timing generation and control unit respectively; the multi-channel timing generation and control unit is connected to the gate control unit, and the protection circuit is connected to the buffer, the multi-channel timing generation and control unit and the gate control unit respectively.

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