Semiconductor device, charging method thereof, and electronic device

Abstract

A novel semiconductor device or a semiconductor device capable of preventing overcharging is provided. The power receiving unit has a function of generating a signal that cancels out a wireless signal sent by a power supply unit when battery charging is completed. Specifically, when the remaining power of the battery of the power receiving unit is 100% or above a predetermined reference value, the power receiving unit has a function of generating an electromagnetic wave that cancels out the electromagnetic wave sent by the power supply unit. Thus, a magnetic boundary that cancels out the magnetic boundary formed by the electromagnetic wave sent by the power supply unit is formed, thereby suppressing overcurrent in the power receiving unit.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As technical fields of one embodiment of the present invention disclosed in this specification, etc., semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, power storage systems, electronic devices, lighting devices, input devices, input / output devices, and driving methods and manufacturing methods thereof can be cited.

[0003] In this specification, etc., a semiconductor device generally refers to a device that can work by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, a computing device, a storage device, etc. are all embodiments of a semiconductor device. In addition, a display device, a camera device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, etc.), and an electronic device each sometimes include a semiconductor device. Background Art

[0004] In recent years, various electronic devices such as portable information terminals, power tools, and electric vehicles, represented by smartphones, are equipped with batteries. Secondary batteries such as lithium-ion batteries that can be repeatedly used by storing electricity through charging are widely used. The battery can be charged by connecting the electronic device equipped with the battery to a power supply device.

[0005] In addition, by wirelessly supplying power from a power supply device to an electronic device equipped with a battery, the battery can be charged even if the electronic device is not physically connected to the power supply device. For example, Patent Document 1 discloses a power supply method using an electromagnetic induction method and a magnetic field resonance method.

[0006] [References]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2012-125115 Summary of the invention

[0009] One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. Another purpose of one embodiment of the present invention is to provide a semiconductor device capable of preventing overcharging. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another purpose of one embodiment of the present invention is to provide a semiconductor device capable of increasing charging speed. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high versatility. Another purpose of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a small area.

[0010] Note that an embodiment of the present invention does not need to achieve all of the above-mentioned purposes, as long as at least one purpose is achieved. The recording of the above-mentioned purposes does not prevent the existence of other purposes. Purposes other than the above-mentioned can be clearly seen and extracted from the description of the specification, claims, drawings, etc.

[0011] A semiconductor device according to one embodiment of the present invention includes a transceiver circuit and a battery. The transceiver circuit is configured to receive a first electromagnetic wave transmitted by a power supply unit, supply power to a battery, and generate a second electromagnetic wave using the power of the battery. The second electromagnetic wave is generated using the power of the battery when the battery is fully charged. The second electromagnetic wave is configured to cancel the first electromagnetic wave.

[0012] In a semiconductor device according to an embodiment of the present invention, a transceiver circuit includes an antenna circuit and a control circuit. The antenna circuit is configured to receive a first electromagnetic wave and transmit a second electromagnetic wave. The control circuit may be configured to: determine whether to generate the second electromagnetic wave based on information about overcharging; and when it is determined to generate the second electromagnetic wave, supply an AC signal for generating the second electromagnetic wave to the antenna circuit.

[0013] In a semiconductor device according to an embodiment of the present invention, a transceiver circuit includes an antenna circuit and a control circuit. The control circuit includes a determination circuit and a signal generation circuit. The antenna circuit is configured to receive a first electromagnetic wave and transmit a second electromagnetic wave. The determination circuit is configured to determine whether to generate a second electromagnetic wave based on information about overcharging. The signal generation circuit may be configured to supply a second AC signal for generating a second electromagnetic wave to the antenna circuit using a first AC signal generated based on the first electromagnetic wave and power supplied by a battery.

[0014] In the semiconductor device according to one embodiment of the present invention, the information on overcharge may further include temperature information measured by a sensor or reception time information of the first electromagnetic wave.

[0015] In a semiconductor device according to an embodiment of the present invention, the transceiver circuit includes a neural network. The input layer of the neural network may be input with data corresponding to information about overcharging. The output layer of the neural network may output data corresponding to a determination result of whether to generate the second electromagnetic wave.

[0016] The semiconductor device according to any one of the embodiments of the present invention may be further configured to transmit a third electromagnetic wave that reinforces the first electromagnetic wave when battery charging is completed.

[0017] An electronic device according to one embodiment of the present invention is an electronic device including the above-mentioned semiconductor device.

[0018] According to an embodiment of the present invention, a novel semiconductor device can be provided. According to an embodiment of the present invention, a semiconductor device capable of preventing overcharging can be provided. According to an embodiment of the present invention, a semiconductor device with high reliability can be provided. According to an embodiment of the present invention, a semiconductor device capable of improving charging speed can be provided. According to an embodiment of the present invention, a semiconductor device with high versatility can be provided. According to an embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to an embodiment of the present invention, a semiconductor device with a small area can be provided.

[0019] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not need to have all of the above effects. Effects other than the above can be clearly seen and extracted from the description of the specification, claims, drawings, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A , Figure 1B1 , Figure 1B2 and Figure 1C A configuration example of a power supply system is shown.

[0021] Figure 2 A configuration example of a power receiving unit is shown.

[0022] Figure 3 A configuration example of an antenna circuit is shown.

[0023] Fig.4A1 , Figure 4A2 , Figure 4B1 and Figure 4B2 A configuration example of a rectifier circuit and a charging circuit is shown.

[0024] Figure 5A , Figure 5B and Figure 5C A configuration example of a control circuit is shown.

[0025] Figure 6 It is a flow chart.

[0026] Fig. 7A and Figure 7B It is a flow chart.

[0027] Fig. 8A and Figure 8B A configuration example of a power supply system is shown.

[0028] Fig. 9 A configuration example of a power receiving unit is shown.

[0029] Fig. 10A and Fig. 10B A configuration example of a delay circuit and an antenna circuit is shown.

[0030] Fig.11 A configuration example of a control circuit is shown.

[0031] Fig. 12A , Fig. 12B and Fig. 12C Each shows a configuration example of a neural network.

[0032] Fig.13 A structural example of a semiconductor device is shown.

[0033] Fig.14 A configuration example of a storage circuit is shown.

[0034] Fig.15 A structural example of a storage unit is shown.

[0035] Fig.16 A configuration example of a circuit is shown.

[0036] Fig.17 It is a timing diagram.

[0037] Fig.18A , Fig.18B and Fig. 18C A structural example of a transistor is shown.

[0038] Fig.19 It can be a diagram.

[0039] Fig. 20 A structural example of a semiconductor device is shown.

[0040] Fig.21A , Fig.21B , Fig. 21C , Fig.21D , Fig.21E and Fig.21F A configuration example of an electronic device is shown.

[0041] Fig.22A and Fig. 22B A configuration example of an electronic device is shown.

[0042] Fig.23 A configuration example of an electronic device is shown. DETAILED DESCRIPTION

[0043] Below, the embodiments of the present invention are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0044] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used in a channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplification effect, a rectification effect, and a switching effect, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor), referred to as OS. In the following description, a transistor containing a metal oxide in a channel formation region is also referred to as an OS transistor.

[0045] In this specification, etc., a metal oxide containing nitrogen may also be referred to as a metal oxide. In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride. The details of the metal oxide will be described later.

[0046] In this specification, when it is clearly stated that "X is connected to Y", it means the following: X is electrically connected to Y; X is functionally connected to Y; and X is directly connected to Y. Therefore, the connection relationships specified are not limited to the connection relationships shown in the drawings or text, and connection relationships other than the connection relationships shown in the drawings or text are also included in the drawings or text. Here, X and Y are each an object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film or layer, etc.).

[0047] Examples of the case where X and Y are directly connected include: a case where an element capable of electrically connecting X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load, etc.) is not connected between X and Y; and a case where X and Y are not connected via an element capable of electrically connecting X and Y.

[0048] As an example of a case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, or loads) that can electrically connect X and Y may be connected between X and Y. Note that the switch is controlled to be on or off. In other words, whether or not current flows is controlled by turning the switch on or off. Alternatively, the switch has the function of selecting and switching a current path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

[0049] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), a level shift circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplifier circuit (a circuit capable of increasing signal amplitude or current, an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a storage circuit, a control circuit, etc.) may be connected between X and Y. For example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are functionally connected. Note that the case where X and Y are functionally connected includes a case where X and Y are directly connected and a case where X and Y are electrically connected.

[0050] Note that when it is explicitly stated that “X is electrically connected to Y”, in this specification, etc., it means the following cases: when X is electrically connected to Y (in other words, when X and Y are connected with another element or another circuit in between); when X and Y are functionally connected (in other words, when X and Y are functionally connected with another circuit in between); and when X and Y are directly connected (in other words, when X and Y are connected without another element or another circuit in between). In other words, in this specification, etc., when it is explicitly stated that “X is electrically connected to Y”, the contents are the same as when it is simply explicitly stated that “X is connected to Y”.

[0051] Even if independent components are electrically connected to each other in the drawings, there is a case where one component has the functions of multiple components. For example, when a part of the wiring is also used as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the category of "electrically connected" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0052] (Implementation Method 1)

[0053] In this embodiment, a semiconductor device and a power supply system according to one embodiment of the present invention are described.

[0054] <Configuration example of power supply system>

[0055] Figure 1A The configuration example of the power supply system 10 is shown. The power supply system 10 includes a power supply unit 11 and a power receiving unit 12. The power supply system 10 has a function of charging the power receiving unit 12 using a wireless signal transmitted by the power supply unit 11. Hereinafter, power supply using a wireless signal is also referred to as wireless power supply or radio frequency (RF) power supply.

[0056] Note that each of the power supply section 11 and the power reception section 12 may be formed of a semiconductor device. Therefore, each of the power supply section 11 and the power reception section 12 may also be referred to as a semiconductor device.

[0057] The power supply unit 11 has a function of supplying power to the power receiving unit 12 using a wireless signal. Specifically, the power supply unit 11 has a function of generating an electromagnetic wave Wf for charging the power receiving unit 12. As the power supply unit 11, for example, a power supply that wirelessly supplies power to the power receiving unit 12 in a non-contact manner or a power supply that wirelessly supplies power to the power receiving unit 12 placed on a power supply plate can be used.

[0058] The power receiving unit 12 has a function of charging using the wireless signal transmitted from the power supply unit 11. Specifically, the power receiving unit 12 includes a battery, and has a function of charging the battery by supplying the battery with power generated using the electromagnetic wave Wf received from the power supply unit 11. As the power receiving unit 12, for example, electronic devices such as portable information terminals (mobile phones, smart phones, tablet information terminals, notebook computers, e-books, etc.), digital cameras, portable game consoles, portable music players, power tools, home appliances, medical equipment, and vehicles can be used.

[0059] The transmission method of the electromagnetic wave Wf between the power supply unit 11 and the power receiving unit 12 can be appropriately set according to the specifications, etc. For example, as the transmission method, an electromagnetic coupling method, an electromagnetic induction method, or a microwave method can be used. There is no particular limitation on the frequency of the electromagnetic wave Wf generated by the power supply unit 11. For example, the following frequencies can be used: submillimeter waves of 300 GHz or more and less than 3 THz, millimeter waves of 30 GHz or more and less than 300 GHz, microwaves of 3 GHz or more and less than 30 GHz, ultrashort waves of 300 MHz or more and less than 3 GHz, ultra-short waves of 30 MHz or more and less than 300 MHz, short waves of 3 MHz or more and less than 30 MHz, medium waves of 300 kHz or more and less than 3 MHz, long waves of 30 kHz or more and less than 300 kHz, or extremely long waves of 3 kHz or more and less than 30 kHz.

[0060] like Figure 1AAs shown, the power supply unit 11 can transmit the electromagnetic force Wf to the plurality of power receiving units 12. Thus, the plurality of power receiving units 12 can be charged at the same time.

[0061] However, the charging end times of the plurality of power receiving units 12 are not necessarily the same. Figure 1B1 As shown, there is a possibility that the charged power receiving unit 12 (the power receiving unit 12 shaded in the figure) and the uncharged power receiving unit 12 are mixed together. As long as there is an uncharged power receiving unit 12, the power supply unit 11 continues to transmit the electromagnetic wave Wf. Therefore, the charged power receiving unit 12 continues to be exposed to the electromagnetic wave Wf and becomes overcharged, causing an overcurrent to be generated in the power receiving unit 12. This causes the metal parts in the power receiving unit 12 to heat up and may cause the components (elements or batteries, etc.) in the power receiving unit 12 to deteriorate or catch fire. Generally, the degradation caused by the temperature rise is particularly significant when the remaining battery power is 100%. Therefore, if the power receiving unit 12 continues to receive the electromagnetic wave Wf after being charged, the battery degradation caused by heat is more likely to occur.

[0062] Here, the power receiving unit 12 according to one embodiment of the present invention has a function of generating a signal to cancel the wireless signal transmitted by the power supply unit 11 when the battery charging is completed. Specifically, when the remaining power of the battery of the power receiving unit 12 is 100% or above a predetermined reference value, as shown in FIG. Figure 1B2 As shown in FIG. 1 , the power receiving unit 12 has a function of generating an electromagnetic wave Wc that cancels out the electromagnetic wave Wf transmitted by the power supply unit 11. Figure 1C As shown, the magnetic boundary Hc is formed to cancel the magnetic boundary Hf formed by the electromagnetic wave Wf transmitted by the power supply unit 11, thereby suppressing the overcurrent of the power reception unit 12. This prevents the power reception unit 12 from being deteriorated or ignited, thereby improving the reliability of the power reception unit 12.

[0063] Note that the electromagnetic wave Wc may be any electromagnetic wave as long as it can cancel the electromagnetic wave Wf. For example, as the electromagnetic wave Wc, an electromagnetic wave transmitted to the power supply unit 11 and having a frequency synchronized with the electromagnetic wave Wf may be used. Specifically, the frequency of the electromagnetic wave Wc is set to an integral multiple of the frequency of the electromagnetic wave Wf.

[0064] Furthermore, the power receiving unit 12 according to one embodiment of the present invention has a function of generating electromagnetic waves Wc using the power stored in the fully charged battery. Thus, the remaining power of the battery can be maintained at a state of less than 100% (e.g., about 95%), and the degradation of the battery due to temperature changes can be suppressed.

[0065] Note that in this specification, etc., "cancelling the electromagnetic wave Wf" includes not only a method of completely canceling the electromagnetic wave Wf received by the power receiving unit 12, but also a method of weakening the electromagnetic wave Wf received by the power receiving unit 12. That is, one embodiment of the present invention includes not only a method of using the electromagnetic wave Wf to prevent the power receiving unit 12 from receiving the electromagnetic wave Wc, but also a method of weakening the electromagnetic wave Wf received by the power receiving unit 12 using the electromagnetic wave Wc.

[0066] <Configuration Example of Power Receiving Unit>

[0067] Figure 2 A specific configuration example of the power receiving unit 12 having the above-mentioned functions is shown. Figure 2 The power receiving unit 12 shown includes a transceiver circuit 20 , a battery 30 , a sensor 40 , and a timer 50 .

[0068] The transceiver circuit 20 has a function of receiving electromagnetic waves Wf to supply power to the battery 30 and a function of generating electromagnetic waves Wc using the power of the battery 30. The transceiver circuit 20 includes an antenna circuit 21, a rectifier circuit 22, a charging circuit 23, and a control circuit 24.

[0069] The antenna circuit 21 has a function of receiving the electromagnetic wave Wf generated by the power supply unit 11 and converting it into an AC signal and then supplying the AC signal to the rectifier circuit 22 and the control circuit 24. In addition, the antenna circuit 21 also has a function of converting the AC signal supplied by the control circuit 24 into an electromagnetic wave Wc and transmitting the electromagnetic wave Wc to the outside of the power receiving unit 12.

[0070] The antenna can be used to receive electromagnetic waves Wf and send electromagnetic waves Wc. The shape of the antenna can be determined according to the transmission method. For example, when the electromagnetic coupling method or the electromagnetic induction method (for example, the 13.56MHz band) is used as the transmission method, electromagnetic induction according to the change of the electric field density is used. Therefore, it is preferable to use a ring-shaped conductive film (for example, a ring antenna) or a spiral conductive film (for example, a spiral antenna) as an antenna. When a microwave method (for example, UHF band (860 to 960MHz band), 2.45GHz band) is used, the length or shape of the conductive film used as an antenna can be appropriately set in consideration of the wavelength of the electromagnetic wave. For example, as an antenna, a linear conductive film (for example, a dipole antenna) or a flat conductive film (for example, a patch antenna) can be used. Note that the shape of the conductive film used as an antenna is not limited to this. For example, considering the wavelength of the electromagnetic wave, a curved shape and / or a serpentine shape can be used. In addition, an antenna that combines multiple shapes and is compatible with electromagnetic waves of multiple frequency bands can also be used.

[0071] Figure 31 shows a configuration example of the antenna circuit 21. The antenna circuit 21 includes a receiving circuit 101 and a transmitting circuit 102. The receiving circuit 101 has a function of converting an electromagnetic wave Wf into an AC signal and supplying the AC signal to the rectifier circuit 22 and the control circuit 24. The transmitting circuit 102 has a function of converting the AC signal supplied by the control circuit 24 into an electromagnetic wave Wc and transmitting the electromagnetic wave Wc to the outside.

[0072] The receiving circuit 101 includes an antenna coil 111 and a capacitor 112. The capacitor 112 has a function of a resonant capacitor. By using a variable capacitor as the capacitor 112 and controlling the capacitance value, the frequency of the received electromagnetic wave can be controlled. The transmitting circuit 102 includes an antenna coil 113 and a capacitor 114. The capacitor 114 has a function of a resonant capacitor. The frequency of the electromagnetic wave Wc generated by the transmitting circuit 102 can be controlled by the frequency of the AC signal input from the control circuit 24. Note that, as each of the receiving circuit 101 and the transmitting circuit 102, a resonant circuit is preferably used.

[0073] Although Figure 3 In the embodiment, the receiving circuit 101 and the transmitting circuit 102 are separately provided, but a circuit common to each other may also be provided. For example, the receiving circuit 101 and the transmitting circuit 102 may be omitted. Figure 3 The transmitting circuit 102 in the receiving circuit 101 is also provided with the function of the transmitting circuit 102.

[0074] The rectifying circuit 22 has a function of rectifying the AC signal supplied from the antenna circuit 21 and converting it into a DC signal. Fig.4A1 1 shows a configuration example of the rectifier circuit 22. The rectifier circuit 22 includes a diode 121, a capacitor 122, and a diode 123. The capacitor 122 has a function as a smoothing capacitor. The DC signal generated by the rectifier circuit 22 is supplied to the charging circuit 23.

[0075] Note that the diode 121 and the diode 123 may each be a diode-connected transistor. Figure 4A2 A configuration example in which transistors are used as the diode 121 and the diode 123 is shown.

[0076] In order to prevent the reverse flow of current, the off-state current of the transistor used as the diode 121 and the diode 123 is preferably extremely low. Therefore, as such a transistor, an OS transistor is suitable. The off-state current of the OS transistor normalized by the channel width at a source-drain voltage of 10 V and room temperature (about 25°C) can be 10×10 -21 A / μm (10zA / μm) or less. Thus, the OS transistor can effectively prevent the reverse flow of current. The OS transistor will be described in detail in Embodiment 5.

[0077] The charging circuit 23 has a function of controlling the voltage level of the DC signal supplied from the rectifying circuit 22 and supplying the DC signal to the battery 30. Thus, a predetermined voltage is applied to the battery 30, and the battery 30 can be charged.

[0078] Figure 4B1 The following is a configuration example of the charging circuit 23. The charging circuit 23 includes a regulator 131 and a switch 132. The regulator 131 has a function of controlling the voltage input from the rectifying circuit 22. The voltage converted by the regulator 131 is supplied to the battery 30 through the switch 132.

[0079] The switch 132 has a function of controlling whether or not to supply power to the battery 30. The switch 132 is in an on state while the battery 30 is being charged, and is in an off state while the battery 30 is not being charged.

[0080] Note that Figure 4B2 As shown, a transistor may be used as the switch 132. In this case, the conduction state of the switch 132 can be controlled by controlling the gate voltage of the transistor. The transistor used as the switch 132 may have a back gate.

[0081] In order to prevent the power leakage of the battery 30, it is preferable that the off-state current of the transistor used as the switch 132 is small. Therefore, it is preferable to use an OS transistor as the switch 132.

[0082] The battery 30 has a function of supplying power to other circuits in the power receiving unit 12. Note that there is no particular limitation on the type of the battery 30. As the battery 30, for example, a secondary battery such as a lithium ion battery, a lead storage battery, a lithium ion polymer secondary battery, a nickel-hydrogen storage battery, a nickel-cadmium storage battery, a nickel-iron storage battery, a nickel-zinc storage battery, a silver-zinc oxide storage battery, etc.; a liquid circulation type secondary battery such as a redox flow battery, a zinc-chloride battery, a zinc-bromine battery, etc.; a mechanical charging type secondary battery such as an aluminum-air battery, an air-zinc battery, an air-iron battery, etc.; and a high temperature working type secondary battery such as a sodium-sulfur battery, a lithium-iron sulfide battery, etc. can be used.

[0083] The control circuit 24 has a function of controlling the generation of the electromagnetic wave Wc. Specifically, the control circuit 24 has a function of determining whether to generate the electromagnetic wave Wc based on information about overcharging (hereinafter, also referred to as overcharging information) input from the outside. When it is determined that the electromagnetic wave Wc needs to be generated, the control circuit 24 supplies an AC signal to the antenna circuit 21. Figure 2 As an example, a configuration example in which the overcharge information is input to the control circuit 24 by the sensor 40 and the timer 50 will be described.

[0084] The sensor 40 has a function of measuring the temperature of the power receiving unit 12. Note that there is no particular limitation on the measurement location. For example, when the power receiving unit 12 is an electronic device, the sensor 40 can measure the temperature of the housing of the electronic device or the temperature of any location inside the electronic device. The sensor 40 can also measure the surface temperature of the battery 30. The temperature measured by the sensor 40 is converted into a signal and input to the control circuit 24.

[0085] The timer 50 has a function of measuring the time of wireless power supply. For example, the timer 50 can measure the following times: the total time that the power receiving unit 12 continuously receives the electromagnetic wave Wf; the time that the power receiving unit 12 continuously receives the electromagnetic wave Wf after the battery 30 is fully charged; etc. The time measured by the timer 50 is converted into a signal and input to the control circuit 24.

[0086] The temperature information obtained by the sensor 40 and the time information of the wireless power supply obtained by the timer 50 are supplied to the control circuit 24 as overcharge information. The control circuit 24 has a function of selecting whether to generate the electromagnetic wave Wc according to the overcharge information. For example, when the temperature of the power receiving unit 12 is above a prescribed value or the total time of the electromagnetic wave Wf continuously received by the power receiving unit 12 is above a prescribed value, the control circuit 24 may generate the electromagnetic wave Wc to stop the wireless power supply.

[0087] Note that one of the sensor 40 and the timer 50 shown in the configuration example may be omitted. In addition, a circuit for measuring other overcharge information (the distance between the power supply unit 11 and the power receiving unit 12, the magnetic induction intensity, the remaining battery power, etc.) may be provided instead of one or both of the sensor 40 and the timer 50.

[0088] Figure 5A The following is a configuration example of the control circuit 24. The control circuit 24 includes a determination circuit 141, a signal generation circuit 142, and a switch circuit 143. Overcharge information output from the sensor 40, the timer 50, and the like is input to the determination circuit 141.

[0089] The determination circuit 141 has a function of determining whether to generate the electromagnetic wave Wc based on the overcharge information. For example, when the temperature of the power receiving unit 12 is above the reference value or the total time for which the power receiving unit 12 continuously receives the electromagnetic wave Wf is above the reference value, the determination circuit 141 can determine to generate the electromagnetic wave Wc. When it is determined that the electromagnetic wave Wc needs to be generated, the determination circuit 141 has a function of providing a signal to the signal generation circuit 142 indicating the generation of the electromagnetic wave Wc.

[0090] In addition, the determination circuit 141 has a function of outputting a control signal corresponding to the determination result to the switch circuit 143. Specifically, when the determination circuit 141 determines that the electromagnetic wave Wc needs to be generated, the determination circuit 141 has a function of controlling the conduction state of the switch circuit 143 so that the battery 30 supplies power to the signal generation circuit 142. Thus, the signal generation circuit 142 can generate the electromagnetic wave Wc using the power of the battery 30.

[0091] The signal generating circuit 142 has a function of generating a signal for generating electromagnetic waves Wc according to the determination result of the determining circuit 141. Specifically, when the determining circuit 141 determines that the electromagnetic waves Wc need to be generated, the signal generating circuit 142 has a function of generating an AC signal using the AC signal supplied by the antenna circuit 21 and the power supplied by the battery 30. When the determining circuit 141 determines that the electromagnetic waves Wc do not need to be generated, the battery 30 does not supply power to the signal generating circuit 142, and the signal generating circuit 142 does not generate an AC signal.

[0092] Figure 5B A structural example of the signal generating circuit 142 is shown. The signal generating circuit 142 includes a buffer circuit 150. The buffer circuit 150 has a function of controlling the output of the AC signal input from the antenna circuit 21 according to the signal input by the determination circuit 141. Specifically, the AC signal generated according to the electromagnetic wave Wf received by the antenna circuit 21 from the power supply unit 11 is input to the buffer circuit 150. The determination circuit 141 inputs a signal corresponding to whether the electromagnetic wave Wc needs to be generated to the buffer circuit 150. And, when the determination circuit 141 determines that the electromagnetic wave Wc needs to be generated, the buffer circuit 150 outputs the AC signal to the antenna circuit 21. Thus, an AC signal synchronized with the frequency of the electromagnetic wave Wf is supplied to the antenna circuit 21. And, the antenna circuit 21 converts the AC signal supplied by the signal generating circuit 142 into the electromagnetic wave Wc and transmits it to the outside.

[0093] Figure 5C 1 shows a specific configuration example of the buffer circuit 150. The buffer circuit 150 includes transistors 151 to 156 and an inverter 157. The transistors 151 to 154 constitute a first inverter. The transistors 155 and 156 constitute a second inverter. Note that the first inverter can control the operating state according to the signal input to the transistors 153 and 154.

[0094] The AC signal output from the antenna circuit 21 is input to the gates of the transistors 151 and 152. The source and drain of the transistors 151 and 152 are connected to the gates of the transistors 155 and 156. The source and drain of the transistors 155 and 156 are connected to the antenna circuit 21.

[0095] The determination circuit 141 inputs a signal corresponding to whether the electromagnetic wave Wc needs to be generated to the gate of the transistor 153. The signal input from the determination circuit 141 is inverted by the inverter 157, and the signal is input to the gate of the transistor 154. The transistor 153 and the transistor 155 are supplied with a high power supply potential VDD. The transistor 154 and the transistor 156 are supplied with a low power supply potential VSS. Note that the high power supply potential VDD and the low power supply potential VSS can be supplied from the battery 30 to the buffer circuit 150 through the switch circuit 143.

[0096] When the electromagnetic wave Wc is generated, the transistors 153 and 154 are turned on according to the signal supplied from the determination circuit 141. Thus, an AC signal synchronized with the frequency of the electromagnetic wave Wf is supplied from each of the source and the drain of the transistors 155 and 156 to the antenna circuit 21. When the electromagnetic wave Wc is not generated, the transistors 153 and 154 are turned off according to the signal supplied from the determination circuit 141. Thus, the buffer circuit 150 stops generating the AC signal.

[0097] As described above, the power receiving unit 12 according to one embodiment of the present invention can generate the electromagnetic wave Wc according to the charging status to control the power supply to the power receiving unit 12. Figure 2 As shown, the power supply unit 11 may have a signal Sr for outputting the following information to the power receiving unit 12: information on whether the battery 30 is fully charged; information on the remaining power of the battery 30; information on the charging time; etc. When the power supply unit 11 outputs the signal Sr, the power receiving unit 12 outputs a signal Sq corresponding to the requested information to the power supply unit 11. Thus, the power supply unit 11 can monitor the charging status of the power receiving unit 12 and select whether to transmit the electromagnetic wave Wf.

[0098] <Operation example of power supply system>

[0099] Next, refer to Figure 6 An operation example of the power supply system 10 will be described. Figure 6 Flowchart showing an operation example of the power supply system 10. Note that here, an example is described in which a plurality of power receiving units 12 are charged using electromagnetic waves Wf transmitted by the power supply unit 11. Here, the temperature of the power receiving unit 12 is used as overcharge information, and whether or not to generate electromagnetic waves Wc is determined based on the temperature of the power receiving unit 12.

[0100] First, when the power receiving unit 12 is located at a position where wireless charging is possible, the power supply unit 11 transmits electromagnetic waves Wf to the power receiving unit 12 (step S1). Then, the electromagnetic waves Wf are supplied to the battery 30 through the antenna circuit 21, the rectifier circuit 22 and the charging circuit 23 to charge the battery 30 (step S2).

[0101] When the battery 30 is fully charged (YES in step S3), it is confirmed whether all other power receiving units 12 are also fully charged (step S4). Step S4 can be performed as follows: the power supply unit 11 sends a signal Sr to all power receiving units 12 and receives a signal Sq from each power receiving unit 12 (see Figure 2 ). When all the power receiving units 12 are fully charged (YES in step S4), the power supply unit 11 stops transmitting the electromagnetic wave Wf (step S5).

[0102] Note that the criterion for whether the battery 30 is fully charged can be freely set. For example, the criterion may be whether the remaining power of the battery has reached a predetermined value (e.g., 100%). In addition, the charging status of the power receiving unit 12 may be monitored by causing the power supply unit 11 to transmit a signal Sr at a predetermined frequency.

[0103] On the other hand, when any power receiving unit 12 is not fully charged (NO in step S4), the electromagnetic wave Wf continues to be transmitted. The temperature of the fully charged power receiving unit 12 is measured by the sensor 40. When the temperature of the power receiving unit 12 is above the reference value (YES in step S6), the control circuit 24 is supplied with power by the discharge of the battery 30 (step S7) to generate the electromagnetic wave Wc (step S8). As a result, the electromagnetic wave Wf is offset and the charging of the power receiving unit 12 is stopped, thereby preventing overcharging. Since the battery 30 is discharged and the remaining power is less than 100%, the deterioration of the battery 30 can be suppressed.

[0104] Then, when the remaining power of the battery 30 is maintained above the reference value (NO in step S9), the operations of steps S6 to S8 are repeated. Note that when the temperature of the power receiving unit 12 is lower than the reference value, the power receiving unit 12 may determine that the influence of heat is small and it is not necessary to generate the electromagnetic wave Wc (NO in step S6).

[0105] When the remaining power of the battery 30 is lower than the reference value due to the generation of the electromagnetic wave Wc (YES in step S9), the charging of the battery 30 is restarted (step S2). The operation after step S3 is performed until all the power receiving units 12 are fully charged.

[0106] By the above operation, all the power receiving units 12 can be charged while suppressing overcharging. Note that the reference value of the temperature in step S6 and the reference value of the remaining power of the battery 30 in step S9 can be freely set according to the characteristics of the battery 30, etc. For example, when the maximum allowable temperature of the battery 30 is T°C, the reference value of the temperature can be set to a temperature of (T-20)°C or more and T°C or less, (T-15)°C or more and T°C or more, (T-10)°C or more and T°C or less, or (T-5)°C or more and T°C or less. The reference value of the remaining power of the battery 30 can be set to a remaining power of 95%, 90%, 85%, 80%, etc.

[0107] [Additional work 1]

[0108] The operation of the power supply system 10 is not limited to Figure 6 Other tasks may be added as appropriate. Figure 6 In the process, only the temperature of the charged power receiving unit 12 is measured (step S6), but in order to suppress heat generation, even if the power receiving unit 12 is being charged, the charging can be stopped as long as the temperature thereof becomes equal to or higher than the reference value. Fig. 7A An operation example in which charging is temporarily stopped according to the temperature of power receiving unit 12 is shown.

[0109] When it is detected that the temperature of the power receiving unit 12 is above the reference value (step S21), charging is stopped regardless of whether the battery 30 is fully charged (step S22). Then, the charging stop state is maintained. When the temperature of the power receiving unit 12 drops below the reference value (YES in step S23), charging of the battery 30 is restarted (step S24). This operation can suppress heat generation during charging.

[0110] [Additional work 2]

[0111] exist Figure 6 and Fig. 7A In the above description, the operation of determining whether to stop charging is based on the temperature of the power receiving unit 12. However, it is also possible to determine whether to stop charging based on other overcharge information. Figure 7B An operation example is shown in which whether or not to temporarily stop charging is determined based on the reception time of the electromagnetic wave Wf.

[0112] First, when it is detected that the period during which the power receiving unit 12 continuously receives electromagnetic waves exceeds a reference value (step S31), charging of the battery 30 is stopped regardless of whether the battery 30 is fully charged (step S32). When the charging stop state has lasted for a certain period of time (YES in step S33), charging of the battery 30 is restarted (step S34). This operation can prevent the power receiving unit 12 from heating up.

[0113] Note that the method of stopping charging in step S22 and step S32 is not limited to this. For example, the method of stopping charging in step S22 and step S32 may be performed by generating electromagnetic waves Wc or by using Figure 4B1 and Figure 4B2 Charging can be stopped by turning off the switch 132 in the circuit.

[0114] Fig. 7A and Figure 7B The work shown can be appropriately added as an add-on work to Figure 6 shown in the work.

[0115] As described above, in one embodiment of the present invention, when the remaining power of the battery 30 is above a predetermined value, the deterioration and ignition of the power receiving unit 12 can be prevented by canceling the electromagnetic waves generated by the power supply unit 11. In addition, by canceling the electromagnetic waves with the power of the battery 30, the remaining power of the battery 30 can be maintained above the reference value and below 100%, thereby preventing the battery from deteriorating.

[0116] This embodiment mode can be combined with any other embodiment mode as appropriate.

[0117] (Implementation Method 2)

[0118] In this embodiment, a modification of the power supply system described in the above embodiment will be described.

[0119] Fig. 8A Another configuration example of the power supply system 10 is shown. Fig. 8A The power supply system 10 shown is Figures 1A to 1C The power supply system 10 shown differs in that Fig. 8A The power receiving unit 12 shown has a function of generating electromagnetic waves We. For other configurations, the description of the first embodiment can be referred to.

[0120] like Fig. 8A As shown in FIG. 1 , the fully charged power receiving unit 12 (the power receiving unit 12 shaded in the figure) has the function of transmitting electromagnetic waves We to other power receiving units 12 that are not fully charged using electromagnetic waves Wf. The electromagnetic waves We can enhance the electromagnetic waves Wf of the power receiving units 12 that are not fully charged. Figure 8B As shown, the magnetic boundary Hf formed by the electromagnetic wave Wf is strengthened by the magnetic boundary He formed by the electromagnetic wave We, thereby strengthening the electromagnetic wave Wf received by the uncharged power receiving unit 12. As a result, the charging efficiency of the uncharged power receiving unit 12 can be improved, thereby increasing the charging speed.

[0121] The electromagnetic wave We may be any electromagnetic wave that can enhance the electromagnetic wave Wf. For example, the electromagnetic wave We may be an electromagnetic wave whose frequency and phase are synchronized with the electromagnetic wave Wf. Note that the phases of the electromagnetic wave Wf and the electromagnetic wave We do not need to be completely consistent, and they may be adjusted to a degree that can promote the charging of the power receiving unit 12 that has not been fully charged.

[0122] Note that the power receiving unit 12 has a function of transmitting the electromagnetic wave Wf described in the first embodiment in addition to being able to transmit the electromagnetic wave We.

[0123] Fig. 9 A specific configuration example of the power receiving unit 12 having the function of transmitting the electromagnetic wave We is shown. Fig. 9 The power receiving unit 12 shown in FIG. Figure 2 The power receiving unit 12 shown is different in that Fig. 9The power receiving unit 12 shown includes a switch circuit 25, a delay circuit 26 and an antenna circuit 27. Figure 2 Description.

[0124] The switch circuit 25 has a function of controlling the antenna circuit 21 to supply an AC signal to the delay circuit 26. When the electromagnetic wave We is generated, the switch circuit 25 is turned on, and the antenna circuit 21 supplies the AC signal to the delay circuit 26.

[0125] The condition under which the antenna circuit 21 supplies the AC signal to the delay circuit 26 can be freely set. For example, the condition may be that the battery 30 is fully charged.

[0126] The delay circuit 26 has a function of delaying the AC signal supplied from the antenna circuit 21 through the switch circuit 25. Thus, the AC signal is supplied to the antenna circuit 27 with a phase shift generated according to the electromagnetic wave Wf. That is, the delay circuit 26 can control the phase of the AC signal supplied to the antenna circuit 27.

[0127] Fig. 10A 1 shows a configuration example of the delay circuit 26. The delay circuit 26 includes a plurality of inverters 161. By connecting a plurality of inverters 161 in series, the signal output from the rectifier circuit 22 can be delayed to shift the phase. Note that there is no particular limitation on the number of inverters 161 connected in series, and the number of inverters 161 can be appropriately selected according to the desired phase shift amount. In addition, resistors or capacitors can be appropriately provided between the inverters 161.

[0128] Note that the delay circuit 26 may also use the power of the battery 30. In this case, the power of the battery 30 is supplied to the delay circuit 26 during the period of generating the electromagnetic wave We.

[0129] The antenna circuit 27 has a function of converting the signal generated by the delay circuit 26 into an electromagnetic wave We and outputting the electromagnetic wave We to the outside. Fig. 10B 1 shows an example of the structure of the antenna circuit 27. The antenna circuit 27 includes an antenna coil 171 and a capacitor 172. The capacitor 172 has a function of a resonant capacitor. Note that it is preferable to use a resonant circuit as the antenna circuit 27.

[0130] Although the antenna circuit 27 and the antenna circuit 21 are provided separately in this structure, the antenna circuit 27 may be omitted when the antenna circuit 21 has the function of the antenna circuit 27.

[0131] As described above, by causing the fully charged power receiving unit 12 to transmit the electromagnetic wave We to the incompletely charged power receiving unit 12, the charging efficiency of the incompletely charged power receiving unit 12 can be improved. Thus, the charging speed can be increased.

[0132] This embodiment mode can be combined with any other embodiment mode as appropriate.

[0133] (Implementation method 3)

[0134] In the present embodiment, a configuration example in which artificial intelligence (AI) is applied to the power supply system described in the above embodiment will be described.

[0135] Note that artificial intelligence is a general term for computers that simulate human intelligence. In this specification, artificial intelligence includes artificial neural networks (ANN). Artificial neural networks refer to circuits that simulate neural networks composed of neurons and synapses. In this specification, "neural network" refers to artificial neural networks in particular.

[0136] <Configuration Example of Control Circuit>

[0137] Fig.11 A configuration example of the control circuit 24 is shown. Fig.11 The control circuit 24 shown is Figure 5A The control circuit 24 shown differs in that Fig.11 The determination circuit 141 of the control circuit 24 shown in FIG. 2 has a neural network NN. Figure 5A Description.

[0138] The neural network NN includes an input layer IL, an output layer OL, and a hidden layer (middle layer) HL. The input layer IL is input with data corresponding to the overcharge information obtained by the sensor 40 and the timer 50, etc.

[0139] The output layer OL, the input layer IL, and the hidden layer HL all include one or more units (neuron circuits), and the output of each unit is multiplied by the weight (connection strength) and supplied to the units in different layers. Note that the number of units in each layer can be set arbitrarily. The neural network NN can also be a network with multiple hidden layers HL (deep neural network (DNN)). Deep neural network learning is sometimes also called deep learning.

[0140] The neural network NN acquires a function of selecting whether to generate electromagnetic waves Wc according to overcharging information (e.g., temperature measured by sensor 40, time measured by timer 50, etc.). When data corresponding to overcharging information is input to the input layer of the neural network NN, each layer performs arithmetic processing. The arithmetic processing of each layer is performed, for example, by performing a product-sum operation of data output from a unit of the previous layer and a weight coefficient. Note that the inter-layer connection may be a complete connection in which all units are connected to each other or a partial connection in which some units are connected to each other. And, data corresponding to the result of the determination of whether to generate electromagnetic waves Wc is output from the output layer OL.

[0141] Thus, by including the neural network NN in the determination circuit 141 , it is possible to appropriately determine whether or not the electromagnetic wave Wc is generated based on various information on overcharging. This can improve the versatility of the control circuit 24 .

[0142] <Structural example of a neural network>

[0143] Next, a more specific structural example of the neural network NN is described. FIG. 12A to FIG. 12C An example of the structure of a neural network is shown. The neural network is composed of neuron circuits NC and synapse circuits SC provided between the neuron circuits.

[0144] Fig. 12A FIG. 1 shows an example of the structure of the neuron circuit NC and the synapse circuit SC. Input data x1 to x2 are input to the synapse circuit SC. L (L is a natural number). In addition, each synaptic circuit SC has a storage weight coefficient w k (k is an integer greater than or equal to 1 and less than or equal to L). Weight coefficient w k Corresponding to the bonding strength between NCs in the neuronal circuit.

[0145] When input data x1 to x1 is input to the synaptic circuit SC L When the neuron circuit NC is supplied with the following value: k and the weight coefficient w stored in the synaptic circuit SC k The product (x k w k ) Under the condition of k = 1 to L (x1w1+x2w2+…+x L w L ), that is, by using x k and w k When the value exceeds the threshold value θ of the neuron circuit NC, the neuron circuit NC outputs a high-level signal y. This phenomenon is called the firing of the neuron circuit NC.

[0146] Fig. 12B The model of a hierarchical neural network using the above-mentioned neuron circuit NC and synapse circuit SC is shown. The neural network includes an input layer IL, a hidden layer HL, and an output layer OL. The input layer IL includes an input neuron circuit IN. The hidden layer HL includes a hidden synapse circuit HS and a hidden neuron circuit HN. The output layer OL includes an output synapse circuit OS and an output neuron circuit ON. The threshold values ​​θ of the input neuron circuit IN, the hidden neuron circuit HN, and the output neuron circuit ON are respectively recorded as θ I ,θ H ,θ O .

[0147] The input layer IL is supplied with data x1 to x2 corresponding to the overcharge information. i (i is a natural number), the output of the input layer IL is supplied to the hidden layer HL. And, the value obtained by the product-sum operation using the output data of the input layer IL and the weight coefficient w held in the hidden synaptic circuit HS is supplied to the hidden neuron circuit HN. The value obtained by the product-sum operation using the output of the hidden neuron circuit HN and the weight coefficient w held in the output synaptic circuit OS is supplied to the output neuron circuit ON. And, data y corresponding to whether the electromagnetic wave Wc is generated is output from the output neuron circuit ON.

[0148] in this way, Fig. 12B The neural network shown has a function of determining whether or not electromagnetic waves Wc need to be generated based on overcharge information.

[0149] In addition, the gradient descent method and the like can be used for learning the neural network, and the back propagation algorithm can be used for calculating the gradient. Fig. 12C A model of a neural network using a back-propagation algorithm for supervised learning is shown.

[0150] The back propagation algorithm is one of the methods to change the weight coefficients of the synaptic circuit in such a way that the error between the output data of the neural network and the supervisory data becomes smaller. Specifically, the error δ determined based on the output data (data y) and the supervisory data (data t) is O The weight coefficient w of the hidden synaptic circuit HS is changed. In addition, the weight coefficient w of the synaptic circuit SC of the previous stage is changed according to the change amount of the weight coefficient w of the hidden synaptic circuit HS. In this way, by sequentially changing the weight coefficients of the synaptic circuit SC based on the supervisory data, the neural network NN can be learned.

[0151] Note that Fig. 12B , Fig. 12C In each case, the number of hidden layers HL is one, but it may be two or more, so that deep learning can be performed.

[0152] This embodiment mode can be combined with any other embodiment mode as appropriate.

[0153] (Implementation 4)

[0154] In this embodiment, a structural example of a semiconductor device that can be used for the neural network described in the above embodiment will be described.

[0155] When the neural network is configured by hardware, the product-sum operation of the neural network can be performed using a product-sum operation element. In this embodiment, a structural example of a semiconductor device that can be used as a product-sum operation element in the neural network NN is described.

[0156] <Structural Example of Semiconductor Device>

[0157] Fig.13 A structural example of the semiconductor device 200 is shown. Fig.13 The semiconductor device 200 shown includes a memory circuit 210 (MEM), a reference memory circuit 220 (RMEM), a circuit 230, and a circuit 240. The semiconductor device 200 may further include a current source circuit 250 (CREF).

[0158] The memory circuit 210 (MEM) includes memory cells MC [p, q] and memory cells MC [p+1, q]. The memory cells MC include elements having the function of converting input potential into current. As the element having the above function, for example, an active element such as a transistor can be used. Fig.13 An example is shown in which the memory cell MC includes a transistor Tr11.

[0159] A first analog potential is input to the memory cell MC through the wiring WD[q] and other wirings WD. The first analog potential corresponds to the first analog data. The memory cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr11 obtained when the first analog potential is supplied to the gate of the transistor Tr11 can be used as the first analog current. Hereinafter, the current flowing through the memory cell MC[p, q] is referred to as I[p, q], and the current flowing through the memory cell MC[p+1, q] is referred to as I[p+1, q].

[0160] Note that when the transistor Tr11 operates in the saturation region, the drain current does not depend on the voltage between the source and the drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is preferred to operate the transistor Tr11 in the saturation region. The gate voltage and the voltage between the source and the drain are appropriately set to voltages that enable the transistor Tr11 to operate in the saturation region.

[0161] Specifically, in Fig.13 In the semiconductor device 200 shown, the first analog potential Vx[p,q] or a potential corresponding to the first analog potential Vx[p,q] is input to the memory cell MC[p,q] through the wiring WD[q]. The memory cell MC[p,q] has a function of generating a first analog current corresponding to the first analog potential Vx[p,q]. In other words, the current I[p,q] of the memory cell MC[p,q] at this time corresponds to the first analog current.

[0162] In addition, Fig.13In the semiconductor device 200 shown, the first analog potential Vx[p+1,q] or a potential corresponding to the first analog potential Vx[p+1,q] is input to the memory cell MC[p+1,q] through the wiring WD[q]. The memory cell MC[p+1,q] has a function of generating a first analog current corresponding to the first analog potential Vx[p+1,q]. In other words, the current I[p+1,q] of the memory cell MC[p+1,q] at this time corresponds to the first analog current.

[0163] The memory cell MC has a function of holding a first analog potential. In other words, the memory cell MC has a function of holding a first analog current corresponding to the first analog potential.

[0164] In addition, a second analog potential is input to the memory cell MC through wiring RW such as wiring RW[p] and wiring RW[p+1]. The second analog potential corresponds to the second analog data. The memory cell MC has a function of adding the second analog potential or a potential corresponding to the second analog potential to the first analog potential that has been retained, and a function of retaining a third analog potential obtained by the addition. The memory cell MC also has a function of generating a second analog current corresponding to the third analog potential. In other words, the memory cell MC has a function of retaining a second analog current corresponding to the third analog potential.

[0165] Specifically, in Fig.13 In the semiconductor device 200 shown, the second analog potential Vw[p,q] is input to the memory cell MC[p,q] through the wiring RW[p]. The memory cell MC[p,q] has a function of holding a third analog potential corresponding to the first analog potential Vx[p,q] and the second analog potential Vw[p,q]. In addition, the memory cell MC[p,q] has a function of generating a second analog current corresponding to the third analog potential. In other words, the current I[p,q] of the memory cell MC[p,q] at this time corresponds to the second analog current.

[0166] In addition, Fig.13 In the semiconductor device 200 shown, the second analog potential Vw[p+1,q] is input to the memory cell MC[p+1,q] through the wiring RW[p+1]. The memory cell MC[p+1,q] has the function of holding the first analog potential Vx[p+1,q] and the third analog potential corresponding to the second analog potential Vw[p+1,q]. In addition, the memory cell MC[p+1,q] has the function of generating a second analog current corresponding to the third analog potential. In other words, the current I[p+1,q] of the memory cell MC[p+1,q] at this time corresponds to the second analog current.

[0167] Current I[p, q] flows between wiring BL[q] and wiring VR[q] through memory cell MC[p, q]. Current I[p+1, q] flows between wiring BL[q] and wiring VR[q] through memory cell MC[p+1, q]. Therefore, current I[q] equivalent to the sum of current I[p, q] and current I[p+1, q] flows between wiring BL[q] and wiring VR[q] through memory cell MC[p, q] and memory cell MC[p+1, q].

[0168] The reference storage circuit 220 (RMEM) includes storage cells MCR such as storage cells MCR[p] and storage cells MCR[p+1]. Note that the first reference potential VPR is input to the storage cells MCR via the wiring WDREF. The storage cells MCR have a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the storage cells MCR[p] is referred to as IREF[p], and the current flowing through the storage cells MCR[p+1] is referred to as IREF[p+1].

[0169] Specifically, in Fig.13 In the semiconductor device 200 shown, the first reference potential VPR is input to the memory cell MCR[p] via the wiring WDREF. The memory cell MCR[p] has a function of generating a first reference current corresponding to the first reference potential VPR. In other words, the current IREF[p] of the memory cell MCR[p] at this time corresponds to the first reference current.

[0170] In addition, Fig.13 In the semiconductor device 200 shown, the first reference potential VPR is input to the memory cell MCR[p+1] via the wiring WDREF. The memory cell MCR[p+1] has a function of generating a first reference current corresponding to the first reference potential VPR. In other words, the current IREF[p+1] of the memory cell MCR[p+1] at this time is equivalent to the first reference current.

[0171] The memory cell MCR has a function of holding the first reference potential VPR. In other words, the memory cell MCR has a function of holding a first reference current corresponding to the first reference potential VPR.

[0172] In addition, the second analog potential is input to the memory cell MCR through the wiring RW such as the wiring RW[p] and the wiring RW[p+1]. The memory cell MCR has a function of adding the second analog potential or a potential corresponding to the second analog potential to the first reference potential VPR that has been held, and a function of holding the second reference potential obtained by the addition. The memory cell MCR also has a function of generating a second reference current corresponding to the second reference potential. In other words, the memory cell MCR has a function of holding the second reference current corresponding to the second reference potential.

[0173] Specifically, in Fig.13 In the semiconductor device 200 shown, the second analog potential Vw[p, q] is input to the memory cell MCR[p] through the wiring RW[p]. The memory cell MCR[p] has a function of maintaining a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw[p, q]. In addition, the memory cell MCR[p] has a function of generating a second reference current corresponding to the second reference potential. In other words, the current IREF[p] of the memory cell MCR[p] at this time is equivalent to the second reference current.

[0174] In addition, Fig.13 In the semiconductor device 200 shown, the second analog potential Vw[p+1,q] is input to the memory cell MCR[p+1] through the wiring RW[p+1]. The memory cell MCR[p+1] has the function of maintaining the first reference potential VPR and the second reference potential corresponding to the second analog potential Vw[p+1,q]. In addition, the memory cell MCR[p+1] has the function of generating a second reference current corresponding to the second reference potential. In other words, the current IREF[p+1] of the memory cell MCR[p+1] at this time is equivalent to the second reference current.

[0175] Current IREF[p] flows between wiring BLREF and wiring VRREF through memory cell MCR[p]. Current IREF[p+1] flows between wiring BLREF and wiring VRREF through memory cell MCR[p+1]. Therefore, current IREF, which is the sum of current IREF[p] and current IREF[p+1], flows between wiring BLREF and wiring VRREF through memory cell MCR[p] and memory cell MCR[p+1].

[0176] The current source circuit 250 has a function of supplying a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF to the wiring BL. When the current I[q] flowing between the wiring BL[q] and the wiring VR[q] through the memory cell MC[p,q] and the memory cell MC[p+1,q] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF through the memory cell MCR[p] and the memory cell MCR[p+1] and an offset current is set as described later, a differential current flows through the circuit 230 or the circuit 240. The circuit 230 has a function as a current source circuit, and the circuit 240 has a function as a current sink circuit.

[0177] Specifically, the circuit 230 has a function of generating a current ΔI[q] corresponding to the difference between the current I[q] and the current IREF when the current I[q] is greater than the current IREF. In addition, the circuit 230 has a function of supplying the generated current ΔI[q] to the wiring BL[q]. In other words, the circuit 230 has a function of maintaining the current ΔI[q].

[0178] The circuit 240 has a function of generating a current ΔI[q] corresponding to the difference between the current I[q] and the current IREF when the current I[q] is smaller than the current IREF. In addition, the circuit 240 has a function of injecting the generated current ΔI[q] from the wiring BL[q]. In other words, the circuit 240 has a function of maintaining the current ΔI[q].

[0179] Next, Fig.13 An operation example of the semiconductor device 200 shown will be described.

[0180] First, a potential corresponding to the first analog potential is stored in the memory cell MC[p,q]. Specifically, a potential VPR-Vx[p,q] obtained by subtracting the first analog potential Vx[p,q] from the first reference potential VPR is input to the memory cell MC[p,q] through the wiring WD[q]. The memory cell MC[p,q] holds the potential VPR-Vx[p,q]. In addition, the memory cell MC[p,q] generates a current I[p,q] corresponding to the potential VPR-Vx[p,q]. For example, the first reference potential VPR is set to a potential higher than the ground potential. Specifically, the first reference potential VPR is preferably higher than the ground potential and equal to or lower than the high-level potential VDD supplied to the current source circuit 250.

[0181] In addition, the first reference potential VPR is stored in the memory cell MCR[p]. Specifically, the first reference potential VPR is input to the memory cell MCR[p] through the wiring WDREF. The memory cell MCR[p] holds the first reference potential VPR. In addition, the memory cell MCR[p] generates a current IREF[p] corresponding to the first reference potential VPR.

[0182] In addition, a potential corresponding to the first analog potential is stored in the memory cell MC[p+1,q]. Specifically, a potential VPR-Vx[p+1,q] obtained by subtracting the first analog potential Vx[p+1,q] from the first reference potential VPR is input to the memory cell MC[p+1,q] through the wiring WD[q]. The memory cell MC[p+1,q] holds the potential VPR-Vx[p+1,q]. In addition, the memory cell MC[p+1,q] generates a current I[p+1,q] corresponding to the potential VPR-Vx[p+1,q].

[0183] In addition, the first reference potential VPR is stored in the memory cell MCR[p+1]. Specifically, the first reference potential VPR is input to the memory cell MCR[p+1] through the wiring WDREF. The memory cell MCR[p+1] holds the first reference potential VPR. In addition, the memory cell MCR[p+1] generates a current IREF[p+1] corresponding to the first reference potential VPR.

[0184] In the above operation, the wiring RW[p] and the wiring RW[p+1] are each set to a reference potential. For example, the ground potential or a low-level potential VSS lower than the ground potential can be used as the reference potential. Alternatively, a potential between the potential VSS and the potential VDD can be used as the ground potential. Regardless of whether the second analog potential Vw is positive or negative, the potential of the wiring RW can be made higher than the ground potential, so it is easy to generate a signal, and positive or negative analog data can be multiplied, which is preferable.

[0185] Through the above operation, the total current generated in each memory cell MC connected to the wiring BL[q] flows through the wiring BL[q]. Fig.13 In the above operation, the total current I[q] of the current I[p,q] generated in the memory cell MC[p,q] and the current I[p+1,q] generated in the memory cell MC[p+1,q] flows through the wiring BL[q]. In addition, through the above operation, the total current of the currents generated in the memory cells MCR connected to the wiring BLREF flows through the wiring BLREF. Specifically, in Fig.13 In the example, a total current IREF of a current IREF[p] generated in the memory cell MCR[p] and a current IREF[p+1] generated in the memory cell MCR[p+1] flows through the wiring BLREF.

[0186] Next, while the potential of wiring RW[p] and wiring RW[p+1] is maintained at the reference potential, an offset current Ioffset[q] that is the difference between the current I[q] obtained by the input of the first analog potential and the current IREF obtained by the input of the first reference potential is maintained in circuit 230 or circuit 240.

[0187] Specifically, when the current I[q] is greater than the current IREF, the circuit 230 supplies the current Ioffset[q] to the wiring BL[q]. In other words, the current ICM[q] flowing through the circuit 230 is equivalent to the current Ioffset[q]. The current ICM[q] is maintained in the circuit 230. When the current I[q] is less than the current IREF, the circuit 240 injects the current Ioffset[q] from the wiring BL[q]. In other words, the current ICP[q] flowing through the circuit 240 is equivalent to the current Ioffset[q]. The current ICP[q] is maintained in the circuit 240.

[0188] Next, the second analog potential or a potential corresponding to the second analog potential is stored in the memory cell MC[p,q] by adding the second analog potential or a potential corresponding to the second analog potential to the first analog potential or a potential corresponding to the first analog potential held in the memory cell MC[p,q]. Specifically, the second analog potential Vw[p] is input to the memory cell MC[p,q] through the wiring RW[p] by setting the potential of the wiring RW[p] to a potential obtained by adding Vw[p] to the reference potential. The memory cell MC[p,q] holds the potential VPR-Vx[p,q]+Vw[p]. In addition, the memory cell MC[p,q] generates a current I[p,q] corresponding to the potential VPR-Vx[p,q]+Vw[p].

[0189] In addition, the second analog potential or a potential corresponding to the second analog potential is stored in the memory cell MC[p+1,q] by adding the second analog potential or a potential corresponding to the second analog potential to the first analog potential or a potential corresponding to the first analog potential already held in the memory cell MC[p+1,q]. Specifically, the second analog potential Vw[p+1] is input to the memory cell MC[p+1,q] through the wiring RW[p+1] by setting the potential of the wiring RW[p+1] to a potential obtained by adding Vw[p+1] to the reference potential. The memory cell MC[p+1,q] holds the potential VPR-Vx[p+1,q]+Vw[p+1]. In addition, the memory cell MC[p+1,q] generates a current I[p+1,q] corresponding to the potential VPR-Vx[p+1,q]+Vw[p+1].

[0190] When the transistor Tr11 operating in the saturation region is used as an element for converting a potential into a current, since the drain current of the transistor Tr11 in the memory cell MC[p, q] is equivalent to the current I[p, q], the second analog current is expressed by the following equation 1. Note that Vw[p] is the potential of the wiring RW[p], Vw[p+1] is the potential of the wiring RW[p+1], k is a coefficient, and Vth is the threshold voltage of the transistor Tr11.

[0191] I[p, q]=k(Vw[p]-Vth+VPR-Vx[p, q]) 2 (Formula 1)

[0192] In addition, since the drain current of the transistor Tr11 in the memory cell MCR[p] corresponds to the current IREF[p], the second reference current is expressed by the following equation 2.

[0193] IREF[p]=k(Vw[p]-Vth+VPR) 2 (Formula 2)

[0194] The current I[q] equivalent to the sum of the current I[p, q] flowing through the memory cell MC[p, q] and the current I[p+1, q] flowing through the memory cell MC[p+1, q] can be expressed as ΣiI[p, q]. The current IREF equivalent to the sum of the current IREF[p] flowing through the memory cell MCR[p] and the current IREF[p+1] flowing through the memory cell MCR[p+1] can be expressed as ΣiIREF[p]. Therefore, the current ΔI[q] equivalent to the difference between the current I[q] and the current IREF is expressed by the following formula 3.

[0195] ΔI[q]=IREF-I[q]=ΣiIREF[p]-ΣiI[p, q] (Equation 3)

[0196] Based on equations 1 to 3, the current ΔI[q] can be obtained by the following equation 4.

[0197] ΔI[q]

[0198] =Σi{k(Vw[p]-Vth+VPR) 2 -k(Vw[p]-Vth+VPR-Vx[p,q]) 2}

[0199] =2kΣi(Vw[p]·Vx[p,q])-2kΣi(Vth-VPR)·Vx[p,q]-kΣiVx[p,q] 2 (Formula 4)

[0200] In Formula 4, the term represented by 2kΣi(Vw[p]·Vx[p,q]) is equivalent to the sum of the product of the first analog potential Vx[p,q] and the second analog potential Vw[p] and the product of the first analog potential Vx[p+1,q] and the second analog potential Vw[p+1].

[0201] In addition, if the current Ioffset[q] is defined as the current ΔI[q] when the potential of the wiring RW[p] is the reference potential (that is, the second analog potential Vw[p] and the second analog potential Vw[p+1] are both 0), then the following formula 5 can be obtained based on formula 4.

[0202] Ioffset[q]=-2kΣi(Vth-VPR)·Vx[p, q]-kΣiVx[p, q] 2 (Formula 5)

[0203] Therefore, according to Formula 3 to Formula 5, 2kΣi(Vw[p]·Vx[p,q]) which is equivalent to the product-sum value of the first analog data and the second analog data is expressed by the following Formula 6.

[0204] 2kΣi(Vw[p]·Vx[p,q])=IREF-I[q]-Ioffset[q] (Formula 6)

[0205] When the current I[q] is the sum of the currents flowing through the memory cell MC, the current IREF is the sum of the currents flowing through the memory cell MCR, and the current Ioffset[q] is the current flowing through the circuit 230 or the circuit 240, the current Iout[q] flowing out of the wiring BL[q] when the potential of the wiring RW[p] is Vw[p] and the potential of the wiring RW[p+1] is Vw[p+1] is represented by IREF-I[q]-Ioffset[q]. According to Formula 6, the current Iout[q] is 2kΣi(Vw[p]·Vx[p,q]), which is equivalent to the sum of the product of the first analog potential Vx[p,q] and the second analog potential Vw[p] and the product of the first analog potential Vx[p+1,q] and the second analog potential Vw[p+1].

[0206] The transistor Tr11 preferably operates in a saturation region. However, even if the operating region of the transistor Tr11 is different from the ideal saturation region, as long as a current equivalent to the sum of the product of the first analog potential Vx[p, q] and the second analog potential Vw[p] and the product of the first analog potential Vx[p+1, q] and the second analog potential Vw[p+1] can be obtained with accuracy within a desired range, the transistor Tr11 can be regarded as operating in a saturation region.

[0207] According to one embodiment of the present invention, arithmetic processing can be performed without converting analog data into digital data, so that the circuit scale of the semiconductor device can be reduced, or the time required for arithmetic processing of analog data can be shortened. In addition, according to one embodiment of the present invention, the time required for arithmetic processing of analog data can be shortened and the power consumption of the semiconductor device can be reduced at the same time.

[0208] <Configuration Example of Memory Circuit>

[0209] Next, refer to Fig.14 A specific structural example of the memory circuit 210 (MEM) and the reference memory circuit 220 (RMEM) will be described.

[0210] Fig.14 An example is shown in which the memory circuit 210 (MEM) includes a plurality of memory cells MC in y rows and x columns (x and y are natural numbers), and the reference memory circuit 220 (RMEM) includes a plurality of memory cells MCR in y rows and one column.

[0211] Note that in this specification, etc., the source of a transistor refers to a source region that is a part of a semiconductor layer that serves as a channel formation region or a source electrode connected to the semiconductor layer, etc. Similarly, the drain of a transistor refers to a drain region that is a part of the semiconductor layer or a drain electrode connected to the semiconductor layer, etc. The gate of a transistor refers to a gate electrode, etc.

[0212] The names of the "source" and "drain" of a transistor are interchanged depending on the conductivity type of the transistor or the level of the potential applied to each terminal. Generally speaking, in an n-channel transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In a p-channel transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, although for convenience in some cases it is assumed that the source and the drain are fixed to describe the connection relationship of the transistor, in fact, the names of the source and the drain are interchanged according to the above-mentioned potential relationship.

[0213] The memory circuit 210 is connected to the wiring RW, the wiring WW, the wiring WD, the wiring VR, and the wiring BL. Fig.14 In the example shown, wiring RW[1] to wiring RW[y] and wiring WW[1] to wiring WW[y] are connected to memory cells MC of each row, respectively. In addition, wiring WD[1] to wiring WD[x], wiring BL[1] to wiring BL[x], and wiring VR[1] to wiring VR[x] are connected to memory cells MC of each column, respectively. Note that wiring VR[1] to wiring VR[x] may be connected to each other.

[0214] The reference storage circuit 220 is connected to the wiring RW, the wiring WW, the wiring WDREF, the wiring VRREF, and the wiring BLREF. Fig.14In the example shown, wiring RW[1] to wiring RW[y] and wiring WW[1] to wiring WW[y] are connected to the memory cells MCR of each row. In addition, wiring WDREF, wiring BLREF, and wiring VRREF are connected to the memory cells MCR of one column. Note that wiring VRREF can also be connected to wiring VR[1] to wiring VR[x].

[0215] As an example, Fig.15 Show Fig.14 Any memory cells MC of 2 rows and 2 columns among the plurality of memory cells MC shown in FIG. Fig.14 The specific circuit structure and connection relationship of the arbitrary 2-row and 1-column memory cells MCR among the plurality of memory cells MCR shown.

[0216] Specifically, in Fig.15 , memory cell MC[p,q] in the p-th row and q-th column, memory cell MC[p+1,q] in the p+1-th row and q-th column, memory cell MC[p,q+1] in the p-th row and q+1-th column, and memory cell MC[p+1,q+1] in the p+1-th row and q+1-th column are shown. In addition, Fig.15 The memory cell MCR[p] in the p-th row and the memory cell MCR[p+1] in the p+1-th row are shown. Note that p and p+1 are arbitrary numbers from 1 to y, and q and q+1 are arbitrary numbers from 1 to x.

[0217] The memory cells MC[p,q], MC[p,q+1], and MCR[p] in the p-th row are connected to the wiring RW[p] and the wiring WW[p]. The memory cells MC[p+1,q], MC[p+1,q+1], and MCR[p+1] in the p+1-th row are connected to the wiring RW[p+1] and the wiring WW[p+1].

[0218] The memory cell MC[p,q] and the memory cell MC[p+1,q] in the qth column are connected to the wiring WD[q], the wiring VR[q] and the wiring BL[q]. The memory cell MC[p,q+1] and the memory cell MC[p+1,q+1] in the q+1th column are connected to the wiring WD[q+1], the wiring VR[q+1] and the wiring BL[q+1]. The memory cell MCR[p] in the pth row and the memory cell MCR[p+1] in the p+1th row are connected to the wiring WDREF, the wiring VRREF and the wiring BLREF.

[0219] The memory cell MC and the memory cell MCR each include a transistor Tr11, a transistor Tr12, and a capacitor C11. The transistor Tr12 has a function of controlling the input of a first analog potential to the memory cell MC or the memory cell MCR. The transistor Tr11 has a function of generating an analog current according to a potential input to a gate. The capacitor C11 has a function of adding a second analog potential or a potential corresponding to the second analog potential to the first analog potential or a potential corresponding to the first analog potential held in the memory cell MC or the memory cell MCR.

[0220] Specifically, in Fig.15 In the memory cell MC shown, the gate of the transistor Tr12 is connected to the wiring WW, one of the source and the drain of the transistor Tr12 is connected to the wiring WD, and the other of the source and the drain of the transistor Tr12 is connected to the gate of the transistor Tr11. In addition, one of the source and the drain of the transistor Tr11 is connected to the wiring VR, and the other of the source and the drain of the transistor Tr11 is connected to the wiring BL. The first electrode of the capacitor C11 is connected to the wiring RW, and the second electrode of the capacitor C11 is connected to the gate of the transistor Tr11.

[0221] In addition, Fig.15 In the memory cell MCR shown, the gate of the transistor Tr12 is connected to the wiring WW, one of the source and the drain of the transistor Tr12 is connected to the wiring WDREF, and the other of the source and the drain of the transistor Tr12 is connected to the gate of the transistor Tr11. In addition, one of the source and the drain of the transistor Tr11 is connected to the wiring VRREF, and the other of the source and the drain of the transistor Tr11 is connected to the wiring BLREF. The first electrode of the capacitor C11 is connected to the wiring RW, and the second electrode of the capacitor C11 is connected to the gate of the transistor Tr11.

[0222] In the memory cell MC, the gate of the transistor Tr11 is referred to as a node N. In the memory cell MC, the first analog potential is input to the node N through the transistor Tr12. Then, when the transistor Tr12 is in the off state, the node N is in a floating state, and the node N holds the first analog potential or a potential corresponding to the first analog potential. In the memory cell MC, when the node N is in a floating state, the second analog potential input to the first electrode of the capacitor C11 is supplied to the node N. Through the above operation, the node N can have a potential obtained by adding the second analog potential or a potential corresponding to the first analog potential to the first analog potential.

[0223] The potential of the first electrode of the capacitor C11 is supplied to the node N through the capacitor C11, so the amount of change in the potential of the first electrode is not actually exactly the same as the amount of change in the potential of the node N. Specifically, by multiplying the amount of change in the potential of the first electrode by the coupling coefficient determined as a unique value according to the capacitance value of the capacitor C11, the capacitance value of the gate capacitance of the transistor Tr11, and the capacitance value of the parasitic capacitance, the amount of change in the potential of the node N can be correctly calculated. In the following, for easy understanding, a case where the amount of change in the potential of the first electrode is substantially the same as the amount of change in the potential of the node N is described.

[0224] The drain current of the transistor Tr11 depends on the potential of the node N. Therefore, when the transistor Tr12 is in the off state, the potential of the node N is maintained, and the value of the drain current of the transistor Tr11 is also maintained. The first analog potential and the second analog potential are reflected in the drain current.

[0225] In the memory cell MCR, the gate of the transistor Tr11 is called the node NREF. In the memory cell MCR, the first reference potential or the potential corresponding to the first reference potential is input to the node NREF through the transistor Tr12. Then, when the transistor Tr12 is in the off state, the node NREF is in a floating state, and the node NREF maintains the first reference potential or the potential corresponding to the first reference potential. In the memory cell MCR, when the node NREF is in a floating state, the second analog potential input to the first electrode of the capacitor C11 is supplied to the node NREF. Through the above operation, the node NREF can have a potential obtained by adding the second analog potential or the potential corresponding to the first reference potential to the first reference potential.

[0226] The drain current of transistor Tr11 depends on the potential of node NREF. Therefore, when transistor Tr12 is in the off state, the potential of node NREF is maintained, and the value of the drain current of transistor Tr11 is also maintained. The first reference potential and the second analog potential are reflected in the drain current.

[0227] When the drain current of the transistor Tr11 flowing through the memory cell MC[p,q] is referred to as current I[p,q], and the drain current of the transistor Tr11 flowing through the memory cell MC[p+1,q] is referred to as current I[p+1,q], the sum of the currents supplied to the memory cell MC[p,q] and the memory cell MC[p+1,q] through the wiring BL[q] is the current I[q]. When the drain current of the transistor Tr11 flowing through the memory cell MC[p,q+1] is referred to as current I[p,q+1], and the drain current of the transistor Tr11 flowing through the memory cell MC[p+1,q+1] is referred to as current I[p+1,q+1], the sum of the currents supplied to the memory cell MC[p,q+1] and the memory cell MC[p+1,q+1] through the wiring BL[q+1] is the current I[q+1]. When the drain current of the transistor Tr11 flowing through the memory cell MCR[p] is referred to as current IREF[p], and the drain current of the transistor Tr11 flowing through the memory cell MCR[p+1] is referred to as current IREF[p+1], the sum of the currents supplied to the memory cell MCR[p] and the memory cell MCR[p+1] through the wiring BLREF is current IREF.

[0228] <Configuration Example of Circuit 230, Circuit 240, and Current Source Circuit>

[0229] Next, refer to Fig.16 A specific structural example of the circuit 230, the circuit 240, and the current source circuit 250 (CREF) will be described.

[0230] Fig.16 Shown corresponding to Fig.15 The circuit 230, the circuit 240, and the current source circuit 250 of the memory cell MC and the memory cell MCR shown in FIG. Fig.16 In FIG. 2 , a circuit 230 [q] corresponding to the memory cell MC in the qth column and a circuit 230 [q+1] corresponding to the memory cell MC in the q+1th column are shown as the circuit 230. Fig.16 In FIG. 2 , a circuit 240 [q] corresponding to the memory cell MC in the q-th column and a circuit 240 [q+1] corresponding to the memory cell MC in the q+1-th column are shown as the circuit 240 .

[0231] The circuit 230[q] and the circuit 240[q] are connected to the wiring BL[q]. The circuit 230[q+1] and the circuit 240[q+1] are connected to the wiring BL[q+1].

[0232] The current source circuit 250 is connected to the wiring BL[q], the wiring BL[q+1], and the wiring BLREF. The current source circuit 250 has a function of supplying a current IREF to the wiring BLREF and a function of supplying a current identical to the current IREF or a current corresponding to the current IREF to each of the wiring BL[q] and the wiring BL[q+1].

[0233] Specifically, each of the circuit 230[q] and the circuit 230[q+1] includes a transistor Tr24, a transistor Tr25, a transistor Tr26, and a capacitor C22. The transistor Tr24 of the circuit 230[q] has a function of generating a current ICM[q] equivalent to the difference between the current I[q] and the current IREF when the current I[q] is greater than the current IREF and an offset current is set. In addition, the transistor Tr24 of the circuit 230[q+1] has a function of generating a current ICM[q+1] equivalent to the difference between the current I[q+1] and the current IREF when the current I[q+1] is greater than the current IREF. The current ICM[q] and the current ICM[q+1] are supplied from the circuit 230[q] and the circuit 230[q+1] to the wiring BL[q] and the wiring BL[q+1], respectively.

[0234] In each of the circuit 230[q] and the circuit 230[q+1], one of the source and drain of the transistor Tr24 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the wiring supplied with a specified potential. One of the source and drain of the transistor Tr25 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the gate of the transistor Tr24. One of the source and drain of the transistor Tr26 is connected to the gate of the transistor Tr24, and the other of the source and drain is connected to the wiring supplied with a specified potential. The first electrode of the capacitor C22 is connected to the gate of the transistor Tr24, and the second electrode of the capacitor C22 is connected to the wiring supplied with a specified potential.

[0235] The gate of the transistor Tr25 is connected to the wiring OSM, and the gate of the transistor Tr26 is connected to the wiring ORM.

[0236] Notice, Fig.16 An example is shown in which the transistor Tr24 is a p-channel transistor and the transistors Tr25 and Tr26 are n-channel transistors.

[0237] Each of the circuit 240[q] and the circuit 240[q+1] includes a transistor Tr21, a transistor Tr22, a transistor Tr23, and a capacitor C21. The transistor Tr21 of the circuit 240[q] has a function of generating a current ICP[q] equivalent to the difference between the current I[q] and the current IREF when the current I[q] is less than the current IREF and an offset current is set. In addition, the transistor Tr21 of the circuit 240[q+1] has a function of generating a current ICP[q+1] equivalent to the difference between the current I[q+1] and the current IREF when the current I[q+1] is less than the current IREF. The current ICP[q] and the current ICP[q+1] are respectively injected into the circuit 240[q] and the circuit 240[q+1].

[0238] Note that current ICM[q] and current ICP[q] are each equivalent to current Ioffset[q], and current ICM[q+1] and current ICP[q+1] are each equivalent to current Ioffset[q+1].

[0239] In each of the circuit 240[q] and the circuit 240[q+1], one of the source and the drain of the transistor Tr21 is connected to the corresponding wiring BL, and the other of the source and the drain is connected to the wiring supplied with a specified potential. One of the source and the drain of the transistor Tr22 is connected to the corresponding wiring BL, and the other of the source and the drain is connected to the gate of the transistor Tr21. One of the source and the drain of the transistor Tr23 is connected to the gate of the transistor Tr21, and the other of the source and the drain is connected to the wiring supplied with a specified potential. The first electrode of the capacitor C21 is connected to the gate of the transistor Tr21, and the second electrode of the capacitor C21 is connected to the wiring supplied with a specified potential.

[0240] The gate of the transistor Tr22 is connected to the wiring OSP, and the gate of the transistor Tr23 is connected to the wiring ORP.

[0241] Notice, Fig.16 An example is shown in which the transistors Tr21 to Tr23 are n-channel transistors.

[0242] The current source circuit 250 includes a transistor Tr27 corresponding to the wiring BL and a transistor Tr28 corresponding to the wiring BLREF. Specifically, Fig.16 The current source circuit 250 shows an example in which a transistor Tr27 [q] corresponding to the wiring BL[q] and a transistor Tr27 [q+1] corresponding to the wiring BL[q+1] are used as the transistor Tr27 .

[0243] The gate of the transistor Tr27 is connected to the gate of the transistor Tr28. One of the source and drain of the transistor Tr27 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the wiring supplied with a specified potential. One of the source and drain of the transistor Tr28 is connected to the wiring BLREF, and the other of the source and drain is connected to the wiring supplied with a specified potential.

[0244] The transistor Tr27 and the transistor Tr28 have the same polarity. Fig.16 The transistor Tr27 and the transistor Tr28 are examples of p-channel transistors.

[0245] The drain current of the transistor Tr28 corresponds to the current IREF. Since the transistors Tr27 and Tr28 function as a current mirror circuit, the drain current of the transistor Tr27 has a value substantially the same as that of the drain current of the transistor Tr28 or a value corresponding to that of the drain current of the transistor Tr28.

[0246] <Working Example of Semiconductor Device>

[0247] Next, refer to Fig.15 , Fig.16 and Fig.17 A specific operation example of the semiconductor device 200 according to one embodiment of the present invention will be described.

[0248] Fig.17 yes Fig.15 The memory cell MC and the memory cell MCR shown, Fig.16 The circuit 230, the circuit 240 and the current source circuit 250 are examples of operation timing diagrams. Fig.17 In the example, from time T01 to time T04, the first analog data is stored in the memory cell MC and the memory cell MCR. From time T05 to time T10, the offset current Ioffset flowing through the circuit 230 and the circuit 240 is set. From time T11 to time T16, data corresponding to the product-sum value of the first analog data and the second analog data is obtained.

[0249] Note that the low level potential VSS is supplied to the wiring VR[q] and the wiring VR[q+1]. The high level potential VDD is supplied to all the wirings having a specified potential connected to the circuit 230. The low level potential VSS is supplied to all the wirings having a specified potential connected to the circuit 240. In addition, the high level potential VDD is supplied to all the wirings having a specified potential connected to the current source circuit 250.

[0250] Each of the transistors Tr11 , Tr21 , Tr24 , Tr27 [q], Tr27 [q+1], and Tr28 operates in a saturation region.

[0251] First, from time T01 to time T02, a high-level potential is supplied to wiring WW[p], and a low-level potential is supplied to wiring WW[p+1]. Fig.15 The transistor Tr12 in the memory cell MC[p,q], the memory cell MC[p,q+1], and the memory cell MCR[p] shown in the figure is turned on. The transistor Tr12 in the memory cell MC[p+1,q], the memory cell MC[p+1,q+1], and the memory cell MCR[p+1] is kept off.

[0252] In addition, from time T01 to time T02, Fig.15 Each of the wiring WD[q] and the wiring WD[q+1] shown is supplied with a potential obtained by subtracting the first analog potential from the first reference potential VPR. Specifically, the wiring WD[q] is supplied with a potential VPR-Vx[p,q], and the wiring WD[q+1] is supplied with a potential VPR-Vx[p,q+1]. The wiring WDREF is supplied with the first reference potential VPR, and the wiring RW[p] and the wiring RW[p+1] are supplied with a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD+VSS) / 2.

[0253] Therefore, the potential VPR-Vx[p,q] is supplied to the Fig.15 The node N[p, q] of the memory cell MC[p, q] shown in the figure, the potential VPR-Vx[p, q+1] is supplied to the node N[p, q+1] of the memory cell MC[p, q+1] through the transistor Tr12, and the first reference potential VPR is supplied to the node NREF[p] of the memory cell MCR[p] through the transistor Tr12.

[0254] After time T02, the supply to Fig.15 The potential of the wiring WW[p] shown changes from a high level potential to a low level potential, thereby turning off the transistor Tr12 in the memory cell MC[p,q], the memory cell MC[p,q+1], and the memory cell MCR[p]. Through the above operation, the node N[p,q] maintains the potential VPR-Vx[p,q], the node N[p,q+1] maintains the potential VPR-Vx[p,q+1], and the node NREF[p] maintains the first reference potential VPR.

[0255] Then, from time T03 to time T04, Fig.15 The potential of the wiring WW[p] shown in FIG. 1 is maintained at a low level, and a high level potential is supplied to the wiring WW[p+1]. Fig.15The transistor Tr12 in the memory cell MC[p+1,q], the memory cell MC[p+1,q+1], and the memory cell MCR[p+1] shown in the figure is turned on. The transistor Tr12 in the memory cell MC[p,q], the memory cell MC[p,q+1], and the memory cell MCR[p] is kept off.

[0256] In addition, from time T03 to time T04, Fig.15 The wiring WD[q] and the wiring WD[q+1] shown in the figure supply a potential obtained by subtracting the first analog potential from the first reference potential VPR. Specifically, the potential VPR-Vx[p+1,q] is supplied to the wiring WD[q], and the potential VPR-Vx[p+1,q+1] is supplied to the wiring WD[q+1]. The first reference potential VPR is supplied to the wiring WDREF, and the potential between the potential VSS and the potential VDD, for example, the potential (VDD+VSS) / 2, is supplied to the wiring RW[p] and the wiring RW[p+1] as a reference potential.

[0257] Therefore, the potential VPR-Vx[p+1,q] is supplied to the Fig.15 The node N[p+1,q] of the memory cell MC[p+1,q] shown in the figure, the potential VPR-Vx[p+1,q+1] is supplied to the node N[p+1,q+1] of the memory cell MC[p+1,q+1] through the transistor Tr12, and the first reference potential VPR is supplied to the node NREF[p+1] of the memory cell MCR[p+1] through the transistor Tr12.

[0258] After time T04, the supply to Fig.15 The potential of the wiring WW[p+1] shown changes from a high level potential to a low level potential, thereby turning off the transistor Tr12 in the memory cells MC[p+1,q], MC[p+1,q+1], and MCR[p+1]. Through the above operation, the node N[p+1,q] maintains the potential VPR-Vx[p+1,q], the node N[p+1,q+1] maintains the potential VPR-Vx[p+1,q+1], and the node NREF[p+1] maintains the first reference potential VPR.

[0259] Next, from time T05 to time T06, Fig.16 The wiring ORP and wiring ORM shown in the figure supply a high level potential. Fig.16 In the circuit 230[q] and the circuit 230[q+1] shown in FIG. 1 , when the wiring ORM is supplied with a high-level potential, the transistor Tr26 is turned on, and thereby the gate of the transistor Tr24 is supplied with the potential VDD and reset. Fig.16In the circuit 240 [q] and the circuit 240 [q+1] shown in the figure, when the wiring ORP is supplied with a high-level potential, the transistor Tr23 is turned on, whereby the gate of the transistor Tr21 is supplied with the potential VSS and reset.

[0260] After time T06, the supply to Fig.15 The potential of the wiring ORP and the wiring ORM shown changes from a high level potential to a low level potential, thereby turning off the transistor Tr26 of the circuit 230[q] and the circuit 230[q+1], and the transistor Tr23 of the circuit 240[q] and the circuit 240[q+1]. Through the above operation, the gate of the transistor Tr24 of each of the circuits 230[q] and the circuit 230[q+1] maintains the potential VDD, and the gate of the transistor Tr21 of each of the circuits 240[q] and the circuit 240[q+1] maintains the potential VSS.

[0261] From time T07 to time T08, Fig.16 The wiring OSP shown in the figure supplies a high level potential. Fig.15 The wiring RW[p] and wiring RW[p+1] shown in the figure supply a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD+VSS) / 2. Since the wiring OSP is supplied with a high level potential, the transistor Tr22 of the circuit 240[q] and the circuit 240[q+1] becomes conductive.

[0262] When the current I[q] flowing through the wiring BL[q] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q] is a positive value, this means Fig.15 The sum of the current that can be poured into the transistor Tr28 of the memory cell MC[p,q] and the current that can be poured into the transistor Tr28 of the memory cell MC[p+1,q] is smaller than the value of the drain current of the transistor Tr27[q]. Therefore, when the current ΔI[q] is a positive value, when the transistor Tr22 of the circuit 240[q] becomes conductive, a part of the drain current of the transistor Tr27[q] flows into the gate of the transistor Tr21, and the gate potential of the transistor Tr21 begins to rise. When the drain current of the transistor Tr21 rises to a value substantially equal to the current ΔI[q], the gate potential of the transistor Tr21 converges to a specified value. The gate potential of the transistor Tr21 at this time is equivalent to the potential when the drain current of the transistor Tr21 is the current ΔI[q] (i.e., the current Ioffset[q] (=ICP[q])). In other words, the transistor Tr21 of the circuit 240[q] is set to a current source state that can flow the current ICP[q].

[0263] Similarly, when the current I[q+1] flowing through the wiring BL[q+1] is less than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q+1] is a positive value, when the transistor Tr22 of the circuit 240[q+1] becomes conductive, a part of the drain current of the transistor Tr27[q+1] flows into the gate of the transistor Tr21, causing the gate potential of the transistor Tr21 to start rising. When the drain current of the transistor Tr21 rises to a value substantially equal to the current ΔI[q+1], the gate potential of the transistor Tr21 converges to a specified value. The gate potential of the transistor Tr21 at this time is equivalent to the potential when the drain current of the transistor Tr21 is the current ΔI[q+1] (that is, the current Ioffset[q+1] (=ICP[q+1])). In other words, the transistor Tr21 of the circuit 240[q+1] is set to a current source state in which the current ICP[q+1] can flow.

[0264] After time T08, the supply to Fig.16 The potential of the wiring OSP shown changes from a high level potential to a low level potential, thereby turning off the transistor Tr22 of the circuit 240[q] and the circuit 240[q+1]. Through the above operation, the gate potential of the transistor Tr21 is maintained. Therefore, the circuit 240[q] maintains a state of being a current source capable of flowing the current ICP[q], and the circuit 240[q+1] maintains a state of being a current source capable of flowing the current ICP[q+1].

[0265] From time T09 to time T10, Fig.16 The wiring OSM shown in the figure supplies a high level potential. Fig.15 Each of the wirings RW[p] and RW[p+1] shown in the figure supplies a potential between the potential VSS and the potential VDD as a reference potential, for example, a potential (VDD+VSS) / 2. Since a high-level potential is supplied to the wiring OSM, the transistors Tr25 of the circuits 230[q] and 230[q+1] are turned on.

[0266] When the current I[q] flowing through the wiring BL[q] is greater than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q] is a negative value, this means Fig.15The sum of the current that can be poured into the transistor Tr28 of the memory cell MC[p,q] and the current that can be poured into the transistor Tr28 of the memory cell MC[p+1,q] is greater than the value of the drain current of the transistor Tr27[q]. Therefore, when the current ΔI[q] is a negative value, when the transistor Tr25 of the circuit 230[q] becomes conductive, the current flows from the gate of the transistor Tr24 to the wiring BL[q], and the gate potential of the transistor Tr24 begins to decrease. When the drain current of the transistor Tr24 decreases to a value substantially equal to the current ΔI[q], the gate potential of the transistor Tr24 converges to a specified value. The gate potential of the transistor Tr24 at this time is equivalent to the potential when the drain current of the transistor Tr24 is the current ΔI[q] (i.e., the current Ioffset[q] (=ICM[q])). In other words, the transistor Tr24 of the circuit 230[q] is set to a current source state that can flow the current ICM[q].

[0267] Similarly, when the current I[q+1] flowing through the wiring BL[q+1] is greater than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q+1] is negative, when the transistor Tr25 of the circuit 230[q+1] is turned on, current flows out from the gate of the transistor Tr24 to the wiring BL[q+1], causing the gate potential of the transistor Tr24 to begin to decrease. When the drain current of the transistor Tr24 decreases to a value substantially equal to the absolute value of the current ΔI[q+1], the gate potential of the transistor Tr24 converges to a predetermined value. The gate potential of the transistor Tr24 at this time is equivalent to the potential when the drain current value of the transistor Tr24 is equal to the absolute value of the current ΔI[q+1] (that is, the current Ioffset[q+1] (=ICM[q+1])). In other words, the transistor Tr24 of the circuit 230[q+1] is set to a current source state in which the current ICM[q+1] can flow.

[0268] After time T08, the supply to Fig.16 The potential of the wiring OSM shown changes from a high level potential to a low level potential, thereby turning off the transistor Tr25 of the circuit 230[q] and the circuit 230[q+1]. Through the above operation, the gate potential of the transistor Tr24 is maintained. Therefore, the circuit 230[q] maintains a state of being a current source capable of flowing the current ICM[q], and the circuit 230[q+1] maintains a state of being a current source capable of flowing the current ICM[q+1].

[0269] In each of the circuit 240[q] and the circuit 240[q+1], the transistor Tr21 has a function of sinking current. Therefore, from time T07 to time T08, when the current I[q] flowing through the wiring BL[q] is greater than the current IREF flowing through the wiring BLREF, that is, the current ΔI[q] is a negative value, or when the current I[q+1] flowing through the wiring BL[q+1] is greater than the current IREF flowing through the wiring BLREF, that is, the current ΔI[q+1] is a negative value, it may be difficult to supply current from the circuit 240[q] or the circuit 240[q+1] to the wiring BL[q] or the wiring BL[q+1] without excess or deficiency. In this case, since the balance between the current flowing through the wiring BLREF and the current flowing through the wiring BL[q] or the wiring BL[q+1] is adjusted, the transistor Tr11 of the storage cell MC, the transistor Tr21 of the circuit 240[q] or the circuit 240[q+1], and the transistor Tr27[q] or Tr27[q+1] may not easily operate simultaneously in the saturation region.

[0270] In order to ensure that the transistors Tr11, Tr21 and the transistor Tr27[q] or Tr27[q+1] operate in the saturation region even when the current ΔI[q] is a negative value from time T07 to time T08, the gate potential of the transistor Tr24 may be set to a potential that can obtain a specified drain current from time T05 to time T06 without resetting the gate of the transistor Tr24 to the potential VDD. By adopting the above structure, in addition to the drain current of the transistor Tr27[q] or Tr27[q+1], a current can be supplied from the transistor Tr24, so that the amount of current that the transistor Tr11 cannot inject can be injected by the transistor Tr21 to a certain extent, so that the transistors Tr11, Tr21 and the transistors Tr27[q] or Tr27[q+1] can be ensured to operate in the saturation region.

[0271] Note that, from time T09 to time T10, when the current I[q] flowing through the wiring BL[q] is less than the current IREF flowing through the wiring BLREF, that is, the current ΔI[q] is a positive value, since the circuit 240[q] has been set as a current source capable of flowing the current ICP[q] from time T07 to time T08, the gate potential of the transistor Tr24 of the circuit 230[q] is maintained at a value substantially equal to the potential VDD. Similarly, when the current I[q+1] flowing through the wiring BL[q+1] is less than the current IREF flowing through the wiring BLREF, that is, the current ΔI[q+1] is a positive value, since the circuit 240[q+1] has been set as a current source capable of flowing the current ICP[q+1] from time T07 to time T08, the gate potential of the transistor Tr24 of the circuit 230[q+1] is maintained at a value substantially equal to the potential VDD.

[0272] Next, from time T11 to time T12, Fig.15 The wiring RW[p] shown in the figure supplies the second analog potential Vw[p]. In addition, the wiring RW[p+1] is continuously supplied with a potential between the potential VSS and the potential VDD as a reference potential, for example, the potential (VDD+VSS) / 2. Specifically, the potential of the wiring RW[p] is a potential obtained by adding the potential difference Vw[p] to the potential between the potential VSS as a reference potential and the potential VDD (for example, the potential (VDD+VSS) / 2), but below, for easy understanding, it is assumed that the potential of the wiring RW[p] is the second analog potential Vw[p].

[0273] When the potential of the wiring RW[p] reaches the second analog potential Vw[p], it is assumed that the amount of change in the potential of the first electrode of the capacitor C11 is substantially the same as the amount of change in the potential of the node N. Fig.15 The potential of the node N of the memory cell MC[p,q] shown in the figure becomes VPR-Vx[p,q]+Vw[p], and the potential of the node N of the memory cell MC[p,q+1] becomes VPR-Vx[p,q+1]+Vw[p]. According to Formula 6, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p,q] is reflected in the current obtained by subtracting the current Ioffset[q] from the current ΔI[q], that is, the current Iout[q] flowing out from the wiring BL[q]. In addition, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p,q+1] is reflected in the current obtained by subtracting the current Ioffset[q+1] from the current ΔI[q+1], that is, the current Iout[q+1] flowing out from the wiring BL[q+1].

[0274] After time T12, a potential between the potential VSS and the potential VDD as a reference potential (for example, a potential (VDD+VSS) / 2) is supplied to the wiring RW[p] again.

[0275] Next, from time T13 to time T14, Fig.15 The wiring RW[p+1] shown in the figure supplies the second analog potential Vw[p+1]. In addition, the wiring RW[p] is continuously supplied with a potential between the potential VSS and the potential VDD as a reference potential, for example, the potential (VDD+VSS) / 2. Specifically, the potential of the wiring RW[p+1] is a potential obtained by adding the potential difference Vw[p+1] to the potential between the potential VSS as a reference potential and the potential VDD (for example, the potential (VDD+VSS) / 2). However, below, for ease of understanding, it is assumed that the potential of the wiring RW[p+1] is the second analog potential Vw[p+1].

[0276] When the potential of the wiring RW[p+1] reaches the second analog potential Vw[p+1], it is assumed that the amount of change in the potential of the first electrode of the capacitor C11 is substantially the same as the amount of change in the potential of the node N. Fig.15 The potential of the node N of the memory cell MC[p+1,q] shown in the figure becomes VPR-Vx[p+1,q]+Vw[p+1], and the potential of the node N of the memory cell MC[p+1,q+1] becomes VPR-Vx[p+1,q+1]+Vw[p+1]. According to Formula 6, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p+1,q] is reflected in the current obtained by subtracting the current Ioffset[q] from the current ΔI[q], that is, the current Iout[q]. In addition, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p+1,q+1] is reflected in the current obtained by subtracting the current Ioffset[q+1] from the current ΔI[q+1], that is, the current Iout[q+1].

[0277] After time T12, a potential between the potential VSS and the potential VDD as a reference potential (for example, the potential (VDD+VSS) / 2) is supplied to the wiring RW[p+1] again.

[0278] Next, from time T15 to time T16, Fig.15 The wiring RW[p] shown in the figure supplies the second analog potential Vw[p], and the wiring RW[p+1] supplies the second analog potential Vw[p+1]. Specifically, the potential of the wiring RW[p] is a potential obtained by adding the potential difference Vw[p] to the potential between the potential VSS as a reference potential and the potential VDD (for example, the potential (VDD+VSS) / 2), and the potential of the wiring RW[p+1] is a potential obtained by adding the potential difference Vw[p+1] to the potential between the potential VSS as a reference potential and the potential VDD (for example, the potential (VDD+VSS) / 2). However, below, for easy understanding, it is assumed that the potential of the wiring RW[p] is the second analog potential Vw[p], and the potential of the wiring RW[p+1] is the second analog potential Vw[p+1].

[0279] When the potential of the wiring RW[p] reaches the second analog potential Vw[p], it is assumed that the amount of change in the potential of the first electrode of the capacitor C11 is substantially the same as the amount of change in the potential of the node N. Fig.15 The potential of the node N of the memory cell MC[p,q] shown in the figure becomes VPR-Vx[p,q]+Vw[p], and the potential of the node N of the memory cell MC[p,q+1] becomes VPR-Vx[p,q+1]+Vw[p]. In addition, when the potential of the wiring RW[p+1] becomes the second analog potential Vw[p+1], it is assumed that the change in the potential of the first electrode of the capacitor C11 is substantially the same as the change in the potential of the node N. Fig.15 The potential of the node N of the memory cell MC[p+1,q] shown in the figure becomes VPR-Vx[p+1,q]+Vw[p+1], and the potential of the node N of the memory cell MC[p+1,q+1] becomes VPR-Vx[p+1,q+1]+Vw[p+1].

[0280] According to Formula 6, the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p, q] and the memory cell MC[p+1, q] is reflected in the current obtained by subtracting the current Ioffset[q] from the current ΔI[q], that is, the current Iout[q]. In addition, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p, q+1] and the memory cell MC[p+1, q+1] is reflected in the current obtained by subtracting the current Ioffset[q+1] from the current ΔI[q+1], that is, the current Iout[q+1].

[0281] After time T16, a potential between the potential VSS and the potential VDD as a reference potential (for example, the potential (VDD+VSS) / 2) is supplied again to the wiring RW[p] and the wiring RW[p+1].

[0282] By means of the above structure, the product-sum operation can be performed with a smaller circuit scale. By means of the above structure, the product-sum operation can be performed at high speed. By means of the above structure, the product-sum operation can be performed with low power consumption.

[0283] Note that it is preferable to use a transistor with extremely low off-state current as the transistor Tr12, Tr22, Tr23, Tr25, or Tr26. By using a transistor with extremely low off-state current as the transistor Tr12, the potential of the node N can be maintained for a long time. By using a transistor with extremely low off-state current as the transistors Tr22 and Tr23, the gate potential of the transistor Tr21 can be maintained for a long time. By using a transistor with extremely low off-state current as the transistors Tr25 and Tr26, the gate potential of the transistor Tr24 can be maintained for a long time.

[0284] OS transistors can be used as transistors with extremely low off-state current. When the source-drain voltage is 10V and the room temperature (about 25°C), the leakage current of the OS transistor normalized by the channel width can be 10×10 -21 A / μm (10zA / μm) or less.

[0285] By using the above-mentioned semiconductor device, it is possible to perform sum-of-product operations in the neural network NN.

[0286] This embodiment mode can be combined with any other embodiment mode as appropriate.

[0287] (Implementation method 5)

[0288] In this embodiment, a structural example of an OS transistor which can be used in the above embodiment will be described.

[0289] <Structural Example of Transistor>

[0290] Fig.18A is a top view showing a structural example of a transistor. Fig.18B yes Fig.18A A cross-sectional view between line X1-X2. Fig. 18C yes Fig.18A The direction of the line X1-X2 is sometimes referred to as the channel length direction, and the direction of the line Y1-Y2 is sometimes referred to as the channel width direction. Fig.18B is a diagram showing a cross-sectional structure of a transistor in the channel length direction, Fig. 18C is a diagram showing a cross-sectional structure of a transistor in the channel width direction. Note that in order to clearly show the device structure, Fig.18A Some components are omitted.

[0291] The semiconductor device according to one embodiment of the present invention includes insulating layers 812 to 820, metal oxide films 821 to 824, and conductive layers 850 to 853. The transistor 801 is formed on an insulating surface. 18A to 18C The transistor 801 is formed over the insulating layer 811. The transistor 801 is covered with insulating layers 818 and 819.

[0292] Note that the insulating layer, metal oxide film, conductive layer, etc. constituting the transistor 801 may each be a single layer or a stack of a plurality of films. These layers may be formed using any deposition method such as sputtering, molecular beam epitaxy (MBE), pulsed laser ablation (PLA), CVD, atomic layer deposition (ALD), etc. Note that the CVD method includes a plasma CVD method, a thermal CVD method, an organic metal CVD method, etc.

[0293] The conductive layer 850 includes a region used as a gate electrode of the transistor 801. The conductive layer 851 and the conductive layer 852 include regions used as a source electrode and a drain electrode. The conductive layer 853 includes a region used as a back gate electrode. The insulating layer 817 includes a region used as a gate insulating layer on the side of the gate electrode (front gate electrode), and the insulating layer composed of the stack of insulating layers 814 to 816 includes a region used as a gate insulating layer on the side of the back gate electrode. The insulating layer 818 is used as an interlayer insulating layer. The insulating layer 819 is used as a blocking layer.

[0294] The metal oxide films 821 to 824 are collectively referred to as an oxide layer 830. Fig.18Band Fig. 18C As shown, the oxide layer 830 includes a region where a metal oxide film 821, a metal oxide film 822, and a metal oxide film 824 are sequentially stacked. In addition, a pair of metal oxide films 823 are located on the conductive layers 851 and 852. When the transistor 801 is in an on state, the channel formation region is mainly formed in the metal oxide film 822 of the oxide layer 830.

[0295] The metal oxide film 824 covers the metal oxide films 821 to 823, the conductive layer 851, and the conductive layer 852. The insulating layer 817 is located between the metal oxide film 823 and the conductive layer 850. The conductive layer 851 and the conductive layer 852 both include regions overlapping with the conductive layer 850 via the metal oxide film 823, the metal oxide film 824, and the insulating layer 817.

[0296] The conductive layer 851 and the conductive layer 852 are formed by using a hard mask for forming the metal oxide film 821 and the metal oxide film 822. Thus, the conductive layer 851 and the conductive layer 852 do not include a region in contact with the side of the metal oxide film 821 and the metal oxide film 822. For example, the metal oxide films 821, 822 and the conductive layer 851 and the conductive layer 852 can be formed by the following steps. First, a conductive film is formed on two stacked metal oxide films. The conductive film is processed (etched) into a desired shape to form a hard mask. The shape of the two metal oxide films is processed using a hard mask to form a stack of the metal oxide film 821 and the metal oxide film 822. Next, the hard mask is processed into a desired shape to form the conductive layer 851 and the conductive layer 852.

[0297] As insulating materials used for the insulating layers 811 to 818, there are the following materials: aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. The insulating layers 811 to 818 are composed of a single layer or a stacked layer including any of these insulating materials. The layers constituting the insulating layers 811 to 818 may contain a plurality of insulating materials.

[0298] In this specification and the like, an oxynitride refers to a compound containing a larger amount of oxygen than nitrogen, and a nitrogen oxide refers to a compound containing a larger amount of nitrogen than oxygen.

[0299] In order to suppress the increase of oxygen vacancies in the oxide layer 830, the insulating layers 816 to 818 preferably contain oxygen. The insulating layers 816 to 818 are preferably formed using an insulating film that can release oxygen by heating (hereinafter, such an insulating film is also referred to as an insulating film containing excess oxygen). By supplying oxygen from the insulating film containing excess oxygen to the oxide layer 830, the oxygen vacancies in the oxide layer 830 can be filled. Therefore, the reliability and electrical characteristics of the transistor 801 can be improved.

[0300] The insulating film containing excess oxygen is a film in which the amount of oxygen molecules released is 1.0×10 18 Molecules / cm 3 The release amount of oxygen molecules is preferably 3.0×10 20 Atom / cm 3 above.

[0301] An insulating film containing excess oxygen can be formed by performing a process of adding oxygen to the insulating film. As the process of adding oxygen, a heat treatment in an oxygen atmosphere, a plasma treatment, or a process using an ion implantation method, an ion doping method, or a plasma immersion ion implantation method can be used. As the gas used to add oxygen, 16 O2 or 18 Oxygen gas such as O2, nitrous oxide gas or ozone gas, etc.

[0302] In order to prevent the increase of the hydrogen concentration in the oxide layer 830, the hydrogen concentration in the insulating layers 812 to 819 is preferably reduced. In particular, the hydrogen concentration in the insulating layers 813 to 818 is preferably reduced. Specifically, the hydrogen concentration is 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 the following.

[0303] The above hydrogen concentration is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

[0304] In the transistor 801, the oxide layer 830 is preferably surrounded by an insulating layer having a barrier property to oxygen and hydrogen (hereinafter, such an insulating layer is also referred to as a barrier layer). By adopting this structure, the release of oxygen from the oxide layer 830 can be suppressed and the intrusion of hydrogen into the oxide layer 830 can be suppressed. Thus, the reliability and electrical characteristics of the transistor 801 can be improved.

[0305] For example, the insulating layer 819 is used as a barrier layer, and at least one of the insulating layers 811, 812, and 814 is used as a barrier layer. The barrier layer can be formed using a material such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or silicon nitride.

[0306] Here, an example of the structure of insulating layers 811 to 818 is shown. In this example, insulating layers 811, 812, 815, and 819 are all used as barrier layers. Insulating layers 816 to 818 are oxide layers containing excess oxygen. Insulating layer 811 is formed using silicon nitride. Insulating layer 812 is formed using aluminum oxide. Insulating layer 813 is formed using silicon oxynitride. Insulating layers 814 to 816 used as gate insulating layers on the back gate electrode side are formed using a stack of silicon oxide, aluminum oxide, and silicon oxide. Insulating layer 817 used as a gate insulating layer on the front gate side is formed using silicon oxynitride. Insulating layer 818 used as an interlayer insulating layer is formed using silicon oxide. Insulating layer 819 is formed using aluminum oxide.

[0307] As the conductive material used for the conductive layers 850 to 853, there are metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, and metal nitrides containing any of the above metals as components (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride), etc. Conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon oxide can be used.

[0308] Here, structural examples of conductive layers 850 to 853 are shown. Conductive layer 850 is a single layer of tantalum nitride or tungsten. Alternatively, conductive layer 850 is a stack of tantalum nitride, tantalum, and tantalum nitride. Conductive layer 851 is a single layer of tantalum nitride or a stack of tantalum nitride and tungsten. The structure of conductive layer 852 is the same as that of conductive layer 851. Conductive layer 853 is a single layer of tantalum nitride or a stack of tantalum nitride and tungsten.

[0309] The metal oxide film 822 preferably has a large energy gap, for example, in order to reduce the off-state current of the transistor 801. The energy gap of the metal oxide film 822 is 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

[0310] The oxide layer 830 preferably has crystallinity. Preferably, at least the metal oxide film 822 has crystallinity. With the above structure, the transistor 801 having high reliability and excellent electric characteristics can be realized.

[0311] Oxides that can be used for the metal oxide film 822 are, for example, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Al, Ga, Y or Sn). The metal oxide film 822 is not limited to an oxide layer containing indium. The metal oxide film 822 can be formed using, for example, Zn-Sn oxide, Ga-Sn oxide, Zn-Mg oxide, etc. The metal oxide films 821, 823, and 824 can also be formed using the same oxide as the metal oxide film 822. In particular, the metal oxide films 821, 823, and 824 can each be formed using Ga oxide.

[0312] When an interface energy level is formed at the interface between the metal oxide film 822 and the metal oxide film 821, the threshold voltage of the transistor 801 varies because the channel formation region is also formed in the region near the interface. The metal oxide film 821 preferably includes at least one of the metal elements constituting the metal oxide film 822 as its constituent element. As a result, an interface energy level is not easily formed at the interface between the metal oxide film 822 and the metal oxide film 821, and the deviation of the electrical characteristics such as the threshold voltage of the transistor 801 can be reduced.

[0313] The metal oxide film 824 preferably contains at least one of the metal elements constituting the metal oxide film 822 as a constituent element because interface scattering is less likely to occur at the interface between the metal oxide film 822 and the metal oxide film 824, and carrier migration is less likely to be hindered. Therefore, the field effect mobility of the transistor 801 can be improved.

[0314] It is preferable that the metal oxide film 822 has the highest carrier mobility among the metal oxide films 821 to 824. Thus, a channel can be formed in the metal oxide film 822 away from the insulating layers 816 and 817.

[0315] For example, metal oxides containing In, such as In-M-Zn oxide, can improve carrier mobility by increasing the In content. In In-M-Zn oxide, it is mainly the s orbital of the heavy metal that drives carrier conduction, and the overlap of the s orbitals of In atoms can be increased by increasing the indium content, so that the mobility of oxides with a high indium content is higher than that of oxides with a low indium content. Therefore, by using an oxide with a high indium content as a metal oxide film, carrier mobility can be improved.

[0316] Therefore, for example, the metal oxide film 822 is formed using In-Ga-Zn oxide, and the metal oxide films 821 and 823 are formed using Ga oxide. For example, when the metal oxide films 821 to 823 are formed using In-M-Zn oxide, the In content of the metal oxide film 822 is made higher than the In content of the metal oxide films 821 and 823. When the In-M-Zn oxide is formed by sputtering, the In content can be changed by changing the atomic ratio of the metal element in the target.

[0317] For example, the atomic ratio of the metal elements of the target used to deposit the metal oxide film 822 is preferably In:M:Zn=1:1:1, 3:1:2, or 4:2:4.1. For example, the atomic ratio of the metal elements of the target used to deposit the metal oxide films 821 and 823 is preferably In:M:Zn=1:3:2 or 1:3:4. The atomic ratio of the In-M-Zn oxide deposited using a target of In:M:Zn=4:2:4.1 is approximately In:M:Zn=4:2:3.

[0318] In order to give the transistor 801 stable electrical characteristics, it is preferable to reduce the impurity concentration in the oxide layer 830. In metal oxides, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are impurities. For example, hydrogen and nitrogen form donor energy levels, resulting in increased carrier density. In addition, silicon and carbon form impurity energy levels in the metal oxide. This impurity energy level becomes a trap, sometimes degrading the electrical characteristics of the transistor.

[0319] For example, the oxide layer 830 has a silicon concentration of 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 The carbon concentration in the oxide layer 830 is also the same.

[0320] The oxide layer 830 has an alkali metal concentration of 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 The alkaline earth metal concentration of the oxide layer 830 is also the same.

[0321] The oxide layer 830 has a hydrogen concentration lower than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3, and more preferably less than 1×10 18 atoms / cm 3 area.

[0322] The impurity concentration in the oxide layer 830 is measured by SIMS.

[0323] In the case where the metal oxide film 822 has oxygen vacancies, a donor energy level is sometimes formed due to the entry of hydrogen into the oxygen vacancy portion. The oxygen vacancies become a factor in the reduction of the on-state current of the transistor 801. Note that the oxygen vacancy portion is more stable when oxygen enters than when hydrogen enters. Therefore, by reducing the oxygen vacancies in the metal oxide film 822, the on-state current of the transistor 801 can sometimes be increased. Thus, the method of preventing hydrogen from entering the oxygen vacancy portion by reducing the hydrogen in the metal oxide film 822 is effective for improving the on-state current characteristics.

[0324] Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to generate water, thereby sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes a part of hydrogen is bonded to oxygen bonded to the metal atom to generate electrons as carriers. Since the metal oxide film 822 includes a channel formation region, when the metal oxide film 822 includes hydrogen, the transistor 801 tends to have a normally-on characteristic. Therefore, it is preferable to reduce the hydrogen in the metal oxide film 822 as much as possible.

[0325] Note that the metal oxide film 822 may include an n-type region 822n in a region in contact with the conductive layer 851 or the conductive layer 852. The region 822n is formed by a phenomenon in which oxygen in the metal oxide film 822 is extracted by the conductive layer 851 or the conductive layer 852, or a phenomenon in which a conductive material in the conductive layer 851 or the conductive layer 852 is bonded to an element in the metal oxide film 822. By forming the region 822n, the contact resistance between the conductive layer 851 or the conductive layer 852 and the metal oxide film 822 can be reduced.

[0326] 18A to 18C Although an example of a four-layer structure of the oxide layer 830 is shown, one embodiment of the present invention is not limited thereto. For example, the oxide layer 830 may also be a three-layer structure without the metal oxide film 821 or the metal oxide film 823. Alternatively, one or more metal oxide films similar to the metal oxide films 821 to 824 may be provided between any layers of the oxide layer 830, above the oxide layer 830, and below the oxide layer 830.

[0327] Reference Fig.19 The effect of stacking the metal oxide films 821 , 822 , and 824 will be described. Fig.19FIG. 8 is a schematic diagram of an energy band structure of a channel formation region of the transistor 801 .

[0328] exist Fig.19 In FIG. 8 , Ec816e, Ec821e, Ec822e, Ec824e, and Ec817e represent the energies of the conduction band bottoms of the insulating layer 816, the metal oxide film 821, the metal oxide film 822, the metal oxide film 824, and the insulating layer 817, respectively.

[0329] Here, the energy difference between the vacuum level and the bottom of the conduction band (this difference is also called electron affinity) is the value obtained by subtracting the energy gap from the energy difference between the vacuum level and the top of the valence band (this difference is also called ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (UT-300 manufactured by HORIBA JOBIN YVON). The energy difference between the vacuum level and the top of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) device (VersaProbe manufactured by PHI).

[0330] Because insulating layers 816 and 817 are insulators, Ec816e and Ec817e are closer to the vacuum level than Ec821e, Ec822e, and Ec824e (ie, the electron affinity of insulating layers 816 and 817 is smaller than that of metal oxide films 821, 822, and 824).

[0331] The electron affinity of the metal oxide film 822 is greater than that of the metal oxide films 821 and 824. For example, the difference in electron affinity between the metal oxide film 822 and the metal oxide film 821 and the difference in electron affinity between the metal oxide film 822 and the metal oxide film 824 are both 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. Note that the electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0332] When a voltage is applied to the gate electrode (conductive layer 850 ) of the transistor 801 , a channel is mainly formed in the metal oxide film 822 having the highest electron affinity among the metal oxide films 821 , 822 , and 824 .

[0333] Indium gallium oxide has a low electron affinity and high oxygen barrier properties. Therefore, the metal oxide film 824 preferably contains indium gallium oxide. The ratio of gallium atoms [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

[0334] Sometimes, a mixed region of the metal oxide film 821 and the metal oxide film 822 exists between the metal oxide film 821 and the metal oxide film 822. Also, sometimes, a mixed region of the metal oxide film 824 and the metal oxide film 822 exists between the metal oxide film 824 and the metal oxide film 822. Since the interface state density in the mixed region is low, in the band structure of the region where the metal oxide films 821, 822, and 824 are stacked, the energy of each interface and its vicinity changes continuously (continuous bonding).

[0335] In the oxide layer 830 having the above-described energy band structure, electrons mainly migrate in the metal oxide film 822. Therefore, even if there are interface energy levels at the interface between the metal oxide film 821 and the insulating layer 816 or at the interface between the metal oxide film 824 and the insulating layer 817, these interface energy levels are not likely to hinder electron migration in the oxide layer 830, and thus the on-state current of the transistor 801 can be increased.

[0336] like Fig.19 As shown, although trap energy levels Et826e and Et827e caused by impurities or defects may be formed near the interface between the metal oxide film 821 and the insulating layer 816 and near the interface between the metal oxide film 824 and the insulating layer 817, the presence of the metal oxide films 821 and 824 can keep the metal oxide film 822 away from the trap energy levels Et826e and Et827e.

[0337] Note that when the energy difference between Ec821e and Ec822e is small, sometimes the electrons of the metal oxide film 822 cross the energy difference and reach the trap level Et826e. Since the electrons are captured by the trap level Et826e, a fixed negative charge is generated at the interface of the insulating film, which causes the threshold voltage of the transistor to drift to the positive direction. The same is true when the energy difference between Ec822e and Ec824e is small.

[0338] In order to reduce the variation in the threshold voltage of the transistor 801 and improve the electrical characteristics of the transistor 801 , the energy difference between Ec821e and Ec822e and the energy difference between Ec824e and Ec822e are preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0339] Note that the transistor 801 may not include a back gate electrode.

[0340] <Example of laminated structure>

[0341] Next, the structure of a semiconductor device in which an OS transistor and other transistors are stacked will be described.

[0342] Fig. 20An example of a stacked structure of a semiconductor device 860 is shown, in which a transistor Tr100 which is a Si transistor, a Tr200 which is an OS transistor, and a capacitor C100 are stacked.

[0343] The semiconductor device 860 is constituted by a stack of a CMOS layer 871, wiring layers W1 to W5, a transistor layer 872, and wiring layers W6 and W7.

[0344] A transistor Tr100 is provided in the CMOS layer 871. A channel formation region of the transistor Tr100 is provided in the single crystal silicon wafer 870. A gate electrode 873 of the transistor Tr100 is connected to one electrode 875 of the capacitor C100 through wiring layers W1 to W5.

[0345] A transistor Tr200 is provided in the transistor layer 872. Fig. 20 In the embodiment, transistor Tr200 and transistor 801 ( 18A to 18C ) has the same structure. The electrode 874 corresponding to one of the source and drain of the transistor Tr200 is connected to an electrode 875 of the capacitor C100. Note that Fig. 20 In the embodiment, the transistor Tr200 has a back gate electrode in the wiring layer W5. The capacitor C100 is provided in the wiring layer W6.

[0346] As described above, by stacking OS transistors and other elements, the circuit area can be reduced.

[0347] The above structure can be applied to the semiconductor device 200 described in Embodiment 3 and the like. Fig.15 A and Fig.15 The transistor Tr11, the transistor Tr12 and the capacitor C11 in B can be replaced by the transistor Tr100, the transistor Tr200 and the capacitor C100 respectively. Fig.16 The transistor Tr21 or Tr24, the transistor Tr22, Tr23, Tr25 or Tr26, and the capacitor C21 or C22 may use the transistor Tr100, the transistor Tr200, and the capacitor C100, respectively.

[0348] This embodiment mode can be combined with any other embodiment mode as appropriate.

[0349] (Implementation 6)

[0350] In this embodiment, metal oxides that can be used for the OS transistor described in the above embodiment are described. In particular, metal oxides and cloud-aligned composite oxide semiconductor (CAC-OS) are described in detail below.

[0351] CAC-OS or CAC metal oxide has a conductive function in a part of the material and an insulating function in another part of the material, and CAC-OS or CAC metal oxide has a semiconductor function as a whole. When CAC-OS or CAC metal oxide is used in the channel formation region of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC metal oxide can have a switching function (on / off function). By separating each function in CAC-OS or CAC metal oxide, each function can be maximized.

[0352] CAC-OS or CAC metal oxide includes a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In the material, the conductive region and the insulating region are sometimes separated at the nanoparticle level. The conductive region and the insulating region are sometimes unevenly distributed in the material. Sometimes, the conductive region is observed to be connected in a cloud-like manner with blurred edges.

[0353] In CAC-OS or CAC metal oxide, the conductive region and the insulating region each have a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, and are dispersed in the material.

[0354] CAC-OS or CAC metal oxide is composed of components with different band gaps. For example, CAC-OS or CACmetal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. The component with the narrow gap interacts with the component with the narrow gap through the complementary effect with the component with the wide gap, and also allows carriers to flow through the component with the wide gap. Therefore, when the above-mentioned CAC-OS or CAC metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on state of the transistor.

[0355] That is, CAC-OS or CAC metal oxide may also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).

[0356] CAC-OS has, for example, a structure in which the elements contained in the oxide semiconductor are unevenly distributed. The materials containing the unevenly distributed elements each have a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a similar size. Note that in the following description of metal oxides, the state in which one or more metal elements are unevenly distributed and mixed with the region containing the metal element is referred to as a mosaic or patch shape. The regions each have a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or a similar size.

[0357] Note that the metal oxide preferably contains at least indium. In particular, it is preferred to contain indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0358] For example, in CAC-OS, In-Ga-Zn oxide (especially such In-Ga-Zn oxide may be referred to as CAC-IGZO) having a CAC-OS structure has a material structure of indium oxide (InO X1 , X1 is a real number greater than 0) or indium zinc oxide (In X2 Zn Y2 O Z2 , X2, Y2 and Z2 are real numbers greater than 0) and gallium oxide (GaO X3 , X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4 , X4, Y4 and Z4 are real numbers greater than 0) etc. to form a mosaic structure. X1 or In X2 Zn Y2 O Z2 Evenly distributed in the film. This formation is also called cloud-like formation.

[0359] In other words, CAC-OS is a GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 Note that in this specification, for example, when the atomic number ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0360] Note that a compound containing In, Ga, Zn, and O is also known as IGZO. As a typical example, InGaO3(ZnO) m1 (m1 is a natural number) and the crystalline compound represented by In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is an arbitrary number).

[0361] The crystalline compound has a single crystal structure, a polycrystalline structure, or a c-axis-aligned crystal (CAAC: c-axis oriented crystal) structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0362] On the other hand, CAC-OS is related to the material composition of metal oxides. In the material composition of CAC-OS containing In, Ga, Zn and O, regions of nanoparticles with Ga as the main component and regions of nanoparticles with In as the main component are partially observed. These nanoparticle regions are scattered irregularly in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0363] Note that CAC-OS does not include a stacked-layer structure including two or more films having different atomic number ratios, for example, a two-layer structure including a film having In as a main component and a film having Ga as a main component.

[0364] Sometimes no GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 There are clear boundaries between the regions of the main components.

[0365] When CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium instead of gallium, nanoparticle-like regions with the metal element as the main component are observed in a part of the CAC-OS and nanoparticle-like regions with In as the main component are observed in a part, and these nanoparticle-like regions are irregularly dispersed in a mosaic shape in the CAC-OS.

[0366] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When CAC-OS is formed by sputtering, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used as a deposition gas. The lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and less than 10%.

[0367] CAC-OS has the following characteristics: when measured by the Out-of-plane method using θ / 2θ scanning, which is one of the X-ray diffraction (XRD) measurement methods, no clear peak is observed. In other words, according to X-ray diffraction, it can be seen that there is no orientation in the ab plane direction and the c-axis direction in the measurement area.

[0368] In the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called a nano-sized electron beam), a ring-shaped area with high brightness and multiple bright spots in the ring-shaped area were observed. Therefore, according to the electron diffraction pattern, it can be seen that the crystalline structure of CAC-OS includes a nanocrystal (nc: nanocrystal) structure that is not oriented in the plane direction and the cross-sectional direction.

[0369] For example, based on the surface analysis image obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that the In-Ga-Zn oxide having a CAC structure has GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 A mixed structure in which the main components are distributed unevenly in the area.

[0370] The structure of CAC-OS is different from that of IGZO compounds in which metal elements are evenly distributed, and it has different properties from those of IGZO compounds. X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 The regions with the main components are separated to form a mosaic shape.

[0371] In X2 Zn Y2 O Z2 or InO X1The conductivity of the area with GaO as the main component is higher than that of the area with GaO as the main component. X3 In other words, when the carrier flows through the region with In X2 Zn Y2 O Z2 or InO X1 When In is the main component of the region, it exhibits the conductivity of an oxide semiconductor. X2 Zn Y2 O Z2 or InO X1 When the region as the main component is distributed in a cloud-like manner in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0372] On the other hand, GaO X3 The insulation of the area with In as the main component is higher than that of the area with In X2 Zn Y2 O Z2 or InO X1 In other words, when GaO X3 When regions with the main components of , etc. are distributed in an oxide semiconductor, the off-state current can be suppressed and good switching operation can be achieved.

[0373] Therefore, when CAC-OS is used in semiconductor devices, the X3 The insulation properties of etc. and the causes of In X2 Zn Y2 O Z2 or InO X1 The complementary effect of conductivity can achieve high on-state current (I on ) and high field effect mobility (μ).

[0374] Semiconductor elements using CAC-OS have high reliability. Therefore, CAC-OS is suitable for various semiconductor devices.

[0375] This embodiment mode can be combined with any other embodiment mode as appropriate.

[0376] (Implementation 7)

[0377] In this embodiment, a configuration example of an electronic device that can be used for the power receiving unit described in the above embodiment will be described.

[0378] FIG. 21A to FIG. 21F5000, a display unit 5001, a speaker 5003, an LED lamp 5004, an operation key 5005 (including a power switch and an operation switch), a connection terminal 5006, a sensor 5007 (a sensor having a function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 5008, etc.

[0379] Fig.21A A mobile computer is shown, which may include a switch 5009, an infrared port 5010, etc. in addition to the above. Fig.21B A portable image reproduction device (for example, a DVD reproduction device) provided with a recording medium is shown, and the portable image reproduction device may include a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above. Fig. 21C A goggle-type display is shown, which may include a second display portion 5002, a support portion 5012, headphones 5013, etc. in addition to the above. Fig.21D The portable game machine is shown, and the portable game machine may include a recording medium reading unit 5011 and the like in addition to the above. Fig.21E A digital camera having a television reception function is shown, and the digital camera may include an antenna 5014, a shutter button 5015, an image receiving unit 5016, and the like in addition to the above. Fig.21F 2004 , a portable game machine is shown, which may include a second display portion 5002 , a recording medium reading portion 5011 , and the like in addition to the above.

[0380] FIG. 21A to FIG. 21FThe electronic device shown may have various functions. For example, it may have the following functions: displaying various data (static images, dynamic images, text images, etc.) on the display unit; touch panel; displaying calendar, date and time, etc.; controlling processing by using various software (programs); performing wireless communications; connecting to various computer networks by using the wireless communication function; sending and receiving various data by using the wireless communication function; reading out programs or data stored in a recording medium to display them on the display unit, etc. Furthermore, in an electronic device having multiple display units, it may have the following functions: one display unit mainly displays image data, while another display unit mainly displays text data; or, images that take parallax into account are displayed on multiple display units to display stereoscopic images, etc. Furthermore, in an electronic device having an image receiving unit, it may have the following functions: shooting static images; shooting dynamic images; automatically or manually correcting the shot images; storing the shot images in a recording medium (external recording medium or a recording medium built into the camera); displaying the shot images on the display unit, etc. Note that, FIG. 21A to FIG. 21F The functions that the electronic device shown may have are not limited to the above functions, but may have various functions.

[0381] The electronic device described in this embodiment has a built-in battery and can perform the wireless power supply described in the above embodiments.

[0382] Fig.22A and Fig. 22B An example of use of electronic equipment is shown.

[0383] Fig.22A An example of operating an information terminal in a moving object such as a car is shown.

[0384] 5103 is a steering wheel having an antenna inside. The antenna inside the steering wheel 5103 can supply power to the electronic device 5100. The electronic device 5100 includes a battery and can be charged by wireless power supply. A bracket capable of fixing the electronic device 5100 can be provided on the steering wheel 5103. When the electronic device 5100 is fixed to the steering wheel 5103, a call or video call can be made without using the hands. In addition, by using the microphone of the electronic device 5100 for voice recognition, driving can be performed using the driver's voice.

[0385] For example, the electronic device 5100 can be operated to display the position information on the display unit 5102 when the vehicle is parked. In addition, information that is not displayed on the in-vehicle display unit 5101 can be displayed on the display unit 5102, such as engine speed, steering wheel angle, temperature, tire pressure, etc. The display unit 5102 has a touch input function. In addition, one or more cameras that take photos of the outside of the vehicle can be used to display the image outside the vehicle on the display unit 5102. That is, for example, the display unit 5102 can be used as a rear monitor. In addition, in order to prevent fatigue driving, the electronic device 5100 can perform the following operations: while monitoring the driving speed while receiving information such as the driving speed from the vehicle in a wireless manner, the electronic device 5100 takes a photo of the driver while driving, and when the driver closes his eyes for a long time, the electronic device 5100 vibrates, emits a warning sound, or plays music, etc. (according to the setting that the driver can appropriately select). In addition, when parking, the driver can stop taking photos to save power. In addition, the battery of the electronic device 5100 can be wirelessly charged when parking.

[0386] As described above, the electronic device 5100 is expected to be applied to mobile objects such as cars in various ways. In order to make the electronic device 5100 have multiple functions, it is preferred that the electronic device 5100 has multiple sensors and multiple antennas built in. Although mobile objects such as cars have power supplies, the power supply is limited. Considering the power required to drive the mobile object, it is preferred that the power used by the electronic device 5100 is as low as possible. Especially for electric vehicles, the power consumption of the electronic device 5100 will shorten the driving distance. Even if the electronic device 5100 has multiple functions, there are few opportunities to use all functions at the same time, and most of the time only one or two functions are used as needed. In the case of preparing batteries corresponding to each function so that the electronic device 5100 with multiple batteries has multiple functions, power can be saved by only turning on the function you want to use and supplying power from the battery corresponding to the function. Furthermore, the battery corresponding to the unused function among the multiple batteries can be wirelessly charged using the antenna provided on the vehicle.

[0387] Fig. 22B An example of operating an information terminal in an airplane etc. is shown. Since the time when a personal information terminal can be used in an airplane etc. is limited, it is preferable that an airplane has an information terminal that passengers can use when the flight time is long.

[0388] The electronic device 5200 is an information terminal that can display images such as movies, games, and advertisements on a display unit 5202 and can instantly obtain the current flight position and remaining flight time using a communication function. The display unit 5202 has a touch input function.

[0389] By embedding the electronic device 5200 in the recess of the seat 5201 and setting the antenna setting part 5203 at a position overlapping with the electronic device 5200, the electronic device 5200 can be wirelessly powered while it is embedded in the recess. When the user is unwell and wants to contact the crew, the electronic device 5200 can also be used as a telephone or communication tool. When the electronic device 5200 has a translation function, a passenger who speaks a different language from the crew can also communicate with the crew using the display unit 5202 of the electronic device 5200. In addition, passengers who speak different languages ​​in adjacent seats can also communicate using the display unit 5202 of the electronic device 5200. In addition, the display unit 5202 can also be used as a message board, for example, when the user is sleeping, the display unit 5202 can be used to display English messages such as "Do Not Disturb".

[0390] The electronic device 5200 can be provided with multiple batteries according to each function, and power can be saved by turning on only the functions that are desired to be used and turning off the functions that are not used. Furthermore, the batteries corresponding to the functions that are not working among the multiple batteries can be wirelessly powered by the antenna setting unit 5203.

[0391] The batteries of the electronic devices 5200 in the plurality of seats can be designed to be used as emergency power sources when an abnormality occurs in the electrical system of the aircraft. Since the electronic devices 5200 in the plurality of seats are all the same product and have the same design, the system can be constructed in such a way that the electronic devices 5200 can be connected in series as emergency power sources.

[0392] As the plurality of small batteries included in the electronic device 5200, one or more selected from lithium ion secondary batteries such as lithium polymer batteries, lithium ion capacitors, electric double layer capacitors, and redox capacitors can be used.

[0393] Next, another example of electronic equipment that can be used for the power receiving unit described in the above embodiment will be described. Fig.23 is a schematic cross-sectional view showing an example of a pacemaker.

[0394] The pacemaker body 5300 includes at least a battery 5301a, a battery 5301b, a regulator, a control circuit, an antenna 5304, a lead 5302 to the right atrium, and a lead 5303 to the right ventricle.

[0395] The pacemaker body 5300 is implanted into the body through surgery, and two wires are inserted into the body through the subclavian vein 5305 and the superior vena cava 5306. The front end of one wire is implanted into the right ventricle, and the front end of the other wire is implanted into the right atrium.

[0396] The battery 5301a and the battery 5301b can be charged by receiving power through the antenna 5304, thereby reducing the replacement frequency of the pacemaker. Since the pacemaker body 5300 has a plurality of batteries and has a high safety, even if one battery fails, another battery can still work. Thus, a plurality of batteries can be used as an auxiliary power source. When the battery used for the pacemaker is divided into a plurality of thin batteries and mounted on a printed board provided with a control circuit including a CPU, etc., the pacemaker body 5300 can be made smaller and thinner.

[0397] In addition to the antenna 5304 that can receive power, the pacemaker may also include an antenna that can send physiological signals. For example, a system for monitoring cardiac activity that can monitor physiological signals such as pulse, respiratory rate, heart rate, and body temperature using an external monitor may be constructed.

[0398] Note that this pacemaker setting method is just an example and can be changed in various ways depending on the heart disease patient.

[0399] This embodiment is not limited to pacemakers. Cochlear implants are more popular artificial organs than pacemakers. Cochlear implants convert sound into electrical signals and directly stimulate the auditory nerve using a stimulator implanted in the cochlea.

[0400] The cochlear implant includes a first device that is surgically implanted in the ear and a second device that uses a microphone to pick up sound and transmits the picked up sound to the implanted first device. The first device and the second device are not electrically connected to each other, and the transmission and reception between the two are performed wirelessly. The first device at least includes an antenna for receiving the electrical signal after the sound is converted and a wire that directly reaches the cochlea. The second device at least includes a sound processing unit for converting the sound into an electrical signal and a transmission circuit that sends the electrical signal to the first device.

[0401] This embodiment mode can be combined with any other embodiment mode as appropriate.

[0402] Explanation of symbols

[0403] 10: Power supply system, 11: Power supply unit, 12: Power receiving unit, 20: Transmitting and receiving circuit, 21: Antenna circuit, 22: Rectification circuit, 23: Charging circuit, 24: Control circuit, 25: Switching circuit, 26: Delay circuit, 27: Antenna circuit, 30: Battery, 40: Sensor, 50: Timer, 101: Receiving circuit, 102: Transmitting circuit, 111: Antenna coil, 112: Capacitor, 113: Antenna coil, 114: Capacitor, 121: Diode, 122: Capacitor, 123: Diode, 131: Regulator, 132: Switch, 141: Determination circuit, 142: Signal generating circuit, 143: Switching circuit, 150 : buffer circuit, 151: transistor, 152: transistor, 153: transistor, 154: transistor, 155: transistor, 156: transistor, 157: inverter, 161: inverter, 171: antenna coil, 172: capacitor, 200: semiconductor device, 210: storage circuit, 220: reference storage circuit, 230: circuit, 240: circuit, 250: current source circuit, 801: transistor, 811: insulating layer, 812: insulating layer, 813: insulating layer, 814: insulating layer, 815: insulating layer, 816: insulating layer, 817: insulating layer, 818: insulating layer, 819: insulating layer, 820: insulating layer, 821: Metal oxide film, 822: Metal oxide film, 822n: Region, 823: Metal oxide film, 824: Metal oxide film, 830: Oxide layer, 850: Conductive layer, 851: Conductive layer, 852: Conductive layer, 853: Conductive layer, 860: Semiconductor device, 870: Single crystal silicon wafer, 871: CMOS layer, 872: Transistor layer, 873: Gate electrode, 874: Electrode, 875: Electrode, 5000: Frame, 5001: Display unit, 5002: Display unit, 5003: Speaker, 5004: LED lamp, 5005: Operation key, 5006: Connection terminal, 5007: Sensor, 5008 : microphone, 5009: switch, 5010: infrared port, 5011: recording medium reading unit, 5012: support unit, 5013: earphone, 5014: antenna, 5015: shutter button, 5016: image receiving unit, 5100: electronic device, 5101: display unit, 5102: display unit, 5103: steering wheel, 5200: electronic device, 5201: seat, 5202: display unit, 5203: antenna setting unit, 5300: pacemaker body, 5301a: battery, 5301b: battery, 5302: lead wire, 5303: lead wire, 5304: antenna, 5305: subclavian vein, 5306: superior vena cava

[0404] This application is based on Japanese Patent Application No. 2017-092025 filed with the Japan Patent Office on May 3, 2017, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device comprising: Transceiver circuit; as well as Battery, The transceiver circuit is configured to receive a first electromagnetic wave transmitted by a power supply unit to supply power to the battery and generate a second electromagnetic wave using the power of the battery. The second electromagnetic wave is generated by using the power of the battery when charging of the battery is completed, The transceiver circuit includes a neural network, The neural network determines whether to generate the second electromagnetic wave based on the information about the overcharge, Furthermore, the second electromagnetic wave is configured to cancel the first electromagnetic wave.

2. The semiconductor device according to claim 1, The transceiver circuit includes an antenna circuit and a control circuit. The antenna circuit is configured to receive the first electromagnetic wave and transmit the second electromagnetic wave, The control circuit is configured to determine whether to generate the second electromagnetic wave based on the information about the overcharge. And the control circuit is configured to supply an AC signal for generating the second electromagnetic wave to the antenna circuit when it is determined to generate the second electromagnetic wave.

3. The semiconductor device according to claim 1, The transceiver circuit includes an antenna circuit and a control circuit. The control circuit includes a determination circuit and a signal generation circuit. The antenna circuit is configured to receive the first electromagnetic wave and transmit the second electromagnetic wave, The determination circuit is configured to determine whether to generate the second electromagnetic wave based on the information about the overcharge. Furthermore, the signal generating circuit is configured to supply the antenna circuit with a second AC signal for generating the second electromagnetic wave using the first AC signal generated based on the first electromagnetic wave and the power supplied by the battery. 4 . The semiconductor device according to claim 2 , wherein the information on overcharge includes temperature information measured by a sensor or information on the first electromagnetic wave reception time.

5. The semiconductor device according to claim 2, wherein the input layer of the neural network is input with data corresponding to the information about overcharging, And the output layer of the neural network outputs data corresponding to the determination result of whether the second electromagnetic wave is generated.

6. The semiconductor device according to claim 1, wherein the semiconductor device is configured to transmit a third electromagnetic wave for enhancing the first electromagnetic wave when charging of the battery is completed.

7. An electronic device comprising the semiconductor device according to claim 1.

8. A semiconductor device comprising: Battery; as well as a transceiver circuit configured to receive a first electromagnetic wave transmitted for charging the battery and to transmit a second electromagnetic wave for canceling the first electromagnetic wave when charging of the battery is completed, Wherein, the transceiver circuit includes a neural network, The neural network determines whether to generate the second electromagnetic wave based on the information about the overcharge.

9. A method for charging a semiconductor device including a battery, the method comprising the following steps: generating electric power using a first electromagnetic wave received from a power supply unit; supplying the power to the battery to charge the battery; generating a second electromagnetic wave using power from the battery when charging of the battery is completed; and By sending the second electromagnetic wave to cancel the first electromagnetic wave, in, The second electromagnetic wave is generated by a transceiver circuit, The transceiver circuit includes a neural network, The neural network determines whether to generate the second electromagnetic wave based on the information about the overcharge.

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