Amplifier and amplifier module having stub circuit

Abstract

An amplifier module is provided. The amplifier module includes a multilayer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multilayer PCB. A second power transistor die is mounted at the top surface of the multilayer PCB. An impedance inverter element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combination node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled to the combination node.

Description

Technical Field

[0001] The present disclosure relates generally to radio frequency (RF) electronic components, and more particularly to RF amplifiers and amplifier modules having stub circuits. Background Art

[0002] Today, radio frequency (RF) systems are used to provide wireless communications for, for example, cellular phones, wireless data networks, and radio systems. In wireless communication systems, power amplifiers form part of the last amplification stage in the transmission chain before providing the amplified signal to an antenna for radiation via an air interface. Desirable amplifier characteristics in such wireless communication systems are high gain, high linearity, stability, and a high level of power plus efficiency. However, achieving these characteristics poses challenges to the architecture of wireless communication systems. Summary of the invention

[0003] According to a first aspect of the present invention, there is provided an amplifier module, comprising:

[0004] Multilayer printed circuit board (PCB);

[0005] a first power transistor die mounted at a top surface of the multi-layer PCB;

[0006] a second power transistor die mounted at the top surface of the multi-layer PCB;

[0007] an impedance inverting element coupled between an output of the first power transistor die and an output of the second power transistor die to form a combined node at the output of the second power transistor die; and

[0008] A first stub circuit is coupled at the combining node, the first stub circuit comprising a first transmission line element having a first end coupled to the combining node.

[0009] In one or more embodiments, the first transmission line element is formed as a first stripline formed by a first inner conductive layer of the multi-layer PCB.

[0010] In one or more embodiments, the impedance inversion element includes a microstrip formed by a top conductive layer of the multi-layer PCB, at least a portion of the microstrip overlapping at least a portion of the first stripline.

[0011] In one or more embodiments, the first stub circuit is configured to act as a baseband (F 0 ) and acts as a second harmonic frequency (2*F0 ) under the ground reference voltage shunt.

[0012] In one or more embodiments, the first stub circuit further includes a first capacitor, a first end of the first capacitor coupled to the second end of the first stripline.

[0013] In one or more embodiments, the first capacitor comprises a surface mount capacitor mounted at the top surface of the multi-layer PCB.

[0014] In one or more embodiments, the surface mount capacitor comprises a metal-insulator-metal (MIM) capacitor.

[0015] In one or more embodiments, the first stub circuit further includes an inductor coupled to the MIM capacitor.

[0016] In one or more embodiments, the module further includes a second short line circuit coupled in parallel with the first short line circuit at the combination node, the second short line circuit including a second stripline, and the second stripline is formed by an inner conductive layer of the multilayer PCB that is different from the inner conductive layer forming the first stripline.

[0017] In one or more embodiments, the second stub circuit is configured to generate a third harmonic frequency (3*F 0 ) acts as a ground reference voltage shunt at the output of the second power transistor die and acts as a disconnect circuit at the output of the first power transistor die.

[0018] In one or more embodiments, the first power transistor die is configured to operate in a class AB mode and the second power transistor die is configured to operate in a class C mode.

[0019] According to a second aspect of the present invention, there is provided an amplifier module, comprising:

[0020] Multilayer printed circuit board (PCB);

[0021] a first power transistor die mounted at a top surface of the multi-layer PCB, the first power transistor die being configured as a carrier amplifier;

[0022] a second power transistor die mounted at the top surface of the multi-layer PCB, the second power transistor die being configured as a peaking amplifier;

[0023] an impedance inverting element coupled between an output of the first power transistor die and an output of the second power transistor die to form a combined node at the output of the second power transistor die; and

[0024] A first stub circuit is coupled to the combining node, the first stub circuit comprising a first stripline having a first end coupled to the combining node.

[0025] In one or more embodiments, the second power transistor die is oriented in a different direction than the first power transistor die.

[0026] In one or more embodiments, the module further includes a second stub circuit coupled in parallel with the first stub circuit at the combining node, the second stub circuit including a second stripline having a first end coupled to the combining node.

[0027] In one or more embodiments, the first stripline is formed from a first inner conductive layer of the multi-layer PCB and the second stripline is formed from a second inner conductive layer of the multi-layer PCB.

[0028] In one or more embodiments, the impedance inversion element includes a microstrip formed by a top conductive layer of the multilayer PCB, at least a portion of the microstrip overlapping at least a portion of the first stripline and at least a portion of the second stripline.

[0029] In one or more embodiments, the first stub circuit is configured to have an electrical length of approximately 90 degrees and the second stub circuit is configured to have an electrical length of approximately 60 degrees.

[0030] According to a third aspect of the present invention, there is provided a Doherty amplifier, comprising:

[0031] Multilayer printed circuit board (PCB);

[0032] a carrier amplifier die mounted at the top surface of the multi-layer PCB;

[0033] a peaking amplifier die mounted at the top surface of the multi-layer PCB;

[0034] an impedance inverting element coupled between a drain terminal of the carrier amplifier die and a drain terminal of the peaking amplifier die to form a combined node at the drain terminal of the peaking amplifier die; and

[0035] A first stub circuit is coupled to the combination node, wherein the first stub circuit includes a first stripline formed by a first conductive layer of the PCB.

[0036] In one or more embodiments, the first stub circuit is configured to act as a baseband (F 0 ) and acts as a second harmonic frequency (2*F 0 ) under the ground reference voltage shunt.

[0037] In one or more embodiments, the amplifier further includes a second stub circuit coupled in parallel with the first stub circuit at the combination node, the second stub circuit including a second stripline formed by a second conductive layer of the PCB, the second conductive layer being different from the first conductive layer.

[0038] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like reference numerals indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0040] Figure 1 An exemplary Doherty amplifier according to an embodiment is shown in schematic form.

[0041] Figure 2 A stub circuit according to an example embodiment is shown in schematic form.

[0042] Figure 3 A portion of a Doherty amplifier module implementation including a stub circuit according to an example embodiment is shown in plan view.

[0043] Figure 4 The cross-sectional view along the section line AA is shown. Figure 3 Parts of the Doherty amplifier module. DETAILED DESCRIPTION

[0044] In the design of a 90 / 0 Doherty amplifier in which the phases from the carrier device and the peaking device to the combination / common node are 90 degrees and 0 degrees, respectively, the harmonic loading to the carrier device can be determined by the loading at the combination / common node. For a 90 / 0 Doherty amplifier, the combination / common node is the output / drain of the peaking amplifier. A peaking amplifier with a high parasitic drain-source capacitance Cds self-terminates high harmonic frequencies as a short circuit. This creates a Class F condition at the carrier device and enhances Doherty efficiency. However, for a peaking amplifier with a low Cds, such as a low peripheral gallium nitride (GaN) power transistor device, the combination node harmonic impedance will be governed by the output converter, which transforms the combination node base impedance into a 50 ohm system load. Without proper attention to the combination node harmonic loading, improper or suboptimal harmonic loading may occur, thereby reducing the power and efficiency of the Doherty amplifier to or below the optimal level.

[0045] In general, a 90 / 0 Doherty amplifier implementation is provided herein that controls second and third harmonics to achieve optimal performance, efficiency, and power. The amplifier includes a first short-circuited stub circuit and a second short-circuited stub circuit coupled in parallel at a combination / common node of the amplifier. The first stub circuit is configured to have an electrical length of approximately 90 degrees and acts as a fundamental frequency F 0 The second harmonic frequency 2*F of the disconnected circuit and ground reference voltage 0 Shunt (short circuit). Likewise, the second stub circuit is configured to have an electrical length of approximately 60 degrees. The second stub circuit acts as a third harmonic frequency 3*F of the ground reference voltage to the output of the peaking amplifier die. 0 The output of the carrier amplifier die is shunted and acts as a disconnect circuit to the Doherty amplifier. An impedance inverter absorbing Cds coupled between the output of the peaking amplifier and the output of the carrier amplifier is used to rotate F 0 , 2*F 0 and 3*F 0 Combining / common node impedance to terminate carrier amplifier harmonics.

[0046] Figure 1 A Doherty amplifier 100 is shown in schematic form according to an example embodiment. Figure 1 Some or all of the components of Doherty amplifier 100 may be implemented in a single device package or module, as indicated by dashed box 110. According to various embodiments, orienting the various amplifier components to produce an angular offset between portions of the carrier amplifier signal path and the peaking amplifier signal path (e.g., paths 130, 140) may have the beneficial effect of reducing package or module size and coupling between signals carried along the carrier path and the peaking path.

[0047] In one embodiment, the Doherty amplifier 100 includes an RF input terminal labeled IN, an RF output terminal labeled OUT, a power splitter 120, a carrier amplifier path 130, a peaking amplifier path 140, an inverting element 152, a combining node 150, a first stub circuit 154 and a second stub circuit 156, and an output transformer 158. In addition, a shunt circuit including shunt inductive elements 160, 164 and shunt capacitive elements 162, 166 is coupled to the carrier amplifier path 130 and the peaking amplifier path 140 to achieve design flexibility in the physical length and electrical length of the inverting element 152.

[0048] When incorporated into an RF system, the RF input IN is coupled to an RF signal source (not shown), and the RF output OUT is coupled to a load 170 (e.g., an antenna or other load). The RF signal source provides an input RF signal, which is an analog signal that includes spectral energy typically centered around one or more carrier frequencies. Basically, the Doherty amplifier 100 is configured to amplify the input RF signal and provide an amplified RF signal at an RF output node OUT.

[0049] In an embodiment, the power splitter 120 has an input 122 and two outputs 124, 126. The power splitter input 122 is coupled to the RF input terminal IN to receive an input RF signal. The power splitter 120 is configured to split the RF input signal received at the input 122 into a first RF signal and a second RF signal (or a carrier signal and a peaking signal), which are provided to the carrier amplifier path 130 and the peaking amplifier path 140 through the outputs 124, 126, respectively. According to an embodiment, the power splitter 120 includes a first phase shift element, which is configured to apply a first phase shift (e.g., an approximately 90 degree phase shift) to the peaking signal, which is then provided to the output 126. Therefore, at the outputs 124 and 126, the carrier signal and the peaking may be approximately 90 degrees out of phase with each other.

[0050] When the Doherty amplifier 100 has a symmetrical configuration (i.e., a configuration in which the carrier amplifier power transistor and the peaking amplifier power transistor have substantially the same size), the power splitter 120 can divide or split the input RF signal received at the input 122 into two signals having very similar powers and, in some embodiments, equal powers. Conversely, when the Doherty amplifier 100 has an asymmetrical configuration (i.e., a configuration in which one of the amplifier power transistors (typically the peaking amplifier transistor) is significantly larger), the power splitter 120 can output signals having unequal powers.

[0051] In some embodiments, the power splitter 120 can be implemented with fixed value passive components. In other embodiments, the power splitter 120 can be implemented with one or more controllable variable attenuators and / or variable phase shifters, which enable the power splitter 120 to attenuate and / or phase shift the carrier signal and the peaking signal based on an externally provided control signal.

[0052] The carrier amplifier path 130 is configured to amplify the carrier signal from the power divider 120 and provide the amplified carrier signal to the combining node 150. Similarly, the peaking amplifier path 140 is configured to amplify the peaking signal from the power splitter 120 and provide the amplified peaking signal to the combining node 150, wherein the paths 130, 140 are designed so that the amplified carrier signal and the peaking signal arrive at the combining node 150 in phase with each other.

[0053] According to an embodiment, carrier amplifier path 130 includes input circuit 138 (e.g., including an impedance matching circuit), carrier amplifier die 132, and inverter element 152. Additionally, and according to an embodiment, carrier amplifier path 130 includes a first shunt circuit coupled between an output of carrier amplifier die 132 and terminal 114 configured for coupling to a ground reference voltage.

[0054] In various embodiments, the carrier amplifier die 132 includes an RF input 134, an RF output 136, and one or more amplifier stages coupled between the input 134 and the output 136. The RF input 134 is coupled to the first output 124 of the power splitter 120 through an input circuit 138, and thus the RF input 134 receives the carrier signal generated by the power splitter 120.

[0055] Each amplifier stage of the carrier amplifier die 132 includes a power transistor. Each power transistor of the carrier amplifier die 132 may be formed as a field effect transistor (FET) on a semiconductor substrate (e.g., a metal oxide semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), a high electron mobility transistor (HEMT), etc.). Alternatively, each of the power transistors may be a bipolar junction transistor (BJT). References herein to "gate," "drain," and "source" commonly used to describe FETs are not intended to be limiting, as each of these names has similar features for BJT implementations. In one embodiment, the carrier amplifier die 132 is formed to include a gallium nitride (GaN) substrate. In other embodiments, other suitable substrate materials may be used to form the carrier amplifier die 132.

[0056] More specifically, each power transistor includes a control electrode (e.g., a gate terminal) and a first current electrode and a second current electrode (e.g., a drain terminal and a source terminal). In a single-stage device including a single power transistor, the control electrode is electrically connected to the RF input terminal 134, one of the current electrodes (e.g., the drain terminal or the source terminal) is electrically connected to the RF output terminal 136, and the other current electrode (e.g., the source terminal or the drain terminal) is electrically connected to a ground reference voltage (or another reference voltage). In a two-stage device including two power transistors coupled in series, the control electrode of the first transistor is electrically connected to the RF input terminal 134, one of the current electrodes of the first transistor (e.g., the drain terminal or the source terminal) is electrically connected to the control electrode of the second transistor, and one of the current electrodes of the second transistor (e.g., the drain terminal or the source terminal) is electrically connected to the RF output terminal 136.

[0057] In addition to the power transistors, portions of the input and output impedance matching networks and bias circuits (not shown) may also be integrally formed as part of and / or electrically coupled to the carrier amplifier die 132. Additionally, in embodiments in which the carrier amplifier die 132 is a two-stage device, an inter-stage matching network (not shown) may also be integrally formed as part of the carrier amplifier die 132.

[0058] The RF output 136 of the carrier amplifier die 132 is coupled to a first shunt circuit. The first shunt circuit includes a shunt inductive element 160 (e.g., an inductor) coupled in series with a shunt capacitive element 162 (e.g., a DC blocking capacitor). More specifically, the capacitance of the shunt capacitor 162 is selected to provide a virtual ground reference voltage for the RF electrical signal at the terminal 112, so that the inductor 160 acts as a shunt inductor for the RF ground voltage. In some embodiments, the terminal 112 may be coupled to a bias circuit to provide a DC drain bias voltage to the drain of the carrier amplifier die 132. The series combination of the inductor 160 and the capacitor 162 is configured to at least partially resonate out the effect of the parasitic drain-source capacitance Cds of the transistors of the carrier amplifier die 132. This enables the physical and electrical length of the inverter element 152 to be longer than required to fully absorb all phases introduced by the transistor drain capacitance.

[0059] In one embodiment, the RF output 136 (e.g., drain terminal) of the carrier amplifier die 132 is coupled to the combining node 150 at the output 146 of the peaking amplifier die 142 by means of an inverting element 152. According to an embodiment, the inverting element 152 acts as a transmission line phase shift element (e.g., an impedance inverter) that applies a 90 degree phase shift relative to the carrier signal after amplification by the carrier amplifier die 132. A first end of the inverting element 152 is coupled to the RF output 136 of the carrier amplifier die 132, and a second end of the inverting element 152 is coupled to the combining node 150. In one embodiment, the inverting element 152 is formed as a microstrip transmission line having a signal conductor formed on a dielectric layer above a ground plane. In other embodiments, the inverting element 152 may be formed as a stripline transmission line having a signal conductor formed between an overlying ground plane and an underlying ground plane.

[0060] Reference is now made to the peaking amplifier path 140, which in one embodiment includes a peaking amplifier die 142 and an input circuit 148 (e.g., including an impedance matching circuit). Additionally and in accordance with an embodiment, the peaking amplifier path 140 includes a second shunt circuit coupled between the output of the peaking amplifier die 142 and a terminal 118 configured for coupling to a ground reference voltage.

[0061] In various embodiments, the peaking amplifier die 142 includes an RF input terminal 144, an RF output terminal 146, and one or more amplifier stages coupled between the input terminal 144 and the output terminal 146. The RF input terminal 144 is coupled to the second output 126 of the power splitter 120, and thus the RF input terminal 144 receives the peaking signal generated by the power splitter 120.

[0062] As with carrier amplifier die 132, each amplifier stage of peaking amplifier die 142 includes a power transistor having a control electrode and first and second current electrodes. The power transistors of peaking amplifier die 142 may be electrically coupled between RF input 144 and RF output 146 in a manner similar to that described above in conjunction with the description of carrier amplifier die 132. Additional other details discussed in conjunction with the description of carrier amplifier die 132 also apply to peaking amplifier die 142, and such additional details are not repeated here for the sake of brevity.

[0063] The RF output 146 (e.g., drain terminal) of the peaking amplifier die 142 is coupled to a combining node 150. According to an embodiment, the RF output 146 of the peaking amplifier die 142 and the combining node 150 are implemented with a common element. More specifically, in an embodiment, the RF output 146 of the peaking amplifier die 142 is configured to serve as the combining node 150 and as the output 146 of the peaking amplifier die 142. The RF output 146 is additionally configured to enable a connection between a second end of the phase shift and inverting element 152 and the peaking amplifier die 142 (e.g., by means of a wire bonding array). Likewise, first ends of the first stub circuit 154 and the second stub circuit 156 are coupled at the combining node 150 (e.g., by means of a wire bonding array).

[0064] The RF output terminal 146 of the peaking amplifier die 142 is coupled to a second shunt circuit. Similar to the first shunt circuit, the second shunt circuit also includes a shunt inductive element 164 (e.g., an inductor) coupled in series with a shunt capacitive element 166 (e.g., a DC blocking capacitor). In addition, the capacitance of the shunt capacitor 166 is selected to provide a virtual ground reference voltage for the RF electrical signal at the terminal 116, so that the inductor 164 acts as a shunt inductor to the RF ground voltage. In some embodiments, the terminal 116 can be coupled to a bias circuit for providing a DC bias voltage to the drain of the peaking amplifier die 142.

[0065] Again, the series combination of inductor 164 and capacitor 166 is configured to at least partially resonate out the effects of the parasitic drain-source capacitance Cds of the transistors of the peaking amplifier die 142. As with the shunt inductor 142 coupled to the carrier amplifier path 130, the shunt inductor 164 coupled to the peaking amplifier path 140 also enables the physical and electrical length of the phase shift and inverter element 152 to be longer than necessary to fully absorb all phases introduced by the transistor drain capacitance.

[0066] Although in one embodiment, the first shunt circuit and the second shunt circuit may be included in the amplifier 100, in other embodiments, either of the shunt circuits may be excluded from the amplifier 100. For example, one alternative embodiment of the amplifier 100 may include the first shunt circuit and may exclude the second shunt circuit, while another alternative embodiment of the amplifier 100 may include the second shunt circuit and may exclude the first shunt circuit.

[0067] Reference is now made to the output transformer 158. The amplified carrier and peak RF signals are combined in phase at the combining node 150. The combining node 150 is electrically coupled to the RF output terminal OUT to provide the amplified and combined RF output signal to the RF output terminal OUT. The output transformer 158 is coupled between the combining node 150 and the RF output terminal OUT and is used to present the appropriate load impedance to each of the peaking amplifier dies 132, 142 and the carrier. In one embodiment, the output transformer 158 is an output impedance matching network that transforms the combining node 150 base impedance to a 50 ohm system load. The resulting amplified RF output signal is produced at the RF output terminal OUT to which the output load 170 (e.g., an antenna) is connected.

[0068] Reference is now made to the first stub circuit 154 and the second stub circuit 156. The first stub circuit 154 and the second stub circuit 156 are coupled at the combining node 150 of the amplifier 100. A first end of the first stub circuit 154 is coupled at the combining node 150, and a second end of the first stub circuit 154 is coupled at a ground reference voltage supply terminal. Similarly, a first end of the second stub circuit 156 is coupled at the combining node 150, and a second end of the second stub circuit 156 is coupled at the ground reference voltage supply terminal. According to an embodiment, the first stub circuit 154 may be characterized as a 90 degree short circuit stub (e.g., configured to have an electrical length of approximately 90 degrees), and the second stub circuit 156 may be characterized as a 60 degree short circuit stub (e.g., configured to have an electrical length of approximately 60 degrees). The 90 degree short circuit stub 154 acts as a fundamental frequency F 0 The 2*F resistor at the open circuit at the top and acts as a ground reference voltage supply terminal to the outputs of both the peaking amplifier die 142 and the carrier amplifier die 132. 0 Harmonic frequency shunting. The 60 degree short circuit stub 156 acts as a 3*F ground reference voltage supply to the output of the peaking amplifier die 142. 0 The harmonic frequencies are shunted and act as an open circuit to the output of the carrier amplifier die 132 .

[0069] Although in one embodiment, the first stub circuit 154 and the second stub circuit 156 may be included in the amplifier 100, in other embodiments, any of the stub circuits may be excluded from the amplifier 100. For example, one alternative embodiment of the amplifier 100 may include the first stub circuit 154 and may exclude the second stub circuit 156, while another alternative embodiment of the amplifier 100 may include the second stub circuit 156 and may exclude the first stub circuit 154. Figure 2 The first stub circuit 154 and the second stub circuit 156 are explained in more detail.

[0070] The amplifier 100 is configured such that the carrier amplifier path 130 provides amplification of active relatively low level input signals, and both amplifier paths 130, 140 operate in combination to provide amplification for relatively high level input signals. This can be accomplished, for example, by applying a bias on the carrier amplifier die 132 so that the carrier amplifier die 132 operates in class AB mode and applying a bias on the peaking amplifier die 142 so that the peaking amplifier die 142 operates in class C mode.

[0071] According to an embodiment, the physical components of the carrier path 130 and the peaking path 140 are oriented relative to each other so that corresponding portions of the carrier amplifier path 130 and the peaking amplifier path 140 extend in directions that are significantly different from each other. As used herein, the term "signal path" refers to a path followed by an RF signal through a circuit. For example, a portion of a first signal path through the carrier amplifier die 132 extends in a first direction (indicated by arrow 130) between the RF input terminal 134 and the RF output terminal 136. Similarly, a portion of a second signal path through the peaking amplifier die 142 extends in a second direction (indicated by arrow 140) between the RF input terminal 144 and the RF output terminal 146, wherein the first direction and the second direction are significantly different from each other. In the illustrated embodiment, the first direction and the second direction are perpendicular to each other (i.e., angularly separated by 90 degrees). In other embodiments, the first direction and the second direction may be angularly separated by less than or more than 90 degrees. As used herein, when referring to the angular separation between the directions of corresponding portions of a first signal path and a second signal path, the term "substantially different" means that the angular separation between the path portions is at least + / - 45 degrees.

[0072] Figure 2A more detailed description of the stub circuits 154, 156 according to an example embodiment is shown in schematic form. The first stub circuit 154 and the second stub circuit 156 are coupled between the combination node 150 and the ground reference voltage supply terminal. The first stub circuit 154 includes a transmission line element (e.g., a stripline) 202, a capacitive element 206 (e.g., a DC blocking capacitor), and an inductive element 208 (e.g., an inductor). The first end of the transmission line element 202 is coupled to the combination node 150, and the second end of the transmission line element 202 is coupled to the first end of the capacitor 206. The second end of the capacitor 206 is coupled to the first end of the inductor 208 and the second end of the inductor 208 is coupled to the ground reference voltage supply terminal. Although in one embodiment, the transmission line element 202, the capacitor 206, and the inductor 208 may be included in the first stub circuit 154, in other embodiments, the inductor 208 may be excluded from the first stub circuit 154. For example, an alternative embodiment of the first stub circuit 154 may include the transmission line element 202 and the capacitor 206 and may exclude the inductor 208. In one embodiment, the transmission line element 202 is formed as a stripline transmission line having a signal conductor formed between an overlying ground plane and an underlying ground plane. In other embodiments, the transmission line element 202 may be formed as a microstrip transmission line having a signal conductor formed on a dielectric layer above the ground plane.

[0073] According to various embodiments, capacitor 206 is selected to be a relatively high-Q surface mount capacitor, such as a metal-insulator-metal (MIM) capacitor, a capacitor integrated into an integrated passive device (IPD), a capacitor integrated into a low-temperature co-fired ceramic (LTCC) device, or another type of surface mount capacitor with a relatively high Q. Inductor 208 can be formed with capacitor 206 in surface mount structure 204, such as mentioned above. Alternatively, inductor 208 can be implemented as an inductive element separate from surface mount structure 204.

[0074] The second stub circuit 156 includes a transmission line element (e.g., a stripline) 212, a capacitive element 216 (e.g., a DC blocking capacitor), and an inductive element 218 (e.g., an inductor). A first end of the transmission line element 212 is coupled to the combining node 150, and a second end of the transmission line element 212 is coupled to a first end of the capacitor 216. A second end of the capacitor 216 is coupled to a first end of the inductor 218, and a second end of the inductor 218 is coupled to a ground reference voltage supply. Although in one embodiment, the transmission line element 212, the capacitor 216, and the inductor 218 may be included in the second stub circuit 156, in other embodiments, the inductor 218 may be excluded from the second stub circuit 156 as described for the stub circuit 154. In one embodiment, the transmission line element 212 is formed as a stripline transmission line having a signal conductor formed between an overlying ground plane and an underlying ground plane. In other embodiments, the transmission line element 212 may be formed as a microstrip transmission line having a signal conductor formed on a dielectric layer above a ground plane.

[0075] As with the stub circuit 154, the capacitor 216 is selected to be a relatively high Q surface mount capacitor, such as a MIM capacitor, a capacitor integrated within an IPD, a capacitor integrated within an LTCC device, or another type of surface mount capacitor. The inductor 218 may be formed with the capacitor 216 in the surface mount structure 214, such as mentioned above. Alternatively, the inductor 218 may be implemented as an inductive element separate from the surface mount structure 214.

[0076] According to an embodiment, the first stub circuit 154 may be characterized as a 90 degree short circuit stub. The dimensions of the transmission line element 202 (e.g., stripline length, width, thickness), the capacitance value of the capacitor 206, and the inductance value of the inductor 208 are selected so that the first stub circuit 154 has an electrical length of approximately 90 degrees and acts as a fundamental frequency F 0 The second harmonic frequency 2*F of the disconnected circuit and ground reference voltage 0 Similarly, the second stub circuit 156 may be characterized as a 60 degree short circuit stub. The dimensions (e.g., stripline length, width, thickness) of the transmission line element 212, the capacitance value of the capacitor 216, and the inductance value of the inductor 218 are selected so that the second stub circuit 156 has an electrical length of approximately 60 degrees and acts as the third harmonic frequency 3*F of the ground reference voltage to the output of the peaking amplifier die 142. 0shunted and act as a disconnect circuit to the output of carrier amplifier die 132. In one embodiment, capacitors 206 and 216 may each have a capacitance value in the range of 5.0 pF to 15.0 pF, and inductors 208 and 218 may each have an inductance value in the range of 0.8 nH to 2.4 nH. In other embodiments, capacitors 206 and 216 may have a capacitance value less than 5.0 pF or greater than 15.0 pF, and inductors 208 and 218 may have an inductance value less than 0.8 nH or greater than 2.4 nH.

[0077] Figure 3 and Figure 4 An example of a physical implementation of a Doherty amplifier 100 is shown in plan view and corresponding cross-sectional views. Figure 3 A Doherty amplifier module portion 300 according to an example embodiment is shown in plan view. Figure 3 and Figure 4 , Figure 4 The cross-sectional view along the section line AA is shown. Figure 3 The Doherty amplifier module portion 300 includes a substrate 310, a carrier amplifier die 332 (eg, Figure 1 carrier amplifier die 132), peaking amplifier die 342 (eg, Figure 1 The peaking amplifier die 142 of the embodiment of the present invention is provided, and the microstrip impedance inverter 352 (for example, Figure 1 The inverter element 152 of the peaking amplifier die 342 is coupled to the first stripline 302 (eg, the common node) of the first stub circuit at the output of the peaking amplifier die 342. Figure 2 The transmission line element 202 of the short stub circuit 154 of the combination node), the second stripline 312 of the second short stub circuit coupled to the combination node (eg, Figure 2 The transmission line element 212 of the short line circuit 156, as well as other module features.

[0078] According to an embodiment, substrate 310 is a multi-layer organic substrate formed of a printed circuit board (PCB) material having a plurality of conductive layers (e.g., metal) 402-414 separated by dielectric materials (e.g., Teflon FR-4). Substrate 310 includes a top mounting surface 320 and a bottom surface 422 for mounting components of a Doherty amplifier. Patterned conductive (e.g., metal) layer 402 is formed at mounting surface 320 to facilitate electrical connection to dies (e.g., carrier amplifier die 332, peaking amplifier die 342) and other components that may be mounted to mounting surface 320. Conductive layer 414 is formed over bottom surface 422 to facilitate, for example, ground reference access to carrier amplifier die 332 and peaking amplifier die 342 and ground plane portions of conductive layers 404, 408, 412. Conductive die attach pads (e.g., pads 418) for electrically coupling carrier amplifier die 332 and peaking amplifier die 342 to mounting surface 320 are formed from a portion of patterned top metal layer 402. In one embodiment, microstrip 352 is formed as a signal line from a portion of patterned metal layer 402 above a ground plane portion of conductive layer 404. The signal line portion is separated from the ground plane portion by a dielectric material. In other embodiments, microstrip 352 may be formed as a stripline on other conductive layers (e.g., layers 404-412) of substrate 310. Conductive vias (e.g., vias 416) are provided for electrical connections between metal layers 402-414.

[0079] In an embodiment, substrate 310 also includes a plurality of electrically conductive and thermally conductive trenches 420 to which carrier amplifier die 332 and peaking amplifier die 342 are coupled (e.g., by solder, brazing material, silver sinter, or other die attach material). Trenches 420 extend through the thickness of the substrate to provide heat sinking and ground reference access to carrier amplifier die 332 and peaking amplifier die 342 (e.g., by means of conductive layer 414). For example, conductive trenches 420 may be filled with copper or another thermally and electrically conductive material. In alternative embodiments, trenches 420 may be replaced with conductive slugs (e.g., copper slugs) or replaced with thermal vias.

[0080] According to an embodiment, the RF output 336 (e.g., drain) of the carrier amplifier die 332 is coupled to the first end of the microstrip 352 by means of the first wire bond array 322. The carrier amplifier die 332 produces an amplified RF carrier signal at the RF output 336. Thus, the signal path through the carrier amplifier die 332 is in a direction extending from the RF input (not shown) toward the RF output 336, which direction is indicated by arrow 330. Similarly, the RF output 346 (e.g., drain) of the peaking amplifier die 342 is coupled to the first end of the microstrip 352 by means of the second wire bond array 324 (e.g., Figure 4 340 ). The peaking amplifier die 342 is coupled to the second end of the microstrip 352 by wire bonds 424. The peaking amplifier die 342 produces an amplified RF peaking signal at an RF output 346. The signal path through the peaking amplifier die 342 is in a direction extending from an RF input (not shown) toward the RF output 346, which direction is indicated by arrow 340. The carrier amplifier die 332 and the peaking amplifier die 342 are oriented relative to each other such that corresponding portions of the carrier signal path 330 and the peaking signal path 340 extend in directions that are significantly different from each other. The RF output 346 acts as a combining node 350 (e.g., Figure 1 The amplified peaking signal is combined in phase with the delayed carrier amplifier signal at the combining node 350 .

[0081] The first stub circuit (eg, Figure 2 The stub circuit 154 includes a first stripline 302 (eg, Figure 2 4. The stripline 302 is formed on a first inner conductive layer (e.g., metal layer 410). The stripline 302 is formed as a stripline transmission line having a signal conductor portion formed on the conductive layer 410 between an overlying ground plane portion of the conductive layer 408 and an underlying ground plane portion of the conductive layer 412. A dielectric material is disposed between the signal conductor portion and the ground plane portion. A first end of the stripline 302 is coupled to the combination node 350 by means of a via 360, and a second end of the stripline 302 is coupled to a first end of the first chip capacitor 304 at a first surface bonding pad 308. The first surface bonding pad 308 may be coupled to the second end of the stripline 302 by means of another via. A second end of the first chip capacitor 304 is coupled to a ground reference voltage supply at the second surface bonding pad 308. In one embodiment, the chip capacitor 304 may include a capacitive element (eg, Figure 2 206) and inductive elements (e.g., Figure 2 208), but in other embodiments, the inductive element may be excluded from the chip capacitor 304. For example, an alternative embodiment of the chip capacitor 304 may include a capacitive element (e.g., Figure 2 206) and can be used without inductive components (e.g., Figure 2 In one embodiment, at least a portion of the microstrip 352 overlaps with at least a portion of the first stripline 302.

[0082] According to various embodiments, the capacitive element (eg, Figure 2206) is selected to be a relatively high Q surface mount capacitor, such as a MIM capacitor, a capacitor integrated into an IPD, a capacitor integrated into an LTCC device, or another type of surface mount capacitor with a relatively high Q. The inductive element of the chip capacitor 304 (e.g., Figure 2 The inductor element 208 may be formed together with the capacitive element in the chip capacitor 304. Alternatively, the inductor element may be implemented separately from the chip capacitor 304.

[0083] The second stub circuit (eg, Figure 2 The stub circuit 156 includes a second stripline 312 (eg, Figure 2 The stripline 312 is a transmission line element 212 of the short line circuit 156 of the conductive layer 404) and a second chip capacitor 314 (for example, a chip capacitor 214 including a capacitive element 216 and an inductive element 218). According to an embodiment, the second stripline 312 is formed on a second inner conductive layer (for example, the metal layer 406) that is different from the first inner conductive layer. The stripline 312 is formed as a stripline transmission line having a signal conductor portion formed on the conductive layer 406 between an overlying ground plane portion of the conductive layer 404 and an underlying ground plane portion of the conductive layer 408. A dielectric material is disposed between the signal conductor portion and the ground plane portion. A first end of the stripline 312 is coupled at the combination node 350 by means of a via 360, and a second end of the stripline 312 is coupled to a first end of the second chip capacitor 314 at a first surface bonding pad 318. The second surface bonding pad 318 can be coupled to the second end of the stripline 312 by means of another via. The second end of the second chip capacitor 314 is coupled to the ground reference voltage supply at the second surface bonding pad 318. Although in one embodiment, the chip capacitor 314 may include a capacitive element (e.g., Figure 2 216) and inductive elements (e.g., Figure 2 218), but in other embodiments, the inductive element may be excluded from the chip capacitor 314. For example, an alternative embodiment of the chip capacitor 314 may include a capacitive element (e.g., Figure 2 216) and can be used without inductive components (e.g., Figure 2 In one embodiment, at least a portion of the microstrip 352 overlaps with at least a portion of the second stripline 312. In one embodiment, at least a portion of the microstrip 352 overlaps with at least a portion of the first stripline 302 and at least a portion of the second stripline 312.

[0084] As with the chip capacitor 304, the capacitive element (eg, Figure 2216) is selected to be a relatively high Q surface mount capacitor, such as a MIM capacitor, a capacitor integrated into an IPD, a capacitor integrated into an LTCC device, or another type of surface mount capacitor. The inductive element of the chip capacitor 314 (e.g., Figure 2 The inductor element 218 may be formed together with the capacitive element in the chip capacitor 314. Alternatively, the inductor element may be implemented separately from the chip capacitor 314.

[0085] According to an embodiment, the first stub circuit (eg, Figure 2 The stub circuit 154 of the transmission line element 302 may be characterized as a 90-degree short circuit stub. The dimensions (e.g., length, width, thickness) of the transmission line element 302 and the capacitance and inductance values ​​of the chip capacitor 304 are selected so that the first stub circuit has an electrical length of approximately 90 degrees and acts as a fundamental frequency F 0 The second harmonic frequency 2*F of the disconnected circuit and ground reference voltage 0 Similarly, the second stub circuit (eg, Figure 2 The second stub circuit 156 may be characterized as a 60 degree short circuit stub. The dimensions (e.g., length, width, thickness) of the transmission line 312 and the capacitance and inductance values ​​of the chip capacitor 314 are selected so that the second stub circuit has an electrical length of approximately 60 degrees and acts as the third harmonic frequency 3*F of the ground reference voltage to the output of the peaking amplifier die 342. 0 The shunt acts as a disconnect circuit to the output of the carrier amplifier die 332 .

[0086] Generally speaking, an amplifier module is provided, which includes a multilayer printed circuit board (PCB); a first power transistor die mounted at the top surface of the multilayer PCB; a second power transistor die mounted at the top surface of the multilayer PCB; an impedance inversion element coupled between the output of the first power transistor die and the output of the second power transistor die, forming a combination node at the output of the second power transistor die; and a first short-line circuit coupled at the combination node, the first short-line circuit including a first transmission line element having a first end coupled to the combination node. The first transmission line element may be formed as a first stripline formed by a first inner conductive layer of the multilayer PCB. The impedance inversion element may include a microstrip formed by the top conductive layer of the multilayer PCB, at least a portion of the microstrip overlapping at least a portion of the first stripline. The first short-line circuit may be configured to act as a fundamental frequency (F 0 ) and acts as a second harmonic frequency (2*F 0) at a ground reference voltage under . The first short line circuit may further include a first capacitor, a first end of the first capacitor coupled to a second end of the first stripline. The first capacitor may include a surface mount capacitor mounted at the top surface of the multilayer PCB. The surface mount capacitor may include a metal-insulator-metal (MIM) capacitor. The first short line circuit may further include an inductor coupled to the MIM capacitor. The module may further include a second short line circuit coupled in parallel with the first short line circuit at the combination node, the second short line circuit including a second stripline, the second stripline being formed by an inner conductive layer of the multilayer PCB that is different from the inner conductive layer of the first stripline formed. The second short line circuit may be configured to generate a third harmonic frequency (3*F 0 ) acts as a ground reference voltage shunt at the output of the second power transistor die and acts as a disconnect circuit at the output of the first power transistor die. The first power transistor die can be configured to operate in a class AB mode and the second power transistor die can be configured to operate in a class C mode.

[0087] In another embodiment, an amplifier module is provided, which includes a multilayer printed circuit board (PCB); a first power transistor die mounted at a top surface of the multilayer PCB, the first power transistor die being configured as a carrier amplifier; a second power transistor die mounted at a top surface of the multilayer PCB, the second power transistor die being configured as a peaking amplifier; an impedance inversion element coupled between an output of the first power transistor die and an output of the second power transistor die, forming a combination node at the output of the second power transistor die; and a first stub circuit coupled at the combination node, the first stub circuit including a first stripline having a first end coupled at the combination node. The second power transistor die may be oriented in a different direction than the first power transistor die. The module may further include a second stub circuit coupled at the combination node in parallel with the first stub circuit, the second stub circuit including a second stripline having a first end coupled at the combination node. The first stripline may be formed by a first inner conductive layer of the multilayer PCB and the second stripline may be formed by a second inner conductive layer of the multilayer PCB. The impedance inversion element may include a microstrip formed by a top conductive layer of the multilayer PCB, at least a portion of the microstrip overlapping at least a portion of the first stripline and at least a portion of the second stripline. The first stub circuit may be configured to have an electrical length of approximately 90 degrees and the second stub circuit may be configured to have an electrical length of approximately 60 degrees.

[0088] In yet another embodiment, a Doherty amplifier is provided, comprising a multi-layer printed circuit board (PCB); a carrier amplifier die mounted at a top surface of the multi-layer PCB; a peaking amplifier die mounted at a top surface of the multi-layer PCB; an impedance inversion element coupled between a drain terminal of the carrier amplifier die and a drain terminal of the peaking amplifier die to form a combined node at the drain terminal of the peaking amplifier die; and a first stub circuit coupled at the combined node, the first stub circuit comprising a first stripline formed by a first conductive layer of the PCB. The first stub circuit may be configured to act as a fundamental frequency (F 0 ) and acts as a second harmonic frequency (2*F 0 ) The amplifier may further include a second stub circuit coupled in parallel with the first stub circuit at the combining node, the second stub circuit comprising a second stripline formed by a second conductive layer of the PCB, the second conductive layer being different from the first conductive layer.

[0089] It should now be appreciated that a 90 / 0 Doherty amplifier implementation is provided herein that controls the second and third harmonics to achieve optimal performance, efficiency, and power. The amplifier includes a first short-circuited stub circuit and a second short-circuited stub circuit coupled in parallel at a combined / common node of the amplifier. The first stub circuit is configured to have an electrical length of approximately 90 degrees and acts as a fundamental frequency F 0 The second harmonic frequency 2*F of the disconnected circuit and ground reference voltage 0 Shunt (short circuit). Likewise, the second stub circuit is configured to have an electrical length of approximately 60 degrees. The second stub circuit acts as a third harmonic frequency 3*F of the ground reference voltage to the output of the peaking amplifier die. 0 The output of the carrier amplifier die is shunted and acts as a disconnect circuit to the Doherty amplifier. An impedance inverter absorbing Cds coupled between the output of the peaking amplifier and the output of the carrier amplifier is used to rotate F 0 , 2*F 0 and 3*F 0 Combining / common node impedance to terminate carrier amplifier harmonics.

[0090] Since the apparatus implementing the present invention is largely composed of electronic components and circuits known to those skilled in the art, in order to understand and appreciate the basic concepts of the present invention and in order not to confuse or deviate from the teachings of the present invention, the circuit details will not be explained to any greater extent than is deemed necessary as shown above.

[0091] Although the present invention has been described with respect to a particular conductivity type or polarity of potential, one skilled in the art will appreciate that the conductivity type or polarity of potential may be reversed.

[0092] Furthermore, the terms "front", "back", "top", "bottom", "above", "below", etc., if any, in the specification and claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

[0093] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive, and all such modifications are expected to be included within the scope of the present invention. It is not intended that any advantage, advantage, or solution to a problem described herein with respect to a specific embodiment be construed as a key, essential, or requisite feature or element of any or all claims.

[0094] Furthermore, as used herein, the terms "a" and "an" are defined as one or more than one. In addition, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "an". The same is true for the use of definite articles.

[0095] Unless otherwise stated, terms such as "first" and "second," etc., are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal priority or other priority of such elements.

Claims

1. An amplifier module, characterized in that: include: Multilayer printed circuit board (PCB); a first power transistor die mounted at a top surface of the multi-layer PCB, the first power transistor die being configured as a carrier amplifier; a second power transistor die mounted at the top surface of the multi-layer PCB, the second power transistor die being configured as a peaking amplifier; an impedance inversion element coupled between an output of the first power transistor die and an output of the second power transistor die, forming a combination node at the output of the second power transistor die, the combination node being coupled to the output of the second power transistor die; a first stub circuit coupled to the combining node, the first stub circuit comprising a first stripline having a first end coupled to the combining node at the output of the second power transistor die, the first stripline formed by a first inner conductive layer of the multilayer PCB; a second stub circuit coupled in parallel with the first stub circuit at the combining node, the second stub circuit comprising a second stripline formed by an inner conductive layer of the multilayer PCB different from a first inner conductive layer forming the first stripline having a first end coupled to the combining node at the output of the second power transistor die, wherein the first stub circuit is a 90 degree short circuit stub and is configured to act as a disconnect circuit at a fundamental frequency F0 and act as a shunt from a ground reference voltage supply terminal at a second harmonic frequency 2*F0 to outputs of both the second power transistor die and the first power transistor die; and The second stub circuit is a 60 degree short circuit stub and is configured to act as a shunt from the ground reference voltage supply terminal at the output of the second power transistor die to the output of the second power transistor die at a third harmonic frequency 3*F0 and to act as a disconnect circuit at the output of the first power transistor die; and wherein the first stub circuit further comprises a first capacitor, a first end of the first capacitor being coupled to a second end of the first stripline; and The second stub circuit further includes a second capacitor having a first end coupled to a second end of the second stripline.

2. The module according to claim 1, characterized in that The impedance inversion element includes a microstrip formed by a top conductive layer of the multi-layer PCB, at least a portion of the microstrip overlapping at least a portion of the first stripline.

3. The module according to claim 1, characterized in that The first capacitor comprises a surface mount capacitor mounted at the top surface of the multi-layer PCB.

4. The module according to claim 1, characterized in that The first power transistor die is configured to operate in a class AB mode and the second power transistor die is configured to operate in a class C mode.

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