Gct chip structure and method of manufacturing

Abstract

The application discloses a GCT chip structure and a preparation method thereof. The GCT chip structure comprises a P+ emitter for leading out an anode, an n+ buffer layer attached to the P+ emitter, and an n drift region attached to the n+ buffer layer. The GCT chip structure further comprises a first P+ region, a second P+ region and an n+ emitter. The first P+ region is attached to the n drift region. The second P+ region is attached to the first P+ region. The n+ emitter is connected to the second P+ region. The n+ emitter leads out a cathode. The second P+ region leads out a gate. The cathode and the gate have a height difference. The height difference ranges from 0 to 10 micrometers.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power semiconductor devices, in particular, it relates to a GCT chip structure and a preparation method. BACKGROUND

[0002] The IGCT device is a new generation of current-controlled device developed on the basis of GTO. From the chip level, the GCT chip adopts transparent anode technology and buffer layer design, which reduces the trigger current level and on-state voltage drop of the device. From the gate drive circuit and turn-on and turn-off mechanism, the IGCT adopts an integrated drive circuit, which reduces the stray parameters of the commutation loop to the nanohen level through optimization of the circuit layout and tube shell packaging structure, so that the current can be fully transferred from the cathode to the gate in a very short time during the turn-off process of the device, and then the PNP transistor is naturally turned off.

[0003] REFERENCE Figure 1 , Figure 1 is a schematic diagram of the existing GCT chip structure. As shown in Figure 1 , there is a longitudinal spacing between the gate and the cathode, that is, there is a groove structure on the cathode side surface. In order to ensure the process feasibility, the lateral dimension h is difficult to be further shortened during unit design, but the lateral dimension directly determines the gate resistance in the GCT unit, which further affects the maximum turn-off current capacity.

[0004] Therefore, it is urgent to develop a GCT chip and a preparation method which overcome the above-mentioned defects. SUMMARY

[0005] In view of the above problems, the present application provides a GCT chip structure, which comprises a P+ emitter leading out an anode, an n+ buffer layer attached to the P+ emitter, and an n drift region attached to the n+ buffer layer, wherein the GCT chip structure further comprises:

[0006] a first P+ region attached to the n drift region;

[0007] a second P+ region attached to the first P+ region; and

[0008] an n+ emitter connected to the second P+ region, the n+ emitter leading out a cathode, the second P+ region leading out a gate, the cathode and the gate having a height difference, and the height difference being in the range of 0-10 μm.

[0009] The above-mentioned GCT chip further comprises a p base region attached to the n drift region and located between the first P+ region and the n drift region, and the first P+ region is attached to the p base region.

[0010] The GCT chip as claimed in the above, wherein the second P+ region has the same thickness as the n+ emitter.

[0011] The GCT chip as claimed in the above, wherein the first P+ region and the n drift region have a wave shape at the junction.

[0012] The GCT chip as claimed in the above, wherein the cathode and the gate are in the same plane.

[0013] The GCT chip as claimed in the above, wherein the wave shape structure has a middle plane protruding to the first P+ region by a height less than 40 μm.

[0014] The GCT chip as claimed in the above, wherein the second P+ region has a thickness of 1-30 μm.

[0015] The present application also provides a method for preparing a GCT chip, comprising:

[0016] Step S11: forming a first P+ region and a p base region on the cathode surface of the n- substrate by ion implantation and post-diffusion or deposition diffusion;

[0017] Step S12: forming an n+ buffer layer on the anode surface of the n- substrate by ion implantation and post-diffusion or deposition diffusion;

[0018] Step S13: growing a second P+ region on the first P+ region by a silicon epitaxy method;

[0019] Step S14: forming an n-type doped region on the second P+ region by selective ion implantation or selective deposition, and advancing by thermal diffusion to form an n+ emitter.

[0020] Step S15: forming a p+ emitter on the n+ buffer layer by ion implantation and post-diffusion or deposition diffusion;

[0021] Step S16: forming two-side metal electrode contact and patterning, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

[0022] The present application also provides a method for preparing a GCT chip, comprising:

[0023] Step S21: forming a first P+ region and a p base region on the cathode surface of the n- substrate by ion implantation and post-diffusion or deposition diffusion;

[0024] Step S22: forming an n+ buffer layer on the anode surface of the n- substrate by ion implantation and post-diffusion or deposition diffusion;

[0025] Step S23: using P-substrate or SOI wafer, connecting P-substrate or SOI wafer with cathode surface of n-substrate which has completed multi-step diffusion process through silicon-silicon bonding, and obtaining second P+ region after thinning;

[0026] Step S24: forming n-type doped region in second P+ region by selective ion implantation or selective deposition, and promoting by thermal diffusion to form n+ emitter;

[0027] Step S25: forming p+ emitter on n+ buffer layer by ion implantation and post-diffusion or deposition diffusion;

[0028] Step S26: forming two-side metal electrode contact and patterning, wherein the metal electrode on cathode surface is higher than that on gate surface.

[0029] The application also provides a preparation method of GCT chip, wherein the method comprises:

[0030] Step S31: forming second P+ region, first P+ region and p-base region on cathode surface of n-substrate by ion implantation and post-diffusion or deposition diffusion;

[0031] Step S32: forming n+ buffer layer on anode surface of n-substrate by ion implantation and post-diffusion or deposition diffusion;

[0032] Step S33: forming n-type doped region in second P+ region by selective ion implantation or selective deposition, and promoting by thermal diffusion to form n+ emitter;

[0033] Step S34: forming p+ emitter on n+ buffer layer by ion implantation and post-diffusion or deposition diffusion;

[0034] Step S35: forming two-side metal electrode contact and patterning, wherein the metal electrode on cathode surface is higher than that on gate surface.

[0035] The application aims at the prior art and has the following advantages:

[0036] 1. Compared with the prior GCT chip structure, the application has similar gate-cathode breakdown voltage.

[0037] 2. Compared with the prior GCT chip structure, the application increases the design space of lateral dimension by designing the height difference between cathode and gate.

[0038] 3. Compared with the prior GCT chip structure, the application has stronger current turn-off ability under the same process uniformity.

[0039] Additional features and advantages of the application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0041] Figure 1 It is a schematic diagram of the existing GCT chip structure;

[0042] Figure 2 It is a schematic diagram of the GCT chip and its doping structure of the present application;

[0043] Figure 3 It is a schematic diagram of the second embodiment of the GCT chip of the present application;

[0044] Figure 4 It is a process path diagram of the existing GCT chip structure;

[0045] Figure 5 It is a flow chart of the first embodiment of the preparation method of the present application;

[0046] Figure 6 It is a process path diagram of Figure 5

[0047] Figure 7 It is a flow chart of the second embodiment of the preparation method of the present application;

[0048] Figure 8 It is a process path diagram of Figure 7

[0049] Figure 8a It is a process path diagram of using SOI wafer;

[0050] Figure 9 It is a flow chart of the third embodiment of the preparation method of the present application;

[0051] Figure 10 It is a process path diagram of Figure 9

[0052] In which, the reference signs are:

[0053] Height difference: d

[0054] Lateral dimension: h​​​

[0055] First P+ area: P1

[0056] Second P+ region: P2

[0057] Wave shape: W Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] The directional terms used in this article, such as up, down, left, right, front, or back, are for reference only when referring to the accompanying drawings. Therefore, the use of directional terms is for illustrative purposes and not to limit this work.

[0060] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0061] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0062] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the GCT chip and its doped structure according to the present invention. Figure 2 As shown, the GCT chip structure of the present invention includes: a P+ emitter with an anode, an n+ buffer layer attached to the P+ emitter, an n-drift region attached to the n+ buffer layer, a first P+ region P1 attached to the n-drift region, a second P+ region P2 attached to the first P+ region P1, and an n+ emitter connected to the second P+ region P2, wherein the n+ emitter leads to a cathode, and the second P+ region P2 leads to a gate. The cathode and the gate have a height difference d, which ranges from 0 to 10 μm.

[0063] It is worth noting that in this embodiment, the cathode and gate are preferably located on the same plane, such that the height difference d is 0, that is, the side of the n+ emitter leading out of the cathode (Cathode) and the side of the second P+ region P2 leading out of the gate (Gate) are on the same plane.

[0064] It should be noted that in the present embodiment, the doping concentration of each structure is shown in the right half of Fig. 1, wherein the abscissa represents the doping concentration. Figure 2 As can be seen from the right half of Fig. 1, the second P+ region P2 of the present application has an approximately uniform doping concentration, thereby increasing the breakdown voltage of the J3 junction, which is different from the Gaussian distribution or the error distribution generated by single impurity thermal diffusion, and the second P+ region P2 can be formed by silicon epitaxy, silicon bonding or multiple ion implantation. Figure 2

[0065] Further, the GCT chip structure further comprises a p-base region, which is in contact with the n-drift region and is located between the first P+ region P1 and the n-drift region, and the first P+ region P1 is in contact with the p-base region.

[0066] It should be noted that in the present embodiment, the GCT chip structure comprises a p-base region, but the present application is not limited thereto, and in other embodiments, the GCT chip structure can not be provided with a p-base region structure to avoid process contamination, and the first P+ region P1 is used to achieve the device voltage resistance.

[0067] The GCT chip is typically asymmetrically structured, and the PN junction is provided inside the GCT chip. The PN junction is formed by different doping processes and diffusion to produce P-type semiconductor and N-type semiconductor on the same semiconductor substrate, and a space charge region is formed at the interface between the P-type semiconductor and the N-type semiconductor, which is called a PN junction. In order to distinguish the PN junctions, the PN junction formed at the connection between the n+ emitter and the second P+ region P2 is set as the J3 junction, the PN junction formed at the connection between the n-drift region and the first P+ region P1 is set as the J2 junction, and the PN junction formed at the connection between the P+ emitter and the n+ buffer layer is set as the J1 junction. In the present embodiment, the J1 junction and the J2 junction can be arranged in parallel, but the present application is not limited thereto.

[0068] In another embodiment of the present application, when the depth of the n+ emitter is completely equal to the thickness of the second P+ region P2, the n+ emitter will form PN junctions with the second P+ region P2 and the first P+ region P1.

[0069] Further, the thickness of the second P+ region P2 is the same as the thickness of the n+ emitter; specifically, the thickness of the second P+ region P2 is 1-30 μm, and the preferred value is 15 μm, but the present application is not limited to the specific value.

[0070] Please refer to Figure 3 , Figure 3 for the schematic diagram of the second embodiment of the GCT chip of the present application. Figure 3 The GCT chip structure shown in Fig. 2 is the same as that shown in Fig. 1. Figure 2 ​The GCT chip structure shown is roughly the same, so the same parts will not be described here, and the different parts will be described as follows. In this embodiment, the edge of the first P+ region P1 has a wave shape W to improve the maximum turn-off current capability, which can be achieved by masked implantation, but the application is not limited thereto.

[0071] Specifically, the middle part of the junction between the n drift region and the first P+ region P1 is provided with a wave structure, the junctions on both sides of the wave structure are planar junctions, the central axis of the wave structure corresponds to the position of the n+ emitter, and the two sides of the wave structure are smooth curved surfaces extending outward from the end lines of the middle plane as starting points. The smooth curved surfaces on both sides are symmetrically arranged about the center line of the middle plane, the middle plane of the wave structure is convex to the first P+ region P1, and the height of the convexity is less than 40 μm, and the preferred range is 25 μm-30 μm, and the smooth curved surfaces on both sides are concave to the n drift region. By arranging the plane and the two curved surfaces of the wave structure, the junction between the n drift region and the first P+ region P1 is wave-shaped, so as to improve the maximum turn-off current capability of the GCT chip structure. At the same time, the damage rate of the GCT chip provided with the wave structure is greatly reduced compared with the GCT chip without the wave structure. The wave structure can also improve the dynamic avalanche resistance of the IGCT device during use, effectively reducing the damage rate of the IGCT device.

[0072] Please refer to Figure 4 , Figure 4 for the process path diagram of the existing GCT chip structure. As shown in Figure 4 , the preparation method of the existing GCT chip structure is described to distinguish from the preparation method of the application. The preparation method of the existing GCT chip structure includes: a. selecting an n- substrate with a specific resistivity and thickness; b. forming a cathode surface p+ base region and a p base region by ion implantation and post-diffusion or deposition diffusion; c. forming an anode surface n+ buffer layer by ion implantation and post-diffusion or deposition diffusion; d. forming a thin layer of high concentration n-type doped region on the cathode surface by ion implantation or deposition; e. forming a groove shape on the cathode surface by dry or wet method; f. forming an n+ emitter by thermal diffusion on the cathode surface; g. forming an anode surface p+ emitter by ion implantation and post-diffusion or deposition diffusion; h. forming two side metal electrode contacts and patterning; i. local passivation treatment.

[0073] Please refer to Figures 5-6 , Figure 5 for the flow chart of the first embodiment of the preparation method of the application; Figure 6 for the process path diagram of Figure 5 . As shown in Figures 5-6 , the preparation method of the application includes:

[0074] Step S11: The first P+ region and p-base region are formed on the cathode surface of the n-substrate by diffusion or deposition after ion implantation. Step S11 includes the step of selecting an n-substrate with a specific resistivity and thickness, but the present invention is not limited thereto.

[0075] Step S12: An n+ buffer layer is formed on the anode surface of the n- substrate by diffusion or deposition after ion implantation;

[0076] Step S13: Grow a second P+ region in the first P+ region using silicon epitaxy;

[0077] Step S14: An n-type doped region is formed in the second P+ region using selective ion implantation or selective deposition, and then advanced by thermal diffusion to form an n+ emitter;

[0078] Step S15: Form a p+ emitter on the n+ buffer layer by diffusion or deposition after ion implantation;

[0079] Step S16: Form contact and patterning of metal electrodes on both sides, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

[0080] In this embodiment, the step of forming a wave shape W by masking injection at the edge of the first P+ region may also be included.

[0081] In another embodiment of the present invention, when the GCT chip may not have a p-base region, step S11 may further include forming a p-type doped region on the cathode surface of the substrate by selective ion implantation or selective deposition, and advancing it by thermal diffusion to form a first P+ region that may have a wavy structure.

[0082] In this embodiment, a local passivation process may be included after step S16.

[0083] Please refer to Figures 7-8 , Figure 7 This is a flowchart of the second embodiment of the preparation method of the present invention; Figure 8 for Figure 7 The process path diagram. For example... Figures 7-8 As shown, the preparation method of the present invention includes:

[0084] Step S21: The first P+ region and p-base region are formed on the cathode surface of the n-substrate by diffusion or deposition after ion implantation. Step S21 includes the step of selecting an n-substrate with a specific resistivity and thickness, but the present invention is not limited thereto.

[0085] Step S22: An n+ buffer layer is formed on the anode surface of the n- substrate by diffusion or deposition after ion implantation;

[0086] Step S23: using P-substrate or SOI wafer, the P-substrate or SOI wafer is connected with the cathode surface of the n-substrate which has completed the multi-step diffusion process through silicon-silicon bonding, and the second P+ region is obtained after processing. Specifically, when using P-substrate, the P-substrate is connected with the cathode surface of the n-substrate which has completed the multi-step diffusion process through silicon-silicon bonding, and the second P+ region is obtained after thinning processing (see Figure 8 ); when using SOI wafer, the SOI wafer is connected with the cathode surface of the n-substrate which has completed the multi-step diffusion process through silicon-silicon bonding, and the second P+ region is obtained after removing SiO2 by etching processing. Please refer to Figure 8a , Figure 8a for the process path diagram of the process path using SOI wafer.

[0087] The SOI (Silicon on Insulator) wafer is a silicon wafer based on insulator. Because the substrate is insulator such as glass (the traditional wafer is silicon crystal), the electron leakage can be reduced, the current efficiency of the wafer can be effectively improved, the power consumption can be reduced, and the reliability can be improved.

[0088] Step S24: forming n-type doped region on the second P+ region by selective ion implantation or selective deposition, and promoting by thermal diffusion to form n+ emitter.

[0089] Step S25: forming p+ emitter on the n+ buffer layer by ion implantation and diffusion or deposition diffusion.

[0090] Step S26: forming two-side metal electrode contact and patterning, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

[0091] In the embodiment, the step of forming wave shape W by masked implantation at the edge of the first P+ region can also be included.

[0092] In the embodiment, the step of local passivation processing can also be included after step S26.

[0093] Please refer to Figures 9-10 , Figure 9 for the flow chart of the third embodiment of the preparation method of the present application. Figure 10 for the process path diagram of the process path of Figure 9 . As shown in Figures 9-10 , the preparation method of the present application comprises:

[0094] Step S31: forming the second P+ region, the first P+ region and the p-base region on the cathode surface of the n-substrate by ion implantation and diffusion or deposition diffusion, wherein step S31 comprises the step of selecting n-substrate with specific resistivity and thickness, but the present application is not limited thereto.

[0095] Step S32: forming an n+ buffer layer on the anode surface of the n-base by post-ion implantation diffusion or deposition diffusion;

[0096] Step S33: forming an n-type doped region in the second P+ region by selective ion implantation or selective deposition, and promoting by thermal diffusion to form an n+ emitter;

[0097] Step S34: forming a p+ emitter on the n+ buffer layer by post-ion implantation diffusion or deposition diffusion;

[0098] Step S35: forming two side metal electrode contacts and patterning, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

[0099] In the present embodiment, a step of forming a wave shape W by masked implantation at the edge of the first P+ region can also be included.

[0100] In the present embodiment, a step of local passivation treatment can also be included after step S35.

[0101] In summary, the GTC chip and the preparation method thereof have strong applicability, can achieve the gate-cathode breakdown voltage of the existing GCT chip structure, increase the design space of the lateral dimension, have stronger current-off capability under the condition of uniformity of the same process, and can further simplify the manufacturing process of the GTC chip through the preparation method.

[0102] Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A GCT chip structure comprising a P+ emitter with an extracted anode, an n+ buffer layer in contact with the P+ emitter, an n drift region in contact with the n+ buffer layer, characterized in that, The GCT chip structure further comprises: a first P+ region, which is in contact with the n drift region, and a connection between the first P+ region and the n drift region has a wave shape, a middle plane of the wave shape is convex to the first P+ region, and a convex height is less than 40 μm; a second P+ region, which is in contact with the first P+ region and is located above the first P+ region, wherein the second P+ region has an approximately uniform doping concentration; and an n+ emitter, which is connected with the second P+ region, the n+ emitter leads out a cathode, the second P+ region leads out a gate, the cathode and the gate have a height difference, and the height difference ranges from 0 to 10 μm.

2. The GCT chip structure of claim 1, wherein, a p base region, which is in contact with the n drift region and is located between the first P+ region and the n drift region, and the first P+ region is in contact with the p base region.

3. The GCT chip structure of claim 1, wherein, The thickness of the second P+ region is the same as the thickness of the n+ emitter.

4. The GCT chip structure of claim 1, wherein, The cathode and the gate are located in the same plane.

5. The GCT chip structure of claim 1, wherein, The thickness of the second P+ region is 1-30 μm.

6. A method of fabricating a GCT chip, characterized by, A method for preparing the GCT chip structure of claim 1 comprises: Step S11: forming a first P+ region and a p base region on a cathode surface of an n- substrate by ion implantation and post-diffusion or deposition diffusion; Step S12: forming an n+ buffer layer on an anode surface of the n- substrate by ion implantation and post-diffusion or deposition diffusion; Step S13: growing a second P+ region on the first P+ region by a silicon epitaxy method, and forming a wave shape at an edge of the first P+ region by mask injection; Step S14: forming an n-type doped region in the second P+ region by selective ion implantation or selective deposition, and promoting by thermal diffusion to form an n+ emitter; Step S15: forming a p+ emitter on the n+ buffer layer by ion implantation and post-diffusion or deposition diffusion; Step S16: forming two-side metal electrode contact and patterning, wherein a metal electrode on the cathode surface is higher than a metal electrode on the gate surface.

7. A method of fabricating a GCT chip, characterized by, A method for preparing the GCT chip structure of claim 1 comprises: Step S21: forming a first P+ region and a p base region on a cathode surface of an n- substrate by ion implantation and post-diffusion or deposition diffusion, and forming a wave shape at an edge of the first P+ region by mask injection; Step S22: forming an n+ buffer layer on an anode surface of the n- substrate by ion implantation and post-diffusion or deposition diffusion; Step S23: using a P- substrate or an SOI sheet, connecting the P- substrate or the SOI sheet with a cathode surface of an n- substrate which has completed a multi-step diffusion process by silicon-silicon bonding, and thinning to obtain a second P+ region, wherein the second P+ region is located above the first P+ region; Step S24: forming an n-type doped region in the second P+ region by selective ion implantation or selective deposition, and promoting by thermal diffusion to form an n+ emitter; Step S25: forming a p+ emitter on the n+ buffer layer by ion implantation and post-diffusion or deposition diffusion; Step S26: forming two-side metal electrode contact and patterning, wherein a metal electrode on the cathode surface is higher than a metal electrode on the gate surface.

8. A method of fabricating a GCT chip, characterized by, A GCT chip structure as claimed in claim 1 is prepared by the steps of: Step S31: forming a second P+ region, a first P+ region and a p-base region by diffusion of ion implantation or deposition diffusion on the cathode surface of the n-base, and forming a wave shape by masked implantation on the edge of the first P+ region, wherein the second P+ region is above the first P+ region; Step S32: forming an n+ buffer layer by diffusion of ion implantation or deposition diffusion on the anode surface of the n-base; Step S33: forming an n-type doped region in the second P+ region by selective ion implantation or selective deposition, and advancing by thermal diffusion to form an n+ emitter; Step S34: forming a p+ emitter on the n+ buffer layer by diffusion of ion implantation or deposition diffusion; Step S35: forming two-sided metal electrode contact and patterning, wherein the metal electrode on the cathode surface is higher than the metal electrode on the gate surface.

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