Integrated circuit device including a boron-containing insulating pattern

Abstract

An integrated circuit (IC) device is provided. The IC device includes a substrate, the substrate includes an active area. The IC device includes a bit line on the substrate. The IC device includes a direct contact portion connected between the active area and the bit line. The IC device includes a contact plug on the substrate. In addition, the IC device includes a boron-containing insulating pattern between the contact plug and the direct contact portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0094613 filed on August 13, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an integrated circuit (IC) device, and more particularly, to an IC device including a plurality of conductive patterns adjacent to each other. Background Art

[0004] In recent years, as the size of TC devices has been rapidly reduced, the distance between interconnects has become narrower, so the distance between the interconnects and the contact plugs between the interconnects has gradually decreased. As a result, the parasitic capacitance between the contact plugs and the interconnects has increased, and the possibility of electrical short circuits between the contact plugs and the conductive regions adjacent thereto has also increased. Summary of the invention

[0005] The present invention is conceived to provide an integrated circuit (IC) device that can have a reduced (e.g., miniaturized) unit cell size as the size of the IC device is reduced, and can reduce parasitic capacitance between a contact plug formed in a limited area and a conductive line adjacent to the contact plug, and reduce the possibility of electrical short circuits between adjacent conductive regions to improve reliability.

[0006] According to some embodiments of the present invention, an IC device is provided. The IC device may include a substrate, the substrate including a first active area and a second active area spaced apart from each other. The IC device may include a bit line extending in a horizontal direction on the substrate. The IC device may include a direct contact portion connected between the first active area and the bit line. The IC device may include a contact plug extending in a vertical direction on the substrate. The contact plug may include an upper portion adjacent to the bit line and a lower portion in contact with the second active area in the substrate. In addition, the IC device may include a boron-containing insulating pattern between the lower portion of the contact plug and the direct contact portion.

[0007] An IC device according to some embodiments of the present invention may include a substrate including a plurality of active regions spaced apart from each other. The IC device may include a bit line extending along a horizontal direction on the substrate. The IC device may include a plurality of contact plugs spaced apart from each other along a horizontal line parallel to the bit line on the substrate. The IC device may include a plurality of insulating fences alternating with the plurality of contact plugs in the horizontal direction. The IC device may include a direct contact portion connected between a first active region in the plurality of active regions and the bit line. In addition, the IC device may include a boron-containing insulating pattern between a first contact plug in the plurality of contact plugs and the direct contact portion.

[0008] An IC device according to some embodiments of the present invention may include a substrate, the substrate including a plurality of active regions. The IC device may include a bit line extending in a horizontal direction on the substrate. The IC device may include a direct contact portion connected between a first active region in the plurality of active regions and the bit line. The IC device may include a first contact plug and a second contact plug facing each other, wherein the bit line is between the first contact plug and the second contact plug. The first contact plug and the second contact plug may be connected to the second active region and the third active region in the plurality of active regions, respectively. The TC device may include a first insulating fence and a second insulating fence facing each other, wherein the bit line is between the first insulating fence and the second insulating fence. In addition, the IC device may include a plurality of boron-containing insulating patterns. The plurality of boron-containing insulating patterns may include a first boron-containing insulating pattern between the direct contact portion and the first contact plug and a second boron-containing insulating pattern between the direct contact portion and the second contact plug. Each of the plurality of boron-containing insulating patterns includes a silicon boron nitride (SiBN) film. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 shows the layout of the main components of the memory cell array area of ​​the integrated circuit (IC) device according to the embodiment;

[0011] Figure 2A shows a cross-sectional view of an IC device according to an embodiment;

[0012] Figure 2B yes Figure 2A An enlarged plan view of a local area;

[0013] Figure 3A shows a cross-sectional view of an IC device according to an embodiment;

[0014] Figure 3B yes Figure 3A An enlarged plan view of a local area;

[0015] Figure 4A shows a cross-sectional view of an IC device according to an embodiment;

[0016] Figure 4B yes Figure 4A An enlarged plan view of a local area;

[0017] Figure 5A shows a cross-sectional view of an IC device according to an embodiment;

[0018] Figure 5B yes Figure 5AAn enlarged plan view of a local area;

[0019] Figure 6 is a cross-sectional view of an IC device according to an embodiment;

[0020] Fig. 7A shows a cross-sectional view of an IC device according to an embodiment;

[0021] Figure 7B yes Fig. 7A An enlarged plan view of a local area;

[0022] Fig. 8A shows a cross-sectional view of an IC device according to an embodiment;

[0023] Figure 8B yes Fig. 8A An enlarged plan view of a local area;

[0024] Fig.9A shows a cross-sectional view of an IC device according to an embodiment;

[0025] Fig. 9B yes Fig.9A An enlarged plan view of a local area;

[0026] Fig. 10A shows a cross-sectional view of an IC device according to an embodiment;

[0027] Fig. 10B yes Fig. 10A An enlarged plan view of a local area;

[0028] Fig.11 is a cross-sectional view of an IC device according to an embodiment;

[0029] FIG. 12A to FIG. 12N is a process sequence diagram of a method for manufacturing an IC device according to an embodiment;

[0030] FIG. 13A to FIG. 13D A cross-sectional view showing a process sequence of a method for manufacturing an IC device according to an embodiment;

[0031] FIG. 14A to FIG. 14E is a process sequence diagram of a method for manufacturing an IC device according to an embodiment; and

[0032] FIG. 15A to FIG. 15E is a process sequence diagram of a method for manufacturing an IC device according to an embodiment. DETAILED DESCRIPTION

[0033] Figure 1 A layout of main components of a memory cell array region of an integrated circuit (IC) device 10 according to an embodiment is shown.

[0034] refer to Figure 1, the IC device 10 may include a plurality of active areas ACT, which may be spaced apart from each other. The plurality of active areas ACT may be arranged at a certain angle to each of the X direction and the Y direction on the plane and extend in the horizontal direction. A plurality of word lines WL may intersect the plurality of active areas ACT and extend parallel to each other in the X direction. A plurality of bit lines BL may be located on the plurality of word lines WL and extend parallel to each other in the Y direction intersecting the X direction. The plurality of bit lines BL may be connected to the plurality of active areas ACT through one or more direct contacts DC.

[0035] A plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. A plurality of conductive landing pads LP may be formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of conductive landing pads LP may be used to connect the lower electrodes of the capacitors formed on the plurality of bit lines BL to the active area ACT. At least a portion of each of the plurality of conductive landing pads LP may overlap with the buried contact BC in the vertical direction.

[0036] Next, we will refer to Figures 2A to 11 A configuration of an IC device according to example embodiments is described. Figures 2A to 11 Each IC device shown may have Figure 1 The layout of the IC device 10 is shown. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A In the figure, (a) is along Figure 1 A cross-sectional view of some parts of the corresponding section taken along the line A-A', (b) is a cross-sectional view of some parts of the corresponding section taken along the line A-A', Figure 1 (c) is a cross-sectional view of some components of a portion corresponding to a cross section taken along line BB', and (c) is an enlarged cross-sectional view of a portion corresponding to a dotted line region indicated by "X1" in (a).

[0037] Figure 2A shows a cross-sectional view of an IC device 100 according to an embodiment, and Figure 2B yes Figure 2A An enlarged plan view of a local area in the figure.

[0038] refer to Figure 2A and Figure 2B , the IC device 100 may include a substrate 110 in which a plurality of active areas ACT are defined by a device isolation film 112. The device isolation film 112 may be formed in a device isolation trench T1 formed in the substrate 110.

[0039] The substrate 110 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 110 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 110 may include a conductive region, such as a doped well or a doped structure.

[0040] A plurality of word line trenches T2 may be formed in the substrate 110 and extend along the first horizontal direction (X direction), and a plurality of gate dielectric films 116, a plurality of word lines 118, and a buried insulating film 120 may be formed in the plurality of word line trenches T2. The plurality of word lines 118 may correspond to Figure 1 The multiple word lines WL shown in FIG.

[0041] A first insulating film 122 and a second insulating film 124 may be sequentially formed on the substrate 110. The first insulating film 122 and the second insulating film 124 may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the first insulating film 122 may include silicon oxide, and the second insulating film 124 may include silicon nitride. A plurality of bit lines BL may be formed on the second insulating film 124 and extend parallel to each other in a second horizontal direction (Y direction).

[0042] A direct contact DC may be formed on a local area of ​​each of the plurality of active areas ACT. Each of the plurality of bit lines BL may be connected to the active area ACT via a direct contact DC. In some embodiments, the direct contact DC may include silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof. Thus, the direct contact DC may include a metal and / or semiconductor material. In some embodiments, the direct contact DC may include an epitaxial silicon layer.

[0043] The plurality of bit lines BL may include a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134 sequentially formed on the substrate 110. Each of the plurality of bit lines BL may be covered by an insulating capping pattern 136. A top surface of the lower conductive layer 130 may be coplanar with a top surface of the direct contact portion DC. Figure 2A An example is shown in which each of the plurality of bit lines BL has a three-layer structure including a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134, but the inventive concept is not limited thereto. For example, each of the plurality of bit lines BL may be formed as a single layer, a double layer, or a multi-layer stacked structure including at least four layers.

[0044] In some embodiments, the lower conductive layer 130 may include conductive polysilicon. Each of the intermediate conductive layer 132 and the upper conductive layer 134 may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide, or a combination thereof. For example, the intermediate conductive layer 132 may include TiN and / or TiSiN, and the upper conductive layer 134 may include W. The insulating capping pattern 136 may include a silicon nitride film.

[0045] A plurality of contact plugs 150 may be formed in the spaces between the respective bit lines BL. Each of the plurality of contact plugs 150 may have a columnar shape extending upward from the substrate 110 in a vertical direction (Z direction). The bottom (i.e., lower portion) 150B of each of the plurality of contact plugs 150 may be in contact with the active area ACT. The bottom 150B of each of the plurality of contact plugs 150 may be located at a height lower than the top surface of the substrate 110 and buried in the substrate 110. For example, the bottom 150B of the contact plug 150 may be lower than the upper portion of the contact plug 150 adjacent to the bit line BL (e.g., the upper portion between the two bit lines BL). The plurality of contact plugs 150 may include doped semiconductor materials, metals, conductive metal nitrides, or a combination thereof, but are not limited thereto.

[0046] In the IC device 100 , one direct contact portion DC and a pair of contact plugs 150 facing each other with the direct contact portion DC interposed therebetween may be connected to different corresponding active regions AC among the plurality of active regions AC.

[0047] A plurality of insulating fences 148 and the plurality of contact plugs 150 may be alternately arranged one by one between a pair of bit lines BL along a straight line parallel to the direction (Y direction) in which the bit lines BL extend. The plurality of contact plugs 150 may be insulated from each other by the plurality of insulating fences 148. Each of the plurality of insulating fences 148 may have a columnar shape extending from the substrate 110 in a vertical direction (Z direction). In some embodiments, the plurality of insulating fences 148 may include a silicon nitride film, but is not limited thereto.

[0048] The IC device 100 may include a boron (B)-containing insulating filling pattern 140P between the contact plug 150 and the direct contact portion DC. The boron-containing insulating filling pattern 140P may be in contact with the bottom 150B of the contact plug 150 and the direct contact portion DC. At least a portion of the boron-containing insulating filling pattern 140P may be buried in the substrate 110. The bottom height of the boron-containing insulating filling pattern 140P may be lower than the top height of the substrate 110, and the top height of the boron-containing insulating filling pattern 140P may be equal to or higher than the top height of the substrate 110. However, the pattern 140P does not necessarily completely fill a specific area, and therefore may be referred to as a "boron-containing insulating pattern" herein.

[0049] The boron-containing insulating fill pattern 140P may have a dielectric constant of about 2 to 6. For example, the boron-containing insulating fill pattern 140P may have a dielectric constant of about 3 to 5. In some embodiments, the boron-containing insulating fill pattern 140P may include a silicon boron nitride (SiBN) film. The boron content of the SiBN film included in the boron-containing insulating fill pattern 140P may be about 10 atomic percent (at%) to about 50 at%. For example, the boron-containing insulating fill pattern 140P may include Si x B y N z (0.1≤x≤0.5, 0.1≤y≤0.5, and 0.1≤z≤0.8).

[0050] In the IC device 100, the boron-containing insulating filling pattern 140P having a relatively low dielectric constant may be interposed between the direct contact portion DC and the bottom 150B of the contact plug 150 adjacent to each other (i.e., there is no other direct contact portion DC or contact plug 150 between the direct contact portion DC and the contact plug 150). Therefore, the undesirable parasitic capacitance between the direct contact portion DC and the contact plug 150 may be reduced.

[0051] The IC device 100 may include a first insulating spacer 142S and a second insulating spacer 144 sequentially covering two (i.e., opposite) sidewalls of the plurality of bit lines BL. The first insulating spacer 142S and the second insulating spacer 144 may be between the contact plug 150 and the bit line BL on the boron-containing insulating filling pattern 140P. The first insulating spacer 142S and the second insulating spacer 144 may include different corresponding materials. The first insulating spacer 142S and the second insulating spacer 144 may not include boron (i.e., may not contain boron). In some embodiments, the first insulating spacer 142S may include a silicon oxide film, and the second insulating spacer 144 may include a silicon nitride film.

[0052] The first insulating spacer 142S may extend in parallel with the bit line BL between the bit line BL and a plurality of contact plugs 150 arranged linearly in the Y direction, and the second insulating spacer 144 may extend in parallel with the bit line BL between the bit line BL and a plurality of insulating fences 148 arranged linearly in the Y direction. Each of the plurality of contact plugs 150 arranged linearly in the Y direction may be spaced apart from the bit line BL, with the first insulating spacer 142S and the second insulating spacer 144 being therebetween. In addition, each insulating fence 148 arranged linearly in the Y direction may be spaced apart from the bit line BL, with the first insulating spacer 142S and the second insulating spacer 144 being therebetween. The second insulating spacer 144 may include a portion having a U-shaped cross-sectional shape to cover two (i.e., opposite) side walls and a bottom surface of each of the plurality of insulating fences 148.

[0053] A metal silicide film 172 and a plurality of conductive landing pads LP may be sequentially formed on each of the plurality of contact plugs 150. The plurality of conductive landing pads LP may be respectively connected to the plurality of contact plugs 150 through the metal silicide film 172. The plurality of conductive landing pads LP may extend from the spaces between the plurality of insulating capping patterns 136 to the tops of the plurality of insulating capping patterns 136, and respectively overlap with a portion of the plurality of bit lines BL in a vertical direction. Each of the plurality of conductive landing pads LP may include a conductive barrier film 174 and a conductive layer 176.

[0054] In some embodiments, the metal silicide film 172 may include cobalt silicide, nickel silicide, or manganese silicide, but is not limited thereto. In some embodiments, the metal silicide film 172 may be omitted. The conductive barrier film 174 may have a Ti / TiN stacked structure. The conductive layer 176 may include doped polysilicon, a metal, a metal silicide, a conductive metal nitride, or a combination thereof. For example, the conductive layer 176 may include tungsten (W). When viewed from above, the plurality of conductive landing pads LP may have a plurality of island pattern shapes. The plurality of conductive landing pads LP may be electrically insulated from each other by an insulating film 180 filling the space around the plurality of conductive landing pads LP.

[0055] Figure 3A A cross-sectional view of an IC device 100A according to an embodiment is shown, and Figure 3B yes Figure 3A An enlarged plan view of a local area in the Figure 3A and Figure 3B In, with Figure 2A and Figure 2B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0056] refer to Figure 3A and Figure 3B , the IC device 100A may have Figure 2A and Figure 2B . However, the IC device 100A may include an air spacer AS1 instead of the first insulating spacer 142S. The term "air" used herein may refer to other gases that may be present in an atmosphere or during a manufacturing process. The air spacer AS1 may include a portion whose bottom is defined by the boron-containing insulating fill pattern 140P and a portion whose bottom is defined by the second insulating film 124.

[0057] Figure 4A shows a cross-sectional view of an IC device 200 according to an embodiment, and Figure 4B yes Figure 4A An enlarged plan view of a local area in the Figure 4Aand Figure 4B In, with Figure 2A and Figure 2B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0058] refer to Figure 4A and Figure 4B , the IC device 200 may have Figure 2A and Figure 2B However, the IC device 200 may include an inner insulating film 242 surrounding a portion of the boron-containing insulating fill pattern 140P.

[0059] The inner insulating film 242 may conformally cover the direct contact portion DC, the sidewalls of each of the plurality of bit lines BL and the plurality of insulating capping patterns 136, and the bottom surface and sidewalls of the boron-containing insulating filling pattern 140P. The inner insulating film 242 may be between the bit line BL and the first insulating spacer 142S. The inner insulating film 242, the first insulating spacer 142S, and the second insulating spacer 144, which may be sequentially located on the sidewalls of the bit line BL, may be between the bit line BL and the contact plug 150, and between the bit line BL and the insulating fence 148.

[0060] The boron-containing insulation filling pattern 140P may be spaced apart from the direct contact portion DC and the contact plug 150, with the inner insulation film 242 being therebetween. The portion of the inner insulation film 242 surrounding the boron-containing insulation filling pattern 140P may constitute a gap insulation film / region. The gap insulation film / region as a part of the inner insulation film 242 may be between the bottom 150B of the plurality of contact plugs 150 and the boron-containing insulation filling pattern 140P and between the direct contact portion DC and the boron-containing insulation filling pattern 140P. The dielectric constant of the gap insulation film / region may be lower than the dielectric constant of the boron-containing insulation filling pattern 140P.

[0061] The inner insulating film 242 and the boron-containing insulating filling pattern 140P may include materials having an etch selectivity with respect to each other. In some embodiments, the inner insulating film 242 may include a silicon oxide film.

[0062] In the IC device 200, the boron-containing insulating filling pattern 140P and the inner insulating film 242 having a relatively low dielectric constant may be interposed between the direct contact portion DC and the bottom 150B of the contact plug 150 adjacent to each other. Therefore, undesirable parasitic capacitance between the direct contact portion DC and the contact plug 150 may be reduced.

[0063] Figure 5A A cross-sectional view of an IC device 200A according to an embodiment is shown, and Figure 5B yes Figure 5A An enlarged plan view of a local area in the Figure 5Aand Figure 5B In, with Figure 4A and Figure 4B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0064] refer to Figure 5A and Figure 5B , the IC device 200A may have Figure 4A and Figure 4B However, the IC device 200A may include an air spacer AS21 that may be disposed between the bit line BL and the second insulating spacer 144 and an inner insulating film 242G1 that may surround a portion of the boron-containing insulating filling pattern 140P at a height lower than the air spacer AS21.

[0065] The inner insulating film 242G1 and the boron-containing insulating filling pattern 140P may include materials having an etch selectivity with respect to each other. In some embodiments, the inner insulating film 242G1 may include a silicon oxide film.

[0066] The air spacer AS21 may include a portion whose bottom is defined by the boron-containing insulating filling pattern 140P and the inner insulating film 242G1 and a portion whose bottom is defined by the second insulating film 124. The air spacer AS21 may include a gap air (i.e., air gap) portion G21 that may extend toward the substrate 110 between the direct contact portion DC and the boron-containing insulating filling pattern 140P.

[0067] In the IC device 200A, the inner insulating film 242G1 and the gap air portion G21 may constitute a gap insulating film / region. In the IC device 200A, the boron-containing insulating filling pattern 140P having a relatively low dielectric constant, the gap air portion G21 of the air spacer AS21, and the inner insulating film 242G1 may be interposed between the direct contact portion DC and the bottom 150B of the contact plug 150 adjacent to each other. Undesirable parasitic capacitance between the direct contact portion DC and the contact plug 150 may be reduced.

[0068] Figure 6 is a cross-sectional view of an IC device 200B according to an embodiment. Figure 6 is with Figure 5A The enlarged cross-sectional view of other parts of the portion corresponding to the dotted area indicated by "X1" in (a). Figure 6 In, with Figure 5A and Figure 5B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0069] refer to Figure 6 , IC device 200B may have Figure 4A and Figure 4BHowever, the IC device 200B may include an air spacer AS22 disposed between the bit line BL and the second insulating spacer 144 and an inner insulating film 242G2 interposed between the boron-containing insulating filling pattern 140P and the bottom 150B of the contact plug 150 .

[0070] The inner insulating film 242G2 and the boron-containing insulating filling pattern 140P may include materials having an etch selectivity with respect to each other. In some embodiments, the inner insulating film 242G2 may include a silicon oxide film.

[0071] The air spacer AS22 may extend from the space between the bit line BL and the second insulating spacer 144 into the substrate 110. The air spacer AS22 may include a gap air portion G22, which may extend between the direct contact portion DC and the boron-containing insulating filling pattern 140P and between the boron-containing insulating filling pattern 140P and the bottom 150B of the contact plug 150, and surround the boron-containing insulating filling pattern 140P. The gap air portion G22 of the air spacer AS22 may surround the sidewall and bottom surface of the boron-containing insulating filling pattern 140P. The air spacer AS22 may include a portion whose bottom is defined by the second insulating film 124. In the IC device 200B, the inner insulating film 242G2 and the gap air portion G22 may constitute a gap insulating film / region.

[0072] In the IC device 200B, the boron-containing insulating filling pattern 140P having a relatively low dielectric constant, the gap air portion G22 of the air spacer AS22, and the inner insulating film 242G2 may be interposed between the direct contact portion DC and the bottom 150B of the contact plug 150 adjacent to each other. Therefore, the undesirable parasitic capacitance between the direct contact portion DC and the contact plug 150 may be reduced.

[0073] Fig. 7A shows a cross-sectional view of an IC device 300 according to an embodiment, and Figure 7B yes Fig. 7A An enlarged plan view of a local area in the Fig. 7A and Figure 7B In, with Figure 2A and Figure 2B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0074] refer to Fig. 7A and Figure 7B , the IC device 300 may have Figure 2A and Figure 2BHowever, the IC device 300 may include a plurality of first insulating spacers 342S and a plurality of second insulating spacers 344 that may cover both (ie, opposite) sidewalls of the plurality of bit lines BL.

[0075] like Figure 7B As shown, the plurality of first insulating spacers 342S and the plurality of second insulating spacers 344, each of which may have a ring-shaped (e.g., circular or rectangular) shape, may respectively surround the periphery of the contact plug 150. Each of the plurality of first insulating spacers 342S and the plurality of second insulating spacers 344 may include a portion between the sidewall of the contact plug 150 and the bit line BL on the boron-containing insulating filling pattern 140P and a portion configured to extend between the contact plug 150 and the insulating fence 348. The first insulating spacers 342S and the second insulating spacers 344 may not be interposed between the bit line BL and the insulating fence 348.

[0076] Between the bit line BL and the contact plug 150 , the first insulating spacer 342S may have an L-shaped cross-sectional shape, and the second insulating spacer 344 may be spaced apart from the second insulating film 124 with the first insulating spacer 342S therebetween.

[0077] Between the direct contact portion DC and the contact plug 150 , the second insulating spacer 344 may be spaced apart from the boron-containing insulation filling pattern 140P with the first insulating spacer 342S therebetween.

[0078] In addition, the IC device 300 may further include a plurality of boron-containing insulating fences 140F that may be between the bit line BL and a plurality of insulating fences 348 that are linearly arranged along the Y direction. The plurality of boron-containing insulating fences 140F may include the same material as the boron-containing insulating filling pattern 140P. Each of the plurality of boron-containing insulating fences 140F may have a U-shaped cross-sectional shape, being located on (e.g., covering) two (i.e., opposite) sidewalls and a bottom surface of the insulating fence 348.

[0079] In some embodiments, each of the boron content and the nitrogen content in the boron-containing insulating fence 140F may be variable in the thickness direction of the boron-containing insulating fence 140F. For example, the boron content in the boron-containing insulating fence 140F may increase toward the bit line BL, and may decrease toward the insulating fence 348. In addition, the nitrogen content in the boron-containing insulating fence 140F may decrease toward the bit line BL, and may increase toward the insulating fence 348.

[0080] The detailed configuration of the first insulating spacer 342S, the second insulating spacer 344 and the insulating fence 348 may be similar to that of reference Figure 2A and Figure 2BThe described first insulating spacers 142S, second insulating spacers 144, and insulating fences 148 are substantially the same.

[0081] Fig. 8A shows a cross-sectional view of an IC device 300A according to an embodiment, and Figure 8B yes Fig. 8A An enlarged plan view of a local area in the Fig. 8A and Figure 8B In, with Fig. 7A and Figure 7B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0082] refer to Fig. 8A and Figure 8B , the IC device 300A may have Fig. 7A and Figure 7B . However, the IC device 300A may include an air spacer AS3 instead of the first insulating spacer 342S. The air spacer AS3 may have a ring shape and surround the contact plug 150.

[0083] The air spacer AS3 may include a portion whose bottom is defined by the boron-containing insulating filling pattern 140P and a portion whose bottom is defined by the second insulating film 124. Between the bit line BL and the contact plug 150, the second insulating spacer 344 may be spaced apart from the second insulating film 124, with the air spacer AS3 therebetween. Between the direct contact portion DC and the contact plug 150, the second insulating spacer 344 may be spaced apart from the boron-containing insulating filling pattern 140P, with the air spacer AS3 therebetween.

[0084] Fig.9A shows a cross-sectional view of an IC device 400 according to an embodiment, and Fig. 9B yes Fig.9A An enlarged plan view of a local area in the Fig.9A and Fig. 9B In, with FIG. 2A to FIG. 7B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0085] refer to Fig.9A and Fig. 9B , the IC device 400 may have Fig. 7A and Figure 7B . However, the IC device 400 may include an inner insulating film 242 configured to surround a portion of the boron-containing insulating fill pattern 140P. The detailed configuration of the inner insulating film 242 may be the same as that of the reference 140. Figure 4A and Figure 4BThe configuration described is basically the same. However, the inner insulating film 242 may contact the boron-containing insulating fence 140F between the bit line BL and the insulating fence 348. The inner insulating film 242 may be spaced apart from the insulating fence 348, with the boron-containing insulating fence 140F being between them. The boron-containing insulating fence 140F may have a U-shaped cross-sectional shape to cover the two (i.e., opposite) sidewalls and bottom surface of the insulating fence 148.

[0086] The inner insulating film 242 may be interposed between the bit line BL and the first insulating spacer 342S. Therefore, the inner insulating film 242, the first insulating spacer 342S, and the second insulating spacer 344, which may be sequentially disposed on the sidewall of the bit line BL, may be interposed between the bit line BL and the contact plug 150. The inner insulating film 242 and the boron-containing insulating fence 140F, which may be sequentially disposed on the sidewall of the bit line BL, may be interposed between the bit line BL and the insulating fence 148.

[0087] Fig. 10A shows a cross-sectional view of an IC device 400A according to an embodiment, and Fig. 10B yes Fig. 10A An enlarged plan view of a local area in the Fig. 10A and Fig. 10B In, with Fig.9A and Fig. 9B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0088] refer to Fig. 10A and Fig. 10B , IC device 400A may have Fig.9A and Fig. 9B However, the IC device 400A may include an air spacer AS41 disposed between the bit line BL and the second insulating spacer 344 and an inner insulating film 242G4 that may surround a portion of the boron-containing insulating filling pattern 140P at a height lower than the air spacer AS41.

[0089] The detailed configuration of the inner insulating film 242G4 can be compared with reference Figure 5A and Figure 5B The detailed configuration of the inner insulating film 242G1 described above is substantially the same. The air spacer AS41 may include a portion whose bottom is defined by the boron-containing insulating filling pattern 140P and the inner insulating film 242G4 and a portion whose bottom is defined by the second insulating film 124. Fig. 10B As shown, the air spacer AS41 may include a plurality of ring-shaped portions configured to surround the plurality of contact plugs 150 and a plurality of linear portions that may communicate with (ie, be connected to) the plurality of ring-shaped portions and be interposed between the bit line BL and the boron-containing insulating fence 140F.

[0090] The air spacer AS41 may include a gap air portion G41 that may extend between the direct contact DC and the boron-containing insulating fill pattern 140P toward the substrate 110. In the IC device 400A, the inner insulating film 242G4 and the gap air portion G41 may constitute a gap insulating film / region.

[0091] In the IC device 400A, the boron-containing insulating filling pattern 140P having a relatively low dielectric constant, the gap air portion G41 of the air spacer AS41, and the inner insulating film 242G4 may be interposed between the direct contact portion DC and the bottom 150B of the contact plug 150 adjacent to each other. Therefore, the undesirable parasitic capacitance between the direct contact portion DC and the contact plug 150 may be reduced.

[0092] Fig.11 is a cross-sectional view of an IC device 400B according to an embodiment. Fig.11 is with Fig. 10A The enlarged cross-sectional view of other parts of the portion corresponding to the dotted area indicated by "X1" in (a). Fig.11 In, with Fig. 10A and Fig. 10B The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0093] refer to Fig.11 , IC device 400B may have Fig.9A and Fig. 9B However, the IC device 400B may include an air spacer AS42 disposed between the bit line BL and the second insulating spacer 344 and an inner insulating film 242G5 between the boron-containing insulating filling pattern 140P and the bottom 150B of the contact plug 150. In some embodiments, the inner insulating film 242G5 may include a silicon oxide film.

[0094] The air spacer AS42 may extend from the space between the bit line BL and the second insulating spacer 344 into the substrate 110. The air spacer AS42 may include a gap air portion G42, which may extend between the direct contact portion DC and the boron-containing insulation filling pattern 140P and between the boron-containing insulation filling pattern 140P and the bottom 150B of the contact plug 150, and may surround the boron-containing insulation filling pattern 140P. The gap air portion G42 of the air spacer AS42 may surround the sidewall and bottom surface of the boron-containing insulation filling pattern 140P. The air spacer AS42 may include a portion whose bottom is defined by the second insulation film 124. In the IC device 400B, the inner insulation film 242G5 and the gap air portion G42 may constitute a gap insulation film / region.

[0095] In the IC device 400B, a boron-containing insulating filling pattern 140P having a relatively low dielectric constant, a gap air portion G42 of an air spacer AS42, and an inner insulating film 242G5 may be interposed between the direct contact portion DC and the bottom 150B of the contact plug 150 adjacent to each other, thereby reducing undesirable parasitic capacitance between the direct contact portion DC and the contact plug 150.

[0096] FIG. 12A to FIG. 12N FIG. 1 is a process sequence diagram of a method for manufacturing an IC device according to an embodiment. FIG. 12A to FIG. 12N In (a), the process sequence is based on the Figure 1 (a) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A', and (b) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A' according to the process sequence. Figure 1 The cross-section taken along the line BB' corresponds to a cross-sectional view of some components of the part. Figures 12G to 12K , (c) is an enlarged cross-sectional view of a portion corresponding to the dotted line region indicated by "X2" in (a) of the corresponding figure. Figure 12L and Figure 12M In FIG. 1 , (c) is an enlarged plan view of a local area in the corresponding figure. FIG. 12A to FIG. 12N Describing the manufacturing process according to some example embodiments Figure 2A and Figure 2B The method of the IC device 100 shown in FIG.

[0097] refer to Fig. 12A , a device isolation trench T1 may be formed in the substrate 110 , and a device isolation film 112 may be formed in the device isolation trench T1 .

[0098] A plurality of active regions ACT may be defined by a device isolation film 112 in the substrate 110. The device isolation film 112 may include an oxide film, a nitride film, or a combination thereof.

[0099] A plurality of word line trenches T2 may be formed in the substrate 110. The plurality of word line trenches T2 may extend parallel to each other in the X direction and have a linear shape spanning the active area ACT. In order to form the plurality of word line trenches T2 having a stepped bottom surface, the device isolation film 112 and the substrate 110 may each be etched using a separate etching process so that the etching depth of the device isolation film 112 may be different from the etching depth of the substrate 110. The resulting structure including the plurality of word line trenches T2 may be cleaned, and a gate dielectric film 116, a word line 118, and a buried insulating film 120 may be sequentially formed in each of the plurality of word line trenches T2. Before or after forming the plurality of word lines 118, an ion implantation process may be performed to form a plurality of source and drain regions in the upper portion of the plurality of active areas ACT.

[0100] The gate dielectric film 116 may include at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO), or a high-k dielectric film having a higher dielectric constant than the silicon oxide film. The high-k dielectric film may include hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ) or a combination thereof. The plurality of word lines 118 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN) or a combination thereof. The plurality of buried insulating films 120 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film or a combination thereof.

[0101] A first insulating film 122 and a second insulating film 124 may be sequentially formed on the substrate 110. The first insulating film 122 and the second insulating film 124 may be formed to cover top surfaces of the plurality of active regions ACT, a top surface of the device isolation film 112, and top surfaces of the plurality of buried insulating films 120. In some embodiments, the first insulating film 122 may include a silicon oxide film, and the second insulating film 124 may include a silicon nitride film, but they are not limited thereto.

[0102] refer to Fig. 12B , a lower conductive layer 130 may be formed on the second insulating film 124. The lower conductive layer 130 may include doped polysilicon.

[0103] refer to Fig. 12C , a mask pattern MP1 may be formed on the lower conductive layer 130, and then the lower conductive layer 130 exposed through the opening MH of the mask pattern MP1 may be etched to expose a portion of the substrate 110 and a portion of the device isolation film 112. The exposed portion of the substrate 110 and the exposed portion of the device isolation film 112 may be etched to form a direct contact hole DCH exposing the active area ACT of the substrate 110. The mask pattern MP1 may include an oxide film, a nitride film, or a combination thereof.

[0104] refer to Fig.12D , can be obtained from Fig. 12C The mask pattern MP1 is removed from the resultant structure, and the direct contact part DC may be formed in the direct contact hole DCH.

[0105] To form the direct contact part DC, a conductive layer having a thickness sufficient to fill the direct contact hole DCH may be formed within the direct contact hole DCH and on the lower conductive layer 130 , and excess / unnecessary portions of the conductive layer may be removed so that the conductive layer may remain only within the direct contact hole DCH.

[0106] refer to Fig.12E , an intermediate conductive layer 132, an upper conductive layer 134, and a plurality of insulating capping patterns 136 may be sequentially formed on the lower conductive layer 130 and the direct contact portion DC. Each of the plurality of insulating capping patterns 136 may include a linear pattern extending in the Y direction.

[0107] refer to Fig.12F , the insulating capping pattern 136 may be used as an etching mask to etch a portion of each of the upper conductive layer 134, the middle conductive layer 132, the lower conductive layer 130, and the direct contact portion DC, thereby forming a plurality of bit lines BL on the substrate 110. The plurality of bit lines BL may include the remaining portions of each of the lower conductive layer 130, the middle conductive layer 132, and the upper conductive layer 134. After the plurality of bit lines BL are formed, a portion of the direct contact hole DCH may be exposed near the direct contact portion DC, and a linear space LS may be defined between the plurality of bit line structures, each of which includes the bit line BL and the insulating capping pattern 136, and may be elongated in the Y direction.

[0108] refer to Figure 12G , a boron-containing insulating film 140 may be formed to fill the remaining space of the direct contact hole DCH and cover the sidewalls of each of the plurality of bit lines BL, the plurality of insulating capping patterns 136, and the plurality of direct contact portions DC. The remaining space of the direct contact hole DCH may be completely filled with the boron-containing insulating film 140 near the direct contact portion DC.

[0109] The boron-containing insulating film 140 may have a dielectric constant of about 2 to 6. For example, the boron-containing insulating film 140 may have a dielectric constant of 3 to 5. In some embodiments, the boron-containing insulating film 140 may include a SiBN film. The boron content of the SiBN film included in the boron-containing insulating film 140 may be about 10 atomic percent (at%) to about 50 at%. For example, the boron-containing insulating film 140 may include Si x B y N z (0.1≤x≤0.5, 0.1≤y≤0.5, and 0.1≤z≤0.8).

[0110] The boron-containing insulating film 140 may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. For example, the boron-containing insulating film 140 may be formed using a plasma enhanced CVD (PECVD) process, a plasma pulsed CVD (PICVD) process, or a plasma enhanced ALD (PEALD) process. The boron-containing insulating film 140 including a SiBN film may be formed using a plasma deposition process so that boron (B) atoms may remain firmly bonded to nitrogen (N) atoms in the SiBN film.

[0111] In some embodiments, in order to form the boron-containing insulating film 140 including the SiBN film, a reaction between a silicon source and a nitrogen source may be induced in an atmosphere of a boron precursor. 2 H 6 ), borazine (B 3 N 3 H 6 ) or alkyl-substituted borazine derivatives can be used as boron precursors. Silane (SiH 4 ) or SiCl 4 gas as a silicon source, and ammonia (NH 3 ) gas as a nitrogen source. However, these precursors and gas sources are only examples, and the present inventive concept is not limited thereto.

[0112] In some embodiments, the boron content in the boron-containing insulating film 140 may be constant in the thickness direction of the boron-containing insulating film 140. In some embodiments, the boron content in the boron-containing insulating film 140 may vary in the thickness direction of the boron-containing insulating film 140.

[0113] During the formation of the boron-containing insulating film 140, the boron content or boron concentration of the boron-containing insulating film 140 may be controlled by adjusting the flow rate of the boron precursor. In some embodiments, the boron content in the boron-containing insulating film 140 may vary in the thickness direction of the boron-containing insulating film 140. For example, the boron content in the boron-containing insulating film 140 may increase toward the bottom surface of the boron-containing insulating film 140 (i.e., toward the inner wall of the direct contact hole DCH and the side wall of the direct contact portion DC), and decrease toward the top surface of the boron-containing insulating film 140. The boron content in the boron-containing insulating film 140 may be the highest in the portion in contact with the inner wall of the direct contact hole DCH and the portion in contact with the direct contact portion DC, and may be the lowest in the surface exposed in the linear space LS. In addition, in the portion of the boron-containing insulating film 140 covering the side wall of the bit line BL, the boron content in the boron-containing insulating film 140 may increase toward the bit line BL, and decrease toward the surface exposed in the linear space LS. Furthermore, in a portion of the boron-containing insulating film 140 covering the sidewall of the bit line BL, the nitrogen content in the boron-containing insulating film 140 may decrease toward the bit line BL, and may decrease toward the surface exposed in the linear space LS.

[0114] In some embodiments, in order to form a boron-containing insulating film 140 including a SiBN film, the flow rate of the boron precursor may be controlled to be relatively high in the initial stage of the process of depositing the boron-containing insulating film 140. As the process of depositing the boron-containing insulating film 140 proceeds, the flow rate of the boron precursor may be gradually reduced, and the flow rate of the nitrogen source may be gradually increased. Therefore, since the boron content of the boron-containing insulating film 140 increases toward the bottom surface of the boron-containing insulating film 140, the dielectric constant of the boron-containing insulating film 140 may decrease toward the bottom surface. On the contrary, since the boron content of the boron-containing insulating film 140 decreases toward the top surface of the boron-containing insulating film 140, the dielectric constant of the boron-containing insulating film 140 may increase toward the top surface. However, since the nitrogen content of the boron-containing insulating film 140 increases toward the top surface of the boron-containing insulating film 140, the dry etching resistance may increase toward the top surface of the boron-containing insulating film 140. Therefore, when as described below with reference to Figure 12L When the dry etching process is performed to remove a portion of the structure exposed by the plurality of contact spaces CS to form a plurality of recessed spaces R1, even if the boron-containing insulating fill pattern 140P formed using the boron-containing insulating film 140 is exposed to a dry etching atmosphere, the boron-containing insulating fill pattern 140P can be suppressed / prevented from being undesirably consumed due to the dry etching atmosphere.

[0115] refer to Fig.12H , can be obtained from Figure 12G The boron-containing insulating film 140 is isotropically etched from the resulting structure, thereby forming a boron-containing insulating fill pattern 140P including a remaining portion (after etching) of the boron-containing insulating film 140 .

[0116] In some embodiments, the isotropic etching process may be performed using phosphoric acid, sulfuric acid, a combination of phosphoric acid and sulfuric acid, a mixture of phosphoric acid and deionized water (DIW), a mixture of sulfuric acid and DIW, a mixture of phosphoric acid and fluoric acid, or a mixture of sulfuric acid and fluoric acid. The boron-containing insulating filling pattern 140P may include a portion of the boron-containing insulating film 140 filled within the direct contact hole DCH and a portion outside the entrance of the direct contact hole DCH covering the entrance of the direct contact hole DCH.

[0117] Referring to FIG. 121, a first insulating spacer layer 142 may be formed to conformally cover the exposed surfaces of each of the plurality of bit lines BL, the plurality of insulating capping patterns 136, and the boron-containing insulating filling pattern 140P. The first insulating spacer layer 142 may include a material having an etching selectivity relative to the boron-containing insulating filling pattern 140P. For example, the first insulating spacer layer 142 may include a silicon oxide film. The first insulating spacer layer 142 may be formed using a CVD process or an ALD process.

[0118] refer to Fig.12J , can be obtained from Fig.12I The first insulating spacer layer 142 is anisotropically etched to form a plurality of first insulating spacers 142S. Each of the plurality of first insulating spacers 142S may cover the sidewalls of the bit lines BL and the sidewalls of the insulating capping pattern 136 on the boron-containing insulating filling pattern 140P and the second insulating film 124. After the plurality of first insulating spacers 142S are formed, a portion of the boron-containing insulating filling pattern 140P may be exposed again.

[0119] refer to Figure 12K , a second insulating spacer 144 may be formed to conformally cover Fig.12J The second insulating spacer 144 may include a material having an etching selectivity with respect to each of the first insulating spacer layer 142 and the boron-containing insulating filling pattern 140P. For example, the second insulating spacer 144 may include a silicon nitride film. The second insulating spacer 144 may be formed using a CVD process or an ALD process.

[0120] refer to Figure 12L , a plurality of insulating fences 148 may be formed between the respective bit lines BL and spaced apart from each other, so that the line-shaped space LS defined by the second insulating spacer 144 may be divided into a plurality of contact spaces CS.

[0121] Each of the plurality of insulating fences 148 may be formed to overlap the word line 118 in a vertical direction on the word line 118. The plurality of insulating fences 148 may include a silicon nitride film. In some embodiments, during the formation of the plurality of insulating fences 148, a portion of the plurality of insulating capping patterns 136 may be consumed, thereby reducing the height of the plurality of insulating capping patterns 136.

[0122] Thereafter, a portion of the structure exposed by the plurality of contact spaces CS may be removed, thereby forming a plurality of recess spaces R1 exposing the active area ACT of the substrate 110 between the respective bit lines BL.

[0123] The plurality of recessed spaces R1 may be formed using an anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process. For example, in a structure in which the plurality of contact spaces CS are exposed between the bit lines BL, the second insulating spacer 144, the second insulating film 124, and the first insulating film 122 may be anisotropically etched sequentially. As a result, a portion of the active area ACT of the substrate 110 may be exposed, and the exposed portion of the active area ACT may be etched to form the plurality of recessed spaces R1. The plurality of recessed spaces R1 may be connected (i.e., connected) to the contact spaces CS, respectively. The active area ACT of the substrate 110 and the boron-containing insulating filling pattern 140P may be exposed through the plurality of recessed spaces R1.

[0124] refer to Figure 12M , a plurality of contact plugs 150 may be formed between the bit lines BL to fill the plurality of recess spaces R1 and a portion of the plurality of contact spaces CS between the bit lines BL.

[0125] A vertical distance from the top surface of the substrate 110 to the top surface of each of the plurality of contact plugs 150 may be greater than a vertical distance from the top surface of the substrate 110 to the top surface of each of the plurality of bit lines BL.

[0126] refer to Fig.12N , can be achieved through the multiple contact spaces CS (see Figure 12M ) A metal silicide film 172 and a plurality of conductive landing pads LP are sequentially formed on the plurality of contact plugs 150 exposed by the step of forming the metal silicide film 172.

[0127] The contact plug 150 and the metal silicide film 172 may constitute Figure 1 The plurality of conductive landing pads LP may extend to the upper portion of the insulating capping pattern 136 to fill the plurality of contact spaces CS on the metal silicide film 172 and overlap with a portion of the plurality of bit lines BL in a vertical direction. The plurality of conductive landing pads LP may include a conductive barrier film 174 and a conductive layer 176.

[0128] In order to form the plurality of conductive landing pads LP, a conductive barrier film 174 and a conductive layer 176 may be formed on the entire surface of the resulting structure including the metal silicide film 172. Thereafter, a mask pattern may be formed on the conductive layer 176 to expose a portion of the conductive layer 176. The conductive layer 176, the conductive barrier film 174, and an insulating film thereabout may be etched using the mask pattern as an etching mask, thereby forming an upper recessed space R2. The mask pattern may include a silicon nitride film, but is not limited thereto.

[0129] The plurality of conductive landing pads LP may be formed into a plurality of island-shaped patterns. Parts of the plurality of conductive landing pads LP extending in the horizontal direction outside the contact space CS may constitute Figure 1 The multiple conductive landing pads LP shown in FIG.

[0130] The upper recess space R2 may be filled with an insulating film 180 near the plurality of conductive landing pads LP so that the plurality of conductive landing pads LP may be electrically insulated from each other. Thereafter, a plurality of capacitor lower electrodes may be formed on the insulating film 180 and may be electrically connected to the plurality of conductive landing pads LP.

[0131] To manufacture Figure 3A and Figure 3B The IC device 100A shown can be used with reference Fig.12NThe plurality of conductive landing pads LP are formed by the process described above. Thereafter, the plurality of first insulating spacers 142S may be removed through the upper recess space R2 using a wet etching process before the upper recess space R2 is filled with the insulating film 180. Thus, air spacers AS1 may be formed between the bit lines BL and the second insulating spacers 144.

[0132] FIG. 13A to FIG. 13D A cross-sectional view showing a process sequence of a method for manufacturing an IC device according to an embodiment. FIG. 13A to FIG. 13D In (a), the process sequence is based on the Figure 1 The cross-sectional view of some parts corresponding to the cross-sectional view taken along the line AA' of FIG. 1 is a cross-sectional view of some parts corresponding to the cross-sectional view taken along the line AA' of FIG. 1 , and (b) is a cross-sectional view of some parts corresponding to the cross-sectional view taken along the line AA' of FIG. 1 according to the process sequence. Figure 1 (c) is a cross-sectional view of some parts of the portion corresponding to the cross section taken along the line BB' of the corresponding figure, and (c) is an enlarged cross-sectional view of the portion corresponding to the dotted line area indicated by "X2" in (a) of the corresponding figure. FIG. 13A to FIG. 13D Describing the manufacturing process according to some example embodiments Figure 4A and Figure 4B The method of the IC device shown in FIG. FIG. 13A to FIG. 13D In, with Figure 4A , Figure 4B and FIG. 12A to FIG. 12N The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0133] refer to Fig.13A , you can execute reference FIG. 12A to FIG. 12F The process is described to form a plurality of bit lines BL on the substrate 110. Thereafter, an inner insulating film 242 may be formed to conformally cover the plurality of bit lines BL, the plurality of insulating capping patterns 136, exposed surfaces of the respective direct contacts DC, inner walls of the direct contact holes DCH, and the top surface of the second insulating film 124.

[0134] Subsequently, you can use the Figure 12G The boron-containing insulating film 140 is formed on the inner insulating film 242 in a similar manner as described above. The remaining space of the direct contact hole DCH may be completely filled with the boron-containing insulating film 140 near the direct contact portion DC. The thickness of the inner insulating film 242 may be smaller than that of the boron-containing insulating film 140.

[0135] refer to Fig. 13B , can be used with reference Fig.12H A similar approach is described from Fig.13A The boron-containing insulating film 140 is isotropically etched to form a boron-containing insulating filling pattern 140P including a remaining portion (after etching) of the boron-containing insulating film 140. The boron-containing insulating filling pattern 140P may be separated from the direct contact portion DC with the inner insulating film 242 therebetween.

[0136] refer to Fig. 13C , can be used with reference Fig.12I and Fig.12J In a similar manner to the method described above, a plurality of first insulating spacers 142S are formed on the boron-containing insulating filling pattern 140P and the inner insulating film 242 to cover the sidewalls of the bit lines BL and the insulating capping pattern 136. The plurality of first insulating spacers 142S may be separated from the bit lines BL and the insulating capping pattern 136 with the inner insulating film 242 therebetween.

[0137] As reference Fig.12J As described above, the plurality of first insulating spacers 142S may be formed by anisotropically etching the first insulating spacer layer 142. Thereafter, the portion of the inner insulating film 242 covering the top surface of the insulating capping pattern 136 and exposed on the bottom of the plurality of linear spaces LS may be continuously etched to expose the top surface of the insulating capping pattern 136, the top surface of the second insulating film 124, and the top surface of the boron-containing insulating filling pattern 140P.

[0138] refer to Fig.13D , can be Fig. 13C The resulting structure is implemented as follows: Figures 12K to 12N Thus, the second insulating spacer 144 may be formed to cover the plurality of first insulating spacers 142S, a plurality of insulating fences 148, a plurality of contact plugs 150, a plurality of metal silicide films 172, and a plurality of conductive landing pads LP may be formed, and an insulating film 180 may be formed to fill the upper recessed space R2. Thus, the Figure 4A and Figure 4B The IC device 200 shown in FIG.

[0139] To manufacture Figure 5A and Figure 5B The IC device 200A shown in FIG. Figure 6 The IC device 200B shown in FIG. Fig.13D After forming the plurality of conductive landing pads LP by the process described above and before filling the upper recessed space R2 with the insulating film 180, the plurality of first insulating spacers 142S and the inner insulating film 242 may be removed through the upper recessed space R2 using a wet etching process so that air spacers AS21 may be formed between the bit lines BL and the second insulating spacers 144. During the wet etching process for forming the air spacers AS21, portions of the inner insulating film 242 between the direct contact portion DC and the boron-containing insulating filling pattern 140P may be removed so that the air spacers AS21 may be formed. Figure 5AThe gap air portion G21 shown in FIG. 1 is removed, and the inner insulating film 242G1 may remain near the boron-containing insulating filling pattern 140P. In addition, the removal amount of the inner insulating film 242 between the direct contact portion DC and the boron-containing insulating filling pattern 140P may be adjusted during the wet etching process so that the inner insulating film 242G1 may remain near the boron-containing insulating filling pattern 140P. Figure 6 The air spacer AS22 including the gap air portion G22 and the inner insulating film 242G2 remain as in the illustrated IC device 200B.

[0140] FIG. 14A to FIG. 14E FIG. 1 is a process sequence diagram of a method for manufacturing an IC device according to an embodiment. FIG. 14A to FIG. 14E In (a), the process sequence is based on the Figure 1 (a) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A', and (b) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A' according to the process sequence. Figure 1 The cross-section taken along the line BB' corresponds to a cross-sectional view of some components of the part. Fig. 14B , Fig.14D and Fig.14E In the figure, (c) is an enlarged plan view of a local area in the corresponding figure. FIG. 14A to FIG. 14E Describing the manufacturing process according to some example embodiments Fig. 7A and Figure 7B The method of the IC device 300 shown in FIG. FIG. 14A to FIG. 14E In, with Fig. 7A , Figure 7B and FIG. 12A to FIG. 12N The same reference numerals are used to denote the same elements, and their description will not be repeated.

[0141] refer to Fig.14A , you can execute reference FIG. 12A to FIG. 12G The process is described to form the boron-containing insulating film 140 on the substrate 110. Thereafter, an interlayer insulating film 340 may be formed to fill the line-shaped space LS between the plurality of bit line structures, each of which includes a bit line BL and an insulating capping pattern 136.

[0142] In some embodiments, the interlayer insulating film 340 may include a silicon oxide film. In the process of forming the interlayer insulating film 340 according to an embodiment, a polysilazane-based insulating film may be formed using a CVD process or a spin-on-glass (SOG) coating process to fill the linear space LS (see Figure 12G ). Thereafter, the polysilazane-based insulating film may be annealed at a temperature of about 300° C. to about 600° C. and densified due to a cross-linking reaction of a silicon-oxygen-silicon (Si-O-Si) network, thereby forming a silicon oxide film. During the annealing of the polysilazane-based insulating film, the boron-containing insulating film 140 may serve to suppress / prevent oxidation of the plurality of bit lines BL.

[0143] refer to Fig. 14B, can be Fig.14A A planarization process is performed on the top surface of the resulting structure, so that a portion of each of the interlayer insulating film 340 and the boron-containing insulating film 140 can be removed, and the top surface of each insulating capping pattern 136 can be exposed. Next, a portion of the interlayer insulating film 340 can be removed to empty a local area of ​​the linear space LS between the respective bit lines BL. Thereafter, a plurality of insulating fences 348 can be formed to fill the empty local areas of the linear space LS.

[0144] refer to Fig. 14C , can be obtained from Fig. 14B The interlayer insulating film 340 remaining between the plurality of bit lines BL is removed from the resulting structure, so that contact spaces CS can be prepared between the respective insulating fences 348. The boron-containing insulating film 140 can be exposed through the plurality of contact spaces CS defined by the plurality of insulating fences 348 between the respective bit lines BL. Thereafter, the boron-containing insulating film 140 exposed through the plurality of contact spaces CS can be isotropically etched to form a boron-containing insulating filling pattern 140P, which exposes the sidewalls of each of the plurality of bit lines BL and the plurality of insulating capping patterns 136 in the plurality of contact spaces CS and covers the two (i.e., opposite) sidewalls of the direct contact portion DC.

[0145] After forming the boron-containing insulating filling pattern 140P, a portion of the boron-containing insulating film 140 between the bit line structure including the bit line BL and the insulating capping pattern 136 and the plurality of insulating fences 348 may remain as a boron-containing insulating fence 140F. Each of the boron-containing insulating fences 140F may have a substantially U-shaped cross-sectional shape to cover the bottom surface and two (i.e., opposite) sidewalls of the insulating fence 348.

[0146] refer to Fig.14D , a silicon oxide film and a silicon nitride film may be formed sequentially to conformally cover Fig. 14C The resulting structure. Thereafter, the silicon oxide film and the silicon nitride film may be anisotropically etched to form first insulating spacers 342S and second insulating spacers 344 in the plurality of contact spaces CS, respectively. The first insulating spacer 342S may include a remaining portion of the silicon oxide film, and the second insulating spacer 344 may include a remaining portion of the silicon nitride film. Each of the first insulating spacer 342S and the second insulating spacer 344 may have a ring shape and conformally cover the inner wall of the contact space CS.

[0147] Afterwards, you can use the Figure 12LA portion of the structure exposed by the plurality of contact spaces CS is removed by a method similar to the method described above, thereby forming a plurality of recessed spaces R1 that expose the active area ACT of the substrate 110. The plurality of recessed spaces R1 may be connected to (i.e., connected to) the contact spaces CS, respectively. The active area CT of the substrate 110 and the boron-containing insulating filling pattern 140P may be exposed by the plurality of recessed spaces R1.

[0148] refer to Fig.14E , by using the reference Figures 12M to 12N The method described above can form a plurality of contact plugs 150, a plurality of metal silicide films 172, a plurality of conductive landing pads LP, and an insulating film 180 filling the upper recessed space R2. Fig. 7A and Figure 7B The IC device 300 shown in FIG.

[0149] In order to form Fig. 8A and Figure 8B The IC device 300A shown in FIG. Fig.14E After the described process forms a plurality of conductive landing pads LP and before filling the upper recessed space R2 with the insulating film 180, a wet etching process can be used to remove the plurality of first insulating spacers 342S through the upper recessed space R2, so that air spacers AS3 can be formed between the bit lines BL and the second insulating spacers 344 and between the insulating fences 348 and the second insulating spacers 344.

[0150] FIG. 15A to FIG. 15E FIG. 1 is a process sequence diagram of a method for manufacturing an IC device according to an embodiment. FIG. 15A to FIG. 15E In (a), the process sequence is based on the Figure 1 (a) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A', and (b) is a cross-sectional view of some components of the section corresponding to the section taken along the line A-A' according to the process sequence. Figure 1 The cross-section taken along the line BB' corresponds to a cross-sectional view of some components of the part. Fig.15A , (c) is an enlarged cross-sectional view of a portion corresponding to the dotted line region indicated by "X2" in (a). Fig. 15B , Fig.15D and Fig.15E In the figure, (c) is an enlarged plan view of a local area in the corresponding figure. FIG. 15A to FIG. 15E Describing the manufacturing process according to some example embodiments Fig.9A and Fig. 9B The method of the IC device 400 shown in FIG.

[0151] refer to Fig.15A , you can execute reference FIG. 12A to FIG. 12F The process described above is used to form a plurality of bit lines BL on the substrate 110. Next, the same process as in reference Fig.13AThe inner insulating film 242 and the boron-containing insulating film 140 are formed by a method similar to the method described in Fig.14A In a similar manner to the described method, the interlayer insulating film 340 is formed to cover the boron-containing insulating film 140 .

[0152] refer to Fig. 15B , can be used with reference Fig. 14B A portion of the interlayer insulating film 340 is removed in a method similar to the described method, and then a plurality of insulating fences 348 may be formed on the boron-containing insulating film 140 to fill partial regions of the line-shaped spaces LS.

[0153] refer to Fig. 15C , can be used with reference Fig. 14C A similar approach is described from Fig. 15B The interlayer insulating film 340 remaining between the plurality of bit lines BL is removed from the resulting structure. Thereafter, the boron-containing insulating film 140 exposed through the plurality of contact spaces CS may be isotropically etched to form a boron-containing insulating filling pattern 140P, which may expose the inner insulating film 242 in the plurality of contact spaces CS and cover the two (i.e., opposite) side walls of the direct contact portion DC. A portion of the boron-containing insulating film 140 may remain (after etching) as a boron-containing insulating fence 140F covering the bottom surface and two (i.e., opposite) side walls of the insulating fence 348.

[0154] refer to Fig.15D , can be used with reference Fig.14D A first insulating spacer 342S and a second insulating spacer 344 are formed in each of the plurality of contact spaces CS in a similar manner as described above. Thereafter, a portion of the structure exposed by the plurality of contact spaces CS may be removed to form a plurality of recess spaces R1 exposing the active area ACT of the substrate 110.

[0155] refer to Fig.15E , can be obtained by using Figure 12M and Fig.12N A plurality of contact plugs 150, a plurality of metal silicide films 172, a plurality of conductive landing pads LP and an insulating film 180 filling the upper recessed space R2 are formed in a similar manner to the method described above. Fig.9A and Fig. 9B An IC device 400 is shown.

[0156] To manufacture Fig. 10A and Fig. 10B The IC device 400A and Fig.11 The IC device 400B shown in FIG. Fig.15EAfter forming the plurality of conductive landing pads LP by the process described above and before filling the upper recessed space R2 with the insulating film 180, the plurality of inner insulating films 242 and the plurality of first insulating spacers 342S may be removed through the upper recessed space R2 using a wet etching process. Thus, air spacers AS41 may be formed between the bit lines BL and the second insulating spacers 344 and between the insulating fences 348 and the second insulating spacers 344. During the wet etching process for forming the air spacers AS41, portions of the inner insulating film 242 between the direct contact portion DC and the boron-containing insulating filling pattern 140P may be removed so that the air spacers AS41 may be formed. Fig. 10A The gap air portion G41 shown in FIG. 1 is formed by removing the inner insulating film 242G4 from the direct contact portion DC and the boron-containing insulating filling pattern 140P. In addition, the amount of the inner insulating film 242 removed between the direct contact portion DC and the boron-containing insulating filling pattern 140P can be adjusted during the wet etching process so that the inner insulating film 242G4 can be removed as shown in FIG. Fig.11 As in the illustrated IC device 400B, the air spacer AS42 including the gap air portion G42 and the inner insulating film 242G5 remain.

[0157] Although referenced FIG. 12A to FIG. 15E A method of manufacturing an IC device according to an exemplary embodiment of the inventive concept is shown and described, but it should be understood that various changes in form and details may be made within the scope of the inventive concept and may be as described with reference to FIG. 12A to FIG. 15E The IC devices with various modifications and changes are manufactured.

[0158] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the claims.

Claims

1. An integrated circuit device, comprising: a substrate including a first active region and a second active region spaced apart from each other; A bit line extending in a horizontal direction on the substrate; a direct contact portion connected between the first active region and the bit line; a contact plug extending in a vertical direction on the substrate, the contact plug comprising an upper portion adjacent to the bit line and a lower portion contacting the second active region in the substrate; a boron-containing insulating pattern between a lower portion of the contact plug and the direct contact portion; as well as An insulating fence extends in a vertical direction on the substrate, and the insulating fence is aligned with the contact plug in the horizontal direction.

2. The integrated circuit device according to claim 1, wherein: The boron-containing insulating pattern includes a silicon boron nitride SiBN film having a dielectric constant of 2 to 6.

3. The integrated circuit device according to claim 1, in, The boron-containing insulating pattern includes Si x B y N z , Among them, 0.1≤x≤0.5, 0.1≤y≤0.5, and 0.1≤z≤0.

8.

4. The integrated circuit device according to claim 1, wherein: A lower portion of the contact plug and the direct contact portion are in contact with the boron-containing insulating pattern.

5. The integrated circuit device according to claim 1, further comprising: an insulating region between a lower portion of the contact plug and the boron-containing insulating pattern and between the direct contact portion and the boron-containing insulating pattern, Wherein, the dielectric constant of the insulating region is lower than the dielectric constant of the boron-containing insulating pattern.

6. The integrated circuit device according to claim 5, wherein: The insulating region includes a silicon oxide film, an air spacer, or a combination thereof.

7. The integrated circuit device according to claim 1, wherein: The boron-containing insulating pattern is buried in the substrate.

8. The integrated circuit device according to claim 1, further comprising: The boron-containing insulating fence on the sidewall of the bit line, The boron content in the boron-containing insulating fence increases toward the bit line.

9. The integrated circuit device according to claim 1, further comprising: a first insulating spacer and a second insulating spacer between the contact plug and the bit line on the boron-containing insulating pattern, the first insulating spacer and the second insulating spacer comprising different respective materials, Wherein each of the first insulating spacer and the second insulating spacer does not contain boron.

10. The integrated circuit device according to claim 9, wherein: Each of the first insulating spacer and the second insulating spacer extends parallel to the bit line.

11. The integrated circuit device according to claim 9, wherein: The first insulating spacer and the second insulating spacer extend between the bit line and the insulating fence.

12. The integrated circuit device according to claim 9, wherein: Each of the first insulating spacer and the second insulating spacer surrounds a periphery of the contact plug.

13. The integrated circuit device according to claim 9, in, The first insulating spacer and the second insulating spacer extend between the contact plug and the insulating fence.

14. The integrated circuit device according to claim 13, further comprising: A boron-containing insulating fence is provided between the bit line and the insulating fence.

15. An integrated circuit device comprising: a substrate including a plurality of active regions spaced apart from one another; A bit line extending in a horizontal direction on the substrate; a plurality of contact plugs spaced apart from one another on the substrate along horizontal lines parallel to the bit lines; a plurality of insulating fences, alternating with the plurality of contact plugs in the horizontal direction; a direct contact portion connected between a first active region among the plurality of active regions and the bit line; as well as A boron-containing insulating pattern is between a first contact plug among the plurality of contact plugs and the direct contact portion.

16. The integrated circuit device according to claim 15, in, The first contact plug contacts a second active region among the plurality of active regions in the substrate, and Wherein, both the first contact plug and the direct contact portion are in contact with the boron-containing insulating pattern.

17. The integrated circuit device of claim 15, further comprising: an insulating film between the direct contact portion and the boron-containing insulating pattern and between the first contact plug and the boron-containing insulating pattern, Wherein, the dielectric constant of the insulating film is lower than the dielectric constant of the boron-containing insulating pattern.

18. The integrated circuit device of claim 15, further comprising: A plurality of boron-containing insulating fences are between the bit lines and the plurality of insulating fences.

19. The integrated circuit device of claim 15, further comprising: A first insulating spacer and a second insulating spacer extend between the bit line and the plurality of contact plugs along the horizontal direction and between the bit line and the plurality of insulating fences, the first insulating spacer and the second insulating spacer comprising different respective materials.

20. The integrated circuit device of claim 15, further comprising: A plurality of first insulating spacers and a plurality of second insulating spacers are provided between the bit lines and the plurality of contact plugs and between the plurality of contact plugs and the plurality of insulating fences, the plurality of first insulating spacers and the plurality of second insulating spacers surrounding respective perimeters of the plurality of contact plugs.

21. An integrated circuit device comprising: a substrate including a plurality of active regions; A bit line extending in a horizontal direction on the substrate; a direct contact portion connected between a first active region among the plurality of active regions and the bit line; a first contact plug and a second contact plug facing each other, wherein the bit line is between the first contact plug and the second contact plug, wherein the first contact plug and the second contact plug are respectively connected to a second active region and a third active region of the plurality of active regions; a first insulating fence and a second insulating fence facing each other, wherein the bit line is between the first insulating fence and the second insulating fence; and a plurality of boron-containing insulating patterns, including a first boron-containing insulating pattern between the direct contact portion and the first contact plug and a second boron-containing insulating pattern between the direct contact portion and the second contact plug, Wherein, each of the plurality of boron-containing insulating patterns includes a silicon boron nitride SiBN film.

22. The integrated circuit device according to claim 21, in, The dielectric constant of each of the plurality of boron-containing insulating patterns is 2 to 6, and Wherein, the boron content in the plurality of boron-containing insulating patterns increases toward the direct contact portion.

23. The integrated circuit device according to claim 21, in, The first contact plug contacts the second active region and the first boron-containing insulating pattern, and The second contact plug is in contact with the third active region and the second boron-containing insulating pattern.

24. The integrated circuit device of claim 21, further comprising: an insulating film between the direct contact portion and the first boron-containing insulating pattern and between the direct contact portion and the second boron-containing insulating pattern, The dielectric constant of the insulating film is lower than the dielectric constant of at least one of the first boron-containing insulating pattern or the second boron-containing insulating pattern.

25. The integrated circuit device of claim 21, further comprising: A plurality of boron-containing insulating fences include a first boron-containing insulating fence between the bit line and the first insulating fence and a second boron-containing insulating fence between the bit line and the second insulating fence.

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