Sub-device field effect transistor architecture for integrated circuits

Abstract

Embodiments of this disclosure relate to sub-device field-effect transistor architectures for integrated circuits. This disclosure describes various aspects of sub-device field-effect transistor architectures for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented using multiple FET sub-devices. During operation, the source-side FET sub-devices of the integrated FET can operate in a linear region rather than a saturation region. Operating in the linear region, the source-side FET sub-devices of the integrated FET can exhibit lower threshold voltage or current sensitivity than other drain-side FET sub-devices operating in saturation. The device layout of the integrated FET can be designed such that less sensitive source-side FET sub-devices surround or protect other more sensitive drain-side sub-devices from random variations or density issues at the edges of the device layout. By doing so, the threshold voltage or current sensitivity of the integrated FET can be reduced, thereby improving the matching between the integrated FET devices.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to U.S. Provisional Patent Application No. 62 / 720,814, filed August 21, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a sub-device field-effect transistor architecture for use in integrated circuits. Background Technology

[0004] In analog circuit design, semiconductor devices are often matched to ensure that individual devices function similarly to guarantee the correct operation of the analog circuit. By designing each semiconductor device with a substantially similar scale and configuration, semiconductor devices in analog circuits are often matched to minimize differences between devices (e.g., threshold voltage). However, as semiconductor technology scales to smaller devices, meeting semiconductor device matching requirements becomes increasingly difficult due to process limitations (such as those associated with photolithography, etching, and chemical mechanical planarization). When semiconductor devices exhibit mismatched characteristics due to stochastic process or manufacturing variability that designers have failed to address, the performance of the semiconductor devices deteriorates, or the function of the circuit is compromised. Summary of the Invention

[0005] This summary is provided to introduce the subject matter further described in the detailed specification and drawings. Accordingly, this summary should not be construed as describing essential features or used to limit the scope of the claimed subject matter.

[0006] This disclosure relates to a sub-device field-effect transistor (FET) architecture for integrated circuits, which may include analog or mixed-signal circuitry. In some aspects, circuitry is implemented using an integrated field-effect transistor formed by or utilizing multiple FET sub-devices. The multiple FET sub-devices may be stacked (e.g., drain-to-source) and have respective gates coupled together. During operation, some source-side FET sub-devices of the integrated FET may operate in a linear region rather than a saturation region. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit a lower threshold voltage or current sensitivity than other FET sub-devices operating in saturation. The device layout of the integrated FET can be designed or optimized such that the less sensitive source-side FET sub-devices surround, shield, or protect other more sensitive sub-devices (e.g., drain-side) of the integrated FET from random variations in device layout edges or density issues. By doing so, the threshold voltage or current sensitivity of the integrated FET can be reduced, thereby improving the matching between the integrated FET devices.

[0007] In some aspects, one method utilizes FET sub-devices to form an integrated FET and includes forming a substrate for the FET sub-devices used in the integrated FET. The method then forms a first set of FET sub-devices for the integrated FET on the substrate. A first FET sub-device of the first set of FET sub-devices is coupled to the drain terminal of the integrated FET. A second set of FET sub-devices for the integrated FET is also formed on the substrate, wherein a second FET sub-device of the second set of FET sub-devices is coupled to the source terminal of the integrated FET. The first set of FET sub-devices is formed on an inner portion of the substrate region on which the integrated FET is formed. Furthermore, the second set of FET sub-devices may be formed near the periphery of the substrate region on which the integrated FET is formed.

[0008] In other aspects, an integrated circuit includes: a substrate having a surface; and an integrated field-effect transistor (FET) comprising an array of FET sub-devices formed on the surface of the substrate. The array of FET sub-devices includes a first group of FET sub-devices with corresponding gate terminals coupled to the gate terminals of the integrated FET, and a drain FET sub-device coupled to a drain terminal of the integrated FET. The array of FET sub-devices also includes a second group of FET sub-devices with corresponding gate terminals coupled to the gate terminals of the integrated FET, and a source FET sub-device coupled to a source terminal of the integrated FET. The array of FET sub-devices is formed on the surface of the substrate such that the second group of FET sub-devices is disposed around at least three sides of a substrate region on which the first group of FET sub-devices is disposed.

[0009] In another aspect, one method provides current via a power rail to the source terminal of an integrated FET formed by a plurality of FET sub-devices. The method then applies a voltage to the gate terminal of the integrated FET to operate a first set of the plurality of FET sub-devices in a linear mode and a second set of the plurality of FET sub-devices in a saturation mode. Based on the voltage applied to the gate terminal, at least a portion of the current is provided to the drain terminal of the integrated FET via the first and second sets of the plurality of FET sub-devices.

[0010] Details of one or more implementations are set forth in the accompanying drawings and the following description. Other features and advantages will become apparent from the specification, drawings, and claims. Attached Figure Description

[0011] Details of one or more implementations of the field-effect transistor (FET) architecture for use in integrated circuits are set forth in the accompanying drawings and the following detailed description. In the drawings, the leftmost digit of the reference number identifies the first drawing in which that reference number appears. The same reference numerals used in different instances of the specification and drawings denote the same elements:

[0012] Figure 1 The figure illustrates an example operating environment with integrated circuits, in which FET sub-devices are implemented.

[0013] Figure 2 The figure illustrates an example layout of a FET sub-device based on one or more aspects of an integrated FET.

[0014] Figure 3 The figure shows an example configuration of a current mirror implemented using a FET sub-device architecture.

[0015] Figure 4 The diagram illustrates the use of one or more aspects. Figure 3 Example layout of multiple arrays of FET sub-devices in the current mirror.

[0016] Figure 5 An example method for forming an integrated FET sub-device on a substrate is described.

[0017] Figure 6 An example method for operating an integrated FET to provide current via multiple FET sub-devices is described.

[0018] Figure 7 The layout of an array for arranging FET sub-devices is described to provide an example method for integrating FET devices.

[0019] Figure 8 The diagram illustrates an example system-on-chip (SoC) environment in which various aspects of the sub-device FET architecture can be implemented.

[0020] Figure 9 The figure illustrates an example computing device in which FET sub-devices are implemented, depending on one or more aspects. Detailed Implementation

[0021] Traditional techniques for managing device mismatch typically rely on scaling the layout of individual devices to the maximum feasible size to minimize variations in the corresponding sizes of two devices. Often, differences in semiconductor regions or geometries between devices due to process variations further exacerbate the mismatch. Specifically, for a given process technology with some mismatch capability, designers typically choose to maximize transistor width and length to achieve a certain level of mismatch capability. VT A device that achieves better matching on the curve, A VT Delta V based on the classic Pelgrom model T The slope of the graph of sigma (threshold voltage) relative to the reciprocal of the square root of WL. As the size of each device increases, it is believed that the percentage change in gate length is better when the device length is maximized.

[0022] However, as semiconductor technology scales to smaller devices, the limitations of traditional technologies become apparent. As mentioned above, meeting the device-matching requirements for advanced analog designs is increasingly difficult due to process limitations associated with photolithography, etching, and chemical mechanical planarization processes. This problem is particularly relevant to advanced FinFETs, where scaling up process technology can significantly reduce the effectiveness of traditional, maximum geometry-based technologies. For example, utilizing nanoscale devices where the silicon substrate is virtually undoped (e.g., FinFETs), A VT Increasingly affected by fluctuations in metal gate work function settings, thickness, composition, etc. These are powerful features of device pattern density used for circuit layout, and, in contrast to multi-gate line edge roughness (LER), their effect tends to be averaged for longer transistors.

[0023] Traditional techniques also fail to effectively address the issues associated with device pattern density because they rely on virtual patterns that consume valuable placement areas. In this approach, non-functional or virtual patterned devices are placed around the actual circuitry, allowing pattern density to be controlled across critical blocks. While this method may have addressed circuit density issues in different areas of the chip, the use of virtual devices is no longer efficient or effective for devices manufactured using current process technologies. The main problem with virtual devices is the low utilization of placement areas and poor mismatch due to the failure of virtual placement techniques to keep pace with newer processing technologies. Another issue is that the post-CMP metal gate work function is a function of metal thickness, which can lead to larger pattern density variations when analog designers use arbitrarily large device sizes (width / length). Therefore, traditional methods of increasing device size typically produce large pattern density variations, resulting in poor VL. T (Threshold voltage) mismatch. As a result, these traditional techniques for managing device mismatch are no longer effective, especially for advanced process technologies that realize metal gate devices.

[0024] In contrast to conventional techniques, this disclosure describes aspects of a sub-device field-effect transistor (FET) architecture for integrated circuits. In some aspects, the circuit is implemented using an integrated FET, which is formed by or utilizes multiple FET sub-devices. The multiple FET sub-devices can be stacked (e.g., drain-to-source) and can have corresponding gates coupled together. During operation, some source-side FET sub-devices of the integrated FET can operate in the linear region rather than in the saturation region. Operating in the linear region, the source-side FET sub-devices of the integrated FET can exhibit lower threshold voltage or current sensitivity than other FET sub-devices operating in the saturation region. The device layout of the integrated FET can be designed or optimized such that the less sensitive source-side FET sub-devices surround, shield, or protect other more sensitive FET sub-devices (e.g., drain-side) of the integrated FET from random variations or density issues at the device layout edges. By doing so, the threshold voltage or current sensitivity of the integrated FET can be reduced, thereby improving the matching between the integrated FET devices.

[0025] By reviewing the data, we recall that metal-oxide-semiconductor field-effect transistors (MOSFETs) have three main operating modes: cutoff, linear, and saturation. By examining the drain current and current sensitivity for each mode in turn, it becomes clear that various aspects of the FET architecture for integrated circuits can reduce threshold voltage sensitivity and improve matching for analog circuits. Specifically, the threshold voltage for a given transistor in saturation mode... The current sensitivity is greater than the current sensitivity of a given transistor at its threshold voltage in linear mode.

[0026] Referring to the following equation illustrating MOSFET operating modes, variables are defined with reference to the voltage and current at the MOSFET terminals, where W / L is the ratio of transistor geometry (width / length) and k′ n These are process transmission parameters.

[0027] V GS -V T <0, I D =0

[0028] Formula 1: MOSFET drain current in the cutoff region.

[0029] V GS -V T <V DS

[0030]

[0031] Formula 2: MOSFET drain current in the linear region (resistive).

[0032] 0 < VGS -V T <V DS

[0033]

[0034] Formula 3: MOSFET drain current in the saturation region.

[0035] Based on Equations 1-3, we observe the following current sensitivity for different operating modes:

[0036]

[0037]

[0038] Formula 4: In the linear region, for V t Current sensitivity.

[0039]

[0040]

[0041] Formula 5: In the saturation region, for V t Current sensitivity.

[0042]

[0043] Formula 6: Current sensitivity ratio between the saturation region and the linear region.

[0044] As shown in Equation 6, the ratio of current sensitivity in the saturation region to current sensitivity in the linear region is greater than 1, because in the linear region V gs -V t Greater than V ds Therefore, devices operating in the saturation region are sensitive to V. t Changes are more easily or more sensitive, such as those associated with uncertainties in the layout environment for devices. Conversely, devices operating in the linear region are more sensitive to V. t Their low sensitivity to change makes these devices less susceptible to environmental uncertainties or layout density issues.

[0045] This can be achieved by arranging FET sub-devices of an integrated FET to protect a more sensitive drain-side FET sub-device by utilizing a source-side FET sub-device that can operate in linear mode. For example, when designing a current mirror circuit, the drain-side FET sub-device can be placed at the center of the current mirror layout array, with other source-side FET sub-devices placed at or around the array edges. By doing so, the more sensitive drain-side FET sub-device that can operate in the saturation region can be protected by source-side FET sub-devices arranged similarly at the array edges.

[0046] These source-side FET sub-devices can operate in linear regions and are therefore less susceptible to random environmental variations around the array. While edge devices may be exposed to a more random external environment in the final layout, these devices eliminate the need for dummy devices, saving valuable design area and cost. Effectively, due to the low current-to-threshold voltage sensitivity of the source-side FET sub-devices, the effects of environmental variations can be minimized by using edge devices to “self-virtually” virtualize the current mirror array. Examples of this layout of the sub-device FET architecture, as well as others, are described throughout this disclosure. In at least some aspects, analog circuit layouts with FET sub-devices can be created and used for optimized device mismatches for a given area budget for cost and / or power. The concepts described herein are also highly scalable to advanced semiconductor process technologies with minimal (if any) impact on circuit design and layout resources.

[0047] The following discussion describes an operating environment, the technologies that can be employed within that operating environment, and a system-on-a-chip (SoC) in which the components of the operating environment can be implemented. In the context of this disclosure, reference to the operating environment is made by way of example only.

[0048] Operating environment

[0049] Figure 1 The figure illustrates an example operating environment 100 having an integrated circuit 102 implemented according to aspects of a sub-device field-effect transistor (FET) architecture for integrated circuits. The integrated circuit 102 may include any suitable circuit type, such as digital circuitry, analog circuitry, or mixed-signal circuitry. In this example, the integrated circuit 102 includes analog circuitry 104 and may include other digital or mixed-signal circuitry (not shown). In some cases, the integrated circuit 102 may be implemented in an analog block of multiple analog circuits 104. Alternatively or additionally, the integrated circuit 102 may be implemented as part of a chip or die, such as a system-on-a-chip (SoC), application-specific integrated circuit (ASIC), application-specific standard product (ASSP), digital signal processor (DSP), multi-chip module (MCM), programmable SoC (PSoC), system-in-package (SiP), or field-programmable gate array (FPGA).

[0050] like Figure 1As shown, analog circuit 104 includes an integrated FET 106 formed from or utilizing multiple FET sub-devices 108. The integrated FET 106 can be implemented as any suitable type of MOSFET device, such as an N-channel MOSFET or a P-channel MOSFET. In this example, the integrated FET 106 is shown as a P-channel MOSFET with corresponding connections to other circuitry, including a gate terminal 110, a source terminal 112, and a drain terminal 114. As shown in 116, the integrated FET 106 comprises or is formed from multiple FET sub-devices 108, shown as 108-1 to 108-n, where n is any suitable integer.

[0051] FET sub-devices 108 can be stacked as shown at 120 (e.g., in the channel length direction), having a gate 118 coupled to or connected to the gate terminal 110 of the integrated FET 106. In some cases, the number and geometry of the stacked FET sub-devices 108 are chosen such that the FET sub-device stack provides a larger electrical equivalent function (W / L) for a single semiconductor device. In other words, circuit designers can divide a single FET device into a stack of FET sub-devices 108 to achieve similar electrical performance with a smaller threshold voltage sensitivity and improved matching characteristics. Implementations and uses of the FET sub-devices 108 are varied and described throughout this disclosure.

[0052] As shown in more detail at 122, the respective gates of each of the stacked FET sub-devices 108 can be connected together. Here, the gate 124 of FET sub-device 108-n is coupled or connected to the gates 126 and 128 of other FET sub-devices in the stack. FET sub-device 108-n can also be coupled to other adjacent FET sub-devices 108 via source-to-drain or drain-to-source coupling. For example, the source 130 of FET sub-device 108-n is coupled to the drain 132 of a higher FET sub-device in the stack. The drain 134 of FET sub-device 108-n is coupled to the source 136 of another lower FET sub-device in the stack. This connection can be similarly made throughout the stack of FET sub-devices to form an integrated FET 106.

[0053] Compared to a single device in an analog circuit (e.g., a current mirror) that operates entirely in saturation, the stack of FET sub-devices integrating FET 106 can operate in a heterogeneous mode, in which some FET sub-devices 108 operate in saturation mode while others in FET sub-devices 108 operate in linear mode. For example, and referring to the terminals of the integrated FET 106, FET sub-devices 108 coupled to or near the drain terminal 114 can operate in saturation mode (0 < V). GS -VT <V DS The device operates in linear mode (V112), while other FET sub-devices 108 coupled to or near the source terminal 112 can operate in linear mode (V112). GS -V T <V DS Therefore, reference can be made to a drain-side FET sub-device configured or likely to operate in saturation mode, or to a source-side FET sub-device configured or likely to operate in linear mode.

[0054] In some aspects, the corresponding operating mode of the FET sub-device 108 is controlled or caused by the configuration of the circuitry in which the integrated FET 106 is implemented. Alternatively or additionally, the circuit designer can configure the stack to include a specific (e.g., maximum) number of FET sub-devices 108 by using a sub-device gate length for a sub-device of approximately the minimum gate length (Lg) allowed by a given process technology. Typically, the stack can be implemented using any suitable ratio of source-side FET sub-devices to drain-side FET sub-devices, which can vary in the range of 55%–45% to 45%–55%. Alternatively or additionally, the integrated FET 106 can be implemented using a wider ratio of source-side FET sub-devices to drain-side FET sub-devices, such as in the range of approximately 65%–35% to 35%–65% in sub-device mode allocation.

[0055] Figure 2 The figure illustrates an example layout at 200 of an integrated FET sub-device according to one or more aspects. Layout 200 may include an array 202 of FET sub-devices 108-1 to 108-n, as shown in the reference. Figure 1 As described above, the difference in threshold voltage sensitivity between the source-side FET sub-devices and the drain-side FET sub-devices can be utilized to optimize the layout of the FET sub-devices used for device matching. In this example, the less sensitive devices, starting with source-side FET sub-devices 108-1 and 108-2, are placed near the edge or periphery of layout 200.

[0056] These source-side FET sub-devices and other less sensitive FET sub-devices can be used as buffers, or "self-virtualized" regions 204 are designated for FET sub-devices that are more sensitive to environmental changes or layout pattern variations. More sensitive devices of array 202, such as drain-side FET sub-devices 108-n, can be placed in region 204 to reduce the impact of environmental changes around the edges of layout 200. Note that the term "self-virtualized" is used to describe source-side FET sub-devices that function as functional devices within the array, as opposed to conventional virtualized devices that consume design area without providing circuit functionality.

[0057] The sub-device 108 can be implemented using either FinFET or three-dimensional (3D) fabrication processes, relative to the layout of the individual FET sub-device. As shown at 208, the sub-device can be fabricated where a FinFET gate structure 208 is formed on the source region 210 and drain region 212 to realize the sub-device. This is merely an example, as any other suitable processing technique can be implemented in association with the sub-device FET architecture described herein. For example, the concepts described, such as sub-device and self-virtualization, are also applicable to sub-20nm process technologies implemented using advanced 3D transistor architectures and EUV (extreme ultraviolet) lithography.

[0058] Figure 3 The figure illustrates an example configuration of a current mirror at 300 implemented using the sub-device FET architecture described herein. In this example, the current mirror is shown schematically, as implemented with an integrated FET device at 302, and the integrated FET device is shown as a corresponding stack of FET sub-devices at 304. Compared to conventional layouts where transistor dimensions (e.g., gate length) are maximized in an attempt to address mismatch, aspects of the sub-device architecture can be implemented using a stack of smaller FET sub-devices operating in a heterogeneous mode, where some FET sub-devices operate in linear mode while others operate in saturation mode. As described herein, FET sub-devices operating in linear mode may be less sensitive to environmental changes, enabling optimized layouts for analog circuit designs.

[0059] In this example, the current mirror 302 is implemented using a reference integrated FET device 306 (reference device 306), which sets a reference current 308 for the current mirror 302. The gate of the reference device 306 is coupled or connected to the respective gates of mirror integrated FET devices 310, 312, and 314 (mirror devices 310, 312, and 314). Based on the matching between the reference device 306 and the mirror devices 310, 312, and 314, the mirror devices 310, 312, and 314 provide corresponding output currents 316, 318, and 320 mirrored from the reference current 308.

[0060] When reference device 306 and mirror devices 310, 312, and 314 are implemented as FET sub-devices, the matching of the corresponding devices can be improved through favorable circuit layout. As an example, consider... Figure 4 This paper depicts the layout of multiple arrays of FET sub-devices for the current mirror 304 at 400 locations. Here, utilizing the concept of "self-virtualization" as discussed herein, the current mirror layout array can be optimized by positioning the drain-side sub-devices in the center and the source-side devices at the edges. This technique eliminates the need to add additional virtual devices to handle mismatches, thereby saving design area and cost.

[0061] In this example, the reference current circuit 402 includes sub-devices of the reference device and has an ambient density 0404, which may be unique to the reference current circuit 402 or may differ from other areas of the layout. The array layout also includes corresponding sub-device arrays for current mirrors 1406 (e.g., mirror device 310), 2408 (e.g., mirror device 312), and 3410 (e.g., mirror device 314). Here, it is noted that each array of sub-devices may be configured with the same or similar number and geometry of sub-devices, while ambient densities 412, 414, and 416 may vary from ambient density 0404 or from each other. Depending on aspects of the sub-device FET architecture, more sensitive sub-devices (e.g., drain-side sub-devices) may be placed in corresponding areas 418, 420, 422, and 424 of the array to reduce environmental variations associated with different ambient densities. By doing so, the matching between the reference array and the mirror array can be improved in the design area with minimal or no cost (e.g., no dummy devices).

[0062] Note that the concepts described here can also be applied to other mixed-signal or analog circuits, such as custom-layout circuits. For example, when device mismatch affects circuit performance, aspects of the sub-device FET architecture and associated layout can be used to improve device performance or to match individual devices with / or devices located in different areas of the circuit layout.

[0063] Technology for FET architecture of sub-devices in ICs

[0064] The following discussion describes techniques for sub-device FET architectures used in integrated circuits. These techniques can be implemented using or embodying any of the entities described herein, such as those referenced. Figure 1-4 , Figure 8 or Figure 9 The entities described. These techniques include illustrations in... Figure 5 , Figure 6 and Figure 7 The methods in the text are shown, where each technique is illustrated as a set of operations performed by one or more entities.

[0065] These methods are not necessarily limited to the order of operations shown. Rather, any operation can be repeated, skipped, replaced, or reordered to achieve the various aspects described herein. Furthermore, these methods can be used in whole or in part in combination with each other, whether performed by the same entity, individual entities, or any combination thereof. Examples will be referenced in the following sections of discussion. Figure 1 Operating environment 100 and Figure 2 , Figure 3 and / or Figure 4The entity. Such references should not be considered as limitations on the description of the operating environment 100, entities, or configuration, but rather as illustrations among various examples. Alternatively or additionally, the operation of the method may also be performed by or utilize references. Figure 8 System-on-a-chip or Figure 9 The physical implementation of the device description.

[0066] Figure 5 An example method 500 for forming an integrated FET sub-device on a substrate is described. In some aspects, method 500 is implemented to provide an integrated FET for analog or mixed-signal circuits. Alternatively or additionally, the operations described with reference to method 500 or other methods can be implemented by one or more semiconductor manufacturing processes, such as photolithography, masking, etching, chemical vapor deposition, and / or chemical mechanical planarization.

[0067] At 502, a substrate for an integrated FET, including FET sub-devices, is formed. The integrated FET can be configured as part of an analog or mixed-signal circuit (such as a current mirror, amplifier, filter, analog-to-digital converter, or digital-to-analog converter). Alternatively or additionally, the substrate can be formed to support multiple integrated FETs, which are matched or configured in a ratio according to the analog circuit design.

[0068] At position 504, a first set of FET sub-devices is formed on the substrate. The first set of FET sub-devices can be stacked in series from source to drain or have coupled gates. One FET sub-device of the formed first set is coupled to the drain terminal of the integrated FET. Thus, the first set of FET sub-devices can be implemented as a drain-side device of the integrated FET. Therefore, the first set of FET sub-devices can be formed on an inner portion of the substrate region on which the integrated FET is formed.

[0069] At position 506, a second set of FET sub-devices is formed on the substrate. This second set of FET sub-devices can be stacked in series from source to drain or have coupled gates. One sub-device in the second set of FET sub-devices is coupled to the source terminal of the integrated FET. Thus, the second set of sub-devices can be implemented as a source-side device of the integrated FET. Therefore, the second set of FET sub-devices is formed near the periphery or edge of the substrate region on which the integrated FET is formed.

[0070] Figure 6 An example method 600 for operating an integrated FET to provide current via multiple FET sub-devices of the integrated FET is described.

[0071] At position 602, current is supplied via the power rail to the source terminal of the integrated FET, which is formed by multiple FET sub-devices. Typically, the multiple FET sub-devices may include a first set of FET sub-devices coupled to the drain terminal of the integrated FET and a second set of FET sub-devices coupled to the source terminal of the integrated FET. In some cases, the source of the second set of FET sub-devices is coupled to the source terminal of the integrated FET. Thus, the second set of FET sub-devices can be implemented as source-side devices that are less sensitive to environmental changes. In the layout of the integrated FET, the second set of FET sub-devices can be arranged as edge devices or as dummy devices for the more sensitive FET sub-devices of the integrated FET.

[0072] At 604, a voltage is applied to the gate terminal of the integrated FET to operate a first group of multiple FET sub-devices in linear mode and a second group of FET sub-devices in saturation mode. In some cases, the respective gates of the first and second groups of multiple FET sub-devices are coupled to the gate terminal of the integrated FET.

[0073] At point 606, based on the voltage applied to the gate terminal, at least a portion of the current is supplied to the drain terminal of the integrated FET via a first and second group of multiple FET sub-devices. In some cases, the drain of the first group of FET sub-devices is coupled to the drain terminal of the integrated FET. Thus, the first group of FET sub-devices can be implemented as drain-side devices that are more sensitive to environmental changes. In the layout of the integrated FET, the first group of FET sub-devices can be arranged at the center of the layout to minimize the impact of layout variations.

[0074] Figure 7 An example method 700 is described for the layout of an array of FET sub-devices for arranging integrated FET devices.

[0075] At 702, geometric information for a single FET device is received. This geometric information may include channel width and length information for the single FET device. In some cases, the single FET device is a large FET device with dimensions suitable for a specific analog circuit, or with dimensions for matching another large FET device.

[0076] At 704, based on geometric information, the layout of a single FET is divided into an array of multiple FET sub-devices. For example, the number and geometry of the stacked FET sub-devices can be selected such that the FET sub-device stack provides a larger electrical equivalent function (W / L) for a single semiconductor device.

[0077] At 706, a first set of FET sub-devices for the array that may operate in saturation mode or saturation region is determined. In some cases, a model or estimate can be made regarding how many stacked FET sub-devices will operate or may operate in saturation mode. The FET sub-device stack can be achieved using any suitable ratio of saturation mode FET sub-devices to linear mode FET sub-devices, which can vary in the range of 40% to 60%.

[0078] At 708, a second set of FET sub-devices for the array that may operate in linear mode or linear region is determined. In some cases, a model or estimate can be made regarding how many stacked FET sub-devices will operate or may operate in linear mode. The FET sub-device stack can be achieved using any suitable ratio of linear mode FET sub-devices to saturation mode FET sub-devices, which can vary in the range of 30% to 70% from 70% to 30% to 70%.

[0079] At 710, the first set of FET sub-devices is placed within the inner portion of the layout for the array of multiple FET sub-devices. For example, the first set of FET sub-devices or the drain-side FET sub-devices may be placed at the center of the layout area for the array or in a region designated for mismatch-sensitive devices (e.g., region 204).

[0080] At 712, a second set of FET sub-devices is placed in the outer portion or edge of the layout for the array of multiple FET sub-devices. For example, the second set of FET sub-devices or the source-side FET sub-devices may be placed near the periphery of the layout area for the array or around an area designated for mismatch-sensitive devices. In some cases, the second set of FET sub-devices may be positioned to surround the first set of FET sub-devices on three or all sides.

[0081] Optionally, at 714, based on the layout, an array of multiple FET sub-devices is fabricated on the substrate to form an integrated FET device. For example, the integrated FET device can be fabricated or formed by implementing one or more operations described in reference method 500.

[0082] System-on-a-Chip

[0083] Figure 8The figure illustrates an exemplary System-on-Chip (SoC) 800 in which aspects of the FET architecture for sub-devices of the integrated circuit are implemented. The SoC 800 can be configured for or implemented in any suitable device, such as a smartphone, netbook, tablet, access point, network-attached storage, smart device, set-top box, server, automotive computing system, or any other suitable type of device (e.g., other devices described herein). Although described with reference to the SoC, Figure 8 The entity can also be implemented as other types of integrated circuits or embedded systems, such as ASICs, memory controllers, storage controllers, communication controllers, ASSPs, DSPs, MCMs, PSoCs, SiPs, or FPGAs.

[0084] The SoC 800 can be integrated with electronic circuitry, a microprocessor, memory, input / output (I / O) control logic, communication interfaces, firmware, and / or software to provide the functionality of a computing device. The SoC 800 may also include an integrated data bus or interconnect organization (not shown) that couples various components of the SoC for data communication between components. The integrated data bus, interconnect organization, or other components of the SoC 800 can be exposed or accessed through external ports, a Serial Peripheral Interface (SPI) port, or any other suitable data interface.

[0085] In this example, the SoC 800 includes various components such as input / output (I / O) control logic 802 and a processor 804, such as a microprocessor, processor core, application processor, DSP, etc. The SoC 800 also includes memory 806 and a power system 810 to provide power management functions for the SoC 800. Memory 806 may include any type and / or combination of RAM, SRAM, DRAM, non-volatile memory, ROM, one-time programmable (OTP) memory, flash memory, and / or other suitable electronic data memory. In the context of this disclosure, memory 806 stores data, instructions, or other information via non-transient signals and does not include carrier or transient signals.

[0086] The SoC 800 may also include firmware, applications, programs, software, and / or an operating system, which may be embodied as processor-executable instructions maintained on memory 806 for execution by processor 804 to implement the functions of the SoC 800. The SoC 800 may also include other communication interfaces, such as transceiver interfaces for controlling or communicating with components of local on-chip (not shown) or off-chip communication transceivers. The transceiver interfaces may also implement signal interfaces to transmit radio frequency (RF), intermediate frequency (IF), or baseband frequency signals off-chip to facilitate wired or wireless communication via transceivers, physical layer transceivers (PHYs), or media access controllers (MACs) coupled to the SoC 800.

[0087] The components of SoC 800 are implemented by integrated circuit 812, which includes analog circuitry 814 and mixed-signal circuitry (not shown). The analog circuitry 814 of SoC 800 includes an integrated FET 106 and FET sub-devices, which can be implemented as described with reference to the various aspects given herein. References Figure 1 The corresponding components or entities of environment 100 or Figure 2 , Figure 3 and / or Figure 4 The corresponding configurations shown herein, examples of these components and / or entities, or their corresponding functions are described. The integrated FET 106 and / or FET sub-device 108 can be implemented independently or in combination with any suitable components or circuitry to achieve the aspects described herein. For example, the integrated FET 106 can be implemented as part of the analog circuitry, mixed-signal circuitry, current mirror, amplifier, filter, analog-to-digital converter, or digital-to-analog converter of the SoC 800.

[0088] computing devices

[0089] Figure 9 The figure illustrates an example computing device at 900, where a FET sub-device is implemented according to one or more aspects. Examples of computing devices 902 include smartphones 904, laptops 906, medical devices 908, set-top boxes 910, and wireless routers 912. Other examples of computing devices 902 (not shown) include tablet computers, set-top boxes, data storage devices, wearable smart devices, televisions, content streaming devices, high-definition multimedia interface (HDMI) media sticks, wearable computers, smart home appliances, home automation controllers, smart thermostats, Internet of Things (IoT) devices, mobile internet devices (MIDs), network-attached storage (NAS) drives, game consoles, automotive entertainment devices, automotive computing systems, automotive control modules (e.g., engine or powertrain control modules), and so on. Typically, computing device 902 can store, communicate, or process data for any suitable purpose, such as implementing the functions of a particular type of device, providing a user interface, enabling network access, etc.

[0090] Computing device 902 includes a processor 914 and a computer-readable storage medium 916. The processor 914 can be implemented as any suitable type or number of processors, single-core or multi-core, for executing instructions or commands of an operating system or other programs of the computing device 902. The computer-readable medium 916 (CRM 916) can include any suitable type or combination of volatile or non-volatile memory. For example, the volatile memory of the computing device 902 can include various types of RAM, DRAM, SRAM, etc. The non-volatile memory can include ROM, flash memory (e.g., either flash or non-flash) or magnetic disk storage. These memories, individually or in combination, can store data associated with applications and / or the operating system of the computing device 902.

[0091] Example computing device 902 may also include I / O port 918, graphics processing unit 920 (GPU 920), and data interface 922. Typically, I / O port 918 allows computing device 902 to interact with other devices, peripheral devices, sensors, or users. For example, I / O port 918 may include a universal serial bus, audio input, audio output, etc. GPU 920 processes and renders graphics-related data for computing device 902, such as user interface elements of the operating system, applications, etc. Data interface 922 of computing device 902 provides connectivity to one or more networks and other devices connected to those networks. Data interface 922 may include a wired interface, such as an Ethernet or fiber optic interface for communication over a local area network (LAN), intranet, or the Internet. Alternatively or additionally, data interface 922 may include a wireless interface that facilitates communication over wireless networks, such as wireless LANs, wide area wireless networks (e.g., cellular networks), and / or wireless personal area networks (WPANs).

[0092] like Figure 9 As shown, various components of the computing device 902 can be implemented using an integrated circuit 102 including analog circuitry 104 or mixed-signal circuitry with an integrated FET device 106. In this example, any of the processor 914, CRM 916, I / O port 918, GPU 920, and / or data interface 922 can be implemented using the integrated FET 106 and FET sub-device 108, depending on one or more aspects of the sub-device FET architecture. Alternatively or additionally, the integrated FET 106 and FET sub-device 108 can be implemented as part of any suitable circuitry, such as analog circuitry, mixed-signal circuitry, current mirrors, amplifiers, filters, analog-to-digital converters, digital-to-analog converters, etc.

[0093] Although the subject matter has been described in language specific to structural features and / or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific examples, features, or operations described herein, including the order in which they are performed.

Claims

1. A method for forming an integrated FET of a field-effect transistor (FET) sub-device, the method comprising: Forming a substrate for the integrated FET; A first set of FET sub-devices is formed on the substrate, and a first FET sub-device in the first set of FET sub-devices is coupled to the drain terminal of the integrated FET; as well as A second set of the FET sub-devices is formed on the substrate, and a second FET sub-device in the second set of the FET sub-devices is coupled to the source terminal of the integrated FET; Wherein (i) the first set of the FET sub-devices is formed on the inner portion of the substrate region on which the integrated FET is formed; and (ii) the second set of the FET sub-devices is formed near the periphery of the substrate region on which the integrated FET is formed.

2. The method of claim 1, wherein the second set of FET sub-devices is formed on the substrate region to surround the first set of FET sub-devices on three sides.

3. The method of claim 1, wherein the second set of FET sub-devices is formed on the substrate region to surround the first set of FET sub-devices on all sides.

4. The method according to claim 1, wherein: The respective gates of the first set of the FET sub-devices are coupled to the gate terminals of the integrated FET; and The respective gates of the second set of the FET sub-devices are coupled to the gate terminals of the integrated FET.

5. The method according to claim 1, wherein: The source of the third FET sub-device in the first set of the FET sub-devices is coupled to the drain of the fourth FET sub-device in the second set of the FET sub-devices.

6. The method of claim 1, further comprising: The first set of the FET sub-devices of the integrated FET is formed into a first FinFET device; or The second set of the FET sub-devices of the integrated FET is formed into a second FinFET device.

7. The method of claim 1, further comprising: The drain terminal of the integrated FET is formed on the substrate; The source terminal of the integrated FET is formed on the substrate; or The gate terminal of the integrated FET is formed on the substrate.

8. The method according to claim 1, wherein: The first set of FET sub-devices includes at least three FET sub-devices configured to operate in saturation mode; or The second set of FET sub-devices includes at least three FET sub-devices configured to operate in linear mode.

9. An integrated circuit, comprising: Substrate, having a surface; An integrated field-effect transistor (FET) includes an array of FET sub-devices formed on the surface of the substrate, the array of FET sub-devices comprising: A first set of FET sub-devices, having a corresponding gate coupled to the gate terminal of the integrated FET, and a first FET sub-device including a drain having a drain terminal coupled to the integrated FET; and The second set of FET sub-devices has a corresponding gate coupled to the gate terminal of the integrated FET, and includes a second FET sub-device having a source terminal coupled to the source terminal of the integrated FET. The array of FET sub-devices is formed on the surface of the substrate, such that the second set of FET sub-devices is disposed around at least three sides of the substrate region on which the first set of FET sub-devices is disposed.

10. The integrated circuit of claim 9, wherein the array of FET sub-devices is formed on the surface of the substrate, such that the second set of FET sub-devices is configured to form a periphery around the substrate region on which the first set of FET sub-devices is disposed.

11. The integrated circuit according to claim 9, wherein: The first group of FET sub-devices of the integrated FET are configured to operate in saturation mode or saturation region; and The second set of FET sub-devices of the integrated FET is configured to operate in linear mode or in the linear region.

12. The integrated circuit according to claim 9, wherein: The respective gates of the first group of FET sub-devices have a gate length approximately equal to the minimum gate length for the process technology by which the integrated circuit is manufactured; or The respective gates of the second set of FET sub-devices have a gate length approximately equal to the minimum gate length for the process technology by which the integrated circuit is manufactured.

13. The integrated circuit according to claim 9, wherein: The source of the third FET sub-device in the first group of FET sub-devices is coupled to the drain of the fourth FET sub-device in the second group of FET sub-devices.

14. The integrated circuit of claim 9, wherein the geometry of the first group of FET sub-devices is substantially similar to the geometry of the second group of FET sub-devices.

15. The integrated circuit according to claim 9, wherein: The functionality of the integrated FET is provided at least in part by the second set of FET sub-devices; and The second group of FET sub-devices is positioned adjacent to the first group of FET sub-devices, without placing non-functional devices between the first group of FET sub-devices and the second group of FET sub-devices.

16. The integrated circuit according to claim 9, wherein: The first group of FET sub-devices is implemented on the surface of the substrate as the first group of FinFET devices of the integrated FET; or The second set of FET sub-devices is implemented on the surface of the substrate as the second set of FinFET devices of the integrated FET.

17. The integrated circuit of claim 9, wherein all or part of the integrated circuit is implemented as an analog circuit, a mixed-signal circuit, a current mirror, an amplifier, a filter, an analog-to-digital converter, or a digital-to-analog converter.

18. A method comprising: Current is supplied to the source terminal of an integrated FET, which is composed of multiple field-effect transistor (FET) sub-devices, via the power rail; A voltage is applied to the gate terminal of the integrated FET to operate the first group of the plurality of FET sub-devices in saturation mode and the second group of the FET sub-devices in linear mode; as well as Based on the voltage applied to the gate terminal, at least a portion of the current is provided to the drain terminal of the integrated FET via the first set of the plurality of FET sub-devices and the second set of the plurality of FET sub-devices.

19. The method of claim 18, wherein: The respective gates of the plurality of FET sub-devices in the first group and the plurality of FET sub-devices in the second group are coupled to the gate terminal of the integrated FET; The drain of the first FET sub-device in the first group of multiple FET sub-devices is coupled to the drain terminal of the integrated FET; as well as The source of the second FET sub-device in the second group of the plurality of FET sub-devices is coupled to the source terminal of the integrated FET.

20. The method of claim 18, wherein the integrated FET is formed on a substrate, the first group of the plurality of FET sub-devices is formed on an inner portion of the substrate region on which the integrated FET is formed, and the second group of the plurality of FET sub-devices is formed near the periphery of the substrate region on which the integrated FET is formed.

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