Semiconductor Devices

Abstract

A semiconductor device may include: a substrate including an active pattern extending in a first direction; a gate electrode extending across the active pattern and in a second direction intersecting the first direction; a source / drain pattern on the active pattern and adjacent to one side of the gate electrode; an active contact in a contact hole exposing the source / drain pattern; an insulating pattern filling a remaining space of the contact hole in which the active contact is provided; a first through hole on the active contact; and a second through hole on the gate electrode. The active contact may include a first segment filling a lower portion of the contact hole and a second segment protruding vertically from the first segment. The first through hole is connected to the second segment. The insulating pattern is adjacent to the second through hole in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0103505 filed on August 31, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and a method for manufacturing the same. Background Art

[0004] Semiconductor devices are beneficial to the electronics industry due to their small size, versatility and / or low manufacturing cost. Semiconductor devices may include semiconductor memory devices that store logic data, semiconductor logic devices that process operations of logic data, and hybrid semiconductor devices having both memory and logic elements. With the advancement of the electronics industry, semiconductor devices increasingly require high integration. For example, semiconductor devices increasingly require high reliability, high speed and / or versatility. Semiconductor devices are gradually becoming more complex and integrated to meet these required characteristics. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a semiconductor device having increased integration and reliability.

[0006] According to some example embodiments of the present invention, a semiconductor device may include: a substrate including an active pattern extending in a first direction; a gate electrode extending across the active pattern in a second direction intersecting the first direction; a source / drain pattern on the active pattern such that the source / drain pattern is adjacent to one side of the gate electrode; an active contact including a first segment and a second segment, the first segment of the active contact being in a first portion of a contact hole exposing the source / drain pattern, the second segment of the active contact protruding vertically from the first segment; an insulating pattern filling the second portion of the contact hole; a first through-hole on the active contact and connected to the second segment of the active contact; and a second through-hole on the gate electrode such that the insulating pattern is adjacent to the second through-hole in the first direction.

[0007] According to some example embodiments of the present invention, a semiconductor device may include: a substrate including a plurality of active patterns extending in parallel along a first direction; a gate electrode extending across the active patterns in a second direction intersecting the first direction; a source / drain pattern on the active pattern such that the source / drain pattern is adjacent to one side of the gate electrode; an active contact including a first segment and a second segment, the first segment of the active contact being on the source / drain pattern and the second segment protruding vertically from the first segment; a first through hole on the second segment; and a second through hole on the gate electrode such that the second through hole vertically overlaps at least one of the active patterns.

[0008] According to some example embodiments conceived in the present invention, a semiconductor device may include: a substrate including a plurality of active patterns extending in parallel along a first direction; a gate electrode extending across the active patterns in a second direction, the second direction intersecting the first direction; a source / drain pattern on the active pattern such that the source / drain pattern is adjacent to one side of the gate electrode; and an active contact including a first segment and a second segment, the first segment of the active contact being on the source / drain pattern and the second segment of the active contact protruding vertically from the first segment, the active contact being shaped such that a width of the second segment of the active contact in the second direction increases toward the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are shown.

[0010] Figure 2A , Figure 2B and Figure 2C Shown are Figure 1 Cross-sectional views taken along lines AA', BB' and CC'.

[0011] Figure 3 Simplified perspective views showing a gate electrode and a pair of active contacts of a semiconductor device according to some example embodiments of the inventive concepts are illustrated.

[0012] Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 Plan views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept are shown.

[0013] Figure 5 , Fig. 7A , Fig. 9A , Fig.11A , Fig.13A and Fig.15A The Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 A cross-sectional view taken along line AA'.

[0014] Figure 7B , Fig. 9B , Fig. 11B , Fig. 13B and Fig. 15B The Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 A cross-sectional view taken along line BB'.

[0015] Figure 7C , Fig. 9C , Fig. 11C , Fig. 13C and Fig. 15C The Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 A cross-sectional view taken along line CC'.

[0016] Fig.16 Plan views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept are shown.

[0017] Fig.17A , Fig. 17B and Fig. 17C Shown are Fig.16 Cross-sectional views taken along lines AA', BB' and CC'.

[0018] Fig.18A and Fig.18B FIG. 1 shows semiconductor devices showing some example embodiments of the present inventive concept. Figure 1 A cross-sectional view taken along line AA' and line BB'.

[0019] Fig.19 FIG. 1 shows a semiconductor device that illustrates some example embodiments of the present inventive concept. Figure 1 A cross-sectional view taken along line AA'. DETAILED DESCRIPTION

[0020] Figure 1 Plan views showing semiconductor devices according to some example embodiments of the inventive concepts are shown. Figure 2A , Figure 2B and Figure 2C Shown are Figure 1 Cross-sectional views taken along lines AA', BB' and CC'. Figure 3 Simplified perspective views showing a gate electrode and a pair of active contacts of a semiconductor device according to some example embodiments of the inventive concepts are illustrated.

[0021] Reference Figure 1 , FIG. 2A to FIG. 2C and Figure 3 The substrate 100 may include a PMOSFET region PR and an NMOSFET region NR. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, silicon germanium, etc. For example, the substrate 100 may be a silicon substrate.

[0022] Each of the PMOSFET region PR and the NMOSFET region NR may be a logic cell region including logic transistors constituting a logic circuit of a semiconductor device. For example, the logic cell region of the substrate 100 may include logic transistors constituting a processor core or an I / O terminal. Each of the PMOSFET region PR and the NMOSFET region NR may include at least one of the logic transistors.

[0023] The PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR2 formed on an upper portion of the substrate 100. The second trench TR2 may be positioned between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other on both sides of the second trench TR2 in the first direction D1. Each of the PMOSFET region PR and the NMOSFET region NR may extend in a second direction D2 intersecting the first direction D1.

[0024] A plurality of active patterns AP1 and AP2 extending in the second direction D2 may be provided on the PMOSFET region PR and the NMOSFET region NR. The active patterns AP1 and AP2 may include a first active pattern AP1 on the PMOSFET region PR and a second active pattern AP2 on the NMOSFET region NR. The first active pattern AP1 and the second active pattern AP2 may be vertical protrusions of the substrate 100. A first trench TR1 may be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2.

[0025] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a dielectric material such as a silicon oxide layer. Upper portions of the first active pattern AP1 and the second active pattern AP2 may vertically protrude beyond the device isolation layer ST. Each of upper portions of the first active pattern AP1 and the second active pattern AP2 may have a fin shape. The device isolation layer ST may not cover upper portions of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover lower sidewalls of the first active pattern AP1 and the second active pattern AP2.

[0026] The first source / drain pattern SD1 may be disposed on an upper portion of the first active pattern AP1. The first source / drain pattern SD1 may be an impurity region having a first conductivity type (e.g., p-type). The first channel region CH1 may be inserted between the pair of first source / drain patterns SD1. The second source / drain pattern SD2 may be disposed on an upper portion of the second active pattern AP2. The second source / drain pattern SD2 may be an impurity region having a second conductivity type (e.g., n-type). The second channel region CH2 may be inserted between the pair of second source / drain patterns SD2.

[0027] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth process. The top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surfaces of the first channel region CH1 and the second channel region CH2. For example, the first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. The first source / drain pattern SD1 may thus provide compressive stress to the first channel region CH1. For example, the second source / drain pattern SD2 may include the same semiconductor element (e.g., Si) as the semiconductor element of the substrate 100.

[0028] The gate electrode GE may be disposed to extend in the first direction D1 while crossing the first active pattern AP1 and the second active pattern AP2. The gate electrodes GE may be spaced apart in the second direction D2. The gate electrodes GE may vertically overlap the first channel region CH1 and the second channel region CH2. Each gate electrode GE may surround a top surface and opposite side walls (see FIG. 1 ) of each of the first channel region CH1 and the second channel region CH2. Figure 2C ). For example, the gate electrode GE may include one or more of a conductive metal nitride (eg, titanium nitride or tantalum nitride) and a metal (eg, titanium, tantalum, tungsten, copper, or aluminum).

[0029] A pair of gate spacers GS may be disposed on opposite sidewalls of each gate electrode GE. The gate spacer GS may extend along the gate electrode GE in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110 (to be discussed below). The gate spacer GS may include one or more of SiCN, SiCON, and SiN. Alternatively, the gate spacer GS may include a multilayer consisting of two or more of SiCN, SiCON, and SiN.

[0030] The gate dielectric pattern GI may be inserted between the gate electrode GE and the first active pattern AP1 and between the gate electrode GE and the second active pattern AP2. Each gate dielectric pattern GI may extend along the bottom surface of a corresponding one of the gate electrodes GE. Each gate dielectric pattern GI may cover the top surface and the opposite sidewalls of each of the first channel region CH1 and the second channel region CH2. The gate dielectric pattern GI may include a high-k dielectric material. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0031] The gate capping pattern GP may be disposed on each gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE in the first direction D1. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120 (to be discussed below). For example, the gate capping pattern GP may include one or more of SiON, SiCN, SiCON, and SiN.

[0032] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate capping pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 covering the gate capping pattern GP may be disposed on the first interlayer insulating layer 110. For example, the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may include a silicon oxide layer.

[0033] The active contact AC may be disposed to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and have electrical connection with the first source / drain pattern SD1 and the second source / drain pattern SD2. The contact hole CNH may be defined to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and expose one of the first source / drain pattern SD1 and the second source / drain pattern SD2. The active contact AC may be disposed in the contact hole CNH. The active contact AC may be disposed between a pair of gate electrodes GE.

[0034] The contact spacer CSP may be disposed on the contact hole CNH. The contact spacer CSP may conformally cover the inner sidewall of the contact hole CNH. The contact spacer CSP may be inserted between the first interlayer insulating layer 110 and the active contact AC. The contact spacer CSP may include one or more of SiCN, SiCON, and SiN. The contact spacer CSP may include a material substantially the same as that of the gate spacer GS.

[0035] Each active contact AC may include a barrier pattern BM and a conductive pattern FM. The barrier pattern BM may be inserted between the conductive pattern FM and the contact spacer CSP and between the conductive pattern FM and one of the first source / drain pattern SD1 and the second source / drain pattern SD2. The barrier pattern BM may conformally cover the opposite sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may not cover the top surface of the conductive pattern FM.

[0036] The barrier pattern BM may include a metal nitride layer, such as one or more of a titanium nitride layer, a tungsten nitride layer, and a tantalum nitride layer. The conductive pattern FM may include a metal material, such as one or more of aluminum, copper, tungsten, molybdenum, and cobalt.

[0037] Each active contact AC may include a first segment PA1 at a lower portion thereof and a second segment PA2 at an upper portion thereof. The second segment PA2 may be disposed on the first segment PA1. The second segment PA2 may protrude from a top surface of the first segment PA1 in a vertical direction (e.g., a third direction D3). The top surface of the first segment PA1 may be lower than the top surface of the gate electrode GE. The bottom surface of the second segment PA2 may be lower than the top surface of the gate electrode GE. The top surface of the second segment PA2 may be higher than the top surface of the gate electrode GE.

[0038] Return to reference Figure 2B , the first segment PA1 may have a first width W1 in the first direction D1, and the second segment PA2 may have a second width W2 in the first direction D1. The first width W1 may be greater than the second width W2. For example, the maximum width of the first segment PA1 in the first direction D1 may be greater than the maximum width of the second segment PA2 in the first direction D1.

[0039] The first width W1 may gradually decrease as approaching the lower portion of the first segment PA1 from the upper portion of the first segment PA1. The first width W1 may decrease as approaching the substrate 100. The second width W2 may gradually increase as approaching the lower portion of the second segment PA2 from the upper portion of the second segment PA2. The second width W2 may increase as approaching the substrate 100.

[0040] The pad CAL and the insulating pattern IP may fill the remaining space of the contact hole CNH provided with the second segment PA2. The pad CAL may be formed to conformally cover the upper sidewall of the contact spacer CSP, the top surface of the first segment PA1, and the sidewall of the second segment PA2. The insulating pattern IP may be disposed on the pad CAL. For example, the pad CAL may be inserted between the insulating pattern IP and the contact spacer CSP and between the insulating pattern IP and the active contact AC. The top surface of the insulating pattern IP may be coplanar with the top surface of the second segment PA2. Each of the pad CAL and the insulating pattern IP may include one or more of SiCN, SiCON, and SiN. Each of the pad CAL and the insulating pattern IP may include a material having an etching selectivity relative to the gate capping pattern GP.

[0041] Return to reference Figure 2B and Figure 3 , the conductive pattern FM of the first segment PA1 may have a first side wall SW1, and the conductive pattern FM of the second segment PA2 may have a second side wall SW2. Each of the first side wall SW1 and the second side wall SW2 may be parallel to the second direction D2. For example, each of the first side wall SW1 and the second side wall SW2 may be perpendicular to the first direction D1.

[0042] The barrier pattern BM may directly cover the first side wall SW1. The barrier pattern BM may not cover the second side wall SW2. The second side wall SW2 may be directly covered by the pad CAL.

[0043] Return to reference Figure 1 and FIG. 2A to FIG. 2C , a silicide layer (not shown) may be inserted between the active contact AC and the first source / drain pattern SD1 and / or between the active contact AC and the second source / drain pattern SD2. The active contact AC may be electrically connected to the first source / drain pattern SD1 or the second source / drain pattern SD2 through the silicide layer. The silicide layer may include metal silicide, such as one or more of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0044] The third interlayer insulating layer 130 and the fourth interlayer insulating layer 140 may be sequentially disposed on the second interlayer insulating layer 120. For example, the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140 may include a silicon oxide layer. The first through hole VI1 may be disposed to penetrate the third interlayer insulating layer 130 and have an electrical connection with the active contact AC. The second through hole VI2 may be disposed to penetrate the third interlayer insulating layer 130, the second interlayer insulating layer 120, and the gate capping pattern GP and have an electrical connection with the gate electrode GE.

[0045] The first via VI1 may be disposed on the corresponding second segment PA2 of the active contact AC. The first via VI1 may contact the top surface of the second segment PA2 of the active contact AC. The first via VI1 may vertically overlap the second segment PA2 of the active contact AC.

[0046] Each second through hole VI2 may contact the top surface of the gate electrode GE. The bottom surface of the second through hole VI2 may be higher than the top surface of the first segment PA1 of the active contact AC. The bottom surface of the second through hole VI2 may be higher than the bottom surface of the second segment PA2 of the active contact AC. The top surfaces of the first through hole VI1 and the second through hole VI2 may be coplanar with the top surface of the third interlayer insulating layer 130.

[0047] In some example embodiments, at least one second through hole VI2 may be disposed on the first active pattern AP1 or on the second active pattern AP2. For example, at least one second through hole VI2 may vertically overlap the first active pattern AP1 or the second active pattern AP2. The second through hole VI2 may be adjacent to the active contact AC in the second direction D2. The relationship between the second through hole VI2 and the active contact AC adjacent thereto will be described in detail below.

[0048] The first segment PA1 of the active contact AC may be adjacent to the second through hole VI2 in the second direction D2. The second segment PA2 of the active contact AC may not be adjacent to the second through hole VI2 in the second direction D2. For example, the second segment PA2 of the active contact AC may not be aligned with the second through hole VI2 in the second direction D2, but may be offset relative to the second through hole VI2.

[0049] When viewed in a plan view, the second segment PA2 of the active contact AC may be spaced apart from the second through hole VI2 by a minimum spacing distance ML. Therefore, an electrical short circuit may be avoided between the second through hole VI2 and the second segment PA2 of the active contact AC. In the case where the second segment PA2 of the active contact AC is adjacent to the second through hole VI2 in the second direction D2, an electrical short circuit may occur because the distance between the second segment PA2 and the second through hole VI2 is extremely small.

[0050] In addition, as described above, the bottom surface of the second via VI2 may be higher than the top surface of the first segment PA1 of the active contact AC. Therefore, an electrical short circuit may be avoided (or alternatively, prevented) between the second via VI2 and the first segment PA1.

[0051] The fourth interlayer insulating layer 140 may be provided with interconnection lines IL. The interconnection lines IL may extend in parallel along the second direction D2. The interconnection lines IL may be arranged along the first direction D1. The interconnection lines IL may include power lines VDD and VSS.

[0052] The interconnection line IL and the active contact AC may be vertically connected to each other through the first through hole VI1 interposed therebetween. The interconnection line IL and the gate electrode GE may be vertically connected to each other through the second through hole VI2 interposed therebetween. The interconnection line IL and the first and second through holes VI1 and VI2 may include a metal material, such as one or more of aluminum, copper, tungsten, molybdenum, and cobalt.

[0053] According to some example embodiments of the inventive concept, since an electrical short circuit is avoided between the second through hole VI2 and the second segment PA2 of the active contact AC, the second through hole VI2 may be placed on the PMOSFET region PR and the NMOSFET region NR. The second through hole VI2 may not be disposed on the region between the PMOSFET region PR and the NMOSFET region NR (e.g., the device isolation layer ST filling the second trench TR2), and then the distance between the PMOSFET region PR and the NMOSFET region NR (e.g., the width of the second trench TR2) may be reduced. In short, the length of the logic unit in the first direction D1 may be reduced to increase the integration of the semiconductor device.

[0054] Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 Plan views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept are shown. Figure 5 , Fig. 7A , Fig. 9A , Fig.11A , Fig.13A and Fig.15A The Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 A cross-sectional view taken along line AA'. Figure 7B , Fig. 9B , Fig. 11B , Fig. 13B and Fig. 15B The Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 A cross-sectional view taken along line BB'. Figure 7C , Fig. 9C , Fig. 11C , Fig. 13C and Fig. 15C The Figure 6 , Figure 8 , Fig.10 , Fig.12 and Fig.14 A cross-sectional view taken along line CC'.

[0055] Reference Figure 4 and Figure 5 , the upper portion of the substrate 100 may be patterned to form a first active pattern AP1 and a second active pattern AP2. A first trench TR1 may be formed between the first active patterns AP1 and between the second active patterns AP2. A second trench TR2 may be formed between the PMOSFET region PR where the first active pattern AP1 is formed and the NMOSFET region NR where the second active pattern AP2 is formed.

[0056] A device isolation layer ST may be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a dielectric material such as a silicon oxide layer. The device isolation layer ST may be recessed until upper portions of the first active pattern AP1 and the second active pattern AP2 are exposed. Therefore, upper portions of the first active pattern AP1 and the second active pattern AP2 may vertically protrude beyond the device isolation layer ST.

[0057] Reference Figure 6 and FIG. 7A to FIG. 7C , the sacrificial pattern PP may be formed to cross the first active pattern AP1 and the second active pattern AP2. Each of the sacrificial patterns PP may be formed to have a linear or bar shape extending in the first direction D1. For example, the formation of the sacrificial pattern PP may include: forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer may include a polysilicon layer.

[0058] A pair of gate spacers GS may be formed on opposite sidewalls of each sacrificial pattern PP. The gate spacers GS may also be formed on opposite sidewalls of each of the first active pattern AP1 and the second active pattern AP2. The opposite sidewalls of each of the first active pattern AP1 and the second active pattern AP2 may be exposed portions not covered by the device isolation layer ST and the sacrificial pattern PP.

[0059] The formation of the gate spacer GS may include: conformally forming a gate spacer layer on the entire surface of the substrate 100, and anisotropically etching the gate spacer layer. The gate spacer layer may include one or more of SiCN, SiCON, and SiN. Alternatively, the gate spacer layer may be a multilayer including two or more of SiCN, SiCON, and SiN.

[0060] Reference Figure 8 and 9A to 9C , a first source / drain pattern SD1 may be formed on an upper portion of each of the first active patterns AP1. The first source / drain pattern SD1 may be formed on opposite sides of each of the sacrificial patterns PP.

[0061] For example, the hard mask pattern MA and the gate spacer GS may be used as an etching mask to etch the upper portion of the first active pattern AP1, which may result in the formation of a first recess. When the upper portion of the first active pattern AP1 is etched, the gate spacer GS may also be removed from the opposite sidewalls of each first active pattern AP1. When the upper portion of the first active pattern AP1 is etched, the device isolation layer ST may be recessed between the first active patterns AP1.

[0062] The first recess of the first active pattern AP1 may have an inner sidewall that serves as a seed layer for a selective epitaxial growth process to form the first source / drain pattern SD1. The formation of the first source / drain pattern SD1 may define a first channel region CH1 between a pair of first source / drain patterns SD1. For example, the selective epitaxial growth process may include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Each of the first source / drain patterns SD1 may be formed of a plurality of semiconductor layers.

[0063] When performing a selective epitaxial growth process to form the first source / drain pattern SD1, impurities may be implanted in situ. Alternatively, impurities may be implanted into the first source / drain pattern SD1 after the first source / drain pattern SD1 is formed. The first source / drain pattern SD1 may be doped to have a first conductivity type (eg, p-type).

[0064] A second source / drain pattern SD2 may be formed at an upper portion of each second active pattern AP2. The second source / drain pattern SD2 may be formed at opposite sides of each sacrificial pattern PP.

[0065] For example, the hard mask pattern MA and the gate spacer GS may be used as an etching mask to etch an upper portion of the second active pattern AP2, which may result in the formation of a second recess. The second recess of the second active pattern AP2 may have an inner sidewall, which serves as a seed layer for a selective epitaxial growth process to form a second source / drain pattern SD2. The formation of the second source / drain pattern SD2 may define a second channel region CH2 between a pair of second source / drain patterns SD2. The second source / drain pattern SD2 may include the same semiconductor element (e.g., Si) as that of the substrate 100. The second source / drain pattern SD2 may be doped to have a second conductivity type (e.g., n-type).

[0066] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be sequentially formed by different processes. For example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may not be formed at the same time.

[0067] Reference Fig.10 and FIG. 11A to FIG. 11C , a first interlayer insulating layer 110 may be formed to cover the first and second source / drain patterns SD1 and SD2 , the hard mask pattern MA, and the gate spacer GS. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0068] The first interlayer insulating layer 110 may be planarized until the top surface of the sacrificial pattern PP is exposed. The first interlayer insulating layer 110 may be planarized using an etch-back or chemical mechanical polishing (CMP) process. The hard mask pattern MA may be completely removed during the planarization process. As a result, the top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0069] The sacrificial pattern PP may be replaced with the gate electrode GE. For example, the exposed sacrificial pattern PP may be selectively removed. The removal of the sacrificial pattern PP may form an empty space. A gate dielectric pattern GI, a gate electrode GE, and a gate capping pattern GP may be formed in each empty space. The gate dielectric pattern GI may be conformally formed so as not to completely fill the empty space. The gate dielectric pattern GI may be formed by atomic layer deposition (ALD) or chemical oxidation. For example, the gate dielectric pattern GI may include a high-k dielectric material.

[0070] The gate electrode GE may be formed by forming a gate electrode layer to completely fill the empty space and planarizing the gate electrode layer. For example, the gate electrode layer may include one or more of a metal and a conductive metal nitride.

[0071] Thereafter, the gate electrode GE may be recessed at an upper portion thereof. A gate capping pattern GP may be formed on the recessed gate electrode GE. The gate capping pattern GP may include one or more of SiON, SiCN, SiCON, and SiN.

[0072] Reference Fig.12 and FIG. 13A to FIG. 13C , a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer or a low-k oxide layer. For example, the low-k oxide layer may include a carbon-doped silicon oxide layer (e.g., SiCOH). The second interlayer insulating layer 120 may be formed by chemical vapor deposition (CVD).

[0073] The contact holes CNH may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 to expose the first source / drain pattern SD1 and the second source / drain pattern SD2. Each of the contact holes CNH may be formed between a pair of gate electrodes GE.

[0074] The contact spacer CSP may be formed to cover the inner sidewalls of each contact hole CNH. The formation of the contact spacer CSP may include: conformally forming a contact spacer layer to cover the inner sidewalls of the contact hole CNH, and anisotropically etching the contact spacer layer. The contact spacer layer may include one or more of SiCN, SiCON, and SiN.

[0075] An active contact AC may be formed to fill the contact hole CNH. The active contact AC may contact the first source / drain pattern SD1 or the second source / drain pattern SD2. The formation of the active contact AC may include forming a barrier pattern BM and a conductive pattern FM filling the contact hole CNH. For example, a barrier layer may be conformally formed to partially fill the contact hole CNH. A conductive layer may be formed on the barrier layer to completely fill the contact hole CNH. The barrier layer and the conductive layer may be recessed to form a barrier pattern BM and a conductive pattern FM, respectively. The barrier layer may include a metal nitride, and the conductive layer may include a metal.

[0076] Reference Fig.14 and FIG. 15A to FIG. 15C , a mask pattern HM may be formed on the active contact AC. For example, a mask layer may be formed on the substrate 100. A photolithography process may be performed to form a photoresist pattern on the mask layer. The mask layer may be patterned using the photoresist pattern as an etching mask, which may result in the formation of the mask pattern HM.

[0077] The active contacts AC may be selectively etched using the mask pattern HM as an etching mask. For example, each active contact AC may include a second segment PA2 at an upper portion thereof and a first segment PA1 at a lower portion thereof. The mask pattern HM may be selectively formed on the second segment PA2. The active contacts AC may be etched using the mask pattern HM as an etching mask, and as a result, the active contacts AC other than the second segment PA2 may be removed at the upper portion of the active contacts AC. When the active contacts AC other than the second segment PA2 are removed at the upper portion of the active contacts AC, a recess RS may be formed. The recess RS may expose the sidewalls of the second segment PA2 and the top surface of the first segment PA1.

[0078] The etching of the active contact AC may be achieved using an etching recipe that can selectively etch metal (e.g., the barrier pattern BM and the conductive pattern FM). Therefore, when the active contact AC is etched, neither the contact spacer CSP nor the second interlayer insulating layer 120 is etched. When the active contact AC is etched, the mask pattern HM may protect the second segment PA2 of the active contact AC from being etched. The etching of the active contact AC may continue until the top surface of the first segment PA1 of the active contact AC becomes lower than the top surface of the gate electrode GE.

[0079] Return to reference Figure 1 and FIG. 2A to FIG. 2C , a pad CAL and an insulating pattern IP may be formed to fill the recess RS. The mask pattern HM may be removed. Each of the pad CAL and the insulating pattern IP may be formed using one or more of SiCN, SiCON, and SiN.

[0080] A third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. The first through hole VI1 may be formed to penetrate the third interlayer insulating layer 130 and have an electrical connection with the active contact AC. Each of the first through holes VI1 may be formed on the second segment PA2 of the active contact AC. For example, each of the first through holes VI1 may be formed to vertically overlap the second segment PA2 of the active contact AC. The second through hole VI2 may be formed to penetrate the third interlayer insulating layer 130, the second interlayer insulating layer 120, and the gate capping pattern GP and have an electrical connection with the gate electrode GE.

[0081] A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. An interconnection line IL may be formed in the fourth interlayer insulating layer 140. The interconnection line IL may be electrically connected to the active contact AC and the gate electrode GE through the first and second vias VI1 and VI2.

[0082] Fig.16 Plan views illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept are shown. Fig.17A , Fig. 17B and Fig. 17C Shown are Fig.16 In the following embodiments, the cross-sectional view taken along the lines A-A', B-B' and CC' of the reference numerals is shown. Figures 1 to 15C Detailed descriptions of repeated technical features of the discussed manufacturing methods will be omitted, and the differences will be discussed in detail.

[0083] Reference Fig.16 and 17A to 17C , available in Fig.12 and FIG. 13A to FIG. 13C A hard mask layer HML is formed on the resultant structure. The hard mask layer HML may be patterned to form openings OP. Each opening OP may partially expose a top surface of the active contact AC. A photolithography process may be performed to pattern the hard mask layer HML.

[0084] The opening OP of the hard mask layer HML may be filled with a mask material to form a mask pattern HM filling the opening OP. Thereafter, the hard mask layer HML may be selectively removed (see Fig.14 and FIG. 15A to FIG. 15C ).

[0085] Fig.18A and Fig.18B FIG. 1 shows semiconductor devices showing some example embodiments of the present inventive concept. Figure 1 In the following embodiments, the cross-sectional view taken along the line A-A' and the line BB' is shown. Figure 1 , FIG. 2A to FIG. 2C and Figure 3 Detailed descriptions of repeated technical features of the discussed semiconductor devices will be omitted, and the differences thereof will be discussed in detail.

[0086] Reference Figure 1 , Figure 2C , Fig.18A and Fig.18B , the mask pattern HM may be disposed on the second segment PA2 of the active contact AC. The first through hole VI1 may penetrate the mask pattern HM and have an electrical connection with the second segment PA2 of the active contact AC. The mask pattern HM may not be removed, but may be disposed on the second segment PA2 of the active contact AC. Fig.14 and FIG. 15A to FIG. 15C The active contacts AC discussed remain after etching.

[0087] Fig.19 FIG. 1 shows a semiconductor device that illustrates some example embodiments of the present inventive concept. Figure 1 In the following exemplary embodiments, the cross-sectional view taken along the line A-A' is shown. Figure 1 , FIG. 2A to FIG. 2C and Figure 3Detailed descriptions of repeated technical features of the discussed semiconductor devices will be omitted, and the differences thereof will be discussed in detail.

[0088] Reference Fig.19 Each of the first and second vias VI1 and VI2 may include a barrier pattern BM and a conductive pattern FM. Each interconnection line IL may include a barrier pattern BM and a conductive pattern FM. The barrier pattern BM may conformally cover opposite sidewalls and a bottom surface of the conductive pattern FM.

[0089] According to the inventive concept, a semiconductor device can be configured such that the size of a logic unit is reduced to increase the integration of the semiconductor device. A through hole connected to a gate electrode can be formed to be offset relative to an upper portion of an active contact adjacent to the through hole, so that an electrical short circuit can be avoided between the through hole and the active contact, and the reliability of the semiconductor device can be increased.

[0090] Although the exemplary embodiments of the present invention have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention. It will therefore be understood that the exemplary embodiments described above are only illustrative in all aspects and not restrictive.

Claims

1. A semiconductor device, comprising: a substrate comprising an active pattern extending in a first direction; a gate electrode extending across the active pattern in a second direction intersecting the first direction; a source / drain pattern on the active pattern such that the source / drain pattern is adjacent to one side of the gate electrode; an active contact including a first section and a second section, the first section of the active contact being in a first portion of a contact hole exposing the source / drain pattern, the second section of the active contact vertically protruding from the first section; an insulating pattern filling a second portion of the contact hole; a first through hole on the active contact and connected to a second segment of the active contact; as well as a second through hole on the gate electrode such that the insulating pattern is adjacent to the second through hole in the first direction, the first segment of the active contact is adjacent to the second through hole in the first direction, and the second segment of the active contact is offset relative to the second through hole in the first direction.

2. The semiconductor device according to claim 1, further comprising: A contact spacer covering the inner sidewall of the contact hole, wherein A top surface of the second segment is coplanar with a top surface of the contact spacer.

3. The semiconductor device according to claim 2, wherein: The insulating pattern is interposed between the contact spacer and the second segment.

4. The semiconductor device according to claim 1, wherein: The active contact is shaped such that a maximum width of a first section of the active contact in the second direction is greater than a maximum width of a second section of the active contact in the second direction.

5. The semiconductor device according to claim 1, wherein The active contact is shaped such that a width of a first section of the active contact in the second direction decreases toward the substrate.

6. The semiconductor device according to claim 1, wherein The active contact is shaped such that a width of a second segment of the active contact in the second direction increases toward the substrate.

7. The semiconductor device according to claim 1, wherein The active contact comprises: a conductive pattern, the conductive pattern of the first section having a first sidewall and the conductive pattern of the second section having a second sidewall; and A barrier pattern covers the first sidewall of the first segment but does not cover the second sidewall of the second segment.

8. The semiconductor device according to claim 1, wherein A top surface of the first segment is lower than a top surface of the gate electrode relative to the substrate.

9. The semiconductor device according to claim 1, wherein: The first through hole vertically overlaps the second segment.

10. The semiconductor device according to claim 1, further comprising: a first interconnection line on the first via, the first interconnection line being electrically connected to the source / drain pattern through the first via and the active contact; as well as a second interconnection line on the second through hole, the second interconnection line being electrically connected to the gate electrode through the second through hole, wherein The first interconnection line and the second interconnection line extend in parallel along the first direction.

11. A semiconductor device comprising: a substrate comprising a plurality of active patterns extending in parallel along a first direction; a gate electrode extending across the active pattern in a second direction intersecting the first direction; a source / drain pattern on the active pattern such that the source / drain pattern is adjacent to one side of the gate electrode; an active contact including a first segment and a second segment, the first segment of the active contact being on the source / drain pattern and the second segment vertically protruding from the first segment; a first through hole, which is on the second section; as well as a second through hole on the gate electrode such that the second through hole vertically overlaps at least one of the active patterns, a first segment of the active contact is adjacent to the second through hole in the first direction, and a second segment of the active contact is offset relative to the second through hole in the first direction.

12. The semiconductor device according to claim 11, further comprising: an insulating pattern on the first section of the active contact and covering a sidewall of the second section of the active contact, Wherein, the insulating pattern is adjacent to the second through hole in the first direction.

13. The semiconductor device according to claim 11, further comprising: A contact spacer covering the sidewalls of the active contact, wherein A top surface of the second segment is coplanar with a top surface of the contact spacer.

14. The semiconductor device according to claim 11, wherein The active contact is shaped such that a maximum width of a first section of the active contact in the second direction is greater than a maximum width of a second section of the active contact in the second direction.

15. The semiconductor device according to claim 11, wherein The active contact is shaped such that a width of a second segment of the active contact in the second direction increases toward the substrate.

16. A semiconductor device comprising: a substrate comprising a plurality of active patterns extending in parallel along a first direction; a gate electrode extending across the active pattern in a second direction intersecting the first direction; a source / drain pattern on the active pattern such that the source / drain pattern is adjacent to one side of the gate electrode; an active contact, comprising a first section and a second section, the first section of the active contact being on the source / drain pattern and the second section of the active contact vertically protruding from the first section, the active contact being shaped such that a width of the second section of the active contact in the second direction increases toward the substrate, wherein the second section is formed by etching the active contact; an insulating pattern on the first segment and covering a sidewall of the second segment of the active contact, the insulating pattern being formed in a recess formed by etching the active contact; a first through hole on the second section of the active contact; and a second through hole on the gate electrode, The insulating pattern is adjacent to the second through hole in the first direction, the first section of the active contact is adjacent to the second through hole in the first direction, and the second section of the active contact is offset relative to the second through hole in the first direction.

17. The semiconductor device according to claim 16, further comprising: A contact spacer covering a sidewall of the active contact, wherein A top surface of the second segment is coplanar with a top surface of the contact spacer.

18. The semiconductor device according to claim 16, wherein: The active contact is shaped such that a maximum width of a first section of the active contact in the second direction is greater than a maximum width of a second section of the active contact in the second direction.

19. The semiconductor device according to claim 16, wherein: The active contact comprises: a conductive pattern, the conductive pattern of the first segment having a first sidewall and the conductive pattern of the second segment having a second sidewall, and A barrier pattern covers the first sidewall of the first segment but does not cover the second sidewall of the second segment.

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