Memory and semiconductor devices

Abstract

The present invention provides a memory and a semiconductor device, wherein the memory comprises: a plurality of memory cells, a plurality of bit lines and a plurality of word lines, each memory cell comprises a ring-gate transistor and a capacitor connected to each other in a first direction, and the plurality of memory cells are arranged in an array, wherein the row direction and the first direction of the array of memory cells form a plane, the column direction of the array of memory cells is perpendicular to the plane, the bit lines extend along the row direction, and a plurality of drain regions corresponding to a plurality of ring-gate transistors in the same row are connected to the same bit line, the word lines extend along the column direction, and the gates of a plurality of ring-gate transistors in the same column are connected to the same word line, and when the sizes in the first direction and the row direction are limited, the memory cells can be continuously stacked in the column direction to increase the number of memory cells, thereby increasing the integration of the memory.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and manufacturing, and in particular to a memory and a semiconductor device. Background Art

[0002] The memory generally includes a plurality of memory cells, each of which includes a storage capacitor and a storage transistor connected to the storage capacitor, wherein the storage capacitor is used to store charges representing the stored information. The storage transistor is formed with an active region, a drain region and a gate, wherein the gate is used to control the current flow between the source region and the drain region and is connected to a word line, wherein the drain region is used to form a bit line contact region to be connected to a bit line, and wherein the source region is used to form a storage node contact region to be connected to the storage capacitor.

[0003] As the integration of semiconductor manufacturing processes continues to increase, it becomes increasingly difficult to produce more memory cells per unit area, and improving the integration density of memory has become a trend. Summary of the invention

[0004] The main purpose of the present invention is to provide a memory and a semiconductor device to increase the integration of the memory.

[0005] To achieve the above object, the present invention provides a memory, comprising:

[0006] A plurality of memory cells, each of the memory cells comprising a gate-all-around transistor and a capacitor connected to each other in a first direction, and the plurality of memory cells are arranged in an array, wherein a row direction of the array of the memory cells and the first direction form a plane, and a column direction of the array of the memory cells is perpendicular to the plane;

[0007] a plurality of bit lines, the bit lines extending along the row direction, and the drain regions of the plurality of gate-all-around transistors in the same row are connected to the same bit line;

[0008] A plurality of word lines are provided, the word lines extending along the column direction, and gates of a plurality of the gate-all-around transistors in the same column are connected to the same word line.

[0009] Optionally, in the memory, the ring-gate transistor also includes a channel extending along the first direction, a source region located on one side of the channel, the drain region located on the other side of the channel, the gate surrounds the channel to form a ring gate, and the bit line is connected to a side of the drain region away from the channel.

[0010] Optionally, in the memory, a plurality of drain regions corresponding to a plurality of the ring-gate transistors in the same row are connected to each other and extend continuously along the row direction.

[0011] Optionally, in the memory, the ring-gate transistor further includes a connecting portion, wherein the connecting portion is connected to a side of the source region away from the channel, and the connecting portion is connected to the capacitor.

[0012] Optionally, in the memory, the channel is a nanowire channel containing silicon and germanium components, the material of the gate contains silicon dioxide, silicon oxynitride, silicon oxycarbide or hafnium dioxide, and the material of the bit line, the word line and the connecting part all contain tungsten, titanium, titanium nitride, titanium cobalt, titanium silicon or polysilicon.

[0013] Optionally, in the memory, the capacitor includes a lower electrode plate, a dielectric layer and an upper electrode plate, and the lower electrode plate is U-shaped and connected to the connecting portion.

[0014] Optionally, in the memory, the lower electrode plate is connected to a side surface of the connection portion away from the source region, and the lower electrode plate is also connected to a top surface of the connection portion.

[0015] Optionally, in the memory, the ends of the upper electrode plates of all the capacitors away from the ring-gate transistor are connected to each other and to a metal plate.

[0016] Optionally, in the memory, the metal plate is a tungsten plate, and the material of the dielectric layer includes aluminum oxide or zirconium oxide.

[0017] Optionally, in the memory, the memory further includes an insulating layer located between adjacent capacitors and adjacent ring-gate transistors.

[0018] Optionally, in the memory, the material of the insulating layer includes silicon dioxide.

[0019] Accordingly, the present invention further provides a semiconductor device, comprising:

[0020] A plurality of memory cells, each of the memory cells comprising a gate-all-around transistor and a capacitor connected to each other in a first direction, and the plurality of memory cells are arranged in an array, wherein a row direction of the array of the memory cells and the first direction form a plane, and a column direction of the array of the memory cells is perpendicular to the plane;

[0021] a plurality of first conductor lines, wherein the first conductor lines extend along the row direction, and the plurality of drain regions corresponding to the plurality of the all-around gate transistors in the same row are connected to the same first conductor line;

[0022] A plurality of second conductor lines are provided, wherein the second conductor lines extend along the column direction, and gates of a plurality of the gate-all-around transistors in the same column are connected to the same second conductor line.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The memory provided by the present invention comprises a plurality of memory cells, a plurality of bit lines and a plurality of word lines, each of the memory cells comprises a ring-gate transistor and a capacitor connected to each other in a first direction, and the plurality of memory cells are arranged in an array, wherein the row direction of the array of the memory cells and the first direction constitute a plane, the column direction of the array of the memory cells is perpendicular to the plane, the bit lines extend along the row direction, and the plurality of drain regions corresponding to the plurality of the ring-gate transistors in the same row are connected to the same bit line, the word lines extend along the column direction, and the gates of the plurality of the ring-gate transistors in the same column are connected to the same word line, and when the dimensions of the first direction and the row direction are limited, the memory cells can be continuously stacked in the column direction to increase the number of memory cells, thereby increasing the integration of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A three-dimensional perspective view of a memory provided by an embodiment of the present invention;

[0026] Figure 2 A schematic top view of a memory provided by an embodiment of the present invention;

[0027] Figure 3 A schematic front view of a memory provided by an embodiment of the present invention;

[0028] Figure 4 for Figure 3 Schematic diagram of the cross section along the AA' direction.

[0029] The reference numerals are as follows:

[0030] 10-Gate-all-around transistor;

[0031] 11-channel;

[0032] 12-drain region; 12'-source region;

[0033] 13-gate;

[0034] 14-connecting part;

[0035] 20-capacitor;

[0036] 21-lower electrode plate;

[0037] 22- dielectric layer;

[0038] 23-upper electrode plate;

[0039] 100 - storage unit;

[0040] 200-bit line;

[0041] 300-word line;

[0042] 400-Metal sheet;

[0043] 500-Insulation layer. DETAILED DESCRIPTION

[0044] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0045] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of convenience, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

[0046] Figure 1 A three-dimensional perspective view of a memory provided by an embodiment of the present invention, Figure 2 A schematic top view of a memory provided by an embodiment of the present invention is shown in FIG. Figure 3 A schematic front view of a memory provided by an embodiment of the present invention, Figure 4 for Figure 3 For a cross-sectional view in the AA' direction, please refer to Figures 1 to 4 As shown, the memory provided by the present invention is introduced in detail.

[0047] The memory includes a plurality of memory cells 100, a plurality of bit lines 200 and a plurality of word lines 300. Each of the memory cells includes a plurality of bit lines 200 and a plurality of word lines 300. Figure 1 A ring-gate transistor 10 and a capacitor 20 are connected to each other in the x direction (as shown in FIG. 1 ), and a plurality of the memory cells 100 are arranged in an array, wherein the row direction (as shown in FIG. 1 ) of the array of the memory cells 100 Figure 1 The y direction shown in FIG. 1 ) and the first direction x form a plane, and the column direction of the array of the storage unit 100 (as shown in FIG. 1 ) and the first direction x form a plane. Figure 1 The bit line 200 extends along the row direction y, and the drain regions 12 of the plurality of the all-around gate transistors 10 in the same row are connected to the same bit line 200. The word line 300 extends along the column direction z, and the gates 13 of the plurality of the all-around gate transistors 10 in the same column are connected to the same word line 300.

[0048] exist Figure 1 In the embodiment, only one storage unit is shown in the first direction x, four storage units are shown in the row direction y, and one storage unit is shown in the column direction z. In other embodiments, multiple storage units may be provided in the first direction x, the row direction y, and the column direction z. In the first direction x, the gate-all-around transistor 10 in each storage unit 100 is connected to the capacitor 20. In the row direction y, the multiple drain regions 12 corresponding to the multiple gate-all-around transistors 10 in the same row are connected to the same bit line 200, and finally form multiple bit lines that are parallel to each other and extend along the row direction y. In the column direction z, the gates 13 of the multiple gate-all-around transistors 10 in the same column are connected to the same word line 300, and finally form multiple word lines that are parallel to each other and extend along the column direction z.

[0049] In this way, when the integration level is continuously improved and the dimensions in the first direction x and the row direction y are limited, the memory cells can be continuously stacked in the column direction z to increase the number of memory cells, thereby increasing the integration level of the memory.

[0050] Please refer to Figure 1 As shown, the all-around gate transistor 10 further includes a channel 11 extending along the first direction x, a source region 12' located on one side of the channel 11, the drain region 12 located on the other side of the channel 11, and the gate 13 surrounds part of the channel 11 to form an all-around gate. In the first direction x, the gate 13 only surrounds part of the channel 11. The bit line 200 is connected to the side of the source region 12 away from the channel 11, and the word line 300 is connected to one side of the gate 13. The drain region 12 extends along the row direction y, and the multiple drain regions 12 corresponding to the multiple all-around gate transistors 10 in the same row are connected to each other and extend continuously along the row direction y.

[0051] In the embodiment of the present application, the channel 11 is a nanowire channel containing silicon and germanium components, and the nanowire channel can effectively increase the density and mobility of carriers in the channel, reduce the subthreshold swing of the transistor, increase the selection switch ratio, and reduce the power consumption of the device. The material of the gate 13 includes but is not limited to silicon dioxide, silicon oxynitride, silicon oxycarbide or hafnium dioxide, the material of the bit line 200 includes but is not limited to tungsten, titanium, titanium nitride, titanium cobalt, titanium silicon or polysilicon, and the material of the word line 300 includes but is not limited to tungsten, titanium, titanium nitride, cobalt silicon, titanium silicon or polysilicon.

[0052] The gate-all-around transistor 10 further includes a connecting portion 14, the connecting portion 14 is connected to a side of the source region 12' away from the channel 11, and the connecting portion 14 is connected to the capacitor 20. In the embodiment of the present application, the material of the connecting portion 14 includes but is not limited to tungsten, titanium, titanium nitride, titanium cobalt, titanium silicon or polysilicon. The connecting portion 14 is used to connect the source region 12' to the capacitor 20.

[0053] In the embodiment of the present application, preferably, the channel 11 is in the form of a cylinder extending along the first direction x. The drain region 12 and the source region 12' are located at both ends of the cylinder, and are both in the form of a cuboid extending along the row direction y, and the drain region 12 connects the channels 11 of all the ring-gate transistors 10 located in the same row direction y, while the source region 12' is only connected to the channel 11 of one of the ring-gate transistors 10, that is, the source region 12' and the channel 11 are in a one-to-one correspondence, and the number of the drain regions 12 is the same as the number of the ring-gate transistors 10 arranged in the first direction x. The gate 13 is in the form of a cube surrounding the channel 11. The connecting portion 14 is in the form of a cuboid extending along the row direction y, and the shape and size of the connecting portion 14 can be the same as the shape and size of the source region 12'. The bit line 200 is in the form of a cuboid extending along the y direction, and the shape and size of the bit line 200 can be the same as the shape and size of the drain region 12. The word line 300 is a rectangular parallelepiped extending along the z direction. Of course, in other embodiments, each component may be in other shapes known to those skilled in the art.

[0054] Please refer to Figure 3 As shown, the capacitor 20 is U-shaped, and the capacitor 20 includes a lower electrode plate 21, a dielectric layer 22 and an upper electrode plate 23, that is, the lower electrode plate 21, the dielectric layer 22 and the upper electrode plate 23 are all U-shaped, and one side of the lower electrode plate 21 is connected to the connecting portion 14. In the embodiment of the present application, one side (for example, the left side) of the U-shape of the lower electrode plate 21 is connected to the connecting portion 14, that is, the lower electrode plate 21 is connected to the side surface of the connecting portion 14 away from the source region 12', and the lower electrode plate 21 is also connected to the top surface of the connecting portion 14, that is, the lower electrode plate 21 covers the top of the connecting portion 14. The side of the upper electrode plate 23 away from the ring-gate transistor 10 is connected to a metal plate 400. In the embodiment of the present application, one side (for example, the right side) of the U-shape of the upper electrode plate 23 is connected to the metal plate 400. Furthermore, the upper electrode plates 23 of all the capacitors 20 are connected to each other at the side away from the ring-gate transistor 10, and are connected to the metal plate 400. The material of the metal plate 400 is preferably tungsten. The metal plate 400 is a structure for connecting to the outside to achieve the connection between the upper electrode plate 23 and the external circuit.

[0055] The lower electrode plate 21 may be a polysilicon electrode or a metal electrode. When the lower electrode plate 21 is a metal electrode, the material of the lower electrode plate 21 may be titanium nitride (TiN). The material of the dielectric layer 22 includes but is not limited to aluminum oxide, zirconium oxide, etc. The upper electrode plate 23 may be a polysilicon electrode or a metal electrode. When the upper electrode plate 23 is a metal electrode, the material of the upper electrode plate 23 may also be titanium nitride (TiN).

[0056] The memory further includes an insulating layer 500, which is located between adjacent capacitors 20 and adjacent ring-gate transistors 10 to play an insulating role. The material of the insulating layer 500 includes but is not limited to silicon dioxide.

[0057] It should be noted that in Figure 1 In the three-dimensional perspective diagram shown in FIG. 1 , for the convenience of display, only one storage unit is set in the column direction z. Figure 3 In the front view shown in the figure, Figure 1 Correspondingly, only one storage unit should be shown, but in order to illustrate that the storage units can be continuously superimposed in the column direction z, Figure 3 Two storage units are shown in FIG.

[0058] Figure 4 yes Figure 3 The cross-sectional view in the AA' direction is also Figure 1 A schematic cross-sectional view in the row direction y and passing through the gate 13, Figure 4 Only the gate 13 , the channel 11 surrounded by the gate 13 , and the word line 300 located on one side of the gate 13 can be seen.

[0059] The memory provided in this embodiment includes a plurality of memory cells 100, a plurality of bit lines 200, and a plurality of word lines 300. Each of the memory cells 100 includes a ring-gate transistor 10 and a capacitor 20 connected to each other in a first direction x, and the plurality of memory cells 100 are arranged in an array, wherein the row direction y of the array of the memory cells 100 and the first direction x form a plane, and the column direction z of the array of the memory cells is perpendicular to the plane. The bit lines 200 extend along the row direction y, and the plurality of drain regions 12 corresponding to the plurality of the ring-gate transistors 10 in the same row are connected to the same bit line 200. The word lines 300 extend along the column direction z, and the gates 13 of the plurality of the ring-gate transistors 10 in the same column are connected to the same word line 300. When the sizes of the first direction x and the row direction y are limited, the memory cells 100 can be continuously stacked in the column direction z to increase the number of memory cells, thereby increasing the integration of the memory.

[0060] Accordingly, the present invention further provides a semiconductor device, comprising:

[0061] A plurality of memory cells, each of the memory cells comprising a gate-all-around transistor and a capacitor connected to each other in a first direction, and the plurality of memory cells are arranged in an array, wherein a row direction of the array of the memory cells and the first direction form a plane, and a column direction of the array of the memory cells is perpendicular to the plane;

[0062] a plurality of first conductor lines, wherein the first conductor lines extend along the row direction, and the plurality of drain regions corresponding to the plurality of the all-around gate transistors in the same row are connected to the same first conductor line;

[0063] A plurality of second conductor lines are provided, wherein the second conductor lines extend along the column direction, and gates of a plurality of the gate-all-around transistors in the same column are connected to the same second conductor line.

[0064] In summary, the memory and semiconductor device provided by the present invention include multiple memory cells, multiple bit lines and multiple word lines, each of the memory cells includes a ring-gate transistor and a capacitor connected to each other in a first direction, and the multiple memory cells are arranged in an array, wherein the row direction of the array of the memory cells and the first direction constitute a plane, the column direction of the array of the memory cells is perpendicular to the plane, the bit lines extend along the row direction, and the multiple drain regions corresponding to the multiple ring-gate transistors in the same row are connected to the same bit line, the word lines extend along the column direction, and the gates of the multiple ring-gate transistors in the same column are connected to the same word line, and when the sizes of the first direction and the row direction are limited, the memory cells can be continuously stacked in the column direction to increase the number of memory cells, thereby increasing the integration of the memory.

[0065] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A memory, characterized in that: include: A plurality of memory cells are arranged in an array in a first direction, a row direction, and a column direction, wherein the row direction of the memory cell array and the first direction form a plane, and the column direction of the memory cell array is perpendicular to the plane, wherein each of the memory cells comprises a ring-gate transistor and a capacitor connected to each other in the first direction, the capacitor is U-shaped, the opening direction of the U-shaped capacitor faces the column direction, one side of the U-shaped capacitor is connected to the ring-gate transistor, and the other side is connected to a metal plate; a plurality of bit lines, the bit lines extending along the row direction, and the drain regions of the plurality of gate-all-around transistors in the same row are connected to the same bit line; A plurality of word lines are provided, the word lines extending along the column direction, and gates of a plurality of the gate-all-around transistors in the same column are connected to the same word line.

2. The memory according to claim 1, wherein: The ring-gate transistor also includes a channel extending along the first direction, a source region located on one side of the channel, the drain region located on the other side of the channel, the gate surrounds the channel to form a ring gate, and the bit line is connected to the side of the drain region away from the channel.

3. The memory according to claim 2, wherein: The plurality of drain regions corresponding to the plurality of gate-all-around transistors in the same row are connected to each other and extend continuously along the row direction.

4. The memory according to claim 3, wherein: The gate-all-around transistor further includes a connection portion connected to a side of the source region away from the channel, and the connection portion is connected to the capacitor.

5. The memory according to claim 4, wherein: The channel is a nanowire channel containing silicon and germanium components, the gate is made of silicon dioxide, silicon oxynitride, silicon oxycarbide or hafnium dioxide, and the bit line, word line and connecting part are made of tungsten, titanium, titanium nitride, titanium cobalt, titanium silicon or polysilicon.

6. The memory according to claim 4, wherein: The capacitor comprises a lower electrode plate, a dielectric layer and an upper electrode plate, all of which are U-shaped; Wherein, the side of the U-shaped lower electrode plate close to the ring-gate transistor is connected to the connecting portion and covers the top of the connecting portion; The side of the U-shaped upper electrode plate away from the ring-gate transistor is connected to the metal plate, and the upper electrode plates of all capacitors in the column direction and the row direction are connected to the metal plate.

7. The memory according to claim 6, wherein: The metal plate is a tungsten plate, and the material of the dielectric layer includes aluminum oxide or zirconium oxide.

8. The memory according to claim 7, wherein: The memory further includes an insulating layer located between adjacent capacitors and adjacent gate-all-around transistors.

9. The memory according to claim 8, characterized in that The material of the insulating layer includes silicon dioxide.

10. The memory according to any one of claims 1 to 9, characterized in that: The word line is connected to one side of the gate.

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