A chip packaging structure and packaging method thereof
By adding the encapsulation layer to the chip packaging structure and reducing the depth and aspect ratio of TSV, the problem of high difficulty and cost of etching and filling of silicon wafer thickness is solved, and the mechanical strength and packaging efficiency of the chip are improved.
Patent Information
- Application Number
- CN201911392601.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-12-30
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2039-12-30
AI Technical Summary
The existing through-silicon (TSV) packaging technology has the problem of high etching when the silicon wafer is thicker and high cost. When the silicon wafer is thinner, the mechanical strength is insufficient, making it difficult to achieve effective electrical connection and filling.
The chip packaging structure is adopted to include through-silicon holes, re-wiring layer, metal connecting columns and solder balls. The chip thickness is increased by the encapsulation layer, the depth-to-face ratio of the TSV is reduced, the process steps are simplified, and the mechanical strength is improved.
It reduces the difficulty of through-silicon etching and filling, reduces costs, improves the mechanical strength and yield of the chip, and simplifies the packaging process.
Smart Images
Figure CN110931460B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a chip packaging structure and a packaging method thereof, belonging to the technical field of semiconductor chip packaging. Background Art
[0002] Through Silicon Via (TSV) interconnection technology is currently considered to be one of the most advanced technologies in the semiconductor industry. It uses short vertical electrical connections or "Through Silicon Via" through silicon to establish electrical connections from the effective surface of the chip to the back, thereby providing the shortest interconnection path. Through Silicon Via filling is a difficult process for TSV production, and the aspect ratio of TSV is one of the factors affecting the difficult process. In semiconductor products, the thickness of the silicon wafer determines the depth of the through silicon via, and the width of the TSV must meet the design requirements and cannot be increased at will. The thicker the silicon wafer, the deeper the TSV, the more difficult it is to etch the through silicon via, and the more difficult it is to form a continuous insulating layer / seed layer / barrier layer on the sidewall of the through silicon via. At the same time, the easier it is to form holes during the filling process of the through silicon via, the greater the difficulty of filling. In general, this packaging technology has the following difficulties: First, if the thickness of the silicon wafer is thicker, the deeper the through silicon via, the more difficult it is to achieve the etching, insulation, seed layer formation and electroplating filling of the through silicon via during the process, and the cost is higher; Second, if the thickness of the silicon wafer is thinner, the chip has the problem of insufficient mechanical strength and easy to break during use. Summary of the invention
[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a packaging structure and packaging method that does not increase the thickness of the silicon wafer and the difficulty of TSV implementation and processing cost, while improving the mechanical strength of the packaged chip.
[0004] The present invention is achieved in that:
[0005] The present invention provides a chip packaging structure, which includes a chip, a through silicon via, a rewiring layer, a metal connecting column and a solder ball from top to bottom, and transmits the signal received by the chip downward;
[0006] The chip comprises a silicon substrate, an electrode and a functional area, wherein the electrode and the functional area are arranged on the front side of the silicon substrate, the rewiring layer is arranged on the lower surface of the chip, a plurality of through silicon vias for transmitting signals are arranged below the electrode, the through silicon vias penetrate the silicon substrate from top to bottom and are fixedly connected to the rewiring layer, a metal connecting column is arranged below the rewiring layer, and the longitudinal section of the metal connecting column is in the shape of a flat-head solder ball;
[0007] The rewiring layer comprises at least one dielectric layer and at least one rewiring metal pattern layer which are arranged alternately with each other, wherein the dielectric layer wraps the rewiring metal pattern layer and / or fills between adjacent rewiring metal pattern layers, and the rewiring metal pattern layers are selectively electrically connected to each other and connected to the through silicon vias;
[0008] It also includes an encapsulation material layer, which encapsulates the metal connecting column. The lower surface of the metal connecting column is flush with the back of the encapsulation material layer and the lower surface of the metal connecting column is exposed. The solder ball is fixedly connected to the lower surface of the metal connecting column.
[0009] Optionally, the cross-section of the through silicon via includes but is not limited to a square hole and a circular hole.
[0010] Optionally, the number of the electrodes is an even number.
[0011] The present invention provides a packaging method for a chip packaging structure, and the implementation steps are as follows:
[0012] Step 1: providing a carrier wafer and a wafer with a functional area on the front, the wafer being a collection of a plurality of chips, and bonding the wafer to the carrier wafer by temporary bonding adhesive;
[0013] Step 2: Thinning the wafer by grinding to form a chip with a functional area on the front side, and thinning the chip to a desired thickness;
[0014] Step 3: Paste or coat a mask material on the back of the chip, form an opening in the mask material by photolithography, form a through-silicon via array at the corresponding electrode according to a pre-designed method by deep silicon etching or laser drilling in the silicon substrate, and remove the mask material;
[0015] An insulating layer is formed on the sidewall of the through silicon via and the back of the chip by sputtering or other processes to insulate the through silicon via from the wafer;
[0016] Step 4: Re-attach or coat the mask material on the back of the chip, and fill the metal in the mask pattern opening by electroplating to complete the through silicon via process; form multiple rewiring layers and multiple rewiring layer openings on the back of the chip;
[0017] The rewiring layer comprises at least one dielectric layer and at least one rewiring metal pattern layer which are arranged alternately with each other, wherein the dielectric layer wraps the rewiring metal pattern layer and / or fills between adjacent rewiring metal pattern layers, the rewiring metal pattern layers are selectively electrically connected to each other, and the multi-layer rewiring layers are fixedly connected downwardly to the metal connection pillars through the openings of the multi-layer rewiring layers;
[0018] Step 5: forming a solder ball-shaped metal connection column in the opening of the multi-layer redistribution layer by ball planting;
[0019] Step 6: Use an encapsulation method to apply an encapsulation material to the back of the functional chip on the front side, and the encapsulation material wraps the metal connecting column to form an encapsulation material layer;
[0020] Step seven: Grind the encapsulation material layer and the metal connection column by performing a planarization process of a chemical mechanical polishing step or a grinding step to expose the lower surface of the metal connection column so that the back side of the encapsulation material layer is flush with the lower surface of the metal connection column; then perform plasma treatment on the above-mentioned wafer plane, and the gas used for the plasma treatment is one or more of argon, oxygen, and carbon tetrafluoride.
[0021] Step 8: forming solder balls on the lower surface of the metal connection pillars by ball planting to complete chip packaging and form a wafer-level package;
[0022] Step nine: separating the carrier wafer from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive;
[0023] Step 10: Use laser or blade to cut the wafer-level package into individual packages.
[0024] Optionally, the metal connecting column is made of one or more of tin, silver and copper.
[0025] Optionally, the thickness of the metal connecting column is 50-200 microns.
[0026] Optionally, in step four, the process of the rewiring layer also includes the following processes: forming an electroplated metal seed layer through a sputtering process, the metal seed layer covering the side walls of the through silicon via and the back side of the chip with a functional area on the front side to facilitate electroplating thickening; forming a through silicon via by electroplating filling; after the electroplating thickening is completed, removing the metal seed layer on the back side of the chip by corrosion and other processes, and then plasma treating the above-mentioned wafer plane.
[0027] Optionally, the redistribution layer is made of one or more materials including copper, gold and silver.
[0028] Optionally, the solder ball is made of one or more of tin, silver, and copper.
[0029] Optionally, the through silicon via filling method is half filling or solid filling.
[0030] Beneficial Effects
[0031] The chip packaging structure proposed in the present invention has the following advantages by adding a 50-150 micron encapsulation material layer on the back of the silicon wafer in an encapsulation manner:
[0032] 1. Maintain the thickness of the silicon wafer at 50-150 microns. Under the TSV requirements of the same opening size, reduce the TSV aspect ratio, reduce the difficulty of etching the silicon via 11, and help form a continuous insulating layer / metal seed layer / barrier layer on the sidewall of the silicon via 11, reduce process difficulty, and reduce costs; a smaller TSV aspect ratio is conducive to filling the silicon via 11, reducing the formation of holes during the filling process, improving the yield rate, reducing the difficulty of production, and reducing costs. By increasing the overall thickness of the wafer through the encapsulation layer, the problem of insufficient mechanical strength and easy breakage of the wafer process and the chip during subsequent use is improved;
[0033] 2. The packaging method proposed for the packaging structure of the present invention has low manufacturing difficulty and low cost. Metal pillars for transmitting signals are formed before the encapsulation material layer to form metal connecting pillars. The process steps are simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 A schematic cross-sectional view of a chip packaging structure of the present invention;
[0035] Figure 2A-2I for Figure 1 A schematic diagram of the process flow of the packaging structure;
[0036] In the figure:
[0037] Chip 10
[0038] Through Silicon Via 11
[0039] Rewiring layer 14
[0040] Electrode 19
[0041] Dielectric layer 29
[0042] Encapsulation material layer 20
[0043] Metal connecting column 25
[0044] Back side of encapsulation material layer 22
[0045] Rewiring layer 14
[0046] Solder ball 24
[0047] The lower surface 26 of the metal connecting column
[0048] Carrier disc 30
[0049] Temporary bonding adhesive31. DETAILED DESCRIPTION Example
[0050] The present invention provides a chip packaging structure, such as Figure 1 As shown, Figure 1It is a cross-sectional schematic diagram of an embodiment of the present invention.
[0051] The chip packaging structure of the present invention includes a chip 10, a through silicon via 11, a redistribution layer (RDL) 14, an encapsulation material layer 20, a metal connection column 25 and a solder ball 24 from top to bottom, and transmits the signal received by the chip 10 downward to a circuit board such as a PCB.
[0052] The front side of the silicon substrate 12 of the chip 10 is provided with an electrode 19 and a functional area (not shown in the figure of the functional area), and the thickness after thinning is in the range of 50-150 microns. The number of electrodes 19 is an even number, and generally, the electrodes 19 are arranged in an array. Under the electrodes 19 in the silicon substrate 12 of the chip 10, a number of silicon through vias 11 for transmitting signals are provided according to a pre-designed scheme, and the cross-section in the figure illustrates two silicon through vias 11. The filling material of the silicon through via 11 is one or more of copper, gold, and silver. The cross section of the silicon through via 11 includes but is not limited to a square hole and a circular hole. The filling method of the silicon through via 11 is half-filled or solid filled.
[0053] The through silicon via 11 penetrates the silicon substrate 12 from top to bottom and is fixedly connected to the redistribution layer (RDL) 14 on the lower surface of the chip.
[0054] The rewiring layer 14 includes at least one dielectric layer 15 and at least one rewiring metal pattern layer arranged alternately with each other. The dielectric layer wraps the rewiring metal pattern layer and / or fills between adjacent rewiring metal pattern layers. The rewiring metal pattern layers are selectively electrically connected to each other and connected to the silicon through-hole 11 for transmitting electrical signals. The material of the rewiring metal pattern layer is one or more of copper, gold and silver.
[0055] At least one metal connection column 25 is provided in the encapsulation material layer 20 according to a pre-designed scheme, and the longitudinal section of the metal connection column 25 is in the shape of a flat-head solder ball. The material of the metal connection column 25 is one or more of tin, silver, and copper. The height of the metal connection column 25 is 50-150 microns; the metal connection column 25 is flush with the back of the encapsulation material layer, and the metal connection column 25 is connected to the solder ball 24, and the material of the solder ball 24 is one or more of tin, silver, and copper.
[0056] The functional area on the front side of the chip 10 receives the signal and transmits it to the redistribution layer (RDL) 14 through its electrode 19 and silicon through via 11. The redistribution layer (RDL) 14 is fixedly connected to the metal connection column 25 located in the encapsulation material layer 20. The metal connection column 25 transmits the signal of the chip 10 downward through the solder ball 24.
[0057] In view of the above chip packaging structure, the present invention provides a packaging method for a chip packaging structure, and the implementation steps are as follows:
[0058] Step 1: If Figure 2AAs shown, a carrier wafer 30 and a wafer with a functional area on the front are provided. The wafer is a collection of a plurality of chips 10. The wafer is bonded to the carrier wafer 30 by a temporary bonding method through a temporary bonding adhesive 31.
[0059] Step 2: If Figure 2B As shown, the chip 10 with the functional area on the front side is formed by thinning the wafer by grinding, and the chip 10 is thinned to a desired thickness, generally 50-150 microns;
[0060] Step 3: If Figure 2C As shown, a mask material is attached or coated on the back of the chip, an opening is formed in the mask material by photolithography, and a through silicon via 11 array is formed in the silicon substrate 12 at the corresponding electrode 19 according to a pre-designed manner by deep silicon etching or laser drilling, and the mask material is removed; the through silicon via 11 includes but is not limited to a square hole and a circular hole;
[0061] An insulating layer is formed on the side wall of the through silicon via 11 and the back side of the chip by a process such as sputtering to insulate the through silicon via 11 from the wafer (the insulating layer is not shown in the figure);
[0062] Step 4: If Figure 2D As shown, a mask material is re-attached or coated on the back of the chip, and metal is filled in the mask pattern opening by electroplating to complete the through silicon via 11 process; a multi-layer rewiring layer 14 and a multi-layer rewiring layer opening 17 are formed on the back of the chip, and the rewiring layer (RDL) 14 is made of one or more of copper, gold, and silver;
[0063] The rewiring layer 14 includes at least one dielectric layer 15 and at least one rewiring metal pattern layer which are arranged alternately with each other, wherein the dielectric layer wraps the rewiring metal pattern layer and / or fills between adjacent rewiring metal pattern layers, and the rewiring metal pattern layers are selectively electrically connected to each other, and the multi-layer rewiring layer 14 is fixedly connected downwardly to the metal connection column 25 through the multi-layer rewiring layer opening 17;
[0064] Specifically, a sputtering process is used to form an electroplated metal seed layer, which covers the side walls of the through silicon via 11 and the front side, and the back side of the chip with a functional area is provided to facilitate electroplating thickening; the through silicon via 11 is formed by electroplating filling, and the filling material can be one or more of gold, silver, and copper, and the filling method can be half-filling or full-filling; after the electroplating thickening is completed, the metal seed layer on the back side of the chip is removed by corrosion and other processes, and then the above-mentioned wafer plane is plasma treated, and the gas used for the plasma treatment is one or more of argon, oxygen, and carbon tetrafluoride.
[0065] Step 5: If Figure 2EAs shown, a solder ball-shaped metal connection column 25 is formed in the multi-layer rewiring layer opening 17 by ball planting, and the material of the metal connection column 25 is one or more of tin, silver, and copper;
[0066] Step 6: If Figure 2F As shown, the encapsulation material is coated on the back of the functional chip on the front side by encapsulation, and the encapsulation material wraps the metal connecting column 25 to form an encapsulation material layer 20;
[0067] Step 7: If Figure 2G As shown, by performing a planarization process of a chemical mechanical polishing (CMP) step or a grinding step, the encapsulation material layer 20 and the metal connection column 25 are ground to expose the lower surface 26 of the metal connection column and make the back side 22 of the encapsulation material layer flush with the lower surface 26 of the metal connection column; then the above-mentioned wafer plane is subjected to plasma treatment, and the gas used in the plasma treatment is one or more of argon, oxygen, and carbon tetrafluoride.
[0068] Step 8: If Figure 2H As shown, a solder ball 24 is formed on the lower surface 26 of the metal connecting column by ball planting to complete chip packaging and form a wafer-level package. The material of the solder ball 24 is one or more of tin, silver, and copper;
[0069] Step 9: If Fig.2I As shown, the carrier wafer 30 is separated from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive 31;
[0070] Step 10: Use laser or blade to cut the wafer-level package into individual packages.
[0071] The specific implementation methods described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.
Claims
1. A chip packaging structure, characterized in that: It comprises, from top to bottom, a chip (10), a through silicon via (11), a redistribution layer (14), a metal connection column (25) and a solder ball (24), and transmits the signal received by the chip (10) downward; The chip (10) comprises a silicon substrate (12), an electrode (19) and a functional area, the chip has a thickness of 50-150 microns, the electrode (19) and the functional area are arranged on the front side of the silicon substrate (12), the rewiring layer (14) is arranged on the back side of the chip (10), a plurality of through-silicon vias (11) for transmitting signals are arranged below the electrode (19), the through-silicon vias (11) penetrate the silicon substrate (12) from top to bottom and are fixedly connected to the rewiring layer (14), a metal connection column (25) is arranged below the rewiring layer (14), and the longitudinal section of the metal connection column (25) is in the shape of a flat-head solder ball; The rewiring layer (14) comprises at least one dielectric layer (15) and at least one rewiring metal pattern layer arranged in an interlaced manner, wherein the dielectric layer wraps the rewiring metal pattern layer and / or fills between adjacent rewiring metal pattern layers, and the rewiring metal pattern layers are selectively electrically connected to each other and are connected to the through silicon via (11); It also includes an encapsulation material layer (20), the encapsulation material layer (20) encapsulating the metal connection column (25), the lower surface of the metal connection column (25) is flush with the back surface of the encapsulation material layer (20), and the lower surface of the metal connection column (25) is exposed, and the solder ball (24) is fixedly connected to the lower surface of the metal connection column (25).
2. The packaging structure according to claim 1, characterized in that: The cross section of the through silicon via (11) is a square hole or a circular hole.
3. The packaging structure according to claim 1, characterized in that: The number of the electrodes (19) is an even number.
4. A packaging method for a chip packaging structure, the implementation steps of which are as follows: Step 1: providing a carrier wafer (30) and a wafer with a functional area on the front side, the wafer being a collection of a plurality of chips (10), and bonding the wafer to the carrier wafer (30) by temporary bonding using a temporary bonding adhesive (31); Step 2: thinning the wafer by grinding to form a chip (10) with a functional area on the front side, thinning the chip (10) to a desired thickness, wherein the thickness of the chip after thinning is 50-150 microns; Step 3: attaching or coating a mask material on the back of the chip, forming an opening in the mask material by photolithography, forming a through-silicon via (11) array at the corresponding electrode (19) in the silicon substrate (12) by deep silicon etching or laser drilling according to a pre-designed method, and removing the mask material; An insulating layer is formed on the side wall of the through silicon via (11) and the back side of the chip to insulate the through silicon via (11) from the wafer; Step 4: re-attach or coat the mask material on the back of the chip, fill the mask pattern opening with metal by electroplating, and complete the through silicon via (11) process; form a multi-layer rewiring layer (14) and a multi-layer rewiring layer opening (17) on the back of the chip; The rewiring layer (14) comprises at least one dielectric layer (15) and at least one rewiring metal pattern layer arranged in an interlaced manner, the dielectric layer wraps the rewiring metal pattern layer and / or fills between adjacent rewiring metal pattern layers, the rewiring metal pattern layers are selectively electrically connected to each other, and the multi-layer rewiring layer (14) is fixedly connected downwardly to the metal connection column (25) through the multi-layer rewiring layer opening (17); Step 5: forming a solder ball-shaped metal connection column (25) in the multi-layer redistribution layer opening (17) by ball planting; Step 6: using an encapsulation method, coating an encapsulation material on the back of the functional chip provided on the front side, and the encapsulation material wraps the metal connecting column (25) to form an encapsulation material layer (20); Step 7: grinding the encapsulation material layer (20) and the metal connection column (25) by performing a planarization process of a chemical mechanical polishing step or a grinding step, exposing the lower surface (26) of the metal connection column and making the back side (22) of the encapsulation material layer flush with the lower surface (26) of the metal connection column; then performing a plasma treatment on the above-mentioned wafer plane, wherein the gas used in the plasma treatment is one or more of argon, oxygen, and carbon tetrafluoride; Step eight: forming solder balls (24) on the lower surface (26) of the metal connection pillars by ball planting, completing chip packaging and forming a wafer-level package; Step nine: separating the carrier wafer (30) from the wafer-level package by irradiating UV light or laser on the temporary bonding adhesive (31); Step 10: Use laser or blade to cut the wafer-level package into individual packages.
5. The packaging method according to claim 4, characterized in that: The material of the metal connection column (25) is one or more of tin, silver and copper.
6. The packaging method according to claim 4 or 5, characterized in that: The thickness of the metal connecting column (25) is 50-200 microns.
7. The packaging method according to claim 4, characterized in that: In step 4, the process of the rewiring layer (14) also includes the following processes: forming an electroplated metal seed layer by a sputtering process, the metal seed layer covering the side walls of the through silicon hole (11) and the front side of the chip with a functional area on the back side, so as to facilitate electroplating thickening; forming the through silicon hole (11) by electroplating filling; after the electroplating thickening is completed, removing the metal seed layer on the back side of the chip by an etching process, and then plasma processing the wafer plane.
8. The packaging method according to claim 4, characterized in that: The material of the rewiring layer (14) is one or more of copper, gold and silver.
9. The packaging method according to claim 4, characterized in that: The material of the solder ball (24) is one or more of tin, silver and copper.
10. The packaging method according to claim 4, characterized in that: The through silicon via (11) is filled in a half-filled or solid-filled manner.