Capacitor array structure and forming method thereof, and semiconductor device

Abstract

The present invention provides a capacitor array structure and a method for forming the same, as well as a semiconductor device. A peripheral wrapping main body support layer is formed on a device region to obtain a flat capacitor array boundary, thereby avoiding the formation of cracks due to uneven capacitor array boundaries during subsequent deposition of filling materials, thereby avoiding the short circuit problem between a plug and the capacitor array boundary caused by the cracks, thereby increasing the stability of the array region and improving the reliability of the capacitor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and manufacturing, and in particular to a capacitor array structure and a forming method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the performance requirements for capacitors in semiconductor integrated circuits are becoming higher and higher. For example, it is hoped that the capacitor formed in a limited area can have a larger capacitance. One solution is to increase the height of the lower electrode in the capacitor to increase the contact area between the lower electrode and the capacitor dielectric layer, so that the formed capacitor has a larger capacitance.

[0003] However, as the height of the lower electrode increases, the aspect ratio of the lower electrode also increases accordingly, which can easily lead to the problem of bending, deformation or collapse of the lower electrode, affecting the reliability of the array area. Currently, stability is increased by adding a lateral continuous support layer of the electrode, but such a continuous support layer will form an uneven capacitor array boundary, and cracks are easily formed at the capacitor array boundary during the subsequent deposition of filling materials, causing a short circuit between the plug and the capacitor array boundary. Therefore, it is necessary to protect the capacitor array boundary. Summary of the invention

[0004] The object of the present invention is to provide a capacitor array structure and a method for forming the same, as well as a semiconductor device, to avoid short circuit problems caused by cracks formed at the boundaries of the capacitor array when depositing filling materials, thereby improving the reliability of the capacitor.

[0005] The present invention provides a method for forming a capacitor array structure, comprising:

[0006] Providing a substrate, wherein the substrate has a device region for forming a capacitor and a peripheral region located outside the device region;

[0007] A sacrificial layer and a main support layer are formed in the device area, wherein the main support layer includes a transverse support layer and a longitudinal support layer, wherein the transverse support layer covers the upper surface of the sacrificial layer, the longitudinal support layer covers the side surface of the sacrificial layer close to the peripheral area, and the longitudinal support layer connects the transverse support layer and the substrate;

[0008] forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate the lateral support layer and the sacrificial layer to expose the substrate;

[0009] forming a lower electrode, wherein the lower electrode covers the sidewall and the bottom of the through hole to form a plurality of cylindrical structures;

[0010] The sacrificial layer is removed, and a capacitor dielectric layer and an upper electrode are sequentially formed on the inner and outer surfaces of the lower electrode to form a capacitor.

[0011] Preferably, at least one lower supporting layer is formed between the transverse supporting layer and the substrate, the lower supporting layer is parallel to the transverse supporting layer, and one end of the lower supporting layer is connected to the longitudinal supporting layer.

[0012] Preferably, the method for forming the lower supporting layer comprises:

[0013] Forming a lower stacked structure with a sacrificial layer and a lower supporting layer alternately arranged on the substrate;

[0014] forming a main support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;

[0015] forming a plurality of through holes, wherein the through holes sequentially penetrate the lateral support layer and the lower laminate structure to expose the substrate;

[0016] forming a lower electrode, the lower electrode covering the sidewall and bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal support layer close to the peripheral area;

[0017] The sacrificial layer is removed, and the lateral support layer and the lower support layer are connected to the outer wall of the lower electrode cylindrical structure.

[0018] Preferably, at least one upper supporting layer is formed on the transverse supporting layer, the upper supporting layer is parallel to the transverse supporting layer, and one end of the upper supporting layer is kept flush with the longitudinal supporting layer in a direction perpendicular to the base.

[0019] Preferably, the method for forming the upper supporting layer includes:

[0020] forming an upper stacked structure in which a sacrificial layer and an upper supporting layer are alternately arranged on the lateral supporting layer;

[0021] forming a plurality of through holes, wherein the through holes sequentially penetrate the upper stacked structure, the lateral support layer and the sacrificial layer to expose the substrate;

[0022] forming a lower electrode, the lower electrode covering the sidewall and bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side of the longitudinal support layer close to the peripheral area and the side of the upper stacked structure close to the peripheral area;

[0023] The sacrificial layer is removed, and the upper supporting layer and the lateral supporting layer are connected to the outer wall of the lower electrode cylindrical structure.

[0024] Preferably, at least one lower supporting layer is formed between the transverse supporting layer and the base, and at least one upper supporting layer is formed on the transverse supporting layer; the upper supporting layer and the lower supporting layer are both parallel to the transverse supporting layer, one end of the lower supporting layer is connected to the longitudinal supporting layer, and one end of the upper supporting layer remains flush with the longitudinal supporting layer in a direction perpendicular to the base.

[0025] Preferably, the method for forming the upper supporting layer and the lower supporting layer comprises:

[0026] Forming a lower stacked structure with a sacrificial layer and a lower supporting layer alternately arranged on the substrate;

[0027] forming a main support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;

[0028] forming an upper stacked structure in which a sacrificial layer and an upper supporting layer are alternately arranged on the lateral supporting layer;

[0029] forming a plurality of through holes, wherein the through holes sequentially penetrate the upper laminate structure, the lateral support layer, and the lower laminate structure to expose the substrate;

[0030] forming a lower electrode, the lower electrode covering the sidewall and bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side of the longitudinal support layer close to the peripheral area and the side of the upper stacked structure close to the peripheral area;

[0031] The sacrificial layer is removed, and the upper supporting layer and the lateral supporting layer are connected to the outer wall of the lower electrode cylindrical structure.

[0032] Preferably, the lower electrode also covers the side surface of the longitudinal support layer close to the peripheral area and the side surface of the upper stacked structure close to the peripheral area.

[0033] Preferably, an isolation layer is formed between the sacrificial layer and the substrate, and the isolation layer is arranged at the periphery of the bottom of the lower electrode cylindrical structure.

[0034] Preferably, a plurality of node contacts are formed in the substrate, the through holes expose the node contacts, and the lower electrodes are connected to the node contacts at the bottoms of the through holes.

[0035] Preferably, the main support layer, the upper support layer, the lower support layer and the isolation layer are all made of silicon nitride.

[0036] Furthermore, the present invention provides a capacitor array structure, comprising:

[0037] A plurality of capacitors arranged in an array in a substrate device region, each of the capacitors comprising: a lower electrode, a capacitor dielectric layer and an upper electrode; wherein the lower electrode is arranged on the substrate and has a plurality of cylindrical structures; the capacitor dielectric layer is arranged on the inner and outer surfaces of the lower electrode; and the upper electrode is arranged on the outer surface of the capacitor dielectric layer;

[0038] The main support layer comprises a transverse support layer and a longitudinal support layer; wherein the transverse support layer is arranged on the device area, and the transverse support layer is connected to the outer wall of the lower electrode tubular structure; the longitudinal support layer is arranged at one end of the transverse support layer, and the longitudinal support layer is connected to the transverse support layer and the substrate; a lower electrode is arranged on a side of the longitudinal support layer different from the transverse support layer.

[0039] Preferably, at least one lower supporting layer is provided between the transverse supporting layer and the substrate, the lower supporting layer is connected to the outer wall of the lower electrode tubular structure, and one end of the lower supporting layer is connected to the longitudinal supporting layer.

[0040] Preferably, at least one upper supporting layer is disposed on the transverse supporting layer, the upper supporting layer is connected to the outer wall of the lower electrode tubular structure, and one end of the upper supporting layer is kept flush with the longitudinal supporting layer in a direction perpendicular to the base.

[0041] Preferably, at least one lower supporting layer is disposed between the transverse supporting layer and the substrate, and at least one upper supporting layer is disposed on the transverse supporting layer.

[0042] Preferably, the lower support layer and the upper support layer are connected to the outer wall of the lower electrode tubular structure, one end of the lower support layer is connected to the longitudinal support layer, and one end of the upper support layer is flush with the longitudinal support layer in a direction perpendicular to the base.

[0043] Preferably, the lower electrode disposed on a side of the longitudinal support layer different from the transverse support layer extends and connects to the upper support layer.

[0044] Preferably, an isolation layer is also provided on the substrate, and the isolation layer is provided at the periphery of the bottom of the lower electrode tubular structure; the capacitor array structure also includes a plurality of node contacts located in the substrate, and the bottom of the lower electrode tubular structure is connected to the node contacts.

[0045] Preferably, the main support layer, the upper support layer and the lower support layer are all made of silicon nitride, and the sacrificial layer is made of silicon oxide.

[0046] Furthermore, the present invention also provides a semiconductor device, comprising the above capacitor array structure.

[0047] Preferably, the semiconductor device is applied to a dynamic random access memory.

[0048] In summary, in the method for forming a capacitor array structure provided by the present invention, a peripherally wrapped main support layer is formed on the device area to obtain a flat capacitor array boundary, thereby avoiding the formation of cracks due to the unevenness of the capacitor array boundary during the subsequent deposition of filling materials, thereby avoiding the short circuit problem between the plug and the capacitor array boundary caused by the cracks, thereby increasing the stability of the array area and improving the reliability of the capacitor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a cross-sectional schematic diagram of a capacitor in the prior art during its preparation process;

[0050] Figure 2 A schematic diagram of a process of forming a capacitor array structure provided in the first embodiment of the present invention;

[0051] Figures 3 to 9 It is a cross-sectional schematic diagram corresponding to corresponding steps in the method for forming a capacitor array structure provided in the first embodiment of the present invention;

[0052] Figures 10 to 15 It is a cross-sectional schematic diagram corresponding to corresponding steps in the method for forming a capacitor array structure provided in the second embodiment of the present invention;

[0053] Figures 16 to 20 It is a cross-sectional schematic diagram corresponding to corresponding steps in the method for forming a capacitor array structure provided in the third embodiment of the present invention;

[0054] Figure 21 to Figure 23 It is a cross-sectional schematic diagram corresponding to corresponding steps in the method for forming a capacitor array structure provided in the fourth embodiment of the present invention.

[0055] The reference numerals are as follows:

[0056] 10 / 100-substrate; 10A / 100A-device area;

[0057] 10B / 100B-peripheral area; 100A-edge part of the device area;

[0058] 11-crack; 12-plug;

[0059] 101-contact point; 102-isolation layer;

[0060] 103-sacrificial layer; 120-main support layer;

[0061] 104- transverse support layer; 105- longitudinal support layer;

[0062] 130-through hole; 106-lower electrode;

[0063] 107-capacitor dielectric layer; 108-upper electrode;

[0064] 109-upper electrode filling layer; 110-upper electrode connecting layer;

[0065] 200-lower laminate structure; 201-first lower supporting layer;

[0066] 202-second lower supporting layer; 210-first lower sacrificial layer;

[0067] 220-second lower sacrificial layer; 300-upper stacking structure;

[0068] 301-first upper supporting layer; 302-second upper supporting layer;

[0069] 310-first upper sacrificial layer; 320-second upper sacrificial layer; DETAILED DESCRIPTION

[0070] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a capacitor in the prior art during its preparation process, as shown in FIG. Figure 1 As shown, in the conventional capacitor formation process, a filling material layer is deposited after the process of the capacitor device in the device area (array area) 10A is completed. Since the capacitor array boundary in the device area 10A is uneven, cracks 11 (Crack) are prone to occur in the uneven places (shown by circles). In the subsequent process of forming plugs 12 (CT), dry etching and wet cleaning of the plug holes will aggravate the gaps of the cracks. When metal is filled later, the metal will also drill into the gaps, causing a short circuit between the plug and the capacitor array boundary or between the plugs, thereby affecting the reliability of the capacitor device.

[0071] The core idea of ​​the invention is to provide a capacitor array structure and a method for forming the same, as well as a semiconductor device. By forming a peripheral wrapping support structure in the device area, a flat capacitor array boundary is obtained, thereby avoiding the formation of cracks due to the unevenness of the capacitor array boundary during the subsequent deposition of filling materials, thereby avoiding the short circuit problem between the plug and the capacitor array boundary caused by the cracks, thereby increasing the stability of the array area and improving the reliability of the capacitor device.

[0072] The following is a further detailed description of the capacitor array and its formation method and semiconductor device proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0073] Embodiment 1

[0074] Figure 2 FIG. 1 is a flow chart of a method for forming a capacitor array structure according to an embodiment of the present invention. Figure 2 As shown, the method for forming a capacitor array structure provided by the present invention includes:

[0075] S01: providing a substrate, wherein the substrate has a device region for forming a capacitor and a peripheral region located outside the device region;

[0076] S02: forming a sacrificial layer and a main support layer in the device area, wherein the main support layer includes a lateral support layer and a longitudinal support layer, wherein the lateral support layer covers the upper surface of the sacrificial layer, and the longitudinal support layer covers the side surface of the sacrificial layer close to the peripheral area, and the longitudinal support layer connects the lateral support layer and the substrate;

[0077] S03: forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate the lateral support layer and the sacrificial layer to expose the substrate;

[0078] S04: forming a lower electrode, wherein the lower electrode covers the sidewall and the bottom of the through hole to form a plurality of cylindrical structures;

[0079] S05: removing the sacrificial layer, and sequentially forming a capacitor dielectric layer and an upper electrode on the inner and outer surfaces of the lower electrode to form a capacitor.

[0080] Figures 3 to 9 The cross-sectional schematic diagrams corresponding to the corresponding steps in the method for forming a capacitor array structure provided in the first embodiment of the present invention are shown below. The method for forming a capacitor array in the present embodiment is further explained in combination with the corresponding structural schematic diagrams of each step.

[0081] In step S01, please refer to Figure 3 As shown, a substrate 100 is provided, the substrate 100 includes a device region 100A for forming a capacitor and a peripheral region 100B located outside the device region 100A, the device region 100A and the peripheral region 100B are isolated by a trench isolation structure. In the cross-sectional structure diagram of the capacitor array below, only the capacitor device region 100A is shown.

[0082] The material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon on insulator (SOI), etc., or other materials known to those skilled in the art. A plurality of node contacts 101 are also formed in the substrate 100, and the node contacts 101 are electrically connected to the lower electrode of the capacitor formed subsequently. Of course, other device structures such as isolation structures can also be formed in the substrate 100, and the present invention is not limited to this.

[0083] In step S02, first, refer to Figure 3 As shown, an isolation layer 102 and a sacrificial layer 103 are sequentially formed on the substrate 100. Then, please refer to Figure 4 As shown, a mask layer (not shown) is formed on the sacrificial layer 102, and the mask layer is patterned. The patterned mask layer covers the area where the capacitor array is formed in the device area 100A, exposing the peripheral area 100B and the edge portion 100A' of the device area 100A connected to the peripheral area 100B, and then the sacrificial layer 103 is etched using the patterned mask layer as a mask until the isolation layer 102 is exposed, and the patterned mask layer is removed.

[0084] Next, please refer to Figure 5 As shown, a main support layer 120 is formed on the sacrificial layer 102, and the main support layer 120 includes a lateral support layer 104 and a longitudinal support layer 105. The lateral support layer 104 covers the upper surface of the sacrificial layer 103, and the longitudinal support layer 105 covers a side surface of the sacrificial layer 103 and the isolation layer 102 on the edge portion 100A' of the device area. The side surface is a side of the longitudinal support layer 105 close to the peripheral area 100B, and the longitudinal support layer 105 connects the lateral support layer 104 and the isolation layer 102.

[0085] The materials of the main support layer 120 and the isolation layer 102 include but are not limited to silicon nitride, and the material of the sacrificial layer includes but is not limited to silicon oxide. The main support layer 120 and the sacrificial layer 103 can be formed by a deposition process, such as a chemical vapor deposition process. The main support layer 120 can be formed in a one-step deposition process, or in two-step deposition processes to form the lateral support layer 104 and the longitudinal support layer 105 respectively. Preferably, in this embodiment, the main support layer 120 can be formed in a one-step deposition process. The thickness of the sacrificial layer 103 defines the height of the lateral support layer 104 formed subsequently, so the thickness of the sacrificial layer 103 can be adjusted according to the height position of the lateral support layer 104 to be formed.

[0086] In step S03, please refer to Figure 6As shown, a plurality of through holes 130 are formed in the device region 100A. The through holes 130 sequentially penetrate the lateral support layer 104 , the sacrificial layer 103 , and the isolation layer 102 to expose the substrate 100 .

[0087] Specifically, a mask layer is formed on the lateral support layer 104, and the mask layer is patterned to expose the area where the through hole is predetermined to be formed, and then the lateral support layer 104, the sacrificial layer 103 and the isolation layer 102 are etched in sequence with the patterned mask layer as a mask to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal pattern. It can be understood that by forming the through holes 130 on the lateral support layer 104 and the sacrificial layer 103, a lower electrode having a tubular structure can be formed at the bottom and sidewall of the through holes 130, and therefore, the total height of the lateral support layer 104 and the sacrificial layer 103 can define the height of the tubular structure in the lower electrode formed subsequently, so that the height of the capacitor formed subsequently can be increased by increasing the thickness of the sacrificial layer 103, thereby increasing the electrode surface area of ​​the capacitor, and thus, the capacitance value of the formed capacitor can be increased.

[0088] In step S04, please refer to Figure 7 As shown, a lower electrode 106 is formed in the through hole 130 , and the lower electrode 106 covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures.

[0089] The portion of the lower electrode 106 located in the through hole 130 has a shape consistent with the shape of the through hole 130, so that the portion of the lower electrode 106 located in the through hole 130 forms a cylindrical structure. Further, the lower electrode 106 can be a polysilicon electrode or a metal electrode. When the lower electrode 106 is a metal electrode, for example, it can be formed of titanium nitride (TiN).

[0090] Specifically, the lower electrode 106 can be formed by combining a planarization process on the basis of a deposition process. For example, first, an electrode material layer is formed on the substrate 100, and the electrode material layer covers the bottom and side walls of the through hole 130, as well as the lateral support layer 104; then, a planarization process (for example, a chemical mechanical polishing process) is performed to remove the portion of the electrode material layer located above the lateral support layer 104, so that the remaining electrode material layer is only formed in the through hole 130 to form a lower electrode with a tubular structure.

[0091] Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 104 close to the peripheral area 100B and the isolation layer on the edge portion 100A′ of the device area.

[0092] In addition, in the present embodiment, the node contact 101 is exposed through the through hole 130 , so that the bottom of the tubular structure of the formed lower electrode 106 can be electrically connected to the node contact 101 .

[0093] In step S05, please refer to Figures 8 to 9 As shown, the sacrificial layer 103 is removed, and a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor.

[0094] Specifically, first, a first opening is formed in the lateral support layer 104 to expose the sacrificial layer 103, and the sacrificial layer 103 is removed by etching to form Figure 8 The structure shown in FIG. wherein one of the first openings overlaps only one of the through holes 130, or one of the first openings overlaps with a plurality of the through holes 130 at the same time. After removing the sacrificial layer 103, the lateral support layer 104 is connected to the outer wall of the tubular structure of the lower electrode 106, and the longitudinal support layer 105 is connected to the lateral support layer 104 and the isolation layer 102, so that a peripheral wrapping support structure is formed on the device area 100A.

[0095] Then, please refer to Fig. 9 As shown, a capacitor dielectric layer 107 is formed on the inner and outer surfaces of the lower electrode 106 and the exposed surface of the lateral support layer 104. The capacitor dielectric layer 107 covers the inner surface of the tubular structure of the lower electrode 106 located inside the tube and the outer surface located outside the tube, so as to make full use of the two opposite surfaces of the lower electrode 106 to form an integrated circuit capacitor with a large electrode surface area. Specifically, the capacitor dielectric layer 107 can be formed by a vapor deposition process. Preferably, the capacitor dielectric layer 107 can be a high-K dielectric layer. Further, the capacitor dielectric layer 107 is a multi-layer structure, for example, a two-layer structure of a silicon dioxide layer / silicon nitride layer. When forming the capacitor dielectric layer 107, the silicon dioxide layer and the silicon nitride layer can be formed in sequence.

[0096] In addition, in the present embodiment, the bottom of the outer part of the tubular structure of the lower electrode 106 is connected to the node contact 101 formed in the device region 100A, and the outer wall of the tubular structure of the lower electrode 106 is connected to the lateral support layer 104 and the isolation layer 102. Therefore, the capacitor dielectric layer 107 does not cover the bottom part of the tubular structure of the lower electrode 106, and does not cover the part of the outer wall of the tubular structure of the lower electrode 106 connected to the lateral support layer 104.

[0097] Next, please continue to refer to Fig. 9 As shown, an upper electrode 108 is formed on the inner surface and the outer surface of the capacitor dielectric layer 107. The upper electrode 108 can form a capacitor with the capacitor dielectric layer 106 and the lower electrode 106 both inside and outside the corresponding cylindrical structure.

[0098] Finally, please continue to refer to Fig. 9 As shown, an electrode filling layer 109 and an electrode connection layer 110 are sequentially formed on the upper electrode 108. The upper electrode filling layer 109 covers the upper electrode 108 and fills the gap between the upper electrodes 108. The material of the upper electrode filling layer 109 includes boron-doped polysilicon; the upper electrode connection layer 110 covers the outer surface of the upper electrode filling layer 109. The material of the upper electrode connection layer 110 includes but is not limited to tungsten.

[0099] In the method for forming a capacitor array structure provided in the first embodiment of the present invention, a peripherally wrapped main support layer is formed on the device area. Compared with the single lateral support layer in the prior art, the boundary of the capacitor array is a flat structure, which avoids the formation of cracks due to the unevenness of the capacitor array boundary during the subsequent deposition of filling materials, thereby avoiding the short circuit problem between the plug and the capacitor array boundary caused by the cracks, thereby increasing the stability of the array area and improving the reliability of the capacitor device.

[0100] Embodiment 2

[0101] This embodiment provides a method for forming a capacitor array structure. Compared with the first embodiment, this embodiment forms at least one lower support layer between the transverse support layer 104 of the main support layer and the isolated layer 102. The lower support layer is parallel to the transverse support layer 104, and one end of the lower support layer is connected to the longitudinal support layer 104. The specific formation steps include:

[0102] S11: forming a lower stacked structure in which a sacrificial layer and a lower supporting layer are alternately arranged on the substrate;

[0103] S12: forming a main support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area;

[0104] S13: forming a plurality of through holes, wherein the through holes sequentially penetrate the lateral support layer and the lower laminate structure to expose the substrate;

[0105] S14: forming a lower electrode, wherein the lower electrode covers the sidewall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal support layer close to the peripheral area;

[0106] S15: removing the sacrificial layer, and connecting the lateral support layer and the lower support layer to the outer wall of the lower electrode cylindrical structure.

[0107] Figures 10 to 15 Schematic diagram of cross-sections corresponding to corresponding steps in the method for forming a capacitor array structure provided in the second embodiment of the present invention. In step S11, please refer to Fig.10 As shown, a first lower sacrificial layer 210, a first lower supporting layer 201 and a second lower sacrificial layer 220 are sequentially formed on the substrate 100 to form a lower stacked structure 200 in which sacrificial layers and lower supporting layers are alternately arranged. Preferably, an isolation layer 102 is also formed between the first lower sacrificial layer 210 and the substrate 100 to isolate the storage transistor in the substrate 100 from the capacitor device above.

[0108] In step S12, please refer to Fig.11 As shown, a main support layer 120 is formed, the transverse support layer 104 covers the upper surface of the lower laminated structure 200, and the longitudinal support layer 105 covers the side surface of the lower laminated structure 200 close to the peripheral area 100B.

[0109] First, a mask layer (not shown) is formed on the second lower sacrificial layer 220, and the mask layer is patterned. The patterned mask layer covers the area where the capacitor array is formed in the device area 100A, exposing the peripheral area 100B and the edge portion 100A' of the device area 100A connected to the peripheral area 100B. Then, the second lower sacrificial layer 220, the first lower supporting layer 201 and the first lower sacrificial layer 210 are etched in turn using the patterned mask layer as a mask until the isolation layer 102 is exposed, and the patterned mask layer is removed.

[0110] Next, a main support layer 120 is formed on the second lower sacrificial layer 220, and the main support layer 120 includes a lateral support layer 104 and a longitudinal support layer 105. The lateral support layer 104 covers the upper surface of the second lower sacrificial layer 220, and the longitudinal support layer 105 covers a side surface of the lower stacked structure 200 and the isolation layer 102 on the edge portion 100A' of the device area. The side surface is a side of the longitudinal support layer 105 close to the peripheral area 100B, and the longitudinal support layer 105 connects the lateral support layer 104 and the isolation layer 102.

[0111] The materials of the main support layer 120 and the isolation layer 102 include but are not limited to silicon nitride, and the material of the sacrificial layer includes but is not limited to silicon oxide. The main support layer 120 and the sacrificial layer can be formed by a deposition process, such as a chemical vapor deposition process. The thickness of the first lower sacrificial layer 210 defines the height of the first lower support layer 201 formed subsequently, so the thickness of the first lower sacrificial layer 210 can be adjusted according to the height position of the first lower support layer 201 to be formed. The thickness of the second lower sacrificial layer 220 defines the height of the lateral support layer 105 to be formed subsequently, so the thickness of the second lower sacrificial layer 220 can be adjusted according to the height position of the lateral support layer 105 to be formed.

[0112] In step S13, please refer to Fig.12 As shown, a plurality of through holes 130 are formed, and the through holes 130 sequentially penetrate the lateral support layer 104 and the lower laminated structure 200 to expose the substrate 100 .

[0113] Specifically, a mask layer is formed on the lateral support layer 104, the mask layer is patterned to expose the area where the through hole is predetermined to be formed, and then the lateral support layer 104, the second lower sacrificial layer 220, the first lower support layer 201, the first lower sacrificial layer 210 and the isolation layer 102 are sequentially etched using the patterned mask layer as a mask to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal pattern. It can be understood that by forming the through hole 130 in the lateral support layer 104 and the lower stacked structure 200, a lower electrode having a tubular structure can be formed at the bottom and side walls of the through hole 130. Therefore, the total height of the lateral support layer 104 and the lower stacked structure 200 can define the height of the tubular structure in the subsequently formed lower electrode, so that the height of the subsequently formed capacitor can be increased by increasing the thickness of the first lower sacrificial layer 210 and the second lower sacrificial layer 220, thereby increasing the electrode surface area of ​​the capacitor. In this way, the capacitance value of the formed capacitor can be increased.

[0114] In step S14, please continue to refer to Fig.12 As shown, a lower electrode 106 is formed in the through hole 130 , and the lower electrode 106 covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures.

[0115] The portion of the lower electrode 106 located in the through hole 130 has a shape consistent with the shape of the through hole 130, so that the portion of the lower electrode 106 located in the through hole 130 forms a cylindrical structure. Further, the lower electrode 106 can be a polysilicon electrode or a metal electrode. When the lower electrode 106 is a metal electrode, for example, it can be formed of titanium nitride (TiN).

[0116] Specifically, the lower electrode 106 can be formed by combining a planarization process on the basis of a deposition process. For example, first, an electrode material layer is formed on the substrate 100, and the electrode material layer covers the bottom and side walls of the through hole 130, as well as the lateral support layer 104; then, a planarization process (for example, a chemical mechanical polishing process) is performed to remove the portion of the electrode material layer located above the lateral support layer 104, so that the remaining electrode material layer is only formed in the through hole 130 to form a lower electrode with a tubular structure.

[0117] Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 105 close to the peripheral area 100B and the isolation layer on the edge portion 100A′ of the device area.

[0118] In addition, in the present embodiment, the node contact 101 is exposed through the through hole 130 , so that the bottom of the tubular structure of the formed lower electrode 106 can be electrically connected to the node contact 101 .

[0119] In step S15, please refer to Fig.13 As shown, the sacrificial layer is removed, and the lateral support layer 104 and the first lower support layer 201 are connected to the outer wall of the tubular structure of the lower electrode 106 .

[0120] Specifically, first, a first opening is formed in the lateral support layer 104 to expose the second lower sacrificial layer 220, and the second lower sacrificial layer 220 is removed by etching; a second opening is formed in the first lower support layer 201 to expose the first lower sacrificial layer 210; the first lower sacrificial layer 210 is removed by etching; wherein, one of the first openings overlaps with only one of the through holes 130, or one of the first openings overlaps with multiple through holes 130 at the same time; one of the second openings overlaps with only one of the through holes 130, or one of the second openings overlaps with multiple through holes 130 at the same time. After removing the sacrificial layer 103, the lateral support layer 104 and the first lower support layer 201 are connected to the outer wall of the tubular structure of the lower electrode 106, and the longitudinal support layer 105 is connected to the lateral support layer 104, the first lower support layer 201 and the isolation layer 102, so that a peripheral wrapping support structure is formed on the device area 100A.

[0121] Then, please refer to Fig.14 As shown, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. Please refer to the first embodiment for the specific formation method.

[0122] In addition, a plurality of lower support layers 200 may be formed between the lateral support layer 104 and the isolation layer 102, such as Fig.15 As shown, a first lower supporting layer 201 and a second lower supporting layer 202 are formed between the lateral supporting layer 104 and the isolation layer 102, and the specific forming method is not repeated here.

[0123] Embodiment 3

[0124] This embodiment provides a method for forming a capacitor array structure. Compared with the first embodiment, this embodiment forms at least one upper support layer on the transverse support layer 104 of the main support layer, the upper support layer is parallel to the transverse support layer 104, and one end of the upper support layer is flush with the longitudinal support layer 104 in a direction perpendicular to the substrate. The specific formation steps include:

[0125] S21: forming an upper stacked structure in which a sacrificial layer and an upper supporting layer are alternately arranged on the lateral supporting layer;

[0126] S22: forming a plurality of through holes, wherein the through holes sequentially penetrate the upper stacked structure, the lateral support layer, and the sacrificial layer to expose the substrate;

[0127] S23: forming a lower electrode, wherein the lower electrode covers the sidewall and the bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal support layer close to the peripheral area and the side surface of the upper stacked structure close to the peripheral area;

[0128] S24: removing the sacrificial layer, and connecting the upper supporting layer and the lateral supporting layer to the outer wall of the lower electrode cylindrical structure.

[0129] Figures 16 to 20 Schematic diagram of cross-section corresponding to the corresponding steps in the method for forming a capacitor array structure provided in the third embodiment of the present invention. In step S21, please refer to Fig.16 As shown, first, a lateral main support layer 120 is formed by referring to steps S01-S02 in the first embodiment. Then, a first upper sacrificial layer 310 and a first upper support layer 301 are sequentially formed on the lateral support layer 104 to form an upper stacked structure 300 .

[0130] In step S21, please refer to Fig.17 As shown, a plurality of through holes 130 are formed, and the through holes 130 sequentially penetrate the upper stacked structure 300 , the lateral support layer 104 , and the sacrificial layer 103 to expose the substrate 100 .

[0131] Specifically, a mask layer is formed on the first upper support layer 301, the mask layer is patterned to expose the area where the through hole is predetermined to be formed, and then the first upper support layer 301, the first upper sacrificial layer 310, the lateral support layer 104, the sacrificial layer 103 and the isolation layer 102 are etched in sequence using the patterned mask layer as a mask to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal pattern.

[0132] In step S23, please continue to refer to Fig.17 As shown, a lower electrode 106 is formed, and the lower electrode covers the sidewall and bottom of the through hole 130 to form a plurality of cylindrical structures. Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 105 close to the peripheral area 100B and the side of the upper stacked structure 300 close to the peripheral area.

[0133] In step S23, please refer to Fig.18 As shown, the sacrificial layer is removed, and the upper supporting layer 300 and the lateral supporting layer 104 are connected to the outer wall of the tubular structure of the lower electrode 106 .

[0134] Specifically, first, a first opening is formed in the first upper supporting layer 301 to expose the first upper sacrificial layer 310, and the first upper sacrificial layer 310 is etched away; a second opening is formed in the lateral supporting layer 104 to expose the sacrificial layer 103, and the sacrificial layer 103 is etched away; wherein, one of the first openings overlaps with only one of the through holes 130, or one of the first openings overlaps with multiple through holes 130 at the same time; one of the second openings overlaps with only one of the through holes 130, or one of the second openings overlaps with multiple through holes 130 at the same time.

[0135] After removing the sacrificial layer, the first upper support layer 301 and the lateral support layer 104 are connected to the outer wall of the tubular structure of the lower electrode 106, and the longitudinal support layer 105 is connected to the lateral support layer 104 and the isolation layer 102, so that a peripheral wrapping support structure is formed on the device area 100A. Further, in this embodiment, one end of the first upper support layer 301 is kept flush with the longitudinal support layer 105 in a direction perpendicular to the substrate, and the lower electrode 106 is formed on the side of the longitudinal support layer 105 close to the peripheral area 100B and extends and connects to the first upper support layer 301 in a direction perpendicular to the substrate 100, thereby ensuring the flatness of the capacitor array boundary, avoiding the formation of cracks due to the unevenness of the capacitor array boundary during the subsequent deposition of the filling material, thereby avoiding the short circuit problem between the plug and the capacitor array boundary caused by the crack, and improving the reliability of the capacitor device while increasing the stability of the array area.

[0136] Then, please refer to Fig.19 As shown, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. Please refer to the first embodiment for the specific formation method.

[0137] In addition, a plurality of upper support layers may be formed on the transverse support layer 104 . As shown in FIG. 20 , a first upper support layer 301 and a second upper support layer 302 are formed on the transverse support layer 104 . The specific formation method will not be described in detail.

[0138] Embodiment 4

[0139] This embodiment provides a method for forming a capacitor array structure. Compared with the first embodiment, in this embodiment, at least one lower support layer is formed between the lateral support layer 104 of the main support layer 120 and the substrate 100, and at least one upper support layer is formed on the lateral support layer 105. The specific formation method includes:

[0140] S31: forming a lower stacked structure 200 in which a sacrificial layer and a lower supporting layer are alternately arranged on the substrate 100;

[0141] S32: forming a main support layer 120, wherein the transverse support layer 104 covers the upper surface of the lower laminated structure 200, and the longitudinal support layer 105 covers the side surface of the lower laminated structure 200 close to the peripheral area;

[0142] S33: forming an upper stacked structure 300 in which a sacrificial layer and an upper supporting layer are alternately arranged on the lateral supporting layer 104;

[0143] S34: forming a plurality of through holes 130, wherein the through holes sequentially penetrate the upper stacked structure 300, the lateral support layer 105 and the lower stacked structure 300 to expose the substrate 100;

[0144] S35: forming a lower electrode 106, wherein the lower electrode 106 covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal support layer close to the peripheral area and the side surface of the upper stacked structure close to the peripheral area;

[0145] S36: removing the sacrificial layer, and connecting the upper supporting layer, the lateral supporting layer 104 and the lower supporting layer 200 to the outer wall of the lower electrode cylindrical structure.

[0146] Figure 21 to Figure 23 This is a cross-sectional schematic diagram corresponding to the corresponding steps in the method for forming a capacitor array structure provided in the fourth embodiment of the present invention. Fig.21 In combination with the second embodiment of the present invention, step S31 and step S32 are performed. In step S31, a first lower sacrificial layer 210, a first lower supporting layer 201 and a second lower sacrificial layer 220 are sequentially formed on the substrate 100 to form a lower stacked structure 200 in which sacrificial layers and lower supporting layers are alternately arranged. Preferably, an isolation layer 102 is also formed between the first lower sacrificial layer 210 and the substrate 100 to isolate the storage transistor in the substrate 100 from the capacitor device above.

[0147] In step S32 , a main support layer 120 is formed, the transverse support layer 104 covers the upper surface of the lower laminated structure 210 , and the longitudinal support layer 105 covers the side surface of the lower laminated structure 210 close to the peripheral area 100B.

[0148] Please refer to Fig.21 and Fig. 22 In combination with the third embodiment of the present invention, step S33 to step S36 are performed. First, in step S33, a first upper sacrificial layer 310 and a first upper supporting layer 301 are sequentially formed on the lateral supporting layer 104 to form an upper stacked structure 300.

[0149] In step S34 , a plurality of through holes 130 are formed. The through holes 130 sequentially penetrate the upper stacked structure 300 , the lateral support layer 104 , the lower stacked structure 200 , and the isolation layer 102 to expose the substrate 100 .

[0150] In step S35, a lower electrode 106 is formed, and the lower electrode covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures. Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 105 close to the peripheral area 100B and the side of the upper stacked structure 300 close to the peripheral area. Furthermore, the lower electrode 106 also covers the isolation layer 102 on the edge portion 100A' of the device area.

[0151] In step S36, the sacrificial layer is removed, and the upper support layer, the lateral support layer 104 and the lower support layer are connected to the outer wall of the tubular structure of the lower electrode 106, such as Fig. 22 shown.

[0152] Then, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108.

[0153] In addition, a plurality of lower support layers may be formed between the transverse support layer 104 of the main support layer 120 and the substrate 100, and a plurality of upper support layers may be formed on the transverse support layer 104. Fig.23 As shown, a first lower support layer 201 and a second lower support layer 202 are formed between the lateral support layer 104 of the main support layer 120 and the substrate 100, and a first upper support layer 301 and a second upper support layer 302 are formed on the lateral support layer 104. The specific formation method is not repeated here.

[0154] Embodiment 5

[0155] The present invention also provides a capacitor array structure, please refer to Fig. 9As shown, the capacitor array structure includes: a plurality of capacitors arranged in an array in a substrate device region, each of the capacitors includes: a lower electrode 106, a capacitor dielectric layer 107 and an upper electrode 108; wherein the lower electrode 106 is arranged on the substrate 100, and the lower electrode 106 has a plurality of cylindrical structures; the capacitor dielectric layer 107 is arranged on the inner and outer surfaces of the lower electrode 106; the upper electrode 108 is arranged on the outer surface of the capacitor dielectric layer 107;

[0156] The main support layer 120 includes a transverse support layer 104 and a longitudinal support layer 105; wherein the transverse support layer 104 is arranged on the device area 100A, and the transverse support layer 104 is connected to the outer wall of the tubular structure of the lower electrode 106; the longitudinal support layer 105 is arranged at one end of the transverse support layer 104, and the longitudinal support layer 105 connects the transverse support layer 104 and the substrate 100; the lower electrode 106 is arranged on a side of the longitudinal support layer 105 different from the transverse support layer 104.

[0157] Preferably, Fig.14 As shown, at least one lower support layer (first lower support layer 201) is disposed between the transverse support layer 104 and the substrate 100, the lower support layer is connected to the outer wall of the tubular structure of the lower electrode 106, and one end of the lower support layer is connected to the longitudinal support layer 104. The longitudinal support layer 105 is provided with a lower electrode on one side different from the transverse support layer 104.

[0158] Preferably, Fig.19 As shown, at least one upper support layer (first upper support layer 301 ) is disposed on the transverse support layer 104 , the upper support layer is connected to the outer wall of the tubular structure of the lower electrode 106 , and one end of the upper support layer is kept flush with the longitudinal support layer 105 in a direction perpendicular to the substrate 100 .

[0159] Preferably, a lower electrode 106 is provided on the side of the longitudinal support layer 105 close to the peripheral area 100B, which extends to connect the upper support layer in a direction perpendicular to the substrate 100. Since the upper support layer and the longitudinal support layer 105 are kept flush in a direction perpendicular to the substrate 100, the flatness of the capacitor array boundary is ensured.

[0160] Preferably, at least one lower support layer is provided between the transverse support layer 104 and the substrate 100, and at least one upper support layer is provided on the transverse support layer. The lower support layer and the upper support layer are connected to the outer wall of the tubular structure of the lower electrode 106, one end of the lower support layer is connected to the longitudinal support layer 105, and one end of the upper support layer is kept flush with the longitudinal support layer 105 in a direction perpendicular to the substrate. Preferably, the lower electrode 106 is provided on a side of the longitudinal support layer 105 different from the transverse support layer 104, and the lower electrode 106 is extended to connect to the upper support layer.

[0161] Preferably, an isolation layer 102 is also provided on the substrate 100, and the isolation layer 102 is provided at the periphery of the bottom of the tubular structure of the lower electrode 106 and covers the edge portion 100A' of the device region. The capacitor array structure also includes a plurality of node contacts 101, which are located in the substrate 100, and the bottom of the tubular structure of the lower electrode 106 is connected to the node contacts.

[0162] Preferably, the materials of the main support layer 120, the upper support layer, the lower support layer and the isolation layer 102 include but are not limited to silicon nitride, and the main support layer 120 can be formed by a deposition process, such as a chemical vapor deposition process. The main support layer 120 can be formed in a one-step deposition process, or in two-step deposition processes to form the lateral support layer 104 and the longitudinal support layer 105 respectively.

[0163] Preferably, the capacitor array structure further includes an electrode filling layer 109 and an electrode connection layer 110. The upper electrode filling layer 109 covers the upper electrodes 108 and fills the gaps between the upper electrodes 108, and the material of the upper electrode filling layer 109 includes boron-doped polysilicon; the upper electrode connection layer 110 covers the outer surface of the upper electrode filling layer 109, and the material of the upper electrode connection layer 110 includes but is not limited to tungsten.

[0164] In the embodiment of the present invention, a main support layer is provided to form a peripheral wrapping support structure on the device area. Compared with the single lateral support layer in the prior art, the capacitor array boundary in the present embodiment is a flat structure, which avoids the formation of cracks due to the unevenness of the capacitor array boundary during the subsequent deposition of filling materials, thereby avoiding the short circuit problem between the plug and the capacitor array boundary caused by the cracks, thereby increasing the stability of the array area and improving the reliability of the capacitor device.

[0165] Furthermore, the present invention also provides a semiconductor device, comprising the capacitor array mechanism as described above, and the semiconductor device is applied to a dynamic random access memory.

[0166] In summary, the present invention provides a capacitor array structure and a method for forming the same, as well as a semiconductor device. By forming a peripherally wrapped main support layer on the device area, a flat capacitor array boundary is obtained, thereby avoiding the formation of cracks due to the unevenness of the capacitor array boundary during the subsequent deposition of filling materials, thereby avoiding the short circuit problem between the plug and the capacitor array boundary caused by the cracks, thereby increasing the stability of the array area and improving the reliability of the capacitor device.

[0167] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0168] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for forming a capacitor array structure, characterized in that: include: Providing a substrate, wherein the substrate has a device region for forming a capacitor and a peripheral region located outside the device region; A sacrificial layer and a main support layer are formed in the device area, the main support layer includes a transverse support layer and a longitudinal support layer, the transverse support layer covers the upper surface of the sacrificial layer, the longitudinal support layer covers the side of the sacrificial layer close to the peripheral area, and the longitudinal support layer connects the transverse support layer and the substrate; wherein at least one lower support layer is formed between the transverse support layer and the substrate, the lower support layer is parallel to the transverse support layer, and one end of the lower support layer is connected to the longitudinal support layer; forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate the lateral support layer and the sacrificial layer to expose the substrate; forming a lower electrode, wherein the lower electrode covers the sidewall and the bottom of the through hole to form a plurality of cylindrical structures; The sacrificial layer is removed, and a capacitor dielectric layer and an upper electrode are sequentially formed on the inner and outer surfaces of the lower electrode to form a capacitor.

2. The method for forming a capacitor array structure according to claim 1, wherein: The method for forming the lower support layer comprises: Forming a lower stacked structure with a sacrificial layer and a lower supporting layer alternately arranged on the substrate; forming a main support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area; forming a plurality of through holes, wherein the through holes sequentially penetrate the lateral support layer and the lower laminate structure to expose the substrate; forming a lower electrode, the lower electrode covering the sidewall and bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side surface of the longitudinal support layer close to the peripheral area; The sacrificial layer is removed, and the lateral support layer and the lower support layer are connected to the outer wall of the lower electrode cylindrical structure.

3. The method for forming a capacitor array structure according to claim 1 or 2, wherein: An isolation layer is also formed between the sacrificial layer and the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure.

4. The method for forming a capacitor array structure according to claim 1 or 2, wherein: A plurality of node contacts are formed in the substrate, the through holes expose the node contacts, and the lower electrodes are connected to the node contacts at the bottoms of the through holes.

5. The method for forming a capacitor array structure according to claim 1 or 2, wherein: The main support layer and the lower support layer are both made of silicon nitride, and the sacrificial layer is made of silicon oxide.

6. A method for forming a capacitor array structure, characterized in that: include: Providing a substrate, wherein the substrate has a device region for forming a capacitor and a peripheral region located outside the device region; A sacrificial layer and a main support layer are formed in the device area, the main support layer includes a transverse support layer and a longitudinal support layer, the transverse support layer covers the upper surface of the sacrificial layer, the longitudinal support layer covers the side of the sacrificial layer close to the peripheral area, and the longitudinal support layer connects the transverse support layer and the substrate; wherein at least one upper support layer is formed on the transverse support layer, the upper support layer is parallel to the transverse support layer, and one end of the upper support layer is kept flush with the longitudinal support layer in a direction perpendicular to the substrate; forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate the lateral support layer and the sacrificial layer to expose the substrate; forming a lower electrode, wherein the lower electrode covers the sidewall and the bottom of the through hole to form a plurality of cylindrical structures; The sacrificial layer is removed, and a capacitor dielectric layer and an upper electrode are sequentially formed on the inner and outer surfaces of the lower electrode to form a capacitor.

7. The method for forming a capacitor array structure according to claim 6, wherein: The method for forming the upper support layer comprises: forming an upper stacked structure in which a sacrificial layer and an upper supporting layer are alternately arranged on the lateral supporting layer; forming a plurality of through holes, wherein the through holes sequentially penetrate the upper stacked structure, the lateral support layer and the sacrificial layer to expose the substrate; forming a lower electrode, the lower electrode covering the sidewall and bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side of the longitudinal support layer close to the peripheral area and the side of the upper stacked structure close to the peripheral area; The sacrificial layer is removed, and the upper supporting layer and the lateral supporting layer are connected to the outer wall of the lower electrode cylindrical structure.

8. The method for forming a capacitor array structure according to claim 6 or 7, wherein: An isolation layer is also formed between the sacrificial layer and the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure.

9. The method for forming a capacitor array structure according to claim 6 or 7, wherein: A plurality of node contacts are formed in the substrate, the through holes expose the node contacts, and the lower electrodes are connected to the node contacts at the bottoms of the through holes.

10. The method for forming a capacitor array structure according to claim 6 or 7, characterized in that: The main support layer and the upper support layer are both made of silicon nitride, and the sacrificial layer is made of silicon oxide.

11. A method for forming a capacitor array structure, characterized in that: include: Providing a substrate, wherein the substrate has a device region for forming a capacitor and a peripheral region located outside the device region; A sacrificial layer and a main support layer are formed in the device area, the main support layer includes a transverse support layer and a longitudinal support layer, the transverse support layer covers the upper surface of the sacrificial layer, the longitudinal support layer covers the side of the sacrificial layer close to the peripheral area, and the longitudinal support layer connects the transverse support layer and the substrate; wherein at least one lower support layer is formed between the transverse support layer and the substrate, and at least one upper support layer is formed on the transverse support layer; the upper support layer and the lower support layer are both parallel to the transverse support layer, one end of the lower support layer is connected to the longitudinal support layer, and one end of the upper support layer is kept flush with the longitudinal support layer in a direction perpendicular to the substrate; forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate the lateral support layer and the sacrificial layer to expose the substrate; forming a lower electrode, wherein the lower electrode covers the sidewall and the bottom of the through hole to form a plurality of cylindrical structures; The sacrificial layer is removed, and a capacitor dielectric layer and an upper electrode are sequentially formed on the inner and outer surfaces of the lower electrode to form a capacitor.

12. The method for forming a capacitor array structure according to claim 11, wherein: The method for forming the upper supporting layer and the lower supporting layer includes: Forming a lower stacked structure with a sacrificial layer and a lower supporting layer alternately arranged on the substrate; forming a main support layer, wherein the transverse support layer covers the upper surface of the lower laminated structure, and the longitudinal support layer covers the side surface of the lower laminated structure close to the peripheral area; forming an upper stacked structure in which a sacrificial layer and an upper supporting layer are alternately arranged on the lateral supporting layer; forming a plurality of through holes, wherein the through holes sequentially penetrate the upper laminate structure, the lateral support layer, and the lower laminate structure to expose the substrate; forming a lower electrode, the lower electrode covering the sidewall and bottom of the through hole to form a plurality of cylindrical structures; the lower electrode also covers the side of the longitudinal support layer close to the peripheral area and the side of the upper stacked structure close to the peripheral area; The sacrificial layer is removed, and the upper supporting layer and the lateral supporting layer are connected to the outer wall of the lower electrode cylindrical structure.

13. The method for forming a capacitor array structure according to claim 11 or 12, wherein: An isolation layer is also formed between the sacrificial layer and the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure.

14. The method for forming a capacitor array structure according to claim 11 or 12, wherein: A plurality of node contacts are formed in the substrate, the through holes expose the node contacts, and the lower electrodes are connected to the node contacts at the bottoms of the through holes.

15. The method for forming a capacitor array structure according to claim 11 or 12, wherein: The main support layer, the upper support layer and the lower support layer are all made of silicon nitride, and the sacrificial layer is made of silicon oxide.

16. A capacitor array structure, characterized in that: include: A plurality of capacitors arranged in an array in a substrate device region, each of the capacitors comprising: a lower electrode, a capacitor dielectric layer and an upper electrode; wherein the lower electrode is arranged on the substrate and has a plurality of cylindrical structures; the capacitor dielectric layer is arranged on the inner and outer surfaces of the lower electrode; and the upper electrode is arranged on the outer surface of the capacitor dielectric layer; A main support layer, the main support layer comprising a transverse support layer and a longitudinal support layer; wherein the transverse support layer is arranged on the device area, and the transverse support layer is connected to the outer wall of the lower electrode tubular structure; the longitudinal support layer is arranged at one end of the transverse support layer, and the longitudinal support layer is connected to the transverse support layer and the substrate; a lower electrode is arranged on a side of the longitudinal support layer different from the transverse support layer; and, At least one lower supporting layer is arranged between the transverse supporting layer and the base, the lower supporting layer is connected to the outer wall of the lower electrode cylindrical structure, and one end of the lower supporting layer is connected to the longitudinal supporting layer.

17. The capacitor array structure according to claim 16, wherein: An isolation layer is also arranged on the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure; the capacitor array structure also includes a plurality of node contacts located in the substrate, and the bottom of the lower electrode cylindrical structure is connected to the node contacts.

18. The capacitor array structure according to claim 17, wherein: The main support layer, the lower support layer and the isolation layer are all made of silicon nitride.

19. A capacitor array structure, characterized in that: include: A plurality of capacitors arranged in an array in a substrate device region, each of the capacitors comprising: a lower electrode, a capacitor dielectric layer and an upper electrode; wherein the lower electrode is arranged on the substrate and has a plurality of cylindrical structures; the capacitor dielectric layer is arranged on the inner and outer surfaces of the lower electrode; and the upper electrode is arranged on the outer surface of the capacitor dielectric layer; A main support layer, the main support layer comprising a transverse support layer and a longitudinal support layer; wherein the transverse support layer is arranged on the device area, and the transverse support layer is connected to the outer wall of the lower electrode tubular structure; the longitudinal support layer is arranged at one end of the transverse support layer, and the longitudinal support layer is connected to the transverse support layer and the substrate; a lower electrode is arranged on a side of the longitudinal support layer different from the transverse support layer; and, At least one upper supporting layer is arranged on the transverse supporting layer, the upper supporting layer is connected to the outer wall of the lower electrode cylindrical structure, and one end of the upper supporting layer is kept flush with the longitudinal supporting layer in a direction perpendicular to the base.

20. The capacitor array structure according to claim 19, wherein: The lower electrode disposed on a side of the longitudinal support layer different from the transverse support layer extends and connects to the upper support layer.

21. The capacitor array structure according to claim 19 or 20, characterized in that: An isolation layer is also arranged on the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure; the capacitor array structure also includes a plurality of node contacts located in the substrate, and the bottom of the lower electrode cylindrical structure is connected to the node contacts.

22. The capacitor array structure according to claim 21, wherein: The main support layer, the upper support layer and the isolation layer are all made of silicon nitride.

23. A capacitor array structure, characterized in that: include: A plurality of capacitors arranged in an array in a substrate device region, each of the capacitors comprising: a lower electrode, a capacitor dielectric layer and an upper electrode; wherein the lower electrode is arranged on the substrate and has a plurality of cylindrical structures; the capacitor dielectric layer is arranged on the inner and outer surfaces of the lower electrode; and the upper electrode is arranged on the outer surface of the capacitor dielectric layer; A main support layer, the main support layer comprising a transverse support layer and a longitudinal support layer; wherein the transverse support layer is arranged on the device area, and the transverse support layer is connected to the outer wall of the lower electrode tubular structure; the longitudinal support layer is arranged at one end of the transverse support layer, and the longitudinal support layer is connected to the transverse support layer and the substrate; a lower electrode is arranged on a side of the longitudinal support layer different from the transverse support layer; and, At least one lower supporting layer is arranged between the transverse supporting layer and the substrate, and at least one upper supporting layer is arranged on the transverse supporting layer.

24. The capacitor array structure according to claim 23, characterized in that: The lower support layer and the upper support layer are connected to the outer wall of the lower electrode cylindrical structure, one end of the lower support layer is connected to the longitudinal support layer, and one end of the upper support layer is kept flush with the longitudinal support layer in a direction perpendicular to the base.

25. The capacitor array structure according to claim 24, characterized in that: The lower electrode disposed on a side of the longitudinal support layer different from the transverse support layer extends and connects to the upper support layer.

26. The capacitor array structure according to any one of claims 23 to 25, characterized in that: An isolation layer is also arranged on the substrate, and the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure; the capacitor array structure also includes a plurality of node contacts located in the substrate, and the bottom of the lower electrode cylindrical structure is connected to the node contacts.

27. The capacitor array structure according to claim 26, wherein: The main support layer, the upper support layer, the lower support layer and the isolation layer are all made of silicon nitride.

28. A semiconductor device, characterized in that: Comprising the capacitor array structure as claimed in any one of claims 16 to 27.

29. The semiconductor device according to claim 28, characterized in that The semiconductor device is applied to a dynamic random access memory.

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