An airborne avionics hard disk destruction system

Abstract

The present invention discloses an airborne avionics hard disk destruction system, including a destruction switch circuit, a main control circuit and a destruction circuit, the destruction switch circuit includes a destruction button and a hardware debounce circuit, the destruction button is connected to the input end of the main control circuit through the hardware debounce circuit, the destruction circuit includes a first drive circuit, a first isolation circuit, a second drive circuit and a second isolation circuit, the output end of the main control circuit is connected to the first isolation circuit through the first drive circuit, the first isolation circuit is connected to the second isolation circuit through the second drive circuit, the first isolation circuit is used to realize the power isolation in the main control circuit and the destruction circuit, and the second isolation circuit realizes the double isolation of the 28V main power supply and the destruction link. The present invention can realize the rapid and irreversible destruction of the hard disk by using high voltage and high current.

Description

Technical Field

[0001] The present invention relates to the field of electronic devices, in particular to an airborne avionics hard disk destruction system, which destroys the airborne avionics hard disk by a simple and fast physical destruction method. Background Art

[0002] With the rapid development of military intelligence, various reconnaissance and detection systems deployed on land, sea, air and space according to the needs of military operations are collecting, transmitting and processing more and more data in real time through uninterrupted battlefield situation monitoring. How to ensure the security of information and data systems is crucial. In an emergency, it becomes particularly critical to achieve rapid destruction of data.

[0003] In airborne equipment, most hard disks have dual destruction functions. The main power supply is 28V. Using this DC power supply and auxiliary control circuit, the data in the hard disk can be destroyed quickly and irreversibly, and the destruction time is no more than 3s.

[0004] At present, the existing solutions for destroying hard disks of airborne equipment have low destruction voltage and current, which may cause the destruction to take a long time. In addition, the destruction circuit is generally not isolated from the motherboard working circuit, which causes damage to the motherboard power supply when the hard disk is destroyed. In the existing technology, it is difficult to meet the design requirements and ultimately affects the performance of the entire system. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an airborne avionics hard disk destruction circuit, which utilizes high voltage and high current to achieve rapid and irreversible destruction of the hard disk.

[0006] In order to solve the technical problem, the technical solution adopted by the present invention is: an airborne avionics hard disk destruction system, including a destruction switch circuit, a main control circuit and a destruction circuit, the destruction switch circuit includes a destruction button and a hardware de-bouncing circuit, the destruction button is connected to the input end of the main control circuit through the hardware de-bouncing circuit, the destruction circuit includes a first drive circuit, a first isolation circuit, a second drive circuit and a second isolation circuit, the output end of the main control circuit is connected to the first isolation circuit through the first drive circuit, the first isolation circuit is connected to the second isolation circuit through the second drive circuit, the first isolation circuit is used to realize power isolation between the main control circuit and the destruction circuit, one end of the second isolation circuit is connected to the 28V main power supply, and the other end is connected to the hard disk to be destroyed, and the second isolation circuit realizes double isolation of the 28V main power supply and the destruction link.

[0007] Furthermore, the first driving circuit is a transistor Q2, the output end of the main control circuit is connected to the base of the transistor Q2 through a resistor R12, the emitter of the transistor Q2 is grounded, and the collector is connected to the input end of the first isolation circuit.

[0008] Furthermore, the first isolation circuit is an optocoupler U3, pin 1 of the optocoupler U3 is connected to 3.3V via a resistor R7, pin 2 is connected to the collector of the transistor Q2, pin 3 is grounded, and pin 4 is connected to the input end of the second drive circuit.

[0009] Furthermore, the second driving circuit includes a MOS tube Q1 and a diode controller LTC4359, the 28V main power supply is connected to the gate of the MOS tube Q1 through a resistor R4, the source of the MOS tube Q1 is grounded, the drain of the MOS tube Q1 is connected to the SHUT terminal of the diode controller LTC4359 in one way, and is connected to the 28V main power supply through a resistor R3 in the other way, the 28V main power supply is connected to the IN terminal of the diode controller LTC4359, and the OUT terminal, Source terminal and Gate terminal of the diode controller LTC4359 are respectively connected to the second isolation circuit.

[0010] Furthermore, the second isolation circuit is two dual MOS devices MOS1 and MOS2, the drain of MOS1 is connected to the 28V main power supply, the source of MOS1 and the source of MOS2 are connected together, and the Source end of LTC4359 is connected to the source of MOS1 and the source of MOS2 respectively, the Gate end of LTC4359 is connected to the gate of MOS2 in one way, and is connected to the gate of MOS1 through resistor R1 in the other way, the OUT end of LTC4359 is connected to the drain of MOS2, and the drain of MOS2 is connected to the hard disk to be destroyed as a destruction output end.

[0011] Furthermore, a filter capacitor C11 is connected between the base of the transistor Q2 and the ground.

[0012] Furthermore, the resistor R4 is grounded through the resistor R13, the drain of the MOS tube Q1 is grounded through the resistor R9, the VSS terminal of the diode controller LTC4359 is grounded through the resistor R10, and the Gate terminal of the diode controller LTC4359 is grounded through the series-connected resistor R2 and capacitor C5.

[0013] Furthermore, the drain of MOS2 is grounded through capacitors C3 and C4 connected in parallel.

[0014] Furthermore, the hardware debouncing circuit is a capacitor C2.

[0015] Beneficial effects of the present invention: The present invention utilizes a single-chip microcomputer to implement simple destruction command detection, and controls the corresponding pin to output a high level, thereby driving the subsequent circuit to implement 28V output and shutdown, and a variety of protection circuits are applied to the destruction circuit to ensure the normal use of the hard disk. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0017] Figure 1 Circuit diagram of main control circuit and destruction switch circuit;

[0018] Figure 2 A circuit schematic for the destruction circuit;

[0019] Figure 3 This is the circuit schematic diagram of the external power supply interface. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Example 1

[0022] This embodiment 1 discloses an airborne avionics hard disk destruction system, including a destruction switch circuit, a main control circuit and a destruction circuit. The destruction switch circuit includes a destruction button and a hardware debouncing circuit. The destruction button is connected to the input end of the main control circuit through the hardware debouncing circuit. The destruction circuit includes a first drive circuit, a first isolation circuit, a second drive circuit and a second isolation circuit. The output end of the main control circuit is connected to the first isolation circuit through the first drive circuit, and the first isolation circuit is connected to the second isolation circuit through the second drive circuit. The first isolation circuit is used to achieve power isolation between the main control circuit and the destruction circuit. One end of the second isolation circuit is connected to a 28V main power supply, and the other end is connected to a hard disk to be destroyed. The second isolation circuit achieves double isolation of the 28V main power supply and the destruction link.

[0023] like Figure 1 As shown, the main control circuit uses chip C8051F340, pin P1.3 is connected to the destruction switch circuit, and is connected to the 3.3V power supply through a pull-up resistor. The main control circuit can be connected to multiple destruction circuits. In this embodiment, four destruction circuits are connected through pins P1.5, P1.6, P1.7, and P2.0 of the main control chip. The main control chip is used to realize time sequence control, which can not only realize the function of rapid destruction, but also greatly control the total power consumption of the circuit during destruction.

[0024] like Figure 1 As shown, in this embodiment, the hardware debouncing circuit of the destruction switch circuit is a coupling capacitor C2 of 0.1uf, which realizes simple hardware debouncing.

[0025] This embodiment is described by taking the destruction circuit connected to the pin P1.5 of the main control chip as an example. Figure 2 As shown, the first driving circuit is a transistor Q2, the first isolating circuit is an optical coupler U3, the second driving circuit includes a MOS tube Q1 and a diode controller LTC4359, and the second isolating circuit is two dual MOS devices MOS1 and MOS2.

[0026] The output terminal P1.5 of the main control circuit is connected to the base of the transistor Q2 through the resistor R12, the emitter of the transistor Q2 is grounded, the pin 1 of the optocoupler U3 is connected to 3.3V through the resistor R7, the pin 2 is connected to the collector of the transistor Q2, the pin 3 is grounded, the pin 4 is connected to the gate of the MOS tube Q1, the 28V main power supply is connected to the gate of the MOS tube Q1 through the resistor R4, the source of the MOS tube Q1 is grounded, the drain of the MOS tube Q1 is connected to the SHUT terminal of the diode controller LTC4359 in one way, and is connected to the 28V main power supply through the resistor R3 in the other way, the 28V main power supply is connected to the IN terminal of the diode controller LTC4359, and the OUT terminal, Source terminal and Gate terminal of the diode controller LTC4359 are respectively connected to the second isolation circuit.

[0027] The drain of MOS1 is connected to the 28V main power supply, the source of MOS1 and the source of MOS2 are connected together, and the Source end of LTC4359 is connected to the source of MOS1 and the source of MOS2 respectively, the Gate end of LTC4359 is connected to the gate of MOS2 in one way, and the other way is connected to the gate of MOS1 through resistor R1, the OUT end of LTC4359 is connected to the drain of MOS2, and the drain of MOS2 is used as the destruction output end ( Figure 2 Connect 28V_Destroy1 in the figure to the hard disk to be destroyed.

[0028] Considering the moment of power-on, the output of the MCU IO port cannot immediately reach the initialized value in the program. In addition, the impact of the power supply and the interference of other signals on the PCB board may cause the transistor Q2 to be turned on momentarily, and the LED light in the coupling device will flash. Add filter capacitor C11 to absorb the peak pulse. Capacitor C11 is connected between the base of the transistor Q2 and the ground.

[0029] In addition, the resistor R4 is grounded through the resistor R13, the drain of the MOS tube Q1 is grounded through the resistor R9, the VSS terminal of the diode controller LTC4359 is grounded through the resistor R10, and the Gate terminal of the diode controller LTC4359 is grounded through the series resistor R2 and capacitor C5. The drain of MOS2 is grounded through the parallel capacitors C3 and C4.

[0030] like Figure 3The external power interface diagram of this embodiment is shown. The +5V power supply is connected through the terminal J1, and the +28 main power supply is connected through the terminal J2. The LDO circuit can be used to convert +5V into 3.3V to provide a pull-up power supply for the resistors in the circuit. The +28V main power supply is the destruction voltage of the hard disk.

[0031] The working process of the hard disk destruction circuit described in this embodiment is as follows:

[0032] When the microcontroller control pin P1.3 is initialized to a low level or a high impedance state, transistor Q2 is not conducting, the output end of the optical coupling device is in a cut-off state, Q1 is conducting, and the SHUT# of the LTC-4359 device is short-circuited to the ground. Using the characteristics of the LTC-4359 device (SHUT# level>2V, turn on the device; SHUT# level<0.6V, turn off the device), control MOS1 and MOS2 devices to be in a closed state, 28V destruction voltage has no output, and the hard disk is in a safe state.

[0033] When the physical destruction button is pressed, the microcontroller P1.3 pin goes through a short delay (software debounce) logic, and after determining that the level is indeed a high-low-high destruction level change, the P1.5 pin is used to output a high level, driving the transistor Q2 to saturate and conduct. The Q2 collector current is calculated to be about 5.5 mA, lighting up the photodiode in the U3 optocoupler, short-circuiting the output stage of the optocoupler to the ground, causing the gate-source voltage of the MOS tube Q1 to be low, Q1 is cut off, causing the 28V power supply to be loaded on the SHUT# pin of the LTC-4359 chip through the 2.2MΩ pull-up resistor, driving the N-channel MOS1 and MOS2 to conduct, and the 28V power supply is directly loaded on the specific pin of the hard disk, using high voltage and high current to achieve rapid and irreversible destruction of the hard disk.

[0034] This embodiment uses a single-chip microcomputer (C8051F340) to implement simple destruction command detection, and controls the corresponding pin to output a high level, thereby driving the subsequent circuit to achieve 28V output and shutdown. Multiple protection circuits are applied to the destruction circuit to ensure the normal use of the hard disk.

[0035] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An airborne avionics hard disk destruction system, characterized by: It includes a destruction switch circuit, a main control circuit and a destruction circuit. The destruction switch circuit includes a destruction button and a hardware de-jitter circuit. The destruction button is connected to the input end of the main control circuit through the hardware de-jitter circuit. The destruction circuit includes a first drive circuit, a first isolation circuit, a second drive circuit and a second isolation circuit. The output end of the main control circuit is connected to the first isolation circuit through the first drive circuit. The first isolation circuit is connected to the second isolation circuit through the second drive circuit. The first isolation circuit is used to realize power supply isolation between the main control circuit and the destruction circuit. One end of the second isolation circuit is connected to the 28V main power supply, and the other end is connected to the power supply to be destroyed. The hard disk, the second isolation circuit realizes the double isolation of the 28V main power supply and the destruction link; the first driving circuit is a transistor Q2, the output end of the main control circuit is connected to the base of the transistor Q2 through a resistor R12, the emitter of the transistor Q2 is grounded, and the collector is connected to the input end of the first isolation circuit; the first isolation circuit is an optical coupler U3, the pin 1 of the optical coupler U3 is connected to the 3.3V power supply through a resistor R7, the pin 2 is connected to the collector of the transistor Q2, the pin 3 is grounded, and the pin 4 is connected to the input end of the second driving circuit; the second driving circuit includes a MOS tube Q1 and a diode The diode controller LTC4359, the 28V main power supply is connected to the gate of the MOS tube Q1 through the resistor R4, the source of the MOS tube Q1 is grounded, the drain of the MOS tube Q1 is connected to the SHUT terminal of the diode controller LTC4359 in one way, and is connected to the 28V main power supply through the resistor R3 in the other way, the 28V main power supply is connected to the IN terminal of the diode controller LTC4359, and the OUT terminal, Source terminal and Gate terminal of the diode controller LTC4359 are respectively connected to the second isolation circuit; the second isolation circuit is composed of two dual MOS devices MOS1, M OS2, the drain of MOS1 is connected to the 28V main power supply, the source of MOS1 and the source of MOS2 are connected together, and the Source end of LTC4359 is connected to the source of MOS1 and the source of MOS2 respectively, the Gate end of LTC4359 is connected to the gate of MOS2 in one way, and the other way is connected to the gate of MOS1 through resistor R1, the OUT end of LTC4359 is connected to the drain of MOS2, and the drain of MOS2 is connected to the hard disk to be destroyed as the destruction output end; a filter capacitor C11 is connected between the base of transistor Q2 and the ground.

2. The airborne avionics hard disk destruction system according to claim 1, characterized in that: The resistor R4 is grounded through the resistor R13, the drain of the MOS tube Q1 is grounded through the resistor R9, the VSS terminal of the diode controller LTC4359 is grounded through the resistor R10, and the Gate terminal of the diode controller LTC4359 is grounded through the series-connected resistor R2 and capacitor C5.

3. The airborne avionics hard disk destruction system according to claim 1, characterized in that: The drain of MOS2 is grounded through capacitors C3 and C4 connected in parallel.

4. The airborne avionics hard disk destruction system according to claim 1, characterized in that: The hardware debouncing circuit is capacitor C2.

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