Control device for switching power supply device

Abstract

The present invention provides a control device for a switching power supply device capable of performing burst control that takes into account both high efficiency and noise suppression under light load. The switching power supply device is made more efficient by performing burst control under light load. During the switching period of the burst control, a control circuit (25) generates a first pulse of a low-side output signal lo_pre, a second pulse of a high-side output signal hi_pre, and a third pulse of a low-side output signal lo_pre. The three-pulse control circuit (22) outputs a signal that turns off the first to third pulses. When the number of bottoms of a ringing voltage generated during the switching stop period after the third pulse is turned off reaches a predetermined number, the VS bottom control circuit (23) outputs a signal that turns on the first pulse during the next switching period. Since the number of resonant cycles is fixed at a predetermined number without mixing, noise is suppressed.

Description

Technical Field

[0001] This invention relates to a control device for a switching power supply device that includes a current-resonant DC-DC switching converter and is capable of performing burst control that balances high efficiency and noise suppression under light load conditions. Background Technology

[0002] To achieve high efficiency and a slim profile, current resonant DC-DC switching converters are widely used in power adapters for televisions, LED (Light Emitting Diode) lighting fixtures, and other applications.

[0003] In such a current-resonant DC-DC converter switching power supply device, during the standby state when the electrical equipment is not in use, burst control that intermittently stops the switching operation is typically implemented (for example, see Patent Document 1). Since the burst control includes a switching stop period, the average standby power of the switching power supply device in the standby state is significantly reduced.

[0004] In burst control, sometimes the frequency range of 20 Hz to 20 kHz is entered, with one cycle consisting of the switching period during the switching action and the stopping period during the switching action. At this time, magnetostrictive noise from the core is generated due to the 20 Hz to 20 kHz current flowing in the transformer, resulting in noise. However, when the load in standby mode is less than 1 watt (W), the amplitude is small at the burst frequency of around 100 Hz, so the noise is effectively suppressed within acceptable limits.

[0005] Recent switching power supply devices have pursued high efficiency under light loads (10-30W). Under such light loads, if the same burst control is performed as before, the burst frequency reaches about 1kHz, and the noise at this frequency is unacceptable.

[0006] To address this, the burst frequency under light load is set to a frequency higher than 20 kHz to avoid noise at audible frequencies (for example, see Non-Patent Document 1). According to Non-Patent Document 1 (page 68, paragraph 9.3.2), the burst frequency under light load is set to a frequency higher than 23 kHz.

[0007] In this burst control under light load, the switching elements on both the high and low sides are turned off and the switching action is stopped during the switching stop period. At this time, a resonant circuit consisting of a resonant capacitor and a magnetizing inductor is connected at the node where the switching elements on both the high and low sides are connected. This resonant circuit uses the stray capacitance between the node and ground to close the circuit. Therefore, during the switching stop period of the burst cycle (the wait period after the dump pulse in the waveform of half-bridge HB on page 69, Figure 46), the resonant circuit resonates at the oscillation frequency.

[0008] Existing technical documents

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 2017-229209

[0011] Non-patent literature

[0012] Non-patent document 1: NXP Semiconductors, “AN11801REA19161 and TEA19162 controller ICs Application note”, [online], May 5, 2017, NXP Semiconductors, [searched August 1, 2017], online.<URL:https: / / www.nxp.com / docs / en / application-note / AN11801.pdf> Summary of the Invention

[0013] Technical issues

[0014] According to the burst control in Non-Patent Document 1, the length of the switch stop period is determined by the output power, i.e., the feedback voltage. However, in reality, the end time of the switch stop period is the moment when the oscillation waveform corresponding to the output power reaches its peak. This is because if the high-side switching element is turned on at the moment when the oscillation waveform reaches its peak, the efficiency is good.

[0015] Here, because the number of resonant periods of the oscillation during the switch-off period is an integer, the number of resonant periods corresponding to the output power sometimes becomes two adjacent discrete numbers (see page 70, paragraph 9.3.2.3 of Non-Patent Document 1). Thus, if different resonant period numbers are mixed, the burst frequency lacks continuity and becomes unstable. Since the mixed state of these resonant period numbers is a shape of multiple overlapping waveforms, even if the periods of each resonant period number do not fall within the audible range, if a Fourier transform is performed, because it contains components within the audible range, it sometimes produces a state exceeding the permissible noise range.

[0016] The present invention was made in view of this, and its object is to provide a control device for a switching power supply device capable of performing burst control that balances high efficiency and noise suppression under light load conditions.

[0017] Technical solution

[0018] In order to solve the above-mentioned problems, this invention provides a control device for a switching power supply, comprising: a load detection circuit that outputs a load signal representing the load state by shunting and averaging the resonant current of a resonant circuit; a turn-off signal generation circuit that generates a plurality of turn-off signals for turning off a first switching element on the high side and a second switching element on the low side during a sudden control switching period under light load; a turn-on signal generation circuit that generates a first pulse turn-on signal for turning on the second switching element at the beginning of the sudden control switching period by counting the number of resonant cycles of the ringing voltage generated during the sudden control switching stop period; and a control circuit that alternately controls the first switching element and the second switching element to turn on / off based on the turn-off signal generated by the turn-off signal generation circuit and the first pulse turn-on signal generated by the turn-on signal generation circuit.

[0019] Invention Effects

[0020] The advantage of the control device of the above-described switching power supply is that, since the number of resonant cycles of the ringing voltage generated during the switching stop period of the sudden control is limited to a preset number, the number of resonant cycles is not mixed, and noise caused by the mixing of resonant cycles can be suppressed. Attached Figure Description

[0021] Figure 1 This is a circuit diagram showing a switching power supply device equipped with the control device of the first embodiment.

[0022] Figure 2 This is a functional block diagram showing a configuration example of a control IC as a control device in the first embodiment.

[0023] Figure 3 This is a circuit diagram illustrating an example configuration of a three-pulse control circuit.

[0024] Figure 4 This is a circuit diagram showing an example configuration of the bottom control circuit of VS.

[0025] Figure 5 This is a graph showing the relationship between the set bottom quantity and the CA voltage.

[0026] Figure 6 This is a circuit diagram illustrating one configuration example of a load detection circuit.

[0027] Figure 7 It is a state transition diagram representing the actions of the control circuit and the bottom control circuit of VS.

[0028] Figure 8 It is a timing diagram of a sudden action.

[0029] Figure 9This is a circuit diagram showing an example configuration of the bottom control circuit of the VS in the control IC of the control device in the second embodiment.

[0030] Figure 10 This is a graph showing the relationship between the set bottom quantity and the FB voltage.

[0031] Figure 11 This is a timing diagram for a sudden increase in load.

[0032] Symbol Explanation

[0033] 10p, 10n: Input terminals

[0034] 11p, 11n: Output terminals

[0035] 12: Control IC

[0036] 13: Shunt circuit

[0037] 21: Starting circuit

[0038] 22: Three-pulse control circuit (shutdown signal generation circuit)

[0039] 23, 23a: VS Bottom Control Circuit (Conduction Signal Generation Circuit)

[0040] 24: Load detection circuit

[0041] 25: Control Circuit

[0042] 26: High-side drive circuit

[0043] 27: Low-side drive circuit

[0044] 31: Analog-to-Digital Converter

[0045] 32: Digital control circuit

[0046] 33, 34: Digital-to-Analog Converters

[0047] 35: Comparator (First Comparator)

[0048] 36: Comparator (Second Comparator)

[0049] 37: Comparator (3rd comparator)

[0050] 41: Analog-to-Digital Converter

[0051] 42: Bottom quantity setting circuit (setting circuit during the stop of the first switch)

[0052] 43: Comparator

[0053] 44: RS Trigger

[0054] 45: Bottom Quantity Counting Circuit

[0055] 46: Bottom quantity comparison circuit

[0056] 47: Delayed Circuits

[0057] 51: Inverter Circuit

[0058] 61: Analog-to-Digital Converter

[0059] 62: Bottom quantity setting circuit (setting circuit during the stop of the second switch)

[0060] 63: Comparator

[0061] 64: Selection Circuit

[0062] C1: Input capacitor

[0063] C2, C3: Capacitors

[0064] C5: Bootstrap capacitor

[0065] C7: Capacitor

[0066] C10: Output capacitor

[0067] Ca, Cb: Capacitance

[0068] Cca: Capacitor

[0069] Cr: Resonant capacitor

[0070] Cs: Capacitor

[0071] D1: Diode

[0072] D2: Bootstrap diode

[0073] D3, D4: Diodes

[0074] P1: Primary winding

[0075] P2: Auxiliary winding

[0076] PC1: Optocoupler

[0077] Qa, Qb: Switching elements

[0078] R1, R2, R3, R4, R6, R7, R8, R9, R10, Rf, Rs: Resistors

[0079] S1, S2: Secondary windings

[0080] SR1: Flow Regulator

[0081] T1: Transformer

[0082] sw1, sw2: Switches Detailed Implementation

[0083] Hereinafter, the embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, parts indicated by the same symbols represent the same constituent elements. Furthermore, in the following description, the terminal names of constituent elements and the voltage, signal, etc., of those terminals are sometimes represented by the same symbols.

[0084] Figure 1 This is a circuit diagram showing a switching power supply device equipped with the control device of the first embodiment. Figure 2 This is a functional block diagram showing a configuration example of a control IC as a control device in the first embodiment.

[0085] Figure 1 The illustrated switching power supply device has input terminals 10p and 10n for applying a DC input voltage Vi. The DC input voltage Vi is, for example, a high voltage generated by a power improvement circuit and is a constant voltage. A half-bridge circuit is connected in parallel to the input terminals 10p and 10n. This half-bridge circuit consists of an input capacitor C1 and a series circuit of a high-side switching element Qa and a low-side switching element Qb. In the illustrated example, the switching elements Qa and Qb use N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The capacitors Ca and Cb connected in parallel with the switching elements Qa and Qb respectively represent the stray capacitances between the drain and source of the switching elements Qa and Qb.

[0086] The common connection point of switching elements Qa and Qb is connected to one terminal of the primary winding P1 of transformer T1, and the other terminal of the primary winding P1 is connected to ground via a resonant capacitor Cr. Here, the resonant reactor and the resonant capacitor Cr constitute a resonant circuit. The resonant reactor utilizes the increased leakage inductance obtained by reducing the coupling coefficient between the primary winding P1 and the secondary windings S1 and S2 of transformer T1. It should be noted that the leakage inductance can be omitted, and an inductor different from the inductance constituting transformer T1 can be connected in series with the resonant capacitor Cr, with this inductor serving as the resonant reactor in the resonant circuit.

[0087] One terminal of the secondary winding S1 of transformer T1 is connected to the anode terminal of diode D3, and one terminal of the secondary winding S2 is connected to the anode terminal of diode D4. The cathode terminals of diodes D3 and D4 are connected to the positive terminal of output capacitor C10 and output terminal 11p. The negative terminal of output capacitor C10 is connected to the common connection point of secondary windings S1 and S2 and output terminal 11n. The secondary windings S1 and S2, diodes D3 and D4, and output capacitor C10 constitute a circuit that rectifies / smooths the AC voltage generated by the secondary windings S1 and S2 into DC voltage, forming the output circuit of the switching power supply device.

[0088] The positive terminal of the output capacitor C10 is connected to the anode terminal of the LED of the optocoupler PC1 via resistor R8. The cathode terminal of the LED is connected to the cathode terminal of the shunt regulator SR1. Resistor R6 is connected in parallel between the anode and cathode terminals of the LED. The anode terminal of the shunt regulator SR1 is connected to the output terminal 11n. The shunt regulator SR1 has a reference terminal, which is connected to the junction of resistors R9 and R10 connected in series between the positive and negative terminals of the output capacitor C10. A series circuit of resistor R7 and capacitor C7 is connected between the reference terminal and the cathode terminal of the shunt regulator SR1. The shunt regulator SR1 causes the LED to flow a current corresponding to the difference between the potential obtained by dividing the output voltage Vo (the voltage across the output capacitor C10) and the built-in reference voltage (equivalent to the target voltage of the output voltage). The collector terminal of the phototransistor of the optocoupler PC1 is connected to the FB terminal of the control IC12, and the emitter terminal is connected to ground. Capacitor C2 is connected in parallel between the collector and emitter terminals.

[0089] Control IC12 has a VH terminal connected to the positive terminal of input capacitor C1 and a GND terminal connected to ground. Control IC12 also has an HO terminal connected to the gate terminal of switching element Qa via resistor R1 and an LO terminal connected to the gate terminal of switching element Qb via resistor R2. Control IC12 also has VB, VS, CA, IS, and VCC terminals. A bootstrap capacitor C5 is connected between the VB and VS terminals, and the VS terminal is connected to a common connection point of switching elements Qa and Qb. One terminal of capacitor Cca is connected to the CA terminal, and the other terminal of capacitor Cca is connected to ground. The IS terminal is connected to a common connection point of a series circuit of capacitor Cs and resistor Rs connected in parallel with resonant capacitor Cr. The VCC terminal is connected to the positive terminal of capacitor C3, and the negative terminal of capacitor C3 is connected to ground. The VCC terminal is also connected to the anode terminal of bootstrap diode D2, and the cathode terminal of bootstrap diode D2 is connected to the VB terminal. The VCC terminal is also connected to the cathode terminal of diode D1. The anode terminal of diode D1 is connected to one terminal of the auxiliary winding P2 of transformer T1, and the other terminal of the auxiliary winding P2 is connected to ground. The auxiliary winding P2 is connected in parallel with the series circuit of resistors R3 and R4, and the common connection point of resistors R3 and R4 is connected to the VW terminal of control IC12.

[0090] Here, the series circuit of capacitor Cs and resistor Rs connected in parallel with resonant capacitor Cr is a shunt circuit 13 that shunts the resonant current. The current shunt by this shunt circuit 13 is converted into a voltage signal through the current sensing resistor Rs and input to the IS terminal of control IC 12. The resonant currents flowing in resonant capacitor Cr and capacitor Cs have substantially the same waveform, and their maximum amplitude is determined by the capacitance ratio of resonant capacitor Cr and capacitor Cs. If the capacitance of capacitor Cs is smaller than that of resonant capacitor Cr, only a very small current flows through the current sensing resistor Rs, and the power consumption for current sensing can be reduced to a negligible level.

[0091] like Figure 2 As shown, the control IC12 has a start-up circuit 21, a three-pulse control circuit (turn-off signal generation circuit) 22, a VS bottom control circuit (conduction signal generation circuit) 23, a load detection circuit 24, a control circuit 25, a high-side drive circuit 26, and a low-side drive circuit 27.

[0092] The input terminal of the starting circuit 21 is connected to the VH terminal, and the output terminal of the starting circuit 21 is connected to the low-side drive circuit 27 and the VCC terminal. The input terminal of the three-pulse control circuit 22 is connected to the FB terminal, the VW terminal, and the IS terminal. The three-pulse control circuit 22 has output terminals for the first pulse turn-off signal 1st_pulse_off, the second pulse turn-off signal 2nd_pulse_off, and the third pulse turn-off signal 3rd_pulse_off, which are respectively connected to the input terminal of the control circuit 25. The output terminal of the third pulse turn-off signal of the three-pulse control circuit 22 is connected to the input terminal of the VS bottom control circuit 23. The input terminal of the VS bottom control circuit 23 is also connected to the VW terminal and the CA terminal, and the output terminal of the VS bottom control circuit 23 is connected to the input terminal of the first pulse turn-on signal 1st_pulse_on of the control circuit 25. The input terminal of the load detection circuit 24 is connected to the IS terminal and the output terminal of the signal sw_ctrl of the control circuit 25, and the output terminal of the load detection circuit 24 is connected to the CA terminal.

[0093] The output terminal of the high-side output signal hi_pre of control circuit 25 is connected to the input terminal of high-side drive circuit 26, and the output terminal of the low-side output signal lo_pre of control circuit 25 is connected to the input terminal of low-side drive circuit 27. The output terminal of high-side drive circuit 26 is connected to the HO terminal, and the output terminal of low-side drive circuit 27 is connected to the LO terminal. High-side drive circuit 26 is also connected to the VB terminal for high-side power supply and the VS terminal, which serves as the reference potential for high-side power.

[0094] The starting circuit 21 converts the DC input voltage Vi into the power supply voltage of the control IC 12 during the startup of the switching power supply device, supplies it to the VCC terminal to charge the capacitor C3, and stops operating after startup. It should be noted that after startup, the power supply of the control IC 12 uses diode D1 and capacitor C3 to convert the AC voltage generated by the auxiliary winding P2 of transformer T1 into DC voltage for use.

[0095] Next, specific examples of the three-pulse control circuit 22, the bottom control circuit 23 of VS, the load detection circuit 24, and the control circuit 25 of the control IC12 will be explained.

[0096] Figure 3 This is a circuit diagram illustrating an example configuration of a three-pulse control circuit. Figure 4 This is a circuit diagram showing an example configuration of the bottom control circuit of the VS. Figure 5 This is a graph showing the relationship between the set bottom quantity and the CA voltage. Figure 6 This is a circuit diagram illustrating one possible configuration of a load detection circuit. Figure 7 This is a state transition diagram representing the actions of the control circuit and the bottom control circuit of VS. Figure 8 It is a timing diagram of a sudden action.

[0097] like Figure 3 As shown, the three-pulse control circuit 22 includes an analog-to-digital converter 31, a digital control circuit 32, digital-to-analog converters 33 and 34, and comparators 35, 36, and 37, which together form a turn-off signal generation circuit.

[0098] The input terminal of analog-to-digital converter 31 is connected to the FB terminal of control IC 12, and the output terminal of analog-to-digital converter 31 is connected to digital control circuit 32. It should be noted that the FB terminal is pulled up to a high potential side within control IC 12 via a pull-up resistor (not shown), becoming a voltage equivalent to the output voltage Vo. Digital control circuit 32 has two output terminals, which are connected to the input terminals of digital-to-analog converters 33 and 34, respectively. The output terminal of digital-to-analog converter 33 is connected to the non-inverting input terminal of comparator 35, and the output terminal of digital-to-analog converter 34 is connected to the inverting input terminal of comparator 36. The inverting input terminal of comparator 35 and the non-inverting input terminal of comparator 36 are connected to the VW terminal of control IC 12. The inverting input terminal of comparator 37 is connected to the IS terminal of control IC 12, and an IS threshold voltage ISth is applied to the non-inverting input terminal of comparator 37. The output terminals of comparators 35, 36, and 37 are connected to the input terminals of control circuit 25. It should be noted that the analog-to-digital converter 31, the digital control circuit 32, and the digital-to-analog converters 33 and 34 constitute the threshold voltage generation circuit.

[0099] In the three-pulse control circuit 22, the analog-to-digital converter 31 converts the feedback voltage input to the FB terminal into a 10-bit digital signal. The digital control circuit 32 outputs two 10-bit digital signals set according to the feedback voltage. For example, to adjust the power transmitted from the primary to the secondary side of transformer T1 according to the load specifications, the digital control circuit 32 is configured such that the larger the input feedback voltage, the smaller the difference between the two output digital signal values. The digital-to-analog converters 33 and 34 convert the digital signals output by the digital control circuit 32 into analog VW threshold voltages Vvwth1 and Vvwth2 and output them. The comparator 35 compares the VW voltage (winding voltage) applied to the VW terminal of the control IC 12 with the VW threshold voltage Vvwth1. If the VW voltage is higher than the VW threshold voltage Vvwth1 when the first pulse is turned on, the first pulse turn-off signal 1st_pulse_off is output. Comparator 36 compares the VW voltage applied to the VW terminal of control IC12 with the VW threshold voltage Vvwth2. If the VW voltage is lower than the VW threshold voltage Vvwth2 when the second pulse is turned on, it outputs the second pulse turn-off signal 2nd_pulse_off. Comparator 37 compares the IS voltage applied to the IS terminal of control IC12 with the IS threshold voltage Isth. When the IS voltage drops to the IS threshold voltage Isth when the third pulse is turned on, it outputs the third pulse turn-off signal 3rd_pulse_off.

[0100] Therefore, the three-pulse control circuit 22 controls the turn-off times of the first, second, and third pulses generated during the switching period (three-pulse control period) in the burst control under light load. Specifically, the first pulse is the signal that turns on the switching element Qb to generate excitation current, and in the following second pulse, it puts the resonant circuit into a resonant state. Its turn-off time is when the VW voltage is higher than the VW threshold voltage Vvwth1. The second pulse is the signal that turns on the switching element Qa to transfer power to the secondary side of the transformer T1. Its turn-off time is when the VW voltage is lower than the VW threshold voltage Vvwth2. The third pulse is the signal that turns on the switching element Qb to store excitation energy in the resonant capacitor Cr. Its turn-off time is when the IS voltage drops to the IS threshold voltage Isth.

[0101] like Figure 4 As shown, the VS bottom control circuit 23 includes an analog-to-digital converter 41, a bottom quantity setting circuit 42, a comparator 43, an RS flip-flop 44, a bottom quantity counting circuit 45, a bottom quantity comparison circuit 46, and a delay circuit 47, which constitute a turn-on signal generation circuit for the first pulse.

[0102] The input terminal of analog-to-digital converter 41 is connected to the CA terminal of control IC 12, and the output terminal of analog-to-digital converter 41 is connected to the input terminal of bottom quantity setting circuit 42. The output terminal of bottom quantity setting circuit 42 is connected to one input terminal of bottom quantity comparison circuit 46. The inverting input terminal of comparator 43 is connected to the VW terminal of control IC 12, and a voltage of 0 volts (V) is applied to the non-inverting input terminal of comparator 43. The output terminal of comparator 43 is connected to the input terminal of bottom quantity counting circuit 45. The set input terminal of RS flip-flop 44 is connected to the output terminal of comparator 37 of three-pulse control circuit 22, and the output terminal of RS flip-flop 44 is connected to the enable terminal of bottom quantity counting circuit 45. The output terminal of bottom quantity counting circuit 45 is connected to the other input terminal of bottom quantity comparison circuit 46. The output terminal of bottom quantity comparison circuit 46 is connected to the input terminal of delay circuit 47, the output terminal of delay circuit 47 is connected to the input terminal of control circuit 25, and is also connected to the reset input terminal of RS flip-flop 44.

[0103] In the VS bottom control circuit 23, the analog-to-digital converter 41 converts the voltage of the capacitor Cca connected to the CA terminal into a 10-bit digital signal. The bottom quantity setting circuit 42 sets the length of the switching stop period (VS bottom control period) in the burst control under light load according to the voltage (load signal) of the CA terminal. In the bottom quantity setting circuit 42, as... Figure 5 As shown, the output corresponds to the set bottom quantity Nca_bot of the CA voltage. The set bottom quantity Nca_bot has different values ​​when the CA voltage rises and falls. By adding hysteresis to the setting of the set bottom quantity Nca_bot, the frequent changes in oscillation frequency during the switching stop period are eliminated. The set bottom quantity Nca_bot is represented, for example, by a 4-bit digital signal. This set bottom quantity Nca_bot corresponds to the switching stop period in burst control.

[0104] The bottom count circuit 45 counts the number of bottom ringing voltages occurring during the switch-off period and outputs the count end bottom number Nvw_bot as a 4-bit digital signal. Here, the switch-off period is the period from the 3rd pulse off until the 1st pulse of the next burst cycle on. Therefore, when the RS flip-flop 44 receives the 3rd pulse off signal 3rd_pulse_off and is set, outputting the enable signal Enb, the bottom count circuit 45 begins counting the bottom number of ringing voltages. Conversely, when the RS flip-flop 44 receives the 1st pulse on signal 1st_pulse_on and is reset, the bottom count circuit 45 stops counting the bottom number of ringing voltages. The ringing voltage is generated in the resonant circuit of transformer T1, including the primary winding P1, but the same voltage waveform also appears in the auxiliary winding P2. Therefore, the VW voltage generated in the auxiliary winding P2 and obtained by voltage division by resistors R3 and R4 is used as the ringing voltage. Comparator 43 compares the VW voltage with 0V and outputs a high-level detection signal when the VW voltage is below 0V. During the input enable signal Enb, the bottom count circuit 45 counts the number of times the VW voltage is below 0V. Thus, comparator 43 detects the moment when the VW voltage is below 0V, but does not detect the bottom of the VW voltage. This is because the bottom of the VW voltage cannot be directly detected. The actual bottom of the VW voltage is delayed by 1 / 4 of the oscillation period T from the zero-crossing moment when the VW voltage is below 0V.

[0105] The bottom quantity comparison circuit 46 compares the set bottom quantity Nca_bot with the count-ending bottom quantity Nvw_bot. When the count-ending bottom quantity Nvw_bot reaches the set bottom quantity Nca_bot, a consistency signal is output. Since this consistency signal is the signal when the VW voltage is below 0V, it is delayed by T / 4 by the delay circuit 47, becoming the first pulse turn-on signal 1st_pulse_on of the next burst cycle. It should be noted that the ringing voltage oscillates at a fixed frequency through a resonant circuit, which consists of the resonant reactor of transformer T1, the resonant capacitor Cr, and the drain-source capacitances Ca and Cb of switching elements Qa and Qb. Therefore, the bottom detection of the VW voltage by the delay circuit 47 is performed accurately.

[0106] The first pulse turn-on signal 1st_pulse_on output by the delay circuit 47 is sent to the control circuit 25. This first pulse turn-on signal 1st_pulse_on is then input to the reset terminal of the RS flip-flop 44, resetting the RS flip-flop 44. Consequently, the bottom count circuit 45 is disabled, and the count is cleared to zero.

[0107] like Figure 6As shown, the load detection circuit 24 has switches sw1 and sw2 connected in series. One terminal of switch sw1 is connected to the IS terminal of control IC 12, and one terminal of switch sw2 is connected to the GND terminal of control IC 12. The IS terminal is connected to the output terminal of shunt circuit 13, which includes capacitor Cs and resistor Rs. The common connection point of switches sw1 and sw2 is connected to the CA terminal of control IC 12 via resistor Rf. A capacitor Cca is connected to the CA terminal. Resistor Rf and capacitor Cca constitute an averaging circuit that averages the voltage signal at the common connection point of switches sw1 and sw2.

[0108] The control terminal of switch sw1 is connected to the sw_ctrl terminal that receives the signal sw_ctrl from control circuit 25, and the control terminal of switch sw2 is connected to the sw_ctrl terminal via inverter circuit 51. Thus, load detection circuit 24 inputs either the signal from IS terminal or a ground level signal to the averaging circuit based on the logic level of signal sw_ctrl. Here, signal sw_ctrl can use the high-side output signal hi_pre that drives the high-side switching element Qa, but in this burst control under light load, it is the same as the second pulse. Therefore, during the conduction period of high-side switching element Qa, a voltage proportional to the resonant current is applied to the averaging circuit, and during the deactivation period of high-side switching element Qa, a ground level voltage is applied to the averaging circuit. In this way, by adding the ground level when switching element Qa is deactivated to the averaging circuit, the average value of the input current of the switching power supply, i.e., the load state of the switching power supply, is accurately detected and sent to VS bottom control circuit 23.

[0109] Control circuit 25 according to Figure 7 The actions are performed in the sequence shown in the state transition diagram. (Refer to...) Figure 8 The timing diagram shown illustrates the operation of the control circuit 25. Figure 8 In this circuit, HO is the drive signal for the HO terminal, having the same waveform as the high-side output signal hi_pre from control circuit 25; LO is the drive signal for the LO terminal, having the same waveform as the low-side output signal lo_pre from control circuit 25. VS is the VS voltage at the VS terminal, VW is the VW voltage at the VW terminal, IS is the IS voltage at the IS terminal, Io_h is the output current on the secondary side of transformer T1, and Enb is the enable signal Enb input to the bottom quantity counting circuit 45. It should be noted that... Figure 8 This does not indicate the start of a burst cycle, but rather the case where the bottom quantity Nca_bot is set to "2" in burst control.

[0110] If, during the idle state of normal continuous switching operation, the load specification decreases to a predetermined light load, the control circuit 25 generates a first pulse turn-on signal 1st_pulse_on and enters the three-pulse control period for the start of burst control switching operation. Thus, the control circuit 25 turns on the first pulse. At this time, the high-side output signal hi_pre of the control circuit 25 is low (0), and the low-side output signal lo_pre is high (1). While the high-side switching element Qa remains off, the low-side switching element Qb is turned on. Therefore, the VS terminal becomes ground potential, and the VW voltage becomes the lowest potential.

[0111] Subsequently, if the VW voltage rises from its lowest potential to above the VW threshold voltage Vvwth1 and receives the first pulse turn-off signal 1st_pulse_off from the three-pulse control circuit 22, then the control circuit 25 turns off the first pulse. At this time, the low-side output signal lo_pre output by the control circuit 25 becomes low (0), turning off the switching element Qb.

[0112] After the switching element Qb is turned off, the control circuit 25 performs dead time adjustment (Td_adj) by making the high-side switching element Qa and the low-side switching element Qb simultaneously turn on without conducting current.

[0113] After implementing dead-time adjustment (Td_adj), control circuit 25 generates a second pulse turn-on signal 2nd_pulse_on, enabling the second pulse to conduct. At this time, the high-side output signal hi_pre output by control circuit 25 becomes high (1), turning on the high-side switching element Qa. Thus, if the VS terminal becomes the potential of the DC input voltage Vi, the VW voltage becomes a potential higher than the VW threshold voltage Vvwth2. During the conduction of the high-side switching element Qa, the IS voltage rises, and the output current Io_h flows on the secondary side of transformer T1.

[0114] Subsequently, if the VW voltage drops to the VW threshold voltage Vvwth2 and the second pulse turn-off signal 2nd_pulse_off is received from the three-pulse control circuit 22, the control circuit 25 turns off the second pulse. At this time, the high-side output signal hi_pre output by the control circuit 25 becomes low (0), turning off the switching element Qa.

[0115] Next, control circuit 25 performs dead-time adjustment (Td_adj) to generate the third pulse turn-on signal 3rd_pulse_on. Thus, control circuit 25 turns on the third pulse. At this time, the low-side output signal lo_pre output by control circuit 25 becomes high (1), turning on the low-side switching element Qb. As a result, the IS voltage decreases.

[0116] If the IS voltage drops to the IS threshold voltage Isth and the third pulse turn-off signal 3rd_pulse_off is received from the three-pulse control circuit 22, then the control circuit 25 turns off the third pulse. At this time, the low-side output signal lo_pre output by the control circuit 25 becomes low (0), turning off the switching element Qb.

[0117] If the third pulse is turned off, the burst cycle enters the VM bottom control period where the switching action stops. During this VM bottom control period, the VS bottom control circuit 23, upon receiving the third pulse turn-off signal 3rd_pulse_off, enables the bottom quantity counting circuit 45 to count the VM bottom quantity. If the count ends and the bottom quantity Nvw_bot reaches the set bottom quantity Nca_bot, then after a delay of 1 / 4 of the oscillation period T from the moment of arrival, the delay circuit 47 outputs the first pulse turn-on signal 1st_pulse_on.

[0118] If control circuit 25 receives the first pulse turn-on signal 1st_pulse_on, the first pulse is turned on, and the next burst cycle begins. Additionally, if VS bottom control circuit 23 receives the first pulse turn-on signal 1st_pulse_on, the bottom quantity counting circuit 45 is disabled, and the counted bottom quantity is cleared to zero.

[0119] As described above, in the control device of this switching power supply, the bottom VS value (VS bottom control period) is set according to the load specifications (CA voltage), and the number of resonant cycles of the oscillation during the switch stop period is controlled based on this set bottom VS value. Under light load conditions, since the number of resonant cycles is preset based on a relatively stable CA voltage, the number of resonant cycles does not change frequently but becomes stable, and no mixing of resonant cycles occurs. Therefore, it is possible to balance the high efficiency based on burst control and the noise suppression based on the non-mixing of resonant cycles.

[0120] In the aforementioned VS bottom control circuit 23, when the load changes abruptly from a light load state to a heavy load state, as when returning from a standby state to a normal state, the output voltage sometimes drops temporarily. This is because the bottom quantity control is based on the load signal representing the load state, i.e., the voltage of the CA terminal with response delay, so the bottom quantity control cannot keep up with abrupt changes in load. Hereinafter, a control device of the second embodiment, which improves the output voltage drop during a rapid increase in load, will be described.

[0121] Figure 9 This is a circuit diagram showing an example configuration of the bottom control circuit of the VS in the control IC of the control device in the second embodiment. Figure 10This is a graph showing the relationship between the set bottom quantity and the FB voltage. Figure 11 This is a timing diagram for a sudden increase in load.

[0122] In the second embodiment, only the VS bottom control circuit 23 in the control IC12 of the first embodiment is changed to Figure 9 The VS bottom control circuit 23a shown retains all other components of the control IC 12. Therefore, the configuration and operation of the modified VS bottom control circuit 23a will be explained here. It should be noted that... Figure 9 In the VS bottom control circuit 23a, for the purpose of... Figure 4 The same components of the VS bottom control circuit 23 are labeled with the same symbols and their detailed descriptions are omitted.

[0123] VS bottom control circuit 23a via Figure 4 The VS bottom control circuit 23 is constructed by adding an analog-to-digital converter 61, a bottom quantity setting circuit 62, a comparator (bottom quantity comparator) 63, and a selection circuit 64.

[0124] The output terminal of analog-to-digital converter 41, whose input terminal is connected to the CA terminal of control IC 12, is connected to the input terminal of bottom quantity setting circuit 42. The output terminal of bottom quantity setting circuit 42 is connected to the non-inverting input terminal of comparator 63 and one input terminal of selection circuit 64. The input terminal of analog-to-digital converter 61 is connected to the FB terminal of control IC 12, and the output terminal of analog-to-digital converter 61 is connected to the input terminal of bottom quantity setting circuit 62. The output terminal of bottom quantity setting circuit 62 is connected to the inverting input terminal of comparator 63 and another input terminal of selection circuit 64. The output terminal of comparator 63 is connected to the control terminal S of selection circuit 64, and the output terminal of selection circuit 64 is connected to one input terminal of bottom quantity comparison circuit 46. Selection circuit 64 can employ, for example, a multiplexer that outputs a signal to one input terminal or another input terminal based on the logic state of control terminal S.

[0125] In the VS bottom control circuit 23a, analog-to-digital converter 41 converts the CA voltage into a 10-bit digital signal, and analog-to-digital converter 61 converts the FB voltage into a 10-bit digital signal. Bottom quantity setting circuit 42 sets the bottom quantity (during switch stop) corresponding to the CA voltage (load signal), and bottom quantity setting circuit 62 sets the bottom quantity (during switch stop) corresponding to the FB voltage (feedback voltage). That is, bottom quantity setting circuit 42 has, for example... Figure 5 The input / output characteristics shown indicate that the output corresponds to the set bottom quantity Nca_bot of the CA voltage. The bottom quantity setting circuit 62 has... Figure 10The input / output characteristics shown output a set bottom quantity Nfb_bot corresponding to the FB voltage. The set bottom quantity Nca_bot and the set bottom quantity Nfb_bot are represented, for example, by 4-bit digital signals. It should be noted that the bottom quantity setting circuits 42 and 62 function as setting circuits during switch-off periods, respectively.

[0126] according to Figure 5 The example shown illustrates the relationship between the set bottom quantity and the CA voltage. The bottom quantity setting circuit 42 outputs a set bottom quantity Nca_bot that decreases sequentially within an integer range of "10-1" within the CA voltage variation range (0-1 volts). On the other hand, according to... Figure 10 The example shown illustrates the relationship between the set bottom quantity and the FB voltage. The bottom quantity setting circuit 62 outputs a set bottom quantity Nfb_bot of "10" within the FB voltage variation range (1.0-1.3 volts) under stable load. Furthermore, the bottom quantity setting circuit 62 outputs a set bottom quantity Nfb_bot that rapidly changes between "10" and "1" within the FB voltage variation range (1.4-1.6 volts) under sudden load changes.

[0127] Comparator 63 compares the set bottom quantity Nca_bot with the set bottom quantity Nfb_bot to determine which one is smaller.

[0128] Here, under a stable load, a set bottom quantity Nca_bot with a value between "10-1" and "7" is input to the non-inverting input terminal of comparator 63, and a set bottom quantity Nfb_bot with a value of "10" is input to the inverting input terminal of comparator 63. Since comparator 63 inputs a value larger than the value at the non-inverting input terminal to the inverting input terminal, it outputs a low-level (0) logic signal, which is input to the control terminal S of selection circuit 64. If selection circuit 64 inputs a low-level (0) logic signal to control terminal S, the set bottom quantity Nca_bot is selected and output as a 4-bit digital signal. That is, selection circuit 64 selects and outputs a set bottom quantity Nca_bot smaller than the value of set bottom quantity Nfb_bot. This set bottom quantity N_bot is input to bottom quantity comparison circuit 46 as a reference signal for comparison.

[0129] Next, if a sudden increase in load occurs, a set bottom quantity Nca_bot, which has a value of "7" and is almost unchanged during stable load conditions, is input to the non-inverting input terminal of comparator 63, and a set bottom quantity Nfb_bot, which has a value of "1", is input to the inverting input terminal of comparator 63. At this time, since a "7" larger than the value of the inverting input terminal is input to the non-inverting input terminal of comparator 63, comparator 63 outputs a high-level (1) logic signal, which is input to the control terminal S of selection circuit 64. If selection circuit 64 inputs a high-level (1) logic signal to control terminal S, the set bottom quantity Nfb_bot is selected and output as the set bottom quantity N_bot. That is, selection circuit 64 selects a set bottom quantity Nfb_bot smaller than the value of set bottom quantity Nca_bot and outputs it as the set bottom quantity N_bot. This set bottom quantity N_bot is input to the bottom quantity comparison circuit 46 as a reference signal for comparison.

[0130] Next, refer to Figure 11 The operation of the switching power supply device equipped with the control IC12 having the VS bottom control circuit 23a configured as described above will be explained. First, when the load is in standby mode and the switching power supply device is suddenly controlled, the output voltage Vo is controlled based on the stable CA voltage. Therefore, the FB voltage (feedback voltage) and the output power Po are in a stable state.

[0131] Here, if the output power Po surges rapidly due to the load returning from standby to normal operation, the FB voltage increases in response to this sudden change in output power Po. Consequently, the values ​​of the set bottom quantity Nca_bot (based on the CA voltage) and the set bottom quantity Nfb_bot (based on the FB voltage) are reversed, and the set bottom quantity Nfb_bot during the VS bottom control period effectively becomes "1". By minimizing the VS bottom control period, which is the period of switch stop, the control responsiveness is improved, and the drop in output voltage Vo is reduced. It should be noted that the curve represented by the dashed line in the output voltage Vo variation curve represents the case where control is used when the CA voltage cannot respond well to the rapid increase in load.

[0132] As described above, in the control device of the switching power supply device of the second embodiment, it is possible to take into account both the high efficiency based on burst control and the noise suppression based on the non-mixing of resonant cycle numbers. In addition, it is also possible to suppress the drop in output voltage when the load increases rapidly.

[0133] It should be noted that in the second embodiment, the smaller of the number of resonance cycles (VS bottom count) of the oscillation corresponding to the CA voltage and the number of resonance cycles (VS bottom count) of the oscillation corresponding to the FB voltage is used in the setting of the VS bottom control period in the burst control. However, the result of selecting the smaller of the number of resonance cycles of the oscillation corresponding to the CA voltage and the number of resonance cycles of the oscillation corresponding to the FB voltage is not necessarily only used in the setting of the VS bottom control period in the burst control.

[0134] In addition, in the above embodiment, the series resonant circuit including the resonant reactor and the resonant capacitor Cr is connected in parallel with the low-side switching element Qb, but it can also be connected in parallel with the high-side switching element Qa.

Claims

1. A control device for a switching power supply device, characterized in that: have: a load detection circuit, the output of which is a load signal indicating a load state by dividing and averaging the resonant current of the resonant circuit; a shutdown signal generating circuit that compares a winding voltage and a voltage signal corresponding to a current obtained by shunting the resonant current with a plurality of threshold voltages, respectively, during a switching period of burst control at light load, and generates a plurality of shutdown signals for turning off a first switching element on a high side and a second switching element on a low side according to the comparison results, the winding voltage being generated by an auxiliary winding of a transformer constituting a part of a resonant reactor of the resonant circuit; a conduction signal generating circuit that counts the number of resonance cycles of the ringing voltage generated during the switching stop period of the burst control, and when the number of resonance cycles reaches a set number of resonance cycles preset according to the specifications of the load, generates a first pulse conduction signal for turning on the second switching element at the start of the switching period of the burst control; as well as A control circuit generates a first control signal and a second control signal for alternately controlling on / off of the first switching element and the second switching element based on the off signal generated by the off signal generating circuit and the first pulse on signal generated by the on signal generating circuit.

2. The control device of the switching power supply device according to claim 1, characterized in that: The shutdown signal generating circuit has: a threshold voltage generating circuit which generates a first threshold voltage for detecting a change in the winding voltage and a second threshold voltage higher than the first threshold voltage by inputting a feedback voltage corresponding to a difference between an output voltage of the switching power supply device and a target voltage of the output voltage; a first comparator, which outputs a first pulse off signal if the winding voltage is higher than the first threshold voltage; a second comparator, which outputs a second pulse off signal if the winding voltage is lower than the second threshold voltage; as well as The third comparator outputs a third pulse-off signal when a voltage signal corresponding to a current obtained by diverting the resonant current is lower than a third threshold voltage.

3. The control device of the switching power supply device according to claim 2, characterized in that: The threshold voltage generating circuit makes the difference between the first threshold voltage and the second threshold voltage outputted by the threshold voltage generating circuit smaller as the feedback voltage increases.

4. The control device of the switching power supply device according to claim 2, characterized in that: The control circuit receives the first pulse shutdown signal, the second pulse shutdown signal and the third pulse shutdown signal output by the shutdown signal generating circuit and the first pulse on signal output by the on signal generating circuit, and generates the first pulse, the second pulse and the third pulse in sequence, uses the first pulse and the third pulse as the second control signal, and uses the second pulse as the first control signal.

5. The control device of the switching power supply device according to claim 4, characterized in that: The control circuit turns on the second pulse and the third pulse after performing dead time adjustment after the first pulse and the second pulse are turned off, respectively.

6. The control device of the switching power supply device according to claim 2, characterized in that: The conduction signal generating circuit comprises: a bottom quantity setting circuit, which sets the bottom quantity of the ringing voltage according to the load signal; A counting circuit, which counts the number of times the winding voltage is lower than zero potential; A bottom number comparison circuit, which outputs a consistent signal when the number counted by the counting circuit is consistent with the bottom number; a delay circuit that delays the coincidence signal by 1 / 4 cycle of the ringing voltage and outputs the signal as the first pulse conduction signal; A trigger that enables the counting circuit by inputting the third pulse-off signal and disables the counting circuit by inputting the first pulse-on signal outputted by the delay circuit.

7. The control device of the switching power supply device according to claim 6, characterized in that: The bottom number setting circuit sets the bottom number to be smaller as the value of the load signal is larger.

8. The control device of the switching power supply device according to claim 2, characterized in that: The conduction signal generating circuit comprises: a first bottom quantity setting circuit, which sets the bottom quantity of the ringing voltage according to the load signal; a second bottom quantity setting circuit for setting the bottom quantity of the ringing voltage according to a feedback voltage corresponding to a difference between an output voltage of the switching power supply device and a target voltage of the output voltage; a bottom quantity comparator for comparing a first bottom quantity set by the first bottom quantity setting circuit with a second bottom quantity set by the second bottom quantity setting circuit; a selection circuit, which selects and outputs the first bottom quantity when the bottom quantity comparator determines that the second bottom quantity is larger than the first bottom quantity, and selects and outputs the second bottom quantity when the bottom quantity comparator determines that the second bottom quantity is smaller than the first bottom quantity; A counting circuit, which counts the number of times the winding voltage is lower than zero potential; a bottom number comparison circuit, which outputs a coincidence signal when the number counted by the counting circuit is consistent with the first bottom number or the second bottom number output by the selection circuit; a delay circuit that delays the coincidence signal by 1 / 4 cycle of the ringing voltage and outputs the signal as the first pulse conduction signal; A trigger that enables the counting circuit by inputting the third pulse-off signal and disables the counting circuit by inputting the first pulse-on signal outputted by the delay circuit.

9. The control device of the switching power supply device according to claim 8, characterized in that: The first bottom number setting circuit sets the first bottom number to be smaller as the value of the load signal is larger, and the second bottom number setting circuit sets the second bottom number to be smaller as the value of the feedback voltage is larger.

10. The control device of the switching power supply device according to claim 4, characterized in that: The load detection circuit outputs the load signal obtained by averaging the voltage signal when the control circuit generates the second pulse and the ground potential when the control circuit does not generate the second pulse.

11. A control device for a switching power supply device, characterized in that: A conduction signal generating circuit is provided, wherein the conduction signal generating circuit comprises: a first switching stop period setting circuit that receives a load signal indicating a load state by dividing and averaging a resonant current of a resonant circuit of a switching power supply device, sets a first switching stop period of a burst control when the load is light, and sets a first set number of resonant cycles in the first switching stop period according to the load signal; a second switching stop period setting circuit that receives a feedback voltage corresponding to a difference between an output voltage of the switching power supply device and a target voltage of the output voltage, sets a second switching stop period of the burst control at a light load, and sets a second set number of resonance cycles in the second switching stop period according to the feedback voltage; a comparator that compares the first set resonance period number with the second set resonance period number; and a selection circuit that selects the second switch stop period as the switch stop period of the burst control and selects the second set resonance period as the set resonance period only when the comparator determines that the second set resonance period is smaller than the first set resonance period, The conduction signal generation circuit counts the number of resonance cycles of the ringing voltage generated during the burst control switching stop period, and generates a pulse conduction signal when the number of resonance cycles reaches the set number of resonance cycles during the burst control switching stop period.

Images