Optical proximity correction method and method for manufacturing photolithography mask using the same

Abstract

The present invention discloses an optical proximity correction (OPC) method and a method for manufacturing a photolithography mask using the same, wherein the OPC method may include: providing a design layout including a conductive pattern; determining a line end void (LEV) risk pattern among the conductive patterns, each of which has a risk of suffering from poor contact due to LEV; setting a mark, the mark including a portion of the LEV risk pattern and a portion of the conductive pattern adjacent to the LEV risk pattern; performing a first OPC on a first pattern included in the mark and performing a second OPC on a second pattern outside the mark, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed multiple times; and calculating a cost function for each mark. The determination may include comparing the risk of poor contact in each conductive pattern based on a scoring function, and the scoring function may be inversely proportional to the width of each conductive pattern.

Description

Technical Field

[0001] The inventive concept relates to an optical proximity correction method and / or a method of manufacturing an extreme ultraviolet (EUV) mask using the same, and more particularly, to an optical proximity correction (OPC) method exhibiting improved reliability and / or a method of manufacturing a photolithography mask using the same. Background Art

[0002] The photolithography process in the manufacturing process of semiconductor chips is a technology that forms circuit patterns by irradiating light onto a photosensitive layer coated on a substrate. Recently, due to the trend of finer size features in semiconductor manufacturing processes, exposure methods using deep ultraviolet (DUV) light, EUV light, or electron beams have attracted attention. Since the pattern has a finer size, an optical proximity effect (OPE) occurs in the exposure process due to the influence between adjacent patterns. In order to solve this OPE, research on optical proximity correction (OPC) is underway. Summary of the invention

[0003] Some example embodiments of the inventive concepts provide an optical proximity correction (OPC) method exhibiting improved reliability and / or a method of manufacturing a photolithography mask by using the OPC method.

[0004] The inventive concept is not limited to the aspects set forth above, and other aspects of the inventive concept will be clearly understood by those skilled in the art from the following description.

[0005] According to an example embodiment of the inventive concept, an optical proximity correction (OPC) method may include: providing a design layout including a conductive pattern; determining a line end void (LEV) risk pattern among the conductive patterns, each of the LEV risk patterns having a risk of suffering from poor contact due to LEV; setting a mark, the mark including a portion of the LEV risk pattern and a portion of the conductive pattern adjacent to the LEV risk pattern; performing LEV-aware OPC on the LEV risk pattern; and calculating at least one cost function for each mark. The LEV-aware OPC may take a bridging target pattern as a target shape, and the bridging target pattern may be determined by a bridging target, wherein the bridging target is a minimum distance between the conductive patterns.

[0006] According to an example embodiment of the inventive concept, an optical proximity correction (OPC) method may include: providing a design layout including a conductive pattern; determining a line end void (LEV) risk pattern among the conductive patterns, each of the LEV risk patterns having a risk of suffering from poor contact due to LEV; setting a mark, the mark including a portion of the LEV risk pattern and a portion of the conductive pattern adjacent to the LEV risk pattern; performing a first OPC on a first pattern included in the mark and performing a second OPC on a second pattern outside the mark, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed multiple times; and calculating a cost function for each mark. The determination may include comparing the risk of poor contact occurring in each conductive pattern based on a scoring function, and the scoring function may be inversely proportional to the width of each conductive pattern.

[0007] According to an example embodiment of the inventive concept, a method for manufacturing a photolithography mask may include: providing a design layout including a conductive pattern; performing optical proximity correction (OPC) on the design layout; and manufacturing a photolithography mask according to the result of the execution. The execution may include determining a line end void (LEV) risk pattern among the conductive patterns, each of which has a risk of suffering from poor contact due to LEV; setting a mark, the mark including a portion of the LEV risk pattern and a portion of the conductive pattern adjacent to the LEV risk pattern; performing a first OPC on a pattern within the mark and performing a second OPC on a pattern outside the mark, the second OPC being different from the first OPC; and calculating each of a plurality of cost functions for each mark by using an OPC optimal profile considering LEV and a process window condition (PWC) profile, the OPC optimal profile considering LEV being a first profile according to an optimal condition for each LEV risk pattern that has been modified by the first OPC, and the PWC profile being a second profile according to the PWC for each LEV risk pattern that has been modified by the first OPC. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Some exemplary embodiments of the present inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a layout diagram illustrating problems of both an optical proximity correction (OPC) method of a comparative example and a method of manufacturing a semiconductor device by using the OPC method;

[0010] Figure 2 is a flow chart illustrating an OPC method according to some example embodiments;

[0011] Figure 3 is a layout diagram illustrating an OPC method according to some example embodiments;

[0012] Figure 4 By magnifying Figure 3 A partial layout diagram shown in the portion “MRK” of the layout diagram;

[0013] Figure 5 is a conceptual diagram illustrating an OPC method according to some example embodiments;

[0014] Figure 6 is a graph illustrating an OPC method according to some example embodiments;

[0015] Figure 7 and Figure 8 are flowcharts respectively illustrating OPC methods according to some example embodiments; and

[0016] Fig. 9 is a flowchart illustrating processes of a method of manufacturing a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components will be denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0018] It will be understood that although the terms first, second, third, etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the example embodiments, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0019] Figure 1 is a layout diagram illustrating problems of both an optical proximity correction (OPC) method of a comparative example and a method of manufacturing a semiconductor device by using the OPC method.

[0020] refer to Figure 1 , the semiconductor chip may include a circuit pattern. The circuit pattern may include a plurality of wiring layers and vias forming connections between the wiring layers. According to some example embodiments, each wiring layer may include a conductive pattern 110 and an insulating layer 120.

[0021] According to some example embodiments, the conductive pattern 110 may form an electrical path for operation of a semiconductor chip. According to some example embodiments, the conductive pattern 110 may be connected to a via of a lower layer therebelow and a via of a subsequent layer (or an upper layer thereon) formed subsequently. Here, in an etching process for forming the conductive pattern 110 having a line shape, skew may occur in an end portion of the conductive pattern 110 due to an optical proximity effect, etc.

[0022] In order to solve the problem described above, a final target layout can be determined by applying a line end etching skew bias to a layout designed according to a design rule, and then performing OPC, wherein the shape of a conductive pattern included in the designed layout is modified so that the circuit pattern actually implemented is close to the final target layout. OPC can be repeatedly performed, and as OPC is further repeated, an actual pattern formed on a wafer by using the modified conductive pattern can be closer and closer to the initial design.

[0023] Here, the end of the conductive pattern 110 having a linear shape may have a shape that narrows toward its end. Such a shape of a linear pattern may cause a line end void (LEV) defect 110V, due to which a metal cannot properly fill an area near the end of the conductive pattern 110. The conductive pattern 110 may be connected to a conductive path to connect to a conductive pattern of a lower layer thereunder or a conductive pattern of a subsequent layer formed thereafter, and when a conductive path is formed adjacent to the end of the conductive pattern 110, a failure of a semiconductor chip may occur due to electrical disconnection caused by the LEV defect 110V.

[0024] Figure 2 is a flow chart illustrating an OPC method according to some example embodiments.

[0025] Figure 3 is a layout diagram illustrating an OPC method according to some example embodiments.

[0026] Figure 4 By magnifying Figure 3 The partial layout diagram is shown in the portion 'MRK' of the layout diagram.

[0027] refer to Figure 2 and Figure 3, in operation P110, a design layout may be provided. The design layout may include various geometric patterns for implementing a semiconductor chip. The design layout may extend in first and second directions (or alternatively, horizontal and vertical directions, or X and Y directions in a Cartesian coordinate system) that intersect each other perpendicularly. The design layout may include a linear conductive pattern 110 having a desired (or alternatively, a predetermined) width and extending in a first direction (X direction) or a second direction (Y direction). According to some example embodiments, the conductive pattern 110 may be designed according to a desired (or alternatively, a predetermined) design rule.

[0028] The design layout may include metal patterns, oxide patterns, semiconductor patterns, etc., for implementing various components of a semiconductor chip. The components may include, for example, active areas, gate electrodes, metal lines, paths for providing interlayer connections, and bonding pads. The components may be formed on a semiconductor substrate or on various material layers deposited on a semiconductor substrate. The design layout may be stored as one or more data files with information about the geometric pattern. For example, the design layout may be stored in any suitable format that is computer readable, such as a Graphic Data System II (GDSII) data format, a Caltech Intermediate Format (CIF) data format, an Open Artwork System Exchange Standard (OASIS) data format, etc.

[0029] According to some example embodiments, the conductive pattern 110 may be connected to the upper conductive via 130U and the lower conductive via 130L. According to some example embodiments, in order to implement a semiconductor chip, a design layout may include a plurality of layouts, each layout including an insulating layer 120 and a conductive pattern 110, and the upper conductive via 130U and the lower conductive via 130L provide interlayer connections between the upper conductive pattern 110 and the lower conductive pattern 110.

[0030] exist Figure 3 The via marked by a dotted line in FIG. 1 may be a lower conductive via 130L that connects a conductive pattern 110 included in a layout to a conductive pattern 110 included in a layout below the layout set forth above. Figure 3 A via marked by a solid line in FIG. 1 may be an upper conductive via 130U that connects the conductive pattern 110 included in the layout to a conductive pattern included in a layout formed after the layout set forth above or to a conductive pattern included in a layout located above the layout set forth above.

[0031] According to some example embodiments, each of the conductive pattern 110 and the upper conductive path 130U and the lower conductive path 130L may include a conductive material. According to some example embodiments, each of the conductive pattern 110 and the upper conductive path 130U and the lower conductive path 130L may include a doped semiconductor material or a metal material. According to some example embodiments, each of the conductive pattern 110 and the upper conductive path 130U and the lower conductive path 130L may include at least one selected from the group consisting of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), carbon (C), and graphene, or an alloy thereof, etc.

[0032] Next, in operation P120, an LEV risk pattern 110R may be selected. Here, the LEV risk pattern 110R refers to a pattern having a risk of generating an LEV defect in the conductive pattern 110 (eg, a relatively high risk relative to a reference value). Figure 5 and Figure 6 Describe a comparison of the risks of developing a LEV defect.

[0033] Figure 5 is a conceptual diagram illustrating an OPC method according to some example embodiments, Figure 6 is a graph illustrating an OPC method according to some example embodiments.

[0034] refer to Figure 5 , showing both a layout view and a cross-sectional view of an end portion of a conductive pattern 110 having a line shape.

[0035] refer to Figure 5 , the conductive pattern 110 may have a line shape. As described above, the end of the conductive pattern 110 implemented on the wafer may have a shape that becomes narrower toward the end thereof.

[0036] The conductive pad may be further disposed between the conductive pattern 110 and the insulating layer 120 and between the conductive pattern 110 and the lower conductive via 130L, without being limited thereto. In addition, the insulating pad 125 may be disposed between adjacent insulating layers 120 .

[0037] For convenience, the length from the lower conductive via 130L to the end of the conductive pattern 110 adjacent to the lower conductive via 130L in the extension direction of the conductive pattern 110 is referred to as the via end length VEL. In other words, the distance between the end of the conductive pattern 110 and the lower conductive via 130L contacting the conductive pattern 110 in the extension direction of the conductive pattern 110 is referred to as the via end length VEL. In addition, the width of the conductive pattern 110 in a direction perpendicular to the direction in which the conductive pattern 110 extends longitudinally is referred to as the pattern width PW. According to some example embodiments, the risk of semiconductor chip failure due to the generation of LEV can be evaluated by using the via end length VEL and the pattern width PW.

[0038] Although, about Figure 5 , the risk of semiconductor chip failure due to LEV is described based on the end of the conductive pattern 110 adjacent to the lower conductive via 130L, but the description may be based on the upper conductive via 130U (see Figure 3 ) and the conductive pattern 110 adjacent to the upper conductive via 130U are similarly performed.

[0039] According to some example embodiments, a scoring function for evaluating a risk of semiconductor chip failure due to generation of LEV may be determined by using a via end length VEL and a pattern width PW as shown in Mathematical Equation 1.

[0040] [Mathematical equation 1]

[0041]

[0042] Each of a and b is a proportionality coefficient and may have a length size, but is not limited thereto. The scoring function is for comparison using relative numerical values ​​and has a normalized value.

[0043] refer to Figure 6 , shows a plurality of contour lines of values ​​of a scoring function regarding via end length VEL and pattern width PW according to Mathematical Equation 1.

[0044] According to some example embodiments, as the via end length VEL and the pattern width PW increase, the risk of failure generation due to LEV may decrease, and as the via end length VEL and the pattern width PW decrease, the risk of failure generation due to LEV may increase. S1 to S4 represent contours obtained by connecting groups of values ​​of the via end length VEL and groups of values ​​of the pattern width PW, which produce equal values ​​of the scoring function, and may be contours corresponding to increasingly larger scoring function values ​​in the order described. For example, S1, S2, S3, and S4 may correspond to approximately 20, approximately 40, approximately 60, and approximately 80, respectively, without limitation thereto. For each design layout, a threshold of the scoring function may be determined based on on-line and offline data on failure generation, and a pattern having a scoring function value greater than the threshold may be classified as an LEV risk pattern.

[0045] Reference again Figure 2 and Figure 3 , determining the LEV risk pattern in operation P120 may include determining the LEV risk pattern 110R from existing online / offline data regarding fault inspection of a layout implemented on a wafer.

[0046] According to some example embodiments, determining the LEV risk pattern 110R in operation P120 may include performing full-chip matching based on the LEV risk pattern 110R determined according to a scoring function or existing online / offline data. The full-chip matching may include finding a conductive pattern 110 that is identical or substantially similar to the LEV risk pattern 110R among the conductive patterns 110 included in the design layout. According to some example embodiments, the conductive pattern 110 that is identical or substantially similar to the LEV risk pattern 110R means that the conductive pattern 110 has a shape that is identical or substantially similar to that of the LEV risk pattern 110R, and has a relative position that is identical or substantially similar to that of the LEV risk pattern 110R with respect to the upper conductive path 130U or the lower conductive path 130L.

[0047] Next, in operation P130, a mark MRK including the determined LEV risk pattern 110R may be defined. According to some example embodiments, the mark MRK may be an area that has undergone an OPC different from the OPC applied to adjacent different parts of the design layout when performing OPC. According to some example embodiments, the mark MRK may be an area that has undergone an OPC that considers LEV (LEV-aware) as described below. According to some example embodiments, the center of the mark MRK may be located near the area where the LEV risk pattern 110R contacts the lower conductive path 130L or the upper conductive path 130U, without being limited thereto. According to some example embodiments, the mark MRK may be an area having a square shape. According to some example embodiments, the mark MRK may be a square area in which half of the length of one side is set in the OPC as the maximum distance that causes interaction between patterns, without being limited thereto. For example, the mark MRK may have any suitable shape, such as a circle, an ellipse, a rectangle, or the like.

[0048] Next, in operation P140, OPC considering LEV may be performed on the LEV risk pattern 110R. According to some example embodiments, when OPC considering LEV is performed, OPC according to the prior art may be performed together with OPC considering LEV. According to some example embodiments, OPC according to the prior art may be performed on an area outside the mark MRK.

[0049] According to some example embodiments, the OPC taking into account LEV may be different from the OPC according to the prior art. Figure 4 Describe OPC considering LEV.

[0050] Figure 4 By magnifying Figure 3 The figure is shown with the mark MRK. Figure 4 , the design shape, target pattern shape, and contour shape of each of the conductive pattern 110 and the LEV risk pattern 110R are shown. For example, a target according to conditions (e.g., optimal conditions or process window conditions) is shown by using a dashed single-dot chain line and a dashed double-dot chain line, and a contour obtained by simulation is shown by using a dashed line.

[0051] As used herein, the term "optimal conditions" refers to the best dose and focus conditions for forming a particular layout. The optimal conditions may vary for each device to be formed and each pattern to be achieved.

[0052] The process window condition (PWC) may include a focus condition that is defocused from an optimal condition by as much as a set value and / or a dose condition that is changed from an optimal condition by as much as a set value. According to some example embodiments, the PWC may include a plurality of focus and dose conditions without being limited thereto. For example, the PWC may include one focus and dose condition or continuous focus and dose conditions.

[0053] The bridging target pattern BRTP is shown as a dashed double-dotted line and can be determined according to the first and second bridging targets BRTx and BRTy. The first and second bridging targets BRTx and BRTy can be determined according to process data about a layout that is the same as or substantially similar to the layout to be subjected to OPC considering LEV. However, the inventive concept is not limited thereto. In some example embodiments, the first and second bridging targets BRTx and BRTy can be determined according to simulation data about the layout to be subjected to OPC considering LEV. Each of the first bridging target BRTx and the second bridging target BRTy can be the minimum distance that does not allow for bridging that may cause an undesirable short circuit between adjacent conductive patterns 110, between LEV risk patterns 110R and conductive patterns 110 adjacent thereto, or between adjacent LEV risk patterns 110R. The first and second bridging targets BRTx and BRTy can be bridging targets in the first direction (X direction) and the second direction (Y direction), respectively, and can have different values ​​from each other.

[0054] The bridge target pattern BRTP may be a maximum size pattern satisfying the first and second bridge targets BRTx and BRTy. That is, when each conductive pattern 110 or LEV risk pattern 110R is larger than the bridge target pattern BRTP, bridges may occur due to a small distance between adjacent patterns.

[0055] The enclosure target pattern ENCTP is shown as a dashed single-dot chain line and may be a target shape determined by the first and second enclosure targets ENCTx and ENCTy and the LEV risk pattern 110R or the LEV risk pattern 110R modified by the OPC considering LEV. In other words, the OPC considering LEV may take the enclosure target pattern ENCTP as a target shape, the enclosure target pattern being determined by the first enclosure target ENCTx and the second enclosure target ENCTy. As used herein, the term 'enclosure' refers to a distance from an upper conductive path 130U or a lower conductive path 130L adjacent to an end of the LEV risk pattern 110R to an end point of the LEV risk pattern 110R in the conductive pattern 110 along a first or second direction (X or Y direction).

[0056] According to some example embodiments, the first and second shell targets ENCTx and ENCTy may be determined based on process data about a layout that is the same as or substantially similar to the layout to be subjected to OPC considering LEV. However, the inventive concept is not limited thereto, and the first and second shell targets ENCTx and ENCTy may be determined based on simulation data about the layout to be subjected to OPC considering LEV. The first and second shell targets ENCTx and ENCTy may be shell targets in a first direction (X direction) and a second direction (Y direction), respectively, and may have different values ​​from each other.

[0057] According to some example embodiments, the shell target pattern ENCTP may be a minimum size pattern that satisfies the first and second shell targets ENCTx and ENCTy in the first and second directions (X and Y directions), respectively. That is, the sum of the distances in the first direction (X direction) from the outer boundary of the shell target pattern ENCTP to the lower conductive path 130L may be the first shell target ENCTx, and the sum of the distances in the second direction (Y direction) from the outer boundary of the shell target pattern ENCTP to the lower conductive path 130L may be the second shell target ENCTy.

[0058] Modification of the conductive pattern 110 and the LEV risk pattern 110R by OPC and OPC considering LEV may be iterated multiple times. According to some example embodiments, the OPC considering LEV may be an OPC using the first and second bridging targets BRTx and BRTy and the first and second shell targets ENCTx and ENCTy. According to some example embodiments, the OPC considering LEV may be an OPC that ensures a margin between the lower conductive path 130L and the line end by targeting the first and second shell targets ENCTx and ENCTy and ensures a bridging margin between adjacent patterns by targeting the first and second bridging targets BRTx and BRTy.

[0059] According to some example embodiments, OPC according to the related art may be performed on both the conductive pattern 110 outside the mark MRK and the LEV risk pattern 110R.

[0060] refer to Figure 2 and Figure 4 In operation P150 , a cost function may be calculated. According to some example embodiments, the calculation of the cost function may include calculating each of the LEV risk pattern 110R-PWC profile distance, the PWC target hull, and the optimal profile hull.

[0061] The PWC profile PCC is shown as a long dashed line and is obtained by simulating a shape when the LEV risk pattern 110R modified by the OPC considering LEV is implemented on a wafer under the PWC by a photolithography process. When the PWC includes a plurality of conditions or includes continuous conditions, the PWC profile PCC can be determined by using a PWC that allows a maximum profile to be obtained among the plurality of conditions or the continuous conditions. When the LEV risk pattern 110R is divided into a plurality of partial patterns, the PWC profile PCC can be determined by applying a different PWC to each divided partial pattern of the LEV risk pattern 110R, without being limited thereto. Dividing each of the conductive pattern 110 and the LEV risk pattern 110R into partial patterns can be performed by any division method known in the art (for example, a method including dividing a pattern in a corner area and dividing a pattern greater than a desired (or alternatively, predetermined) length into equal parts).

[0062] While performing the photolithography process, exposure may be locally performed under exposure conditions different from the optimal conditions due to effects caused by aberration or interference (e.g., flare) between adjacent patterns. Due to this local tolerance, a pattern having a larger line width than a result simulated by using the optimal conditions may be transferred onto the wafer. According to some example embodiments, the PWC profile PCC may be determined based on a maximum pattern calculated by using the PWC, thereby mitigating or preventing the generation of bridges in both the LEV risk pattern 110R and the conductive pattern 110 modified by the OPC considering the LEV.

[0063] According to some example embodiments, the PWC profile distance may be determined based on the PWC profile PCC. Figure 4 In the embodiment, the PWC contour distance may be the sum of the distances between the PWC contour PCC of the LEV risk pattern 110R and the PWC contour PCC of the conductive pattern 110 adjacent to the LEV risk pattern 110R. For example, the PWC contour distance may be the sum of the first and second PWC contour distances PCDx and PCDy.

[0064] Here, the first PWC profile distances PCDx each refer to a first direction (X direction) distance between the PWC profile PCC of the LEV risk pattern 110R and the PWC profile PCC of the conductive pattern 110 spaced apart from the LEV risk pattern 110R in the first direction (X direction). In addition, the second PWC profile distances PCDy each refer to a second direction (Y direction) distance between the PWC profile PCC of the LEV risk pattern 110R and the PWC profile PCC of the conductive pattern 110 spaced apart from the LEV risk pattern 110R in the second direction (Y direction). Here, since the risk of generating a bridge between the patterns is relatively low, the first and second PWC target distances PTDx and PTDy (not shown) greater than a desired (or alternatively, predetermined) value may be excluded when calculating the PWC target.

[0065] exist Figure 4 In the embodiment, since the second direction (Y direction) end of the PWC profile PCC has a rounded shape, the second PWC target distance PTDy can be selected as the minimum distance in the second direction (Y direction) between the PWC profile PCC of the conductive pattern 110 and the PWC profile PCC of the LEV risk pattern 110R.

[0066] Therefore, the PWC profile distance PCD can be determined by mathematical equation 2.

[0067] [Mathematical equation 2]

[0068] PCD=∑PCDx+∑PCDy

[0069] The LEV-considered OPC optimal profile LAOBC is shown as a short dashed line, and is obtained by simulating a shape when the LEV risk pattern 110R modified by the LEV-considered OPC is realized on a wafer under optimal (or alternatively, optimum) conditions by a photolithography process.

[0070] According to some example embodiments, the optimal profile shell may be determined based on the OPC optimal profile LAOBC considering LEV. According to some example embodiments, the optimal profile shell may be the sum of the distances between the edge of the lower conductive path 130L contacting the LEV risk pattern 110R in the mark MRK and the OPC optimal profile LAOBC considering LEV. For example, the optimal profile shell may be the sum of the first and second optimal profile shells BCEx and BCEy.

[0071] Here, the first optimal contour shell BCEx refers to the first direction (X direction) distance between the lower conductive path 130L contacting the LEV risk pattern 110R and the OPC optimal contour LAOBC considering LEV. The second optimal contour shell BCEy refers to the second direction (Y direction) distance between the lower conductive path 130L contacting the LEV risk pattern 110R and the OPC optimal contour LAOBC considering LEV.

[0072] The optimal contour enclosure BCE can be determined by mathematical equation 3.

[0073] [Mathematical equation 3]

[0074] BCE=∑BCEx+∑BCEy

[0075] In addition, the bridge target distance BTD and the shell target distance ETD can be determined by mathematical equation 4.

[0076] [Mathematical equation 4]

[0077] BTD=ΣBRTx+ΣBRTy

[0078] ETD=∑ENCTx+∑ENCTy

[0079] Wherein BRTx and BRTy represent the first and second bridge targets BRTx and BRTy described above, respectively, and ENCTx and ENCTy represent the first and second PWC target enclosures ENCTx and ENCTy described above, respectively.

[0080] According to some example embodiments, the cost function of the ith iteration of OPC, that is, Ci, may be calculated by Mathematical Equation 5. Here, i represents the number of times OPC is performed and is an ordinal number equal to or greater than 0, i=0 means that OPC has not been performed yet.

[0081] [Mathematical equation 5]

[0082]

[0083] In some example embodiments, the i-th cost function, ie, Ci, may be calculated by mathematical equation 6.

[0084] [Mathematical equation 6]

[0085]

[0086] In mathematical equations 5 and 6, f is an ordinal number used to indicate a partial pattern in a mark. According to some example embodiments, a cost function may be calculated separately for each mark MRK. As described above, the LEV risk pattern 110R may be divided into partial patterns during OPC, and each partial pattern of the LEV risk pattern 110R may be modified differently according to the OPC considering LEV. Therefore, the cost function corresponding to each mark MRK, that is, Ci, is defined as being proportional to the difference between the PWC contour distance PCD and the bridge target distance BTD of each partial pattern, and proportional to the difference between the optimal contour shell BCE and the shell target distance ETD of each partial pattern.

[0087] Next, in operation P160, the cost function of the i-th iteration may be compared with the cost function of the i-1-th iteration. According to some example embodiments, the comparison between the cost functions may be performed separately for each marker MRK.

[0088] When the cost function of the i-th iteration is reduced from the cost function of the i-1-th iteration ("Yes"), returning to operation P140, the mark MRK corresponding thereto may be subjected to iteration of OPC considering LEV.

[0089] When the cost function of the i-th iteration increases from the cost function of the i-1-th iteration ("No"), the corresponding marker MRK can take the result of the i-1-th OPC considering LEV as the final result. Therefore, the OPC considering LEV can be iterated only for some marker MRKs in which the cost function is reduced. In this case, when the iteration of the OPC continues, the corresponding marker MRK can maintain the shape obtained as the result of the i-1-th OPC considering LEV.

[0090] Referring to mathematical equations 5 and 6, as the difference between the optimal contour shell BCE and the shell target distance ETD decreases, the value of the cost function increases. As described above, because the bridge target distance BTD is a reference value that does not allow a bridge failure to occur, the final OPC result can ensure that the shell is maximized as long as no bridge occurs, thereby reducing the risk of poor contact due to LEV. The "poor contact" condition between conductive elements (or patterns) can be defined based on one or more reference electrical characteristics.

[0091] Figure 7 is a flow chart illustrating an OPC method according to some example embodiments.

[0092] For convenience, references will be omitted Figure 2 A repeated description is given, and different points will be mainly described.

[0093] refer to Figure 7, in operation P160, the cost functions of the marking MRK before and after the OPC of the i-th considered LEV may be compared with each other.

[0094] When the value of the cost function decreases in operation P160, the result of the i-th OPC considering LEV can be applied in operation P170, and when the value of the cost function increases in operation P160, the result of the i-1-th OPC considering LEV can be maintained in operation P180 without reflecting the result of the i-th OPC considering LEV.

[0095] With reference Figure 2 Unlike the description of , in operation P190 after operation P170 or P180, it can be checked whether the OPC is the last OPC. The number of iterations of the OPC can be set before executing the OPC, and the OPC can be terminated when the set number of iterations of the OPC is completed. Because the OPC considering the LEV can be terminated according to the change in the value of the cost function before the set number of iterations of the OPC is completed, the number of iterations of the OPC considering the LEV for some marked MRKs can be less than the number of iterations of the entire OPC.

[0096] Figure 8 is a flow chart illustrating an OPC method according to some example embodiments.

[0097] For convenience, references will be omitted Figure 2 A repeated description is given, and different points will be mainly described.

[0098] refer to Figure 8 , Figure 8 The operation of P210 to P240 can be respectively with reference to Figure 2 The described operations P110 to P140 are the same or substantially similar.

[0099] Next, in operation P250 , first and second cost functions may be calculated.

[0100] According to some example embodiments, according to the result of the i-th OPC iteration, the first and second cost functions, that is, C1i and C2i, may be calculated by Mathematical Equation 7.

[0101] [Mathematical equation 7]

[0102]

[0103]

[0104] Therefore, the first cost function can be proportional to the difference between the bridge target pattern BRTP (which is associated with the bridge target distance BTD) and the PWC contour PCC (which is associated with the PWC contour distance PCD), and the second cost function can be proportional to the difference between the shell target pattern ENCTP (which is associated with the shell target distance ETD) and the OPC optimal contour LAOBC (which is associated with the optimal contour shell BCE) that has been modified to take into account LEV.

[0105] In some example embodiments, the first and second cost functions C1i and C2i according to the i-th OPC iteration result may be calculated by Mathematical Equation 8.

[0106] [Mathematical equation 8]

[0107]

[0108]

[0109] Next, in operation P260, the value of the first cost function according to the result of the i-th OPC iteration may be compared with the value of the first cost function according to the result of the i-1-th OPC iteration. According to some example embodiments, when the value of the first cost function according to the result of the i-th OPC iteration decreases from the value of the first cost function according to the result of the i-1-th OPC iteration ("Yes"), comparison of the second cost function may be performed in operation P270. On the other hand, when the value of the first cost function according to the result of the i-th OPC iteration increases from the value of the first cost function according to the result of the i-1-th OPC iteration ("No"), the iteration of the OPC considering the LEV may be terminated.

[0110] refer to Figure 4 , the first cost function is proportional to the difference between the bridging target pattern BRTP and the PWC profile PCC (e.g., the difference between the PWC profile distance and the PWC target distance). For example, before performing the OPC considering LEV, the PWC profile distance may be greater than the PWC target distance. As the OPC considering LEV is repeatedly performed, the difference between the PWC profile distance and the PWC target distance decreases because the PWC profile PCC is closer to the bridging target pattern BRTP, and thus the value of the first cost function also decreases. Here, the increase in the value of the first cost function caused by the OPC iteration considering LEV means that the PWC profile PCC is greater than the bridging target pattern BRTP. The bridging target pattern BRTP is a target shape for mitigating or preventing bridging failures, and the PWC profile PCC being greater than the bridging target pattern BRTP may mean that the risk of generating a bridging failure is high.

[0111] Therefore, when the first cost function increases by a specific OPC considering LEV, the OPC considering LEV can be terminated. Here, the comparison of the first cost function can be performed separately for each marker MRK. For example, when the value of the first cost function is increased by the OPC considering LEV for some of the multiple markers MRK, the OPC considering LEV can be terminated only for the marker MRK whose value of the first cost function is increased.

[0112] Next, in operation P270, the value of the second cost function according to the result of the i-th OPC iteration may be compared with the value of the second cost function according to the result of the i-1-th OPC iteration. According to some example embodiments, when the value of the second cost function according to the result of the i-th OPC iteration decreases from the value of the second cost function according to the result of the i-1-th OPC iteration ("Yes"), return to operation P240, and the OPC considering LEV may be iterated. On the other hand, when the value of the second cost function according to the result of the i-th OPC iteration increases from the value of the second cost function according to the result of the i-1-th OPC iteration ("No"), the iteration of the OPC considering LEV for the corresponding marker MRK may be terminated.

[0113] As described above, minimizing the second cost function means ensuring that the housing is maximized. Therefore, the risk of poor contact caused by LEV can be reduced. In some cases, in operation P270, the sum of the first cost function and the second cost function of the OPC based on the i-th considered LEV can be compared with the sum of the first cost function and the second cost function of the OPC based on the i-1-th considered LEV.

[0114] Fig. 9 is a flowchart illustrating processes of a method of manufacturing a semiconductor device according to some example embodiments.

[0115] refer to Fig. 9 In operation P1010, a design layout for forming a semiconductor device may be provided. Operation P1010 may be similar to that of reference Figure 2 The described operation P110 is the same or substantially similar.

[0116] Next, refer to Figure 3 and Figure 8 In operation P1020, OPC may be performed on the design layout. The performing of OPC may include performing first and second OPCs that are different from each other.

[0117] According to some example embodiments, a first OPC may be performed on a pattern in the mark MRK. According to some example embodiments, the first OPC may be a reference Figures 2 to 6 Described in consideration of LEV OPC, reference Figure 7Describes the considerations of LEV OPC and reference Figure 8 One of the OPCs described takes LEV into consideration. The second OPC may be an OPC for an area other than the mark MRK.

[0118] According to some example embodiments, the execution of OPC may be iterated multiple times. During the iterative process, the first OPC of some or all of the marking MRKs may be terminated first, as shown in FIG. Figure 2 , Figure 6 and Figure 7 Therefore, the number of iterations of the second OPC may be equal to or greater than the number of iterations of the first OPC.

[0119] Next, in operation P1030, mask tape-out (MTO) design data may be input. The acronym "MTO" may mean that design data (according to which OPC is completed) is transmitted to request the manufacture of a mask. According to some example embodiments, the MTO design data may have a graphic data format used in electronic design automation (EDA) software, etc. According to some example embodiments, the MTO design data may have a data format such as GDS2, CIF, OASIS, etc.

[0120] Next, in operation P1040, mask data preparation (MDP) may be performed. According to some example embodiments, for example, the MDP may include format conversion known as fracturing, enhancement of barcodes for mechanical reading, standard mask patterns for inspection, job-decks, and / or automatic and manual verification. According to some example embodiments, a job-deck may refer to a text file that produces a series of instructions including layout information, exposure speeds or methods, etc. for multiple mask files. In order to mitigate or prevent failures due to tolerances by ensuring sufficient margins in the semiconductor manufacturing process, the MDP may include a mask rule check, in which it is checked whether the modified design layout complies with mask generation rules, including restrictions on specific geometries and connections.

[0121] According to some example embodiments, format conversion, that is, fracturing may refer to a process of dividing MTO design data by region and then changing the MTO design data into a format for an electron beam writer. According to some example embodiments, fracturing may be a process actively performed to improve the quality of the final mask and correct the mask process. Fracturing may include, for example, data manipulation (e.g., scaling, resizing of data, rotation of data, pattern reflection, or color inversion).

[0122] According to some example embodiments, in the conversion process by means of fracturing, data on systematic errors that may be generated during the transfer process from design data to an image on a semiconductor substrate may be corrected. For example, the systematic errors may be generated by distortions that occur in processes such as mask development and etching, semiconductor substrate imaging, etc.

[0123] According to some example embodiments, the MDP may include a mask process correction (MPC), which is a data correction process regarding a systematic error. According to some example embodiments, the MPC may include operations such as adjusting a critical dimension and / or improving pattern placement accuracy.

[0124] Next, in operation P1050, the substrate for the mask may be exposed based on the mask data. According to some example embodiments, the exposure may be performed by, for example, electron beam writing. According to some example embodiments, the electron beam writing may be performed using a multi-beam mask writer (MBMW) in a manner such as gray writing. According to some example embodiments, the electron beam writing may be performed by using a deformable wave beam (VSB) writer.

[0125] According to some example embodiments, data processing may be performed before the exposure process. According to some example embodiments, data processing is a preprocessing process for mask data, and may include syntax checking of mask data, exposure time prediction, and the like. According to some example embodiments, after MDP, before the exposure process, a process of converting mask data into pixel data may be performed. Pixel data may be data directly used for actual exposure, and may include data on a shape that is an exposure object and data on a dose assigned to each shape. According to some example embodiments, data on a shape that is an exposure object may be bitmap data converted from shape data by rasterization, etc., and the shape data is vector data.

[0126] Next, a photolithography mask may be formed by performing a subsequent process. According to some example embodiments, the subsequent process may include processes such as development, etching, and cleaning. According to some example embodiments, the subsequent process for forming the photolithography mask may include a measurement process and a defect inspection or repair process. According to some example embodiments, the subsequent process for forming the photolithography mask may include a pellicle coating process. The pellicle coating process may refer to a process in which it is confirmed that there are no contaminating particles or chemical stains on the surface of the photolithography mask, and then a pellicle is attached to the surface of the photolithography mask to protect the photolithography mask from contamination, impact, etc. during transportation and the usable life of the photolithography mask.

[0127] Next, in operation P1060, various semiconductor processes may be performed on the semiconductor substrate using a photolithography mask to form a semiconductor chip. According to some example embodiments, the process using the photolithography mask may include a patterning process using a photolithography exposure process, etc. According to some example embodiments, a desired pattern may be formed on a semiconductor substrate or a material layer by a process using a photolithography mask.

[0128] According to some example embodiments, the process using the photolithography mask may include a deposition process, an etching process, an ion process, a cleaning process, and the like. According to some example embodiments, the deposition process may include a process of depositing a material layer, such as chemical vapor deposition, atomic layer deposition, sputtering, or spin coating. According to some example embodiments, the ion process may include a process such as ion implantation, diffusion, or heat treatment. According to some example embodiments, the process using the photolithography mask may include a packaging process, in which a semiconductor chip is mounted on a printed circuit board (PCB) and then sealed with a sealant. According to some example embodiments, the process using the photolithography mask may include a testing process, in which a test is performed on a semiconductor chip or a package.

[0129] Although the present invention has been specifically shown and described with reference to some example embodiments of the present invention, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the following claims. In addition, it should be understood that the specific terms used herein are only used for the purpose of describing the disclosed example embodiments and are not intended to limit the present invention. Therefore, the scope of the present invention should be limited by the appended claims and their equivalents.

[0130] This application claims the benefit of Korean Patent Application No. 10-2018-0125405 filed on October 19, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An optical proximity correction method, comprising: providing a design layout including a conductive pattern; determining line end gap risk patterns among the conductive patterns, the line end gap risk patterns all having a risk of suffering from poor contact due to line end gaps; providing a mark, the mark comprising a portion of the line end void risk pattern and a portion of the conductive pattern adjacent to the line end void risk pattern; performing optical proximity correction considering line end gaps on the line end gap risk pattern; and At least one cost function is calculated for each of the marks, the cost function being proportional to the difference between the process window condition contour distance and the bridge target distance, and being proportional to the difference between the optimal contour shell and the shell target distance for optical proximity correction considering line end gaps, wherein the optical proximity correction considering line end gaps takes a bridge target pattern as a target shape, the bridge target pattern being determined by a bridge target, and the bridge target being the minimum distance between the conductive patterns.

2. The optical proximity correction method according to claim 1, wherein the optical proximity correction taking into account line-end gaps takes a shell target pattern as a target shape, the shell target pattern being determined by a first shell target and a second shell target, the first shell target being a first minimum distance between an upper conductive path or a lower conductive path adjacent to each of the line-end gap risk patterns and an end point of each of the line-end gap risk patterns in one direction, and the second shell target being a second minimum distance between the upper conductive path or the lower conductive path adjacent to each of the line-end gap risk patterns and an adjacent one of the conductive patterns in another direction different from the one direction.

3. The optical proximity correction method according to claim 2, wherein: The calculation includes calculating an optimal profile for optical proximity correction considering line end voids and a process window condition profile, wherein the optimal profile for optical proximity correction considering line end voids is a first profile based on the optimal conditions for each of the modified line end void risk patterns, and the process window condition profile is a second profile based on the process window conditions.

4. The optical proximity correction method according to claim 3, wherein The at least one cost function includes a first cost function and a second cost function, and The first cost function is proportional to a difference between a bridge target pattern and the process window condition profile.

5. The optical proximity correction method according to claim 4, further comprising: In response to a current value of the first cost function being greater than an immediately previous value of the first cost function, the optical proximity correction considering line end gaps is terminated.

6. The optical proximity correction method according to claim 4, wherein: The second cost function is proportional to a difference between the shell target pattern and the optical proximity corrected optimal profile that has been modified to account for line end gaps.

7. The optical proximity correction method according to claim 6, wherein: In response to a current value of the second cost function being less than an immediately previous value of the second cost function, performing the optical proximity correction taking into account line end gaps is iterated.

8. The optical proximity correction method according to claim 1, wherein The determining includes comparing the risk of bad contact occurring in each of the conductive patterns based on a scoring function, and The scoring function is inversely proportional to the width of each of the conductive patterns. 9 . The optical proximity correction method according to claim 8 , wherein the score function is inversely proportional to a distance between an end of each of the conductive patterns and a via contacting each of the conductive patterns in an extending direction of each of the conductive patterns.

10. An optical proximity correction method, comprising: providing a design layout including a conductive pattern; determining line end gap risk patterns among the conductive patterns, the line end gap risk patterns all having a risk of suffering from poor contact due to line end gaps; providing a mark, the mark comprising a portion of the line end gap risk pattern and a portion of the conductive pattern adjacent to the line end gap risk pattern; performing a first optical proximity correction on a pattern within the mark and performing a second optical proximity correction on a pattern outside the mark, the second optical proximity correction being different from the first optical proximity correction, and each of the first optical proximity correction and the second optical proximity correction being performed a plurality of times; and calculating a cost function for each of the marks, the cost function being proportional to the difference between the process window condition profile distance and the bridge target distance, and being proportional to the difference between the optical proximity corrected optimal profile shell and the shell target distance taking into account line end gaps, wherein the determining comprises comparing the risk of bad contact occurring in each of the conductive patterns based on a scoring function, and The scoring function is inversely proportional to the width of each of the conductive patterns. 11 . The optical proximity correction method according to claim 10 , wherein the score function is inversely proportional to a distance between an end of each of the conductive patterns and a via contacting each of the conductive patterns. 12 . The optical proximity correction method of claim 10 , wherein a first iteration number of the first optical proximity correction is equal to or less than a second iteration number of the second optical proximity correction.

13. The optical proximity correction method according to claim 10, further comprising: In response to a current value of the cost function for one or more of the marks being greater than an immediately previous value of the cost function thereof, terminating the first optical proximity correction for the one or more of the marks.

14. A method for manufacturing a photolithography mask, the method comprising: providing a design layout including a conductive pattern; performing optical proximity correction on the design layout; and manufacturing the photolithography mask according to the result of the execution, Wherein said execution comprises, determining line end void risk patterns among the conductive patterns, each of the line end void risk patterns having a risk of suffering from poor contact due to line end voids, providing a mark, the mark comprising a portion of the line end void risk pattern and a portion of the conductive pattern adjacent to the line end void risk pattern, performing a first optical proximity correction on a pattern within the mark and performing a second optical proximity correction on a pattern outside the mark, the second optical proximity correction being different from the first optical proximity correction, and each of the plurality of cost functions for each of the marks is calculated by using an optical proximity correction optimal profile considering line end voids and a process window condition profile, the optical proximity correction optimal profile considering line end voids being a first profile according to an optimal condition for each of the line end void risk patterns that have been modified by the first optical proximity correction, and the process window condition profile being a second profile according to a process window condition for each of the line end void risk patterns that have been modified by the first optical proximity correction, The cost function is proportional to the difference between the process window condition profile distance and the bridge target distance, and is proportional to the difference between the optical proximity corrected optimal profile shell considering line end gaps and the shell target distance.

15. The method according to claim 14, wherein The first optical proximity correction and the second optical proximity correction are iterated a plurality of times, and A first number of iterations of the second optical proximity correction is equal to or greater than a second number of iterations of the first optical proximity correction.

16. The method of claim 14, wherein the first optical proximity correction uses the following pattern as a target shape: a bridging target pattern determined by a bridging target, the bridging target being a first minimum distance between the conductive patterns; and A shell target pattern determined by a first shell target and a second shell target, wherein the first shell target is a second minimum distance between an upper conductive path or a lower conductive path adjacent to each of the line-end gap risk patterns and an end point of each of the line-end gap risk patterns in one direction, and the second shell target is a third minimum distance between the upper conductive path or the lower conductive path adjacent to each of the line-end gap risk patterns and an adjacent one of the conductive patterns in another direction different from the one direction.

17. The method according to claim 16, wherein The plurality of cost functions include a first cost function and a second cost function, and The first cost function is proportional to a difference between the bridge target pattern and the process window condition profile.

18. The method according to claim 17, further comprising: In response to a current value of the first cost function being greater than an immediately previous value of the first cost function, the first optical proximity correction is terminated.

19. The method of claim 17, wherein the second cost function is proportional to a difference between the optical proximity corrected optimal profile accounting for line end voids and the housing target pattern.

20. The method according to claim 19, further comprising: In response to a current value of the first cost function being less than an immediately previous value of the first cost function, and in response to a current value of the second cost function of some of the marks being greater than an immediately previous value of the second cost function thereof, the first optical proximity correction is terminated, and the shape of the conductive pattern is maintained in the some of the marks.

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