Device, method, and system for enhancing channel stress in an NMOS transistor

Abstract

Techniques and mechanisms for applying stress on the channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source regions or drain regions of a transistor, wherein the channel region of the transistor is located between the source region or the drain region. At least such source region or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound cause at least one source region or drain region to apply tensile stress on the channel region. In another embodiment, both the source region or the drain region of the transistor include a SiGe compound containing at least 50 wt% germanium.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to semiconductor technology, and more specifically but not exclusively to strained transistors. Background Art

[0002] In semiconductor processing, transistors are typically formed on a semiconductor wafer. In CMOS (Complementary Metal Oxide Semiconductor) technology, transistors generally belong to one of two types: NMOS (Negative-channel Metal Oxide Semiconductor) or PMOS (Positive-channel Metal Oxide Semiconductor) transistors. Transistors and other devices can be interconnected to form an integrated circuit (IC) that performs many useful functions.

[0003] The operation of such an IC depends at least in part on the performance of the transistors, which in turn can be improved by applying stress in the channel region. Specifically, the performance of NMOS transistors is improved by providing tensile stress in the channel region of the NMOS transistors, and the performance of PMOS transistors is improved by providing compressive stress in the channel region of the PMOS transistors.

[0004] A FinFET is a transistor built around a thin strip of semiconductor material, typically referred to as a fin. The transistor includes standard field effect transistor (FET) nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of such a device exists on the outer sides of the fin under the gate dielectric. Specifically, current flows along the two sidewalls (the sides perpendicular to the substrate surface) of the fin / within the two sidewalls of the fin and along the top (the side parallel to the substrate surface) of the fin. Since the conductive channel of this configuration substantially exists along three different outer planar regions of the fin, this FinFET design is sometimes referred to as a triple-gate FinFET. Other types of FinFET configurations are also available, such as the so-called double-gate FinFET, where the conductive channel mainly exists only along the two sidewalls of the fin (and not along the top of the fin). There are many non-trivial problems associated with manufacturing such fin-based transistors. Brief Description of the Drawings

[0005] Various embodiments of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, and in the drawings:

[0006] Figure 1 Various views are shown that illustrate elements of an integrated circuit for enhancing transistor stress according to an embodiment.

[0007] Figure 2 is a flowchart showing elements of a method for enhancing stress in a channel of a transistor according to an embodiment.

[0008] Figure 3A andFigure 3B Cross-sectional views are shown that each show a structure at a corresponding stage of a semiconductor manufacturing process according to an embodiment.

[0009] Figure 4 is a functional block diagram showing a computing device according to one embodiment.

[0010] Figure 5 is a functional block diagram showing an exemplary computer system according to one embodiment. DETAILED DESCRIPTION

[0011] In various embodiments, apparatuses and methods related to stress transistors are described. Briefly, some embodiments enhance the performance of one or more NMOS transistors by boosting channel stress in various ways. However, various embodiments may be practiced without one or more of the specific details, or with other methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of some embodiments. However, some embodiments may be practiced without the specific details. Additionally, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0012] The techniques described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the techniques described herein include any kind of mobile device and / or fixed device, such as a camera, cellular phone, computer terminal, desktop computer, electronic reader, fax machine, kiosk, laptop computer, netbook computer, notebook computer, Internet appliance, payment terminal, personal digital assistant, media player and / or recorder, server (e.g., blade server, rack-mounted server, combinations thereof, etc.), set-top box, smart phone, tablet personal computer, ultra-mobile personal computer, landline telephone, combinations thereof, etc. More generally, embodiments may be employed in any of a variety of electronic devices that include one or more transistors including structures formed according to the techniques described herein.

[0013] Figure 1 An integrated circuit (IC) device 100 including a structure for applying stress on an NMOS transistor is shown in a perspective view according to an embodiment. Figure 1 A cross-sectional perspective view 102 and a top plan view 104 of the IC device 100 are also shown.

[0014] IC device 100 is an example of an embodiment in which an NMOS transistor includes a source region or a drain region that includes a doped silicon germanium (SiGe) compound. Such an NMOS transistor may include a doped source region or drain region of a fin structure, and a gate structure extending over the fin structure, for example, which includes a gate dielectric and a gate electrode. The fin structure may be formed from a first semiconductor body disposed on a second semiconductor body (referred to herein as a "buffer layer") that facilitates the application of tensile stress on the NMOS transistor. For at least one source region or drain region of the NMOS transistor, dislocations in the source region or drain region may cause tensile stress to be applied on an adjacent channel region of the NMOS transistor.

[0015] In the illustrated exemplary embodiment, IC device 100 includes a buffer layer 110 having a side surface 112. Buffer layer 110 may include one or more epitaxial single crystal semiconductor layers (e.g., silicon, germanium, silicon germanium, gallium arsenide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, etc.), for example, which may be grown on top of different bulk semiconductor substrates (e.g., the illustrated illustrative silicon substrate 140).

[0016] Although some embodiments are not limited in this regard, buffer layer 110 may include various epitaxially grown semiconductor sublayers having different lattice constants. Such semiconductor sublayers may be used to grade the lattice constant along the z-axis of the illustrated xyz coordinate system. For example, the germanium concentration of SiGe buffer layer 110 may increase from 30% germanium in the bottommost buffer layer to 70% germanium in the topmost buffer layer, thereby gradually increasing the lattice constant.

[0017] IC device 100 may also include a first semiconductor body on buffer layer 110 that forms a fin structure (e.g., the illustrated illustrative fin structure 120). For example, the first semiconductor body may be formed in part from an epitaxially grown single crystal semiconductor, such as but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In some embodiments, fin structure 120 may extend to side surface 112. In other embodiments, the first semiconductor body may also include a underlying sublayer portion from which fin structure 120 extends (e.g., where the underlying sublayer portion is disposed between side surface 112 and fin structure 120 and is adjacent to each of side surface 112 and fin structure 120).

[0018] As used herein, a "source region or drain region" (or alternatively, a "source / drain region") refers to a structure configured to serve as either a source of a transistor or a drain of a transistor. The doped portions of the fin structure 120 can provide the source and the drain of the NMOS transistor (e.g., the illustrative source / drain regions 124, 126 as shown). The channel region of the NMOS transistor can be disposed between the source / drain regions 124, 126, where the gate dielectric 132 and the gate electrode 130 extend differently over a portion of the fin structure 120 including the channel region. For example, the source / drain regions 124, 126 can extend under the laterally opposite sides of the gate electrode 130.

[0019] The source / drain regions 124, 126 and the channel region can be configured to conduct current during operation of the IC device 100 - for example, current controlled using the gate electrode 130. For example, the source / drain regions 124, 126 can be disposed in source / drain wells formed by the fin structure 120. One or both of the source / drain regions 124, 126 can include a SiGe compound - for example, where other portions of the fin structure 120 have a compound different from the SiGe compound. The source / drain regions 124, 126 can include any of a variety of suitable n-type dopants, such as one of phosphorus or arsenic.

[0020] The structure of the buffer layer 110 and / or the structure of the fin structure 120 can be at least partially electrically isolated from other circuit structures of the IC device 100 by the insulating structure 114 (e.g.). The insulating structure 114 can include silicon dioxide or any of a variety of other dielectric materials adjusted according to conventional isolation techniques. In other embodiments, the size, shape, number, and relative configuration of the insulating structure 114 are merely exemplary, and the IC device 100 can include any of a variety of additional or alternative insulating structures.

[0021] The gate dielectric 132 can include a high-k gate dielectric, such as hafnium oxide. In various other embodiments, the gate dielectric 132 can include hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, or lead zinc niobate. In another embodiment, the gate dielectric 132 includes silicon dioxide.

[0022] The gate electrode 130 can be formed of any suitable gate electrode material. In an embodiment, the gate electrode 130 includes doped polysilicon. Alternatively or additionally, the gate electrode 130 can include a metal material such as, but not limited to, tungsten, tantalum, titanium, and their nitrides. It should be understood that the gate electrode 130 does not necessarily have to be a single material and can be a composite stack of thin films such as, but not limited to, polysilicon / metal electrodes or metal / polysilicon electrodes.

[0023] Dielectric sidewall spacers 150, 160 can be formed at opposite sidewalls of the gate electrode 130 - for example, where the spacers 150, 160 include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The respective thicknesses of the sidewall spacers 150, 160 can facilitate the isolation of the gate electrode 130 during the process of forming the source / drain regions 124, 126.

[0024] Although some embodiments are not limited in this regard, the NMOS transistor can include multiple different channel regions, each channel region being between the source / drain regions 124, 126 - for example, the multiple channel regions include one or more nanowire structures. Such one or more nanowires can be formed of, for example, any of a variety of suitable materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, and carbon nanotubes.

[0025] In an embodiment, the first semiconductor body forming the fin structure 120 can have a crystal structure other than the crystal structure of the adjacent buffer layer 110. The mismatch (e.g., lattice constant mismatch) between the fin structure 120 and the side 112 can cause tensile stress to be applied in the channel region between the source / drain regions 124, 126. For example, the lattice constant of the side 112 can be different from the lattice constant of the fin structure 120. In one such embodiment, one of the side 112 and the fin structure 120 includes silicon germanium having a first silicon germanium composition ratio, where the other of the side 112 and the fin structure 120 includes pure silicon or silicon germanium having a second silicon germanium composition ratio other than the first silicon germanium composition ratio. However, in different embodiments, any of various other lattice mismatches can be provided between the 110 and the fin structure 120.

[0026] To facilitate the application of tensile stress, a corresponding dislocation can be formed in one of the two source-drain regions 124, 126. For example, the source-drain region 124 can include a dislocation 154 and / or the source-drain region 126 can include a dislocation 164. Some embodiments are based on the inventors' recognition that SiGe compounds conventionally used to provide compressive stress in PMOS transistors can alternatively apply tensile stress, which also includes dislocations.

[0027] In the accompanying drawings of the present disclosure, dislocations (e.g., dislocations 154, 164) of some embodiments are represented in various ways by thick lines, as in views 102, 104. However, such lines are merely symbolic and do not necessarily limit the number, size, direction, and / or shape of the dislocations in the source-drain regions. For example, dislocation 154 and / or dislocation 164 may each extend differently along the corresponding direction in any of the y-axis direction, the x-axis direction, or various other directions. In some embodiments, multiple dislocations within a single source-drain region may extend differently along different corresponding directions. Alternatively or additionally, a given dislocation may form one or more angled regions (e.g., where such a dislocation follows a zigzag path within the source-drain region). In some embodiments, one or more dislocations may each appear as point dislocations in a given cross-sectional plane.

[0028] Figure 2 Features of a method 200 for providing stress on a structure of a transistor according to an embodiment are shown. Method 200 may include, for example, processes for fabricating some or all of the structures of IC device 100. To illustrate certain features of various embodiments, method 200 is described herein with reference to Figure 3A 、 Figure 3B the structures shown therein. However, in different embodiments, any of various additional or alternative structures may be fabricated according to method 200.

[0029] Method 200 may include: at 210, forming a fin structure on a buffer layer, and at 220, forming a gate structure of an NMOS transistor, wherein the gate structure extends over the fin structure. For example, now referring to Figure 3A 、 Figure 3B cross-sectional side views of corresponding stages 300 - 305 of a process for fabricating a transistor structure according to an embodiment are shown. Figure 3A 、 Figure 3BCross-sectional end views 300a - 305a corresponding to stages 300 - 305 are also shown respectively. As shown in stage 300, the fin structure 320 can be disposed directly or indirectly on the buffer layer 315 - for example, where the fin structure 320 and the buffer layer 315 functionally correspond to the fin structure 120 and the buffer layer 110 respectively. The gate dielectric 332 and the gate electrode 330 can be selectively formed in sequence, and both the gate dielectric 332 and the gate electrode 330 extend at least partially around the fin structure 320. The fin structure 320, the gate dielectric 332, the gate electrode 330, and / or other structures can be formed, for example, using operations adjusted according to conventional semiconductor manufacturing techniques during stages 300 - 305 - such techniques include, for example, masking, lithography, deposition (e.g., chemical vapor deposition), etching, and / or other processes. Some of these conventional techniques are not described in detail herein to avoid obscuring certain features of the various embodiments.

[0030] As shown in stage 301, one or more spacer portions (e.g., the illustrative spacer portions 350, 352 shown) can be formed - for example, each spacer portion is formed at a respective one of two opposite sidewalls of the gate electrode 330. The spacers 350, 352 can be formed by conformally depositing a dielectric film of uniform thickness, such as, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The dielectric material of the spacers 350, 352 can be deposited in a conformal manner such that the dielectric film forms at a substantially equal height on vertical surfaces such as the sidewalls of the gate electrode 330. In one exemplary embodiment, the dielectric film is a silicon nitride film formed by a hot-wall low-pressure chemical vapor deposition (LPCVD) process. The deposition thickness of the dielectric film can determine the width or thickness of the formed spacers 350, 352. In an embodiment, the thickness of one of the spacer portions 350, 352 can facilitate the isolation of the gate electrode 330 during subsequent processes to form one or more doped source / drain regions. For example, such a dielectric film can be formed to a thickness (x-axis dimension) in the range of 4 to 15 nm - for example, where the thickness is in the range of 4 nm to 8 nm.

[0031] In an embodiment, method 200 further includes: at 230, forming a source / drain region of an NMOS transistor in the fin structure, the source / drain region including silicon germanium (SiGe). Method 200 can also include: at 240, forming a channel region of the NMOS transistor in the fin structure, wherein tensile stress is applied to the channel region using dislocations in the buffer layer and the SiGe of the source / drain region.

[0032] After forming spacer portions 350, 352, one or more recessed structures can be etched or otherwise formed in fin structure 320. For example, as shown in stage 302, wet etching and / or other subtractive processes can be performed—e.g., through a patterned mask (not shown)—to remove portions of fin structure 320, thereby forming one or both of the illustrative recesses 322 shown. One or each of recesses 322 can allow subsequent deposition of SiGe material therein, which will provide at least part of the source / drain regions.

[0033] For example, as shown in stage 303, at 230 of method 200, a SiGe compound can be epitaxially grown—e.g., by chemical vapor deposition (CVD) or other such additive processes—to form one or both of the illustrative SiGe bodies 324, 326 shown. The SiGe compound can include dopants during its deposition, or alternatively, the SiGe compound can be subsequently doped using ion implantation, plasma implantation, or other such doping processes after forming SiGe bodies 324, 326.

[0034] During and / or after epitaxial growth and / or its doping, dislocations can be formed in SiGe bodies 324, 326. For example, as shown in stage 304, dislocation 354 can be formed in SiGe body 324 and / or dislocation 364 can be formed in SiGe body 326. The total number of dislocations 354 (and / or the total number of dislocations 364) can be at least partially attributed to the relatively high composition ratio of germanium in SiGe bodies 324, 326. For example, one or each of SiGe bodies 324, 326 can include at least 50 wt% germanium, and in some embodiments, can include 60 wt% or more germanium.

[0035] The total number of dislocations 354 can cause SiGe body 324 to exert tensile stress on the channel region between SiGe bodies 324, 326—e.g., rather than compressive stress. Alternatively or additionally, the total number of dislocations 364 can similarly cause SiGe body 326 to exert tensile stress on such channel region. In one exemplary embodiment, the gate structure of the transistor (e.g., including one or both of gate electrode 330 and gate dielectric 332) can extend across the length (x-axis dimension) of fin structure 320. In such an embodiment, the extent of the source / drain regions along the length of fin structure 320 can be between 5 nanometers (nm) and 100 nm, where the total number of dislocations in the SiGe of the source / drain regions is at least 4—e.g., in the range of 4 to 10 (including the end values). However, the source / drain regions can exert tensile stress due to more or fewer dislocations—e.g., depending on the size and composition of the source / drain regions.

[0036] In some embodiments, method 200 may further include forming a doped silicon capping layer on the source / drain regions. For example, as shown in stage 305, doped silicon capping layers 360, 362 may be formed over SiGe bodies 324, 326, respectively. Without such a silicon capping layer, the transistor may otherwise have a high Schottky contact resistance, which may, for example, affect the overall device current and switching performance. In some embodiments, one or more insulating structures (not shown) may be formed during or after stages 300 - 305 - for example, including insulating structure 114.

[0037] Similar to the transistor formed by the processes shown in stages 300 - 305, multiple transistors of an IC device (e.g., an IC die) may be fabricated according to method 200. For example, method 200 may further include forming the structure of a second NMOS transistor (e.g., a second source / drain region and a second channel region) in a fin structure. In such an embodiment, the second NMOS transistor may have one or more of the stress - inducing features described herein - for example, where the second source / drain region similarly includes a SiGe compound that applies a tensile stress on the adjacent second channel region. Alternatively or additionally, method 200 may further include forming a second fin structure on a buffer layer, and forming the structure of another NMOS transistor (e.g., another source / drain region and another channel region) in the second fin structure. In such an embodiment, the another NMOS transistor may have one or more of the stress - inducing features described herein - for example, where the another source / drain region similarly includes a SiGe compound that applies a compressive stress on the adjacent channel region.

[0038] Figure 4 A computing device 400 is shown in accordance with one embodiment. The computing device 400 houses a board 402. The board 402 may include multiple components, including but not limited to a processor 404 and at least one communication chip 406. The processor 404 is physically and electrically coupled to the board 402. In some implementations, at least one communication chip 406 is also physically and electrically coupled to the board 402. In other implementations, the communication chip 406 is part of the processor 404.

[0039] Depending on its application, computing device 400 may include other components that may or may not be physically and electrically coupled to board 402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, crypto-processors, chip sets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0040] Communication chip 406 implements wireless communication for transmitting data to and from computing device 400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data by using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not. Communication chip 406 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and higher. Computing device 400 may include multiple communication chips 406. For example, a first communication chip 406 may be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 406 may be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0041] Processor 404 of computing device 400 includes an integrated circuit die encapsulated within processor 404. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. Communication chip 406 also includes an integrated circuit die encapsulated within communication chip 406.

[0042] In various embodiments, computing device 400 can be a laptop computer, netbook, notebook, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other embodiments, computing device 400 can be any other electronic device that processes data.

[0043] Some embodiments may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform a process according to the embodiments. The machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, the machine-readable (e.g., computer-readable) medium includes machine (e.g., computer) readable storage media (e.g., read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash device, etc.), machine (e.g., computer) readable transmission media (electrical, optical, acoustic, or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

[0044] Figure 5 A schematic representation of a machine in an exemplary form of a computer system 500 is shown, in which a set of instructions can be executed to cause the machine to perform any one or more of the methods described herein. In alternative embodiments, the machine can be connected (e.g., network-connected) to other machines in a local area network (LAN), intranet, extranet, or the Internet. The machine can operate as a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by that machine. Further, although only a single machine is shown, the term “machine” shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods described herein.

[0045] The exemplary computer system 500 includes a processor 502, a main memory 504 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and an auxiliary memory 518 (e.g., a data storage device), which communicate with each other via a bus 530.

[0046] The processor 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processor 502 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processor 502 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processor 502 is configured to execute processing logic 526 for performing the operations described herein.

[0047] The computer system 500 may also include a network interface device 508. The computer system 500 may also include a video display unit 510 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 512 (e.g., a keyboard), a cursor control device 514 (e.g., a mouse), and a signal generation device 516 (e.g., a speaker).

[0048] The auxiliary memory 518 may include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 532, on which is stored a set or multiple sets of instructions (e.g., software 522) embodying any one or more of the methods or functions described herein. During execution of the software 522 by the computer system 500, the software 522 may also be present, in whole or at least in part, within the main memory 504 and / or within the processor 502, which also constitute machine-readable storage media. The software 522 may be further transmitted or received via the network interface device 508 over a network 520.

[0049] Although the machine-accessible storage medium 532 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store a set of instructions or multiple sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one of the one or more embodiments. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memories as well as optical and magnetic media.

[0050] In one embodiment, an integrated circuit (IC) device includes a buffer layer and a fin structure disposed on the buffer layer, the fin structure including a source region or a drain region of an NMOS transistor and a channel region of the NMOS transistor, the channel region being adjacent to the source region or the drain region, wherein tensile stress is applied to the channel region by dislocations in the silicon germanium (SiGe) of the buffer layer and the source region or the drain region. The IC device further includes a gate structure of the NMOS transistor, wherein the gate structure extends over the fin structure.

[0051] In an embodiment, the IC device further includes a silicon capping layer disposed on the source region or the drain region. In another embodiment, the gate structure extends across the length of the fin structure, wherein the extent of the source region or the drain region along the length of the fin structure is between 5 nanometers (nm) and 100 nm, and wherein the total number of dislocations in the SiGe of the source region or the drain region is in the range of 4 to 10, including the end values. In another embodiment, the SiGe of the source region or the drain region includes at least 50% germanium. In another embodiment, the SiGe of the source region or the drain region includes at least 60% germanium. In another embodiment, the fin structure further includes a second source region or a second drain region of a second NMOS transistor and a second channel region of the second NMOS transistor, the second channel region being adjacent to the second source region or the second drain region, wherein tensile stress is applied to the second channel region by using a buffer layer and dislocations in the SiGe of the second source region or the second drain region. In another embodiment, the IC device further includes a second fin structure, the second fin structure including a second source region or a second drain region of a second NMOS transistor and a second channel region of the second NMOS transistor, the second channel region being adjacent to the second source region or the second drain region, wherein tensile stress is applied to the second channel region by using a buffer layer and dislocations in the SiGe of the second source region or the second drain region. The IC device further includes a second gate structure of the second NMOS transistor, wherein the second gate structure extends over the fin structure. In another embodiment, the fin structure further includes a third source region or a third drain region of a third NMOS transistor and a third channel region of the third NMOS transistor, the third channel region being adjacent to the third source region or the third drain region, wherein tensile stress is applied to the third channel region by using a buffer layer and dislocations in the SiGe of the third source region or the third drain region.

[0052] In another embodiment, a method includes: forming a fin-like structure including silicon germanium (SiGe) on a buffer layer, and forming a source region or a drain region of an NMOS transistor and a channel region of the NMOS transistor in the fin-like structure, the channel region being adjacent to the source region or the drain region, wherein tensile stress is applied to the channel region by using a buffer layer and dislocations in the silicon germanium (SiGe) of the source region or the drain region. The method further includes forming a gate structure of the NMOS transistor, wherein the gate structure extends over the fin structure.

[0053] In an embodiment, the method further includes forming a silicon capping layer over the source region or the drain region. In another embodiment, the gate structure extends across the length of the fin structure, wherein the extent of the source region or the drain region along the length of the fin structure is between 5 nanometers (nm) and 100 nm, and wherein the total number of dislocations in the SiGe of the source region or the drain region is in the range of 4 to 10, including the end values. In another embodiment, the SiGe of the source region or the drain region includes at least 50% germanium. In another embodiment, the SiGe of the source region or the drain region includes at least 60% germanium. In another embodiment, the method further includes forming a second source region or a second drain region of a second NMOS transistor and a second channel region of the second NMOS transistor in the fin structure, the second channel region being adjacent to the second source region or the second drain region, wherein tensile stress is applied to the second channel region by using the buffer layer and dislocations in the SiGe of the second source region or the second drain region. In another embodiment, the method further includes forming a second fin structure including SiGe over the buffer layer, and forming a second source region or a second drain region of a second NMOS transistor and a second channel region of the second NMOS transistor in the second fin structure, the second channel region being adjacent to the second source region or the second drain region, wherein tensile stress is applied to the second channel region by using the buffer layer and dislocations in the SiGe of the second source region or the second drain region. In another embodiment, the method further includes: forming a third source region or a third drain region of a third NMOS transistor and a third channel region of the third NMOS transistor in the fin-like structure, the third channel region being adjacent to the third source region or the third drain region, wherein tensile stress is applied to the third channel region by using the buffer layer and dislocations in the SiGe of the third source region or the third drain region; and forming a third gate structure of the third NMOS transistor, wherein the third gate structure extends over the fin structure.

[0054] In another embodiment, a system includes an integrated circuit (IC) device including a buffer layer, a fin structure disposed over the buffer layer, the fin structure including a source region or a drain region of an NMOS transistor and a channel region of the NMOS transistor, the channel region being adjacent to the source region or the drain region, wherein tensile stress is applied to the channel region by using the buffer layer and dislocations in the silicon germanium (SiGe) of the source region or the drain region. The IC device further includes a gate structure of the NMOS transistor, wherein the gate structure extends over the fin structure. The system further includes a display device coupled to the IC device, the display device displaying an image based on a signal communicated with the IC device.

[0055] In an embodiment, the IC device further includes a silicon capping layer disposed on the source region or the drain region. In another embodiment, the gate structure extends across the length of the fin structure, wherein the extent of the source region or the drain region along the length of the fin structure is between 5 nanometers (nm) and 100 nm, and wherein the total number of dislocations in the SiGe of the source region or the drain region is in the range of 4 to 10, including the end values. In another embodiment, the SiGe of the source region or the drain region includes at least 50% germanium. In another embodiment, the SiGe of the source region or the drain region includes at least 60% germanium. In another embodiment, the fin structure further includes a second source region or a second drain region of a second NMOS transistor and a second channel region of the second NMOS transistor, the second channel region being adjacent to the second source region or the second drain region, wherein tensile stress is applied to the second channel region by using a buffer layer and dislocations in the SiGe of the second source region or the second drain region. In another embodiment, the IC device further includes a second fin structure, the second fin structure including a second source region or a second drain region of a second NMOS transistor and a second channel region of the second NMOS transistor, the second channel region being adjacent to the second source region or the second drain region, wherein tensile stress is applied to the second channel region by using a buffer layer and dislocations in the SiGe of the second source region or the second drain region. The IC device further includes a second gate structure of the second NMOS transistor, wherein the second gate structure extends over the fin structure. In another embodiment, the fin structure further includes a third source region or a third drain region of a third NMOS transistor and a third channel region of the third NMOS transistor, the third channel region being adjacent to the third source region or the third drain region, wherein tensile stress is applied to the third channel region by using a buffer layer and dislocations in the SiGe of the third source region or the third drain region.

[0056] Techniques and architectures for enhancing stress in transistors are described herein. In the foregoing description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. However, it will be apparent to those skilled in the art that some embodiments may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form to avoid obscuring the description.

[0057] References to "an embodiment" or "embodiments" in the specification refer to the particular features, structures, or characteristics described in connection with the embodiments being included in at least one embodiment of the invention. The phrase "in an embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment.

[0058] Some portions of the detailed embodiments herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing art to most effectively convey the substance of their work to others skilled in the art. Here, an algorithm is usually considered a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. For general reasons mainly, it has sometimes proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0059] However, it should be borne in mind that all such and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless clearly indicated otherwise from the context of the discussion herein, it should be understood that throughout the description, discussions using terms such as "processing" or "estimating" or "calculating" or "determining" or "displaying" refer to the actions and processes of a computer system or similar electronic computing device that transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers or other such information storage, transmission, or display devices of the computer system.

[0060] Certain embodiments also relate to apparatus for performing the operations herein. The apparatus may be specially constructed for the required purposes or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as but not limited to any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM) (such as dynamic RAM (DRAM), EPROM, EEPROM), magnetic or optical cards, or any type of medium suitable for storing electronic instructions and coupled to a computer system bus.

[0061] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The structure required for various such systems will emerge from the description herein. Additionally, certain embodiments are not described with reference to any particular programming language. It should be understood that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

[0062] Except as described herein, various modifications may be made to the disclosed embodiments and their implementations without departing from their scope. Accordingly, the illustrations and examples in this document should be construed in an illustrative rather than a restrictive sense. The scope of the invention should be measured solely by reference to the appended claims.

Claims

1. An integrated circuit (IC) device for transmitting signals, the integrated circuit device comprising: a buffer layer; a fin structure disposed on the buffer layer, the fin structure comprising: a first source or drain region of a first NMOS transistor; a first channel region of the first NMOS transistor, the first channel region being adjacent to the first source or drain region, wherein tensile stress is applied to the first channel region by dislocations in the silicon germanium (SiGe) of the first source or drain region and the buffer layer, wherein the SiGe of the first source or drain region of the first NMOS transistor comprises at least 50% germanium; a second source / drain region of a second NMOS transistor; and a second channel region of the second NMOS transistor, the second channel region being adjacent to the second source / drain region, wherein tensile stress is applied to the second channel region by dislocations in the SiGe of the second source / drain region and the buffer layer; and a gate structure of the first NMOS transistor, wherein the gate structure extends over the fin structure.

2. The integrated circuit device according to claim 1, further comprising a silicon capping layer disposed on the first source or drain region.

3. The integrated circuit device according to claim 1, wherein, the gate structure extends across the length of the fin structure, wherein the extent of the first source or drain region along the length of the fin structure is between 5 nanometers (nm) and 100 nm, and wherein the total number of the dislocations in the SiGe of the first source or drain region is in the range of 4 to 10, including the end values.

4. The integrated circuit device according to claim 1, wherein, the SiGe of the first source or drain region comprises at least 60% germanium.

5. The integrated circuit device according to claim 1, further comprising: a second fin structure, comprising: a third source / drain region of a third NMOS transistor; and a third channel region of the third NMOS transistor, the third channel region being adjacent to the third source / drain region, wherein tensile stress is applied to the third channel region by dislocations in the buffer layer and the SiGe of the third source / drain region; and a third gate structure of the third NMOS transistor, wherein the third gate structure extends over the second fin structure.

6. The integrated circuit device according to claim 1, the fin structure further comprising: a third source / drain region of a third NMOS transistor; and a third channel region of the third NMOS transistor, the third channel region being adjacent to the third source / drain region, wherein tensile stress is applied to the third channel region by dislocations in the buffer layer and the silicon germanium (SiGe) of the third source / drain region.

7. A method for manufacturing an integrated circuit, the method comprising: forming a fin structure comprising silicon germanium (SiGe) on a buffer layer; forming in the fin structure: a first source or drain region of a first NMOS transistor; The first channel region of the first NMOS transistor, the first channel region being adjacent to the first source region or drain region, wherein tensile stress is applied to the first channel region by dislocations in the SiGe of the first source region or drain region and the buffer layer, wherein the silicon germanium of the first source region or drain region of the first NMOS transistor comprises at least 50% germanium; The second source / drain region of the second NMOS transistor; and The second channel region of the second NMOS transistor, the second channel region being adjacent to the second source / drain region, wherein tensile stress is applied to the second channel region by dislocations in the SiGe of the second source / drain region and the buffer layer; and Forming a gate structure of the first NMOS transistor, wherein the gate structure extends over the fin structure.

8. The method according to claim 7, further comprising forming a silicon capping layer on the first source region or drain region.

9. The method according to claim 7, wherein, The gate structure extends across the length of the fin structure, wherein the extent of the first source region or drain region along the length of the fin structure is between 5 nanometers (nm) and 100 nm, and wherein the total number of dislocations in the SiGe of the first source region or drain region is in the range of 4 to 10, inclusive of the end values.

10. The method according to claim 7, wherein, The SiGe of the first source region or drain region comprises at least 60% germanium.

11. The method according to claim 7, further comprising: Forming a second fin structure comprising SiGe on the buffer layer; Forming in the second fin structure: A third source / drain region of a third NMOS transistor; and A third channel region of the third NMOS transistor, the third channel region being adjacent to the third source / drain region, wherein tensile stress is applied to the third channel region by dislocations in the SiGe of the third source / drain region and the buffer layer.

12. The method according to claim 7, further comprising: Forming in the fin structure: A third source / drain region of a third NMOS transistor; and A third channel region of the third NMOS transistor, the third channel region being adjacent to the third source / drain region, wherein tensile stress is applied to the third channel region by dislocations in the SiGe of the third source / drain region and the buffer layer; and Forming a third gate structure of the third NMOS transistor, wherein the third gate structure extends over the fin structure.

13. A system for transmitting signals, the system comprising: An integrated circuit (IC) device, comprising: A buffer layer; A fin structure disposed on the buffer layer, the fin structure comprising: A first source region or drain region of a first NMOS transistor; The first channel region of the first NMOS transistor, the first channel region being adjacent to the first source region or drain region, wherein tensile stress is applied to the first channel region by dislocations in the silicon germanium (SiGe) of the first source region or drain region and the buffer layer, wherein the SiGe of the first source region or drain region of the first NMOS transistor comprises at least 50% germanium; The second source / drain region of the second NMOS transistor; and The second channel region of the second NMOS transistor, the second channel region being adjacent to the second source / drain region, wherein tensile stress is applied to the second channel region by dislocations in the SiGe of the second source / drain region and the buffer layer; and The gate structure of the first NMOS transistor, wherein the gate structure extends over the fin structure; and A display device, coupled to the integrated circuit device, the display device displaying an image based on signals communicated with the integrated circuit device.

14. The system of claim 13, wherein the integrated circuit device further comprises a silicon capping layer disposed on the first source region or drain region.

15. The system of claim 13, wherein, the gate structure extends across the length of the fin structure, wherein the extent of the first source region or drain region along the length of the fin structure is between 5 nanometers (nm) and 100 nm, and wherein the total number of dislocations in the SiGe of the first source region or drain region is in the range of 4 to 10, inclusive of the end values.

16. The system of claim 13, wherein, the SiGe of the first source region or drain region comprises at least 60% germanium.

17. The system of claim 13, the integrated circuit device further comprises: A second fin structure, comprising: The third source / drain region of the third NMOS transistor; and The third channel region of the third NMOS transistor, the third channel region being adjacent to the third source / drain region, wherein tensile stress is applied to the third channel region by dislocations in the SiGe of the third source / drain region and the buffer layer; and The third gate structure of the third NMOS transistor, wherein the third gate structure extends over the second fin structure.

18. The system of claim 13, the fin structure further comprises: The third source / drain region of the third NMOS transistor; and The third channel region of the third NMOS transistor, the third channel region being adjacent to the third source / drain region, wherein tensile stress is applied to the third channel region by dislocations in the SiGe of the third source / drain region and the buffer layer.

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