Mud logging parameter simulator

Abstract

A logging parameter simulator belongs to the technical field of simulators, and in particular, relates to a logging parameter simulator. The present invention provides a logging parameter simulator. The present invention comprises a controller, wherein the signal output port of the controller is respectively connected to a 4-20mA output part, a 0-5V output part, a frequency output part, and a counting output part.

Description

Technical Field

[0001] The invention belongs to the technical field of simulators, and in particular relates to a logging parameter simulator. Background Art

[0002] Mud logging technology is a drilling site service. The main task of mud logging is to extract first-hand and reliable information for oil and gas exploration and development in real time. Mud logging technology is based on the three major technologies of communication network, sensor instrumentation and computer application. It is a high-tech geometric body integrating multiple sciences and technologies. Its obvious information technology characteristics enable it to obtain a large amount of drilling, geological and other parameters and information at the construction site. The transmitted information is timely, diverse, and quickly interpreted and evaluated. Therefore, mud logging technology has become the most basic and necessary technology in the oil and gas exploration and development industry.

[0003] The comprehensive logging instrument collects and analyzes logging data through the cooperation of sensors installed in various places, data acquisition and transmission processing units, and computer technology. At present, the data acquisition and transmission processing unit collects data by connecting physical sensors for debugging. The comprehensive logging instrument measures a large amount of data and needs to collect a variety of signals. Using the above method to test the performance of the comprehensive logging instrument, it is necessary to connect more than 20 physical sensors for testing, which seriously affects the efficiency and is not intelligent enough. Therefore, the demand for a parameter simulator that emits multiple analog quantities, frequency quantities, and counting quantities has greatly increased. Summary of the invention

[0004] The present invention aims at the above problems and provides a logging parameter simulator.

[0005] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme. The present invention includes a controller, characterized in that the signal output port of the controller is respectively connected to the 4-20mA output part, the 0-5V output part, the frequency output part, and the counting output part.

[0006] As a preferred solution, the display signal output port of the controller of the present invention is connected to the display circuit, the alarm signal output port of the controller is connected to the alarm circuit, and the signal input port of the controller is connected to the key input part.

[0007] As another preferred solution, the power port of the controller described in the present invention is connected to the output port of the regulated power supply, the input port of the regulated power supply is connected to the output port of the charging management part, and the charging management part is respectively connected to the lithium battery and the USB port.

[0008] As a preferred solution, the controller of the present invention adopts STMCU_LQFP64 chip U5, pin 5 of U5 is connected to one end of crystal oscillator X3, the other end of X3 is connected to pin 6 of U5, pin 1 of U5 is respectively connected to VBAT / VLCD end, VDD end, one end of capacitor C29, and the other end of C29 is grounded;

[0009] Pin 13 of U5 is connected to the AVDD terminal and one end of inductor L1 respectively. The other end of L1 is connected to the VDD terminal, pin 32 of U5, pin 64 of U5, pin 48 of U5, and pin 19 of U5 respectively. Pin 18 of U5 is grounded. Pin 47 of U5 is grounded through capacitor C22. Pin 63 of U5 is grounded. Pin 31 of U5 is grounded through capacitor C25. Pin 12 of U5 is grounded. Pin 60 of U5 is grounded through resistor R55. Pin 7 of U5 is connected to one end of resistor R54, one end of switch S2, and one end of capacitor C14 respectively. The other end of R54 is connected to the VDD terminal. The other end of S2 and the other end of C14 are grounded.

[0010] As another preferred solution, the charging management part of the present invention adopts bq24195 chip U9, and pin 1 of U9 is respectively connected to one end of capacitor C39, one end of capacitor C38, VBUS end, and pin 24 of U9, and the other end of C39 and the other end of C38 are grounded;

[0011] Pin 2 of U9 is connected to pin 3 of U9 through CB2;

[0012] Pin 4 of U9 is connected to the cathode of LED1 through resistor R50, and the anode of LED1 is connected to the VREG terminal;

[0013] Pin 5 of U9 is connected to VCC3.3 through resistor R48;

[0014] Pin 6 of U9 is connected to VCC3.3 through resistor R49;

[0015] Pin 8 of U9 is connected to one end of resistor R52 and collector of NPN transistor Q7 respectively. The other end of R52 is connected to VSYS. The base of Q7 is connected to one end of resistor R51 and one end of resistor R62 respectively. The other end of R51 is connected to VBUS_IN. The other end of R62 is connected to collector of Q7 and ground respectively.

[0016] Pin 9 of U9 is grounded through resistor R58;

[0017] Pin 10 of U9 is connected to ground through resistor R59;

[0018] The 11th pin of U9 is connected to the 12th pin of U9, one end of the resistor R53, one end of the resistor R60, and one end of the resistor R61 respectively. The other end of R53 is connected to the VREG end. The other ends of R60 and R61 are grounded.

[0019] The 13th pin of U9 is connected to the 14th pin of U9, one end of capacitor C44, one end of capacitor C43, and the VBAT end respectively, and the other end of C44 and the other end of C43 are grounded;

[0020] The 15th pin of U9 is connected to the 16th pin of U9, one end of the inductor L6, one end of the capacitor C42, one end of the capacitor C40, one end of the capacitor C41, and the VSYS end respectively. The other end of C42, the other end of C40, and the other end of C41 are grounded. The other end of L6 is connected to one end of the capacitor C37, the 19th pin of U9, and the 20th pin of U9 respectively. The other end of C37 is connected to the 21st pin of U9.

[0021] Pins 17 and 18 of U9 are grounded;

[0022] Pin 22 of U9 is connected to one end of capacitor C35 and VREG respectively, and the other end of C35 is grounded;

[0023] Pin 23 of U9 is connected to one end of capacitor C36, one end of capacitor C34, one end of capacitor C33, the VBST5V1 end, and one end of resistor R45 respectively. The other ends of C36, C34, and C33 are grounded. The other end of R45 is connected to one end of resistor R46 and the LOWBATb end respectively. The other end of R46 is grounded.

[0024] As another preferred solution, the voltage-stabilized power supply described in the present invention adopts the RT9193-33GB chip U2, pin 1 of U2 is respectively connected to the VSYS end, one end of the capacitor C9, and one end of the resistor R1, the other end of C9 is grounded, the other end of R1 is respectively connected to pin 3 of U2 and the switch SW1, pin 2 of U2 is grounded, pin 4 of U2 is respectively connected to the ground line and one end of the capacitor C11 through capacitor C10, the other end of C11 is respectively connected to the VCC3.3 end, pin 5 of U2, and one end of the inductor L3, and the other end of L3 is connected to VDD.

[0025] As another preferred embodiment, the key input part of the present invention includes SW-PB4 switches S1, S3, S4, and S5, wherein pins 1 and 4 of S1 are respectively connected to the BTN1 terminal and one end of the resistor R2, the other end of R2 is connected to the VCC3.3 terminal, and pins 2 and 3 of S1 are grounded; pins 1 and 4 of S3 are respectively connected to the BTN2 terminal and one end of the resistor R3, the other end of R3 is connected to the VCC3.3 terminal, and pins 2 and 3 of S3 are grounded; pins 1 and 4 of S4 are respectively connected to the BTN3 terminal and one end of the resistor R4, the other end of R4 is connected to the VCC3.3 terminal, and pins 2 and 3 of S4 are grounded; pins 1 and 4 of S5 are respectively connected to the BTN4 terminal and one end of the resistor R5, the other end of R5 is connected to the VCC3.3 terminal, and pins 2 and 3 of S1 are grounded.

[0026] As another preferred solution, the 4-20mA output part of the present invention adopts DAC7311IDCKR chip U3, the 0-5V output part adopts LM358 chip U7, pin 2 of U3 is respectively connected to PA5 end and one end of resistor R11 through resistor R15, pin 3 of U3 is connected to PA7 end through resistor R17, pin 1 of U3 is connected to PA4 end through resistor R19, and pin 4 of U3 is respectively connected to REF3 end, one end of capacitor C16, one end of resistor R10, one end of capacitor C12, pin 1 of TL431 chip Q1, one end of resistor R8, and one end of resistor R7;

[0027] The other end of C16 is grounded, the 6th pin of U3 is connected to the other end of R11 and the 4th pin of BL1551 chip U4 respectively, the 5th pin of U4 is connected to the REF3 terminal and one end of capacitor C17 respectively, the other end of C17 is grounded, and the 6th pin of U4 is connected to the PA6 terminal through resistor R18;

[0028] Pin 2 of U4 is grounded, and pin 3 of U4 is connected to one end of resistor R12, one end of resistor R20, and pin 3 of OPA365AIDBVR chip U6 through resistors R13 and R14 respectively, and the other end of R12 is connected to the other end of R10;

[0029] The other end of C12 is connected to pin 2 of U6, the ground wire, pin 3 of Q1, and one end of resistor R9. The other end of resistor R9 is connected to pin 2 of Q1 and the other end of resistor R8.

[0030] The other end of R7 is connected to the collector of NPN transistor Q2, one end of inductor L4 and one end of capacitor C13 respectively; the other end of L4 is connected to the cathode of diode D1 and one end of TVS tube D5 respectively; the other end of D5 is connected to one end of inductor L5; the other end of L5 is connected to the other end of C13, one end of resistor R21 and the other end of R20 respectively; the other end of R21 is connected to pin 4 of U6, one end of capacitor C15 and one end of resistor R16 respectively; the other end of C15 is connected to pin 5 of U6 and REF3 respectively; the other end of R16 is connected to the emitter of Q2;

[0031] Pin 1 of U4 is connected to one end of capacitor C19 and one end of resistor R26 through resistor R25 respectively. The other end of R26 is connected to one end of capacitor C20 and pin 3 of LM358 chip U7 respectively. The other end of C20 is connected to pin 4 of U7 and ground respectively. Pin 2 of U7 is connected to one end of resistor R22, one end of resistor R23 and one end of variable resistor VR1 respectively. The other end of VR1 is connected to the other end of C19, the other end of R23, pin 1 of U7 and pin 5 of U7 respectively. Pin 6 of U7 is connected to pin 7 of U7 and one end of resistor R24 ​​respectively. The other end of R24 is connected to one end of capacitor C18 and the cathode of PESD3V3U1UA diode D6 respectively. The anode of D6 is grounded.

[0032] As another preferred solution, the frequency output part and the counting output part of the present invention adopt a 74LVCH2T45DC chip U8, and the pin 1 of U8 is respectively connected to the VCC3.3 terminal, one end of the capacitor C21, and one end of the resistor R30, the other end of C21 is grounded, the other end of R30 is respectively connected to the DO_EN terminal and the 5th pin of U8, the 2nd pin of U8 is connected to the DO_A terminal through the resistor R31, the 3rd pin of U8 is connected to the DO_B terminal through the resistor R32, and the 8th pin of U8 is respectively connected to the VCC5 terminal and one end of the capacitor C26, and the other end of C26 is grounded;

[0033] Pin 7 of U8 is connected to one end of resistor R29 and the base of NPN transistor Q3 through resistor R28. The other end of R29 is connected to the ground, the emitter of Q3 and the anode of PESD24VS1UB diode D7. The collector of Q3 is connected to one end of resistor R27 and the cathode of D7. The other end of R27 is connected to the DEXT end and the cathode of diode D2.

[0034] Pin 6 of U8 is connected to one end of resistor R35 and the base of NPN transistor Q4 through resistor R34. The other end of R35 is connected to the ground, the emitter of Q4, and the anode of PESD24VS1UB diode D8. The collector of Q4 is connected to one end of resistor R33 and the cathode of D8. The other end of R33 is connected to the DEXT end.

[0035] As another preferred solution, the present invention also includes an SGM41000 chip U10, pin 1 of U10 is respectively connected to one end of a resistor R63 and one end of a capacitor C46, ​​the other end of R63 is connected to the VBAT end, pins 2, 3, and 7 of U10 are grounded, pins 4 and 5 of U10 are grounded, pin 6 of U10 is grounded through a capacitor C45, and the other end of C46 is grounded.

[0036] As another preferred embodiment, the alarm circuit of the present invention includes buzzers BZ1 and BZ2, the positive electrode of BZ1 is respectively connected to the VCC3.3 terminal, the positive electrode of BZ2, and the cathode of diode D10, the negative electrode of BZ1 is respectively connected to the anode of D10, the negative electrode of BZ1, the negative electrode of BZ2, and the collector of SS8050 transistor Q10, the base of Q10 is respectively connected to one end of resistor R74 and one end of resistor R75, the other end of R74 is connected to the BEEP terminal, and the other end of R75 is respectively connected to the emitter of Q10 and the ground wire.

[0037] The invention has beneficial effects.

[0038] The 4-20mA output part and the 0-5V output part of the invention are used as analog quantity outputs, and have frequency quantity output and counting quantity output at the same time; the use is convenient and the efficiency is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. The protection scope of the present invention is not limited to the following description.

[0040] Figure 1 It is a circuit principle block diagram of the present invention.

[0041] Figure 2 , 3 4 is a circuit schematic diagram of the 4-20mA output part and the 0-5V output part of the present invention.

[0042] Figure 5 It is a circuit principle diagram of the frequency quantity output part and the counting quantity output part of the present invention.

[0043] Figure 6 It is a connection relationship diagram of various parts of the present invention.

[0044] Figure 7 It is a schematic diagram of the voltage-stabilized power supply circuit of the present invention.

[0045] Figure 8 It is a schematic diagram of the controller circuit of the present invention.

[0046] Fig. 9 It is a schematic diagram of the display circuit and key input circuit of the present invention.

[0047] Fig.10 , 11 It is a circuit schematic diagram of the charging management part of the present invention.

[0048] Fig.12 It is the LCD wiring diagram of the present invention.

[0049] Fig.13 It is the principle diagram of the alarm circuit of the present invention.

[0050] Fig.14 It is a schematic diagram of the memory circuit of the present invention.

[0051] Fig.15 is a simplified schematic diagram of the voltage / current converter of the present invention. DETAILED DESCRIPTION

[0052] As shown in the figure, the present invention includes a controller, and the signal output port of the controller is respectively connected to the 4-20mA output part, the 0-5V output part, the frequency output part, and the counting output part.

[0053] The display signal output port of the controller is connected to the display circuit, the alarm signal output port of the controller is connected to the alarm circuit, and the signal input port of the controller is connected to the key input part. The display circuit is connected to the display device, and the display device can be used to display the current analog quantity, voltage analog quantity, frequency quantity, and counting quantity.

[0054] The power port of the controller is connected to the output port of the voltage-stabilized power supply, the input port of the voltage-stabilized power supply is connected to the output port of the charging management part, and the charging management part is respectively connected to the lithium battery and the USB port.

[0055] The controller uses STMCU_LQFP64 chip U5, the 5th pin of U5 is connected to one end of the crystal oscillator X3, the other end of X3 is connected to the 6th pin of U5, the 1st pin of U5 is respectively connected to the VBAT / VLCD end, the VDD end, and one end of the capacitor C29, and the other end of C29 is grounded;

[0056] Pin 13 of U5 is connected to the AVDD terminal and one end of inductor L1 respectively. The other end of L1 is connected to the VDD terminal, pin 32 of U5, pin 64 of U5, pin 48 of U5, and pin 19 of U5 respectively. Pin 18 of U5 is grounded. Pin 47 of U5 is grounded through capacitor C22. Pin 63 of U5 is grounded. Pin 31 of U5 is grounded through capacitor C25. Pin 12 of U5 is grounded. Pin 60 of U5 is grounded through resistor R55. Pin 7 of U5 is connected to one end of resistor R54, one end of switch S2, and one end of capacitor C14 respectively. The other end of R54 is connected to the VDD terminal. The other end of S2 and the other end of C14 are grounded.

[0057] The 8MHz crystal oscillator X3 is multiplied by the frequency multiplication circuit inside the MCU to 72MHz for use as the system main clock.

[0058] The present invention adopts RC reset. When the system is just powered on, the capacitor C14 is charged through the resistor R54, the RESET pin is at a low level, and the STM is in a reset state. When charging is completed, the RESET pin returns to a high level, and the system works normally.

[0059] The PWM function frequency and count output of the STMCU_LQFP64 chip timer provides the original signal, which is converted into the frequency and count of the specified voltage value after level conversion.

[0060] The built-in 12-bit DAC function of the STMCU_LQFP64 chip provides DAC signals to the 4-20mA analog output and 0-5V analog output, which are converted by the transmitter to finally obtain the corresponding current and voltage values.

[0061] The STMCU_LQFP64 chip of the present invention uses hardware I2C to communicate with the charging management chip to realize the status monitoring function during the charging and discharging process of the lithium battery.

[0062] The STMCU_LQFP64 chip of the present invention uses hardware SPI communication and displays signal output information through an OLED screen.

[0063] The STMCU_LQFP64 chip of the present invention realizes working mode switching and output parameter setting through ordinary IO port buttons.

[0064] The STMCU_LQFP64 chip is a control chip with timer hardware resources that support PWM output and a DA converter, which can output analog, frequency, and counting quantities.

[0065] The charging management part adopts bq24195 chip U9, and the 1st pin of U9 is respectively connected to one end of capacitor C39, one end of capacitor C38, VBUS end, and the 24th pin of U9, and the other end of C39 and the other end of C38 are grounded;

[0066] Pin 2 of U9 is connected to pin 3 of U9 through CB2 (which can be a 0 ohm resistor);

[0067] Pin 4 of U9 is connected to the cathode of LED1 through resistor R50, and the anode of LED1 is connected to the VREG terminal;

[0068] Pin 5 of U9 is connected to VCC3.3 through resistor R48;

[0069] Pin 6 of U9 is connected to VCC3.3 through resistor R49;

[0070] Pin 8 of U9 is connected to one end of resistor R52 and collector of NPN transistor Q7 respectively. The other end of R52 is connected to VSYS. The base of Q7 is connected to one end of resistor R51 and one end of resistor R62 respectively. The other end of R51 is connected to VBUS_IN. The other end of R62 is connected to collector of Q7 and ground respectively.

[0071] Pin 9 of U9 is grounded through resistor R58;

[0072] Pin 10 of U9 is connected to ground through resistor R59;

[0073] The 11th pin of U9 is connected to the 12th pin of U9, one end of the resistor R53, one end of the resistor R60, and one end of the resistor R61 respectively. The other end of R53 is connected to the VREG end. The other ends of R60 and R61 are grounded.

[0074] The 13th pin of U9 is connected to the 14th pin of U9, one end of capacitor C44, one end of capacitor C43, and the VBAT end respectively, and the other end of C44 and the other end of C43 are grounded;

[0075] The 15th pin of U9 is connected to the 16th pin of U9, one end of the inductor L6, one end of the capacitor C42, one end of the capacitor C40, one end of the capacitor C41, and the VSYS end respectively. The other end of C42, the other end of C40, and the other end of C41 are grounded. The other end of L6 is connected to one end of the capacitor C37, the 19th pin of U9, and the 20th pin of U9 respectively. The other end of C37 is connected to the 21st pin of U9.

[0076] Pins 17 and 18 of U9 are grounded;

[0077] Pin 22 of U9 is connected to one end of capacitor C35 and VREG respectively, and the other end of C35 is grounded;

[0078] Pin 23 of U9 is connected to one end of capacitor C36, one end of capacitor C34, one end of capacitor C33, the VBST5V1 end, and one end of resistor R45 respectively. The other ends of C36, C34, and C33 are grounded. The other end of R45 is connected to one end of resistor R46 and the LOWBATb end respectively. The other end of R46 is grounded.

[0079] The voltages used in this hardware circuit are 5V and 3.3V, and the system input power supply is a 3.7-4.2V lithium battery.

[0080] The 5V power supply output circuit is obtained by the battery voltage through the charge management chip BQ24195 in boost mode. The power inductor L6, capacitors C33, C34, and C36 are all used for filtering to reduce the ripple of the power supply.

[0081] The voltage regulated power supply adopts RT9193-33GB chip U2, pin 1 of U2 is respectively connected to the VSYS end, one end of capacitor C9, and one end of resistor R1, the other end of C9 is grounded, the other end of R1 is respectively connected to pin 3 of U2 and switch SW1, pin 2 of U2 is grounded, pin 4 of U2 is respectively connected to the ground line and one end of capacitor C11 through capacitor C10, the other end of C11 is respectively connected to VCC3.3 end, pin 5 of U2, and one end of inductor L3, and the other end of L3 is connected to VDD.

[0082] The 3.3V voltage output circuit is a circuit where the battery voltage is passed through a low voltage drop linear regulator chip RT9193-33GB to obtain a 3.3V voltage, and the maximum output current is 300mA.

[0083] The key input part includes SW-PB4 switches S1, S3, S4, and S5, the 1st and 4th pins of S1 are respectively connected to the BTN1 terminal and one end of the resistor R2, the other end of R2 is connected to the VCC3.3 terminal, and the 2nd and 3rd pins of S1 are grounded;

[0084] Pins 1 and 4 of S3 are connected to the BTN2 terminal and one end of resistor R3 respectively. The other end of R3 is connected to the VCC3.3 terminal. Pins 2 and 3 of S3 are grounded.

[0085] Pins 1 and 4 of S4 are connected to the BTN3 terminal and one end of resistor R4 respectively. The other end of R4 is connected to the VCC3.3 terminal. Pins 2 and 3 of S4 are grounded.

[0086] Pins 1 and 4 of S5 are connected to the BTN4 terminal and one end of resistor R5 respectively, the other end of R5 is connected to the VCC3.3 terminal, and pins 2 and 3 of S1 are grounded.

[0087] The button can be used to set the analog current mode, analog voltage mode, frequency mode, counting mode and output parameters. One end of the button is connected to the controller's common IO, and the other end is connected to the ground. When the button is not pressed, it is pulled to a high level through an external pull-up resistor. When the button is pressed, the controller reads a low level through the IO, and returns to a high level after it is released.

[0088] JTAG is used to transmit debugging information. The host computer uses this interface to debug programs, download programs, and control the chip's internal registers, memory, and related peripherals.

[0089] SWD can be debugged using 4 wires, and the main signal lines are SWDIO and SWCLK. The present invention uses a 4-pin SWD debugging interface. The button and SWD debugging interface circuit design is as follows Fig. 9 shown.

[0090] The 4-20mA output part adopts DAC7311IDCKR chip U3, the 0-5V output part adopts LM358 chip U7, the 2nd foot of U3 is respectively connected to the PA5 end and one end of the resistor R11 through the resistor R15, the 3rd foot of U3 is connected to the PA7 end through the resistor R17, the 1st foot of U3 is connected to the PA4 end through the resistor R19, and the 4th foot of U3 is respectively connected to the REF3 end, one end of the capacitor C16, one end of the resistor R10, one end of the capacitor C12, the 1st foot of the TL431 chip Q1, one end of the resistor R8, and one end of the resistor R7;

[0091] The other end of C16 is grounded, the 6th pin of U3 is connected to the other end of R11 and the 4th pin of BL1551 chip U4 respectively, the 5th pin of U4 is connected to the REF3 terminal and one end of capacitor C17 respectively, the other end of C17 is grounded, and the 6th pin of U4 is connected to the PA6 terminal through resistor R18;

[0092] Pin 2 of U4 is grounded, and pin 3 of U4 is connected to one end of resistor R12, one end of resistor R20, and pin 3 of OPA365AIDBVR chip U6 through resistors R13 and R14 respectively, and the other end of R12 is connected to the other end of R10;

[0093] The other end of C12 is connected to pin 2 of U6, the ground wire, pin 3 of Q1, and one end of resistor R9. The other end of resistor R9 is connected to pin 2 of Q1 and the other end of resistor R8.

[0094] The other end of R7 is connected to the collector of NPN transistor Q2, one end of inductor L4 and one end of capacitor C13 respectively; the other end of L4 is connected to the cathode of diode D1 and one end of TVS tube D5 respectively; the other end of D5 is connected to one end of inductor L5; the other end of L5 is connected to the other end of C13, one end of resistor R21 and the other end of R20 respectively; the other end of R21 is connected to pin 4 of U6, one end of capacitor C15 and one end of resistor R16 respectively; the other end of C15 is connected to pin 5 of U6 and REF3 respectively; the other end of R16 is connected to the emitter of Q2;

[0095] Pin 1 of U4 is connected to one end of capacitor C19 and one end of resistor R26 through resistor R25 respectively. The other end of R26 is connected to one end of capacitor C20 and pin 3 of LM358 chip U7 respectively. The other end of C20 is connected to pin 4 of U7 and ground respectively. Pin 2 of U7 is connected to one end of resistor R22, one end of resistor R23 and one end of variable resistor VR1 respectively. The other end of VR1 is connected to the other end of C19, the other end of R23, pin 1 of U7 and pin 5 of U7 respectively. Pin 6 of U7 is connected to pin 7 of U7 and one end of resistor R24 ​​respectively. The other end of R24 is connected to one end of capacitor C18 and the cathode of PESD3V3U1UA diode D6 respectively. The anode of D6 is grounded.

[0096] Limited by the power input voltage of the microcontroller, the voltage range of the DAC analog signal outputted by it is only 0-3.3V. In order to achieve the output of 0-5V at the interface end, the DAC signal must be voltage amplified. At the same time, in order to improve the driving ability of the analog output, a voltage follower is added at the later stage so that the output interface has sufficient load capacity. The present invention adopts the structure of a non-inverting proportional amplifier + follower.

[0097] Its working principle and design steps are as follows:

[0098] The output voltage transfer function is:

[0099]

[0100] Choose the appropriate VR1 / R22 ratio:

[0101]

[0102] Calculate Vout from the DAC zero-scale voltage (0V) and gain ratio (VR1 / R22).

[0103]

[0104] Calculate Vout based on the DAC full-scale voltage (3V here) and the gain ratio (VR1 / R22).

[0105]

[0106] The 4-20mA signal standard first appeared in the 1950s. It is an analog signal transmission standard adopted by the International Electrotechnical Commission (IEC) process control system and is commonly used for signal transmission and electronic control in industrial environments. my country also adopts this international standard signal system. The instrument transmission signal uses 4-20mA and the receiving signal uses 1-5V, that is, a signal system that uses current transmission and voltage reception. Because it uses current signal transmission, it has the advantages of being less susceptible to interference, safe and reliable, making it a commonly used signal transmission method in industry.

[0107] The 4-20mA interface circuit designed by the present invention is as follows Figure 2 , 3 As shown in Figure 4, it consists of a voltage stabilizing circuit, a voltage / current conversion circuit, and an interface protection circuit.

[0108] A simplified schematic diagram of a voltage / current converter is shown below: Fig.15 As shown, it is a loop-powered or 2-wire 4-20mA transmitter. The transmitter has only two external input terminals. The transmitter communicates with the host by precisely controlling the magnitude of its return current to communicate with the host.

[0109] Its working principle and design steps are as follows:

[0110] The output current transfer function is:

[0111]

[0112] Choose a larger R3 / R4 ratio:

[0113]

[0114] Calculate R2 based on the zero-scale current (4mA), the regulator voltage, and the gain ratio (R3 / R4).

[0115]

[0116] Calculate R1 based on the full-scale DAC voltage and the current range of 16mA to set the full-scale current.

[0117]

[0118] The zero-scale current is calculated based on the selected resistor value.

[0119]

[0120] Calculate the full-scale current based on the selected resistor value.

[0121]

[0122] The voltage regulator circuit uses the TL431 programmable parallel regulator chip, which has an accuracy specification of 0.5%, low cost and good performance. Even if the load changes, the regulator output will remain relatively consistent.

[0123] Since instruments using the 4-20mA signal standard are often used in industrial environments, which can be very dangerous for sensitive electronic components, a protection circuit is added to the interface to prevent environmental hazards such as electrical overstress or poor performance that may be caused by incorrect wiring. The present invention utilizes the unidirectional conductivity of the diode D1 and the reverse breakdown characteristics of the TVS tube D5 to prevent system failures caused by incorrect wiring and external signal interference.

[0124] The frequency output part and the counting output part adopt the 74LVCH2T45DC chip U8, the 1st pin of U8 is respectively connected to the VCC3.3 terminal, one end of the capacitor C21, and one end of the resistor R30, the other end of C21 is grounded, the other end of R30 is respectively connected to the DO_EN terminal and the 5th pin of U8, the 2nd pin of U8 is connected to the DO_A terminal through the resistor R31, the 3rd pin of U8 is connected to the DO_B terminal through the resistor R32, the 8th pin of U8 is respectively connected to the VCC5 terminal and one end of the capacitor C26, and the other end of C26 is grounded;

[0125] Pin 7 of U8 is connected to one end of resistor R29 and the base of NPN transistor Q3 through resistor R28. The other end of R29 is connected to the ground, the emitter of Q3 and the anode of PESD24VS1UB diode D7. The collector of Q3 is connected to one end of resistor R27 and the cathode of D7. The other end of R27 is connected to the DEXT end and the cathode of diode D2.

[0126] Pin 6 of U8 is connected to one end of resistor R35 and the base of NPN transistor Q4 through resistor R34. The other end of R35 is connected to the ground, the emitter of Q4, and the anode of PESD24VS1UB diode D8. The collector of Q4 is connected to one end of resistor R33 and the cathode of D8. The other end of R33 is connected to the DEXT end.

[0127] The frequency output (digital output) uses the controller's timer function to output a PWM signal with a programmable frequency. The 74LVCH2T45DC chip is used to complete the signal voltage conversion from 3.3V to 5V. The interface output is designed as an NPN open-drain output, which allows the user to provide an external voltage reference and output the frequency output at a specified voltage through an external load.

[0128] The counting output uses the controller's IO port function and timer function to output a low-speed switch signal. The 74LVCH2T45DC chip is used to complete the signal voltage conversion from 3.3V to 5V. The interface output is designed as an NPN open-drain output. This design allows the user to provide an external voltage reference and output the counting output at a specified voltage through an external load.

[0129] The present invention also includes an SGM41000 chip U10, wherein pin 1 of U10 is respectively connected to one end of a resistor R63 and one end of a capacitor C46, ​​the other end of R63 is connected to a VBAT end, pins 2, 3, and 7 of U10 are grounded, pins 4 and 5 of U10 are grounded, pin 6 of U10 is grounded through a capacitor C45, and the other end of C46 is grounded.

[0130] The alarm circuit includes buzzers BZ1 and BZ2. The positive electrode of BZ1 is respectively connected to the VCC3.3 terminal, the positive electrode of BZ2, and the cathode of diode D10. The negative electrode of BZ1 is respectively connected to the anode of D10, the negative electrode of BZ1, the negative electrode of BZ2, and the collector of SS8050 transistor Q10. The base of Q10 is respectively connected to one end of resistor R74 and one end of resistor R75. The other end of R74 is connected to the BEEP terminal. The other end of R75 is respectively connected to the emitter of Q10 and the ground wire.

[0131] The signals of the present invention can be divided into four types: four types of analog quantities, one type of frequency quantity and one type of counting quantity.

[0132] Analog quantity (the range can be set to 5-6 levels, for example, 4-20mA can output 4, 8, 12, 16, 20MA, voltage 0, 1, 2, 3, 4, 5): (1) 4-20mA, two-wire system, power supply 24V. (2) 4-20mA, two-wire system, no power supply is required, direct output signal. (3) 0-5V, two-wire system, power supply 24V. (4) 0-5V, two-wire system, no power supply is required, direct output signal.

[0133] Frequency: power supply 24V, two-wire system, output 60HZ, 120HZ, 360HZ, 540HZ, 720HZ, 1200HZ, 1800HZ, 24000HZ.

[0134] Counting quantity: The initial count value can be 40000, which can be increased or decreased in sequence, and one pulse can be added each time, and the speed can reach 1HZ. This channel can lead to 4 terminals, namely power positive (8V), power negative, signal A, and signal B. The electrical signals output by signal A and signal B directly are +8, 0, 0, -8 (increasing in the positive direction), and -8, 0, 0+8 (decreasing in the reverse direction).

[0135] The invention can be powered by batteries and is convenient to hold and carry.

[0136] It can be understood that the above specific description of the present invention is only used to illustrate the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that the present invention can still be modified or replaced by equivalents to achieve the same technical effects; as long as the use requirements are met, they are within the protection scope of the present invention.

Claims

1. A logging parameter simulator, including a controller, characterized in that The signal output port of the controller is respectively connected to the 4-20mA output part, the 0-5V output part, the frequency output part, and the counting output part; The display signal output port of the controller is connected to the display circuit, the alarm signal output port of the controller is connected to the alarm circuit, and the signal input port of the controller is connected to the key input part; The power port of the controller is connected to the output port of the voltage-stabilized power supply, the input port of the voltage-stabilized power supply is connected to the output port of the charging management part, and the charging management part is connected to the lithium battery and the USB port respectively; The controller uses STMCU_LQFP64 chip U5, the 5th pin of U5 is connected to one end of the crystal oscillator X3, the other end of X3 is connected to the 6th pin of U5, the 1st pin of U5 is respectively connected to the VBAT / VLCD end, the VDD end, and one end of the capacitor C29, and the other end of C29 is grounded; Pin 13 of U5 is connected to the AVDD terminal and one end of the inductor L1 respectively, the other end of L1 is connected to the VDD terminal, pin 32 of U5, pin 64 of U5, pin 48 of U5, and pin 19 of U5 respectively, pin 18 of U5 is grounded, pin 47 of U5 is grounded through capacitor C22, pin 63 of U5 is grounded, pin 31 of U5 is grounded through capacitor C25, pin 12 of U5 is grounded, pin 60 of U5 is grounded through resistor R55, pin 7 of U5 is connected to one end of resistor R54, one end of switch S2, and one end of capacitor C14 respectively, the other end of R54 is connected to the VDD terminal, and the other end of S2 and the other end of C14 are grounded; The charging management part adopts bq24195 chip U9, and the 1st pin of U9 is respectively connected to one end of capacitor C39, one end of capacitor C38, VBUS end, and the 24th pin of U9, and the other end of C39 and the other end of C38 are grounded; Pin 2 of U9 is connected to pin 3 of U9 through CB2; Pin 4 of U9 is connected to the cathode of LED1 through resistor R50, and the anode of LED1 is connected to the VREG terminal; Pin 5 of U9 is connected to VCC3.3 through resistor R48; Pin 6 of U9 is connected to VCC3.3 through resistor R49; Pin 8 of U9 is connected to one end of resistor R52 and collector of NPN transistor Q7 respectively. The other end of R52 is connected to VSYS. The base of Q7 is connected to one end of resistor R51 and one end of resistor R62 respectively. The other end of R51 is connected to VBUS_IN. The other end of R62 is connected to collector of Q7 and ground respectively. Pin 9 of U9 is grounded through resistor R58; Pin 10 of U9 is connected to ground through resistor R59; The 11th pin of U9 is connected to the 12th pin of U9, one end of the resistor R53, one end of the resistor R60, and one end of the resistor R61 respectively. The other end of R53 is connected to the VREG end. The other ends of R60 and R61 are grounded. The 13th pin of U9 is connected to the 14th pin of U9, one end of capacitor C44, one end of capacitor C43, and the VBAT end respectively, and the other end of C44 and the other end of C43 are grounded; The 15th pin of U9 is connected to the 16th pin of U9, one end of the inductor L6, one end of the capacitor C42, one end of the capacitor C40, one end of the capacitor C41, and the VSYS end respectively. The other end of C42, the other end of C40, and the other end of C41 are grounded. The other end of L6 is connected to one end of the capacitor C37, the 19th pin of U9, and the 20th pin of U9 respectively. The other end of C37 is connected to the 21st pin of U9. Pins 17 and 18 of U9 are grounded; Pin 22 of U9 is connected to one end of capacitor C35 and VREG respectively, and the other end of C35 is grounded; Pin 23 of U9 is respectively connected to one end of capacitor C36, one end of capacitor C34, one end of capacitor C33, the end of VBST5V1, and one end of resistor R45. The other ends of C36, C34, and C33 are grounded. The other end of R45 is respectively connected to one end of resistor R46 and the end of LOWBATb. The other end of R46 is grounded. The 4-20mA output part adopts DAC7311IDCKR chip U3, the 0-5V output part adopts LM358 chip U7, the 2nd foot of U3 is respectively connected to the PA5 end and one end of the resistor R11 through the resistor R15, the 3rd foot of U3 is connected to the PA7 end through the resistor R17, the 1st foot of U3 is connected to the PA4 end through the resistor R19, and the 4th foot of U3 is respectively connected to the REF3 end, one end of the capacitor C16, one end of the resistor R10, one end of the capacitor C12, the 1st foot of the TL431 chip Q1, one end of the resistor R8, and one end of the resistor R7; The other end of C16 is grounded, the 6th pin of U3 is connected to the other end of R11 and the 4th pin of BL1551 chip U4 respectively, the 5th pin of U4 is connected to the REF3 terminal and one end of capacitor C17 respectively, the other end of C17 is grounded, and the 6th pin of U4 is connected to the PA6 terminal through resistor R18; Pin 2 of U4 is grounded, and pin 3 of U4 is connected to one end of resistor R12, one end of resistor R20, and pin 3 of OPA365AIDBVR chip U6 through resistors R13 and R14 respectively. The other end of R12 is connected to the other end of R10; the other end of C12 is connected to pin 2 of U6, ground, pin 3 of Q1, and one end of resistor R9 respectively, and the other end of resistor R9 is connected to pin 2 of Q1 and the other end of resistor R8 respectively; The other end of R7 is connected to the collector of NPN transistor Q2, one end of inductor L4 and one end of capacitor C13 respectively; the other end of L4 is connected to the cathode of diode D1 and one end of TVS tube D5 respectively; the other end of D5 is connected to one end of inductor L5; the other end of L5 is connected to the other end of C13, one end of resistor R21 and the other end of R20 respectively; the other end of R21 is connected to pin 4 of U6, one end of capacitor C15 and one end of resistor R16 respectively; the other end of C15 is connected to pin 5 of U6 and REF3 respectively; the other end of R16 is connected to the emitter of Q2; Pin 1 of U4 is connected to one end of capacitor C19 and one end of resistor R26 through resistor R25 respectively. The other end of R26 is connected to one end of capacitor C20 and pin 3 of LM358 chip U7 respectively. The other end of C20 is connected to pin 4 of U7 and ground respectively. Pin 2 of U7 is connected to one end of resistor R22, one end of resistor R23 and one end of variable resistor VR1 respectively. The other end of VR1 is connected to the other end of C19, the other end of R23, pin 1 of U7 and pin 5 of U7 respectively. Pin 6 of U7 is connected to pin 7 of U7 and one end of resistor R24 ​​respectively. The other end of R24 is connected to one end of capacitor C18 and the cathode of PESD3V3U1UA diode D6 respectively. The anode of D6 is grounded.

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