SPDT Switch

Abstract

A single-pole double-throw switch, comprising switch units respectively arranged between a first port and a second port and between the first port and a third port, and configured to perform complementarily. Each switch unit comprises: an antenna port; a circuit port; a transmission line configured to couple the antenna port and the circuit port; and a switch element connected between the transmission line and ground. The switch element comprises: a parallel circuit comprising a transistor and an inductor connected in parallel; and a capacitor connected in series with the parallel circuit. The transmission line has a characteristic impedance different from an impedance seen from the antenna port inside the switch unit and an impedance seen from the circuit port inside the switch unit.

Description

Technical Field

[0001] Aspects of the present invention relate to a single-pole double-throw switch that selectively inputs and outputs signals. Background Art

[0002] Conventionally, a single-pole double-throw switch (SPDT) has been used, which selectively connects a device for high-frequency signal processing such as an antenna to two input / output terminals. For example, the high-frequency switching circuit described in Patent Document 1 (Japanese Unexamined Patent Publication No. H8-213802) includes: a semiconductor switching element, which is arranged between a point on a transmission line connecting two input / output terminals and ground; a 1 / 4 wavelength line, which is inserted into the transmission line; and an inductive reactance element, which is arranged between a point on the transmission line and ground and is configured to be combined with the semiconductor switching element to form a resonant circuit. As other switching circuits, those described in Patent Document 2 (Japanese Unexamined Patent Publication No. H9-008501) and Patent Document 3 (Japanese Unexamined Patent Publication No. 2016-010045) are also known.

[0003] In the above-mentioned conventional high-frequency switching circuit, in high-frequency or high-power applications, there is a tendency that the open-circuit characteristics and short-circuit characteristics of the transistor as a switching element tend to be biased. As a result, when the transistor is open-circuited, the channel loss between the terminals may increase significantly. Therefore, a single-pole double-throw switch is needed that can reduce the channel loss between the terminals when the transistor is open-circuited. Summary of the invention

[0004] According to one aspect of the present invention, a single-pole double-throw switch is provided, which includes: a first port; a second port; a third port; a first switch unit connected between the first port and the second port; and a second switch unit connected between the first port and the third port. The first switch unit includes: a first antenna port connected to the first port; a first circuit port connected to the second port; a first transmission line configured to couple the first antenna port to the first circuit port; and a first switch element connected between the first transmission line and ground. The first switch element includes: a first parallel circuit including a first transistor and a first inductor connected in parallel with the first transistor, the first parallel circuit being grounded; and a first capacitor connected between the first transmission line and the first parallel circuit. The second switch unit includes: a second antenna port connected to the first port; a second circuit port connected to the third port; a second transmission line configured to couple the second antenna port to the second circuit port; and a second switch element connected between the second transmission line and ground. The second switching element includes: a second parallel circuit including a second transistor and a second inductor connected in parallel with the second transistor, the second parallel circuit being grounded; and a second capacitor connected between the second transmission line and the second parallel circuit. The characteristic impedance of the first transmission line is different from each of the first impedance seen from the first antenna port and the second impedance seen from the first circuit port, and the characteristic impedance of the second transmission line is different from each of the first impedance seen from the second antenna port and the third impedance seen from the second circuit port. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 : is a circuit diagram showing a schematic configuration of the SPDT 1 according to the embodiment.

[0006] Figure 2 yes Figure 1 An equivalent circuit diagram of transistor 13.

[0007] Figure 3 is a diagram showing calculation results of impedance seen from the drain of a general FET on a Smith chart.

[0008] Figure 4 : is a diagram showing the calculation result of the impedance seen from the drain of the transistor 13 to which the inductor 17 is added on the Smith chart.

[0009] Figure 5 : is a diagram showing the calculation result of the impedance seen from the drain of the transistor 13 to which the capacitor 15 is added on the Smith chart.

[0010] Figure 6 is a diagram showing a calculation result of the impedance seen from the drain of the transistor 13 on the Smith chart when the reflection characteristic is compensated by the embodiment.

[0011] Figure 7 is from Figure 1 The switching unit Ua removes a portion of the transmission line circuit diagram.

[0012] Figure 8 It is shown in Figure 7 A graph showing the results of calculating the strength of a signal directed from the first port P1 to the second port P2 at various frequencies in the configuration shown.

[0013] Fig. 9 yes Figure 1 Circuit diagram of switching unit Ua.

[0014] Fig.10 : is a diagram showing the calculation result of the impedance seen from the first port P1 on the Smith chart in the embodiment.

[0015] Fig.11 It is shown in Fig. 9 A graph showing the results of calculating the strength of a signal directed from the first port P1 to the second port P2 at various frequencies in the configuration shown.

[0016] Fig. 12A is a diagram showing a configuration example of the impedance conversion circuits 5 a and 9 a .

[0017] Fig. 12B is a diagram showing a configuration example of the impedance conversion circuits 5 a and 9 a .

[0018] Fig. 12C is a diagram showing a configuration example of the impedance conversion circuits 5 a and 9 a . DETAILED DESCRIPTION

[0019] Embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and repeated descriptions will be omitted.

[0020] [Configuration of SPDT switch]

[0021] Figure 1 1 is a block diagram showing a configuration of a single-pole double-throw switch (hereinafter referred to as SPDT) according to an embodiment. The SPDT is a switch capable of switching electrical connection between two ports with respect to one port, and is used, for example, to switch connection between a device such as a high-frequency antenna and a transmitter and a receiver. Figure 1 As shown in FIG. 1 , the SPDT 1 includes a first port P1, a second port P2, a third port P3, a switch unit Ua disposed between the first port P1 and the second port P2, and a switch unit Ub disposed between the first port P1 and the third port P3. The two switch units Ua and Ub operate complementarily to each other and have the same configuration.

[0022] The switching unit Ua includes: an antenna port P4, which is directly electrically connected to the first port P1; a circuit port P5, which is directly electrically connected to the second port P2; and a transmission line 3a, an impedance conversion circuit 5a, a transmission line 7a, and an impedance conversion circuit 9a, which are connected in this order between the antenna port P4 and the circuit port P5. In addition, the switching unit Ua includes a switching element 11a electrically connected between an intermediate connection point on the transmission line 7a and the ground (grounding). The switching unit Ub also has a similar configuration between the antenna port P4 and the circuit port P6 directly electrically connected to the third port P3, and includes a transmission line 3b, an impedance conversion circuit 5b, a transmission line 7b, an impedance conversion circuit 9b, and a switching element 11b.

[0023] The switching element 11a is an element that alternately blocks or conducts between the first port P1 and the second port by making the connection between the transmission line 7a and the ground conductive (short circuit) or disconnected (open circuit). The switching element 11a includes a transistor 13 as a FET, a capacitor 15, and an inductor 17. The transistor 13 can be turned on / off by providing a gate bias from the outside via a resistor element. The source of the transistor 13 is electrically connected to the ground, and the drain of the transistor 13 is electrically connected to the middle point (connection point) of the transmission line 7a via the capacitor 15, and is also electrically connected to the ground via the inductor 17. In other words, the inductor 17 and the transistor 13 are connected in parallel between the middle point of the transmission line 7a and the ground, and the parallel circuit of the transistor 13 and the inductor 17 is connected in series with the capacitor 15.

[0024] The capacitor 15 and the inductor 17 included in the switching element 11 a are provided to compensate for the parasitic inductor and the parasitic capacitance of the transistor 13 . Figure 2 FIG. 1 shows an equivalent circuit of transistor 13. As shown in the figure, transistor 13 having a relatively large size (eg, gate width) has a capacitance value C DS The parasitic capacitance between drain and source R DS When the transistor 13 is turned off, especially in a signal region with a high frequency, the capacitance C has a large value. DS , the impedance Z between the drain and source DS has a finite value, and the transistor 13 cannot be regarded as being turned off. On the other hand, even when the transistor 13 is turned on, the resistor R DS hours, due to the inductance L of the drain line D and the source line inductance L S Due to the influence of L, the inductance component is also added to the output of transistor 13. As a result, the open circuit (off) characteristic and the short circuit (on) characteristic of transistor 13 are affected by the inductance L. D and L S And the capacitance value CDS The size of the bias.

[0025] In the embodiment, due to the presence of the inductor 17, the inductor component LDS and the parasitic capacitance C DS inserted in parallel, thus forming a peak circuit, and the parasitic capacitance C DS In addition, due to the presence of capacitor 15, the inductor L D and L S Adding capacitance in series with the inductive component significantly eliminates the inductive component.

[0026] In the transmission line 3a, the impedance conversion circuit 5a, the transmission line 7a, and the impedance conversion circuit 9a connected between the antenna port P4 and the circuit port P5, when the wavelength of the signal for which the SPDT 1 is directed is λ, the length from the antenna port P4 to the connection point of the switch element 11a and the length from the circuit port P5 to the connection point of the switch element 11a are set to λ / 4. Therefore, when the transistor 13 is turned off, when viewed from the side of the antenna port P4 and the circuit port P5, the connection point of the switch element 11a appears to be alternately short-circuited, and the antenna port P4 and the circuit port P5 are electrically connected. On the other hand, when the transistor 13 is turned on, when viewed from the side of the antenna port P4 and the circuit port P5, the connection point of the switch element 11a appears to be alternately open, and the connection between the antenna port P4 and the circuit port P5 is blocked.

[0027] The impedance conversion circuits 5a and 9a are provided to correct the imbalance of the reflection characteristics seen from the drain of the transistor 13 when the transistor 13 of the switching element 11a is turned on / off. Specifically, the impedance conversion circuit 5a performs impedance conversion between the first characteristic impedance in the antenna port P4 and the second characteristic impedance different from the first characteristic impedance. Similarly, the impedance conversion circuit 9a performs impedance conversion between the first characteristic impedance in the circuit port P5 and the second characteristic impedance different from the first characteristic impedance. In the case where the characteristic impedance Z0=50Ω in the first port P1 to the third port P3, the characteristic impedance of the transmission line 3a is set to Z0, and the impedance conversion circuits 5a and 9a perform impedance conversion between the first characteristic impedance Z1=Z0 and the second characteristic impedance Z2 (for example, Z2=21Ω). In addition, the characteristic impedance of the transmission line 7a is set to the second characteristic impedance Z2 (for example, Z2=21Ω).

[0028] The characteristic impedance is set to the square root of the product of the first characteristic impedance Z1 and the second characteristic impedance Z2 (Z1×Z2) 1 / 2A microstrip line of a value of is used as the configuration of such impedance conversion circuits 5a and 9a. That is, the impedance conversion circuits 5a and 9a are set to a characteristic impedance different from the first characteristic impedance Z1 in which the switch unit Ua is viewed from the first port P1 and the second port P2. When the length of the transmission line constituting each of the impedance conversion circuits 5a and 9a is set to λ / 4, the transmission lines 3a and 7a are not necessary.

[0029] The switch unit Ub has the same configuration as the switch unit Ua, and the transistor 13 of the switch element 11b is uniquely turned on / off relative to the transistor of the switch element 11a. Thus, the electrical connection between the first port P1, the second port P2, and the third port P3 is uniquely switched.

[0030] [Characteristics of SPDT]

[0031] Then, the circuit characteristics of the above-mentioned SPDT1 will be described.

[0032] First, in Figure 3 In the example, the impedance Z seen from the drain when the transistor 13 configured by only a normal FET is turned on / off on and Z off It is calculated in the frequency range of 0.4 to 43.5 GHz and shown on the Smith chart. Here, the impedance centered on the characteristic impedance Z0 = 50Ω is shown (hereinafter, the same applies unless otherwise specified). Figure 3 As shown in FIG. 1 , the impedance characteristic Z when the transistor 13 is turned off off 0.4 GHz at the right end is in an infinite state and can be regarded as a direct current. It transitions clockwise as the frequency increases and approaches a short circuit near 43.5 GHz at the left end. This is because the capacitor C DS The contribution of the inductor L D and L S On the other hand, due to the inductance L D and L S Contribution, impedance characteristic Z when conducting on At 0.4 GHz, it is not completely short-circuited (left end), but starts from a false short-circuit state, and due to the inductance L D and L S As the frequency increases, it moves clockwise to a point closer to the right end. Assuming the target frequency of SPDT 1 is 28 GHz, the impedance at this time is calculated as Z on Ang = Z0×(0.106+0.129j) and Z off = Z0×(0.059-0.583j) (points m2 and m1 on the Smith chart), and does not have Z on to 0, Z off to the value of ∞.

[0033] exist Figure 4 , relative to the impedance Z of the transistor 13 to which the inductor 17 is added on and Z off It is calculated in the frequency range of 1 to 40 GHz and shown on a Smith chart. In this case, the peak operating frequency is f0 = 1 / {2π×(C DS ×L DS ) 1 / 2 Here, the inductor L is set DS The impedance Z when the peak operating frequency f0 matches the 28 GHz for SPDT 1 is on and Z off Thus, the impedance Z at turn-off off Short-circuited at the left end at 1 GHz, Z0×2.432 (point m1) is calculated at 28 GHz, and Z0×(0.25-0.45j) is calculated at 40 GHz (clockwise end point). From this result, it can be understood that due to the effect of inductor 17, the characteristics of transistor 13 at 28 GHz when turned off are close to an infinite impedance state.

[0034] exist Figure 5 , relative to the impedance Z of the transistor 13 to which the capacitor 15 is additionally added. on and Z off It is calculated in the frequency range of 1 to 40 GHz and shown on the Smith chart. D and L S Considered as an inductor component L S '=L D +L S When the frequency f S =(1 / 2π)×(C S ÷L S ') 1 / 2 Here, the capacitor C of capacitor 15 is shown. S Set to the frequency f where the notch occurs at 28 GHz for SPDT 1 S The impedance Z is matched to the value on and Z off In this way, the impedance Z on At 28 GHz (point m2), which is the starting point of 1 GHz in the clockwise direction, it becomes Z0×0.071, and at 40 GHz (the end point in the clockwise direction), it is infinite. At this time, the impedance Z when turned off is off is also affected by capacitor 15, and the characteristic at 28 GHz is calculated as Z off=Z0×(2.432−0.122j) (point m1) From this result, it can be understood that, due to the action of the capacitor 15, the impedance at 28 GHz when the transistor 13 is turned on is close to a state in which the impedance is zero.

[0035] As described above, although the reflection characteristic seen from the drain when the transistor 13 is turned on / off is improved, its value is not balanced. That is, the reflection characteristic (reflection coefficient S11) can be changed by Figure 5 The distance from the origin (Z0=50Ω) on the Smith chart shown in is evaluated, but it is Z0×2.432 (point m1) when turned off, and it is Z0×0.071 (point m2) when turned on, and the distances of the points from the origin are unbalanced.

[0036] In this embodiment, by setting a characteristic impedance that compensates for different reflection characteristics on the transmission line connected to the drain of the transistor 13, the reflection characteristics when the transistor 13 is turned on / off can be set to a similar value. Figure 6 In the SPDT 1 of this embodiment, the impedance Z seen from the drain of the transistor 13 is on and Z off The calculation is performed in the frequency range of 1 to 40 GHz and is shown on the Smith chart. In this embodiment, since the characteristic impedance in the drain of the transistor 13 is set to the second impedance Z2, the reflection characteristics are evaluated on the Smith chart centered on the impedance Z2. For example, when Z2=21Ω is set, Figure 6 As shown in , the characteristics at points m1 and m2 when the transistor 13 is turned on / off can be set to symmetrical positions (Z2=21Ω) centered on the origin, thereby correcting the imbalance of the reflection characteristics when the transistor 13 is turned on / off.

[0037] Figure 7 A configuration is shown in which the transmission line 3a and the impedance conversion circuits 5a and 9a are removed from the switch unit Ua. Figure 8 Shown in Figure 7 The results of the signal strength from the first port P1 to the second port P2 calculated at various frequencies in the configuration shown in FIG. The gate width of the transistor 13 here is 400 μm, and the capacitance of the capacitor 15 is set to C S =1pF, the width of the inductor 17 is 10μm, the length is 400μm, the strength of the transistor 13 when it is turned off is indicated by the curve SToff, and the strength of the transistor 13 when it is turned on is indicated by the curve STon. According to the result, the loss at a frequency of 27.7GHz when the transistor 13 is turned off is calculated to be 0.714dB (point m3), and the loss at the same frequency when the transistor 13 is turned on is calculated to be 11.275dB (point m4), and a value of a strength ratio of 10dB or more when it is turned on / off is obtained.

[0038] However, it is not possible to Figure 7 The configuration shown in FIG. 1 is used as a switch on one side of the SPDT 1. This is because the impedance of the transmission path is not 50Ω, and the impedance of the first port P1 is not open when the transistor 13 is turned on (when the signal is blocked), so the signal to be propagated to the other side of the transmission path may also be blocked. Therefore, the SPDT 1 adopts Fig. 9 In the present embodiment, when the impedance conversion circuits 5a, 9a are short-circuited with the transistor 13, the transmission line 3a is set by adjusting the length of the transmission line so that the first port P1 is open-circuited. That is, when the transistor 13 is turned on, since the length from the middle connection point of the transmission line 7a to the first port P1 is set to λ / 4, the impedance seen from the first port P1 may be open-circuited so that the switch unit on the other side is not affected.

[0039] exist Fig.10 In the present embodiment, the result of calculating the impedance seen from the first port P1 when the transistor 13 is turned on in the frequency range of 0.4 to 45.5 GHz is shown on the Smith chart. The result is shown here on the Smith chart centered on the characteristic impedance Z0=50Ω. As described above, the impedance is approximately located at the origin at a frequency of 0.4 GHz, and the characteristic impedance 50Ω on the second port P2 is directly observed, transitioning clockwise with increasing frequency, becoming impedance Z0×(7.188-0.454j) at a frequency of 28 GHz (point m5), and becoming impedance Z0×(0.15+0.15j) at a frequency of 45.5 GHz (end point).

[0040] Fig.11 The result in which the signal strength directed from the first port P1 to the second port P2 is calculated at each frequency in the embodiment is shown. Here, the strength when the transistor 13 is turned off is indicated by the curve SToff, and the strength when the transistor 13 is turned on is indicated by the curve STon. According to the result, the loss at a frequency of 28 GHz when the transistor 13 is turned off is calculated to be 0.655 dB (point m3), and the loss at the same frequency when the transistor 13 is turned on is calculated to be 11.275 dB (point m4), and a value of a strength ratio of 10 dB or more when turned on / off is obtained.

[0041] [SPDT operation and effects]

[0042] According to the SPDT 1 of the above-described embodiment, when the transistor 13 is turned on, the parasitic inductance component is offset by the capacitor 15 of the switching element 11a, and when the transistor 13 is turned off, the parasitic capacitance component is offset by the inductor 17 of the switching element 11a. In addition, since there are impedance conversion circuits 5a and 9a having characteristic impedances different from the first impedance Z0 in which the inside of the switching unit Ua is seen, the reflection characteristics of the switching unit Ua seen from the ports P1 and P2 when the transistor 13 is turned on / off can be uniformized. As a result, when the transistor 13 is turned off (open circuit), the through loss between the ports (between the first port P and the second port P2 and the third port P3) is reduced.

[0043] In particular, the characteristic impedance of the impedance conversion circuits 5a and 9a is set to a value of the square root of the product of the first characteristic impedance Z1 and the second characteristic impedance Z2. According to such impedance conversion circuits 5a and 9a, the characteristic impedance can be converted between the first characteristic impedance and the second characteristic impedance by a simple configuration.

[0044] Furthermore, according to the present embodiment, the impedance of the switching element 11a when the transistor 13 is turned on and the impedance of the switching element 11a when the transistor 13 is turned off are values ​​indicating symmetrical points on the Smith chart with reference to the second characteristic impedance Z2 with respect to the frequency of the signal targeted by the SPDT 1. By this configuration, when the transistor 13 is turned on / off, the reflection characteristics in which the switch unit Ua is seen from each of the ports P1 and P2 can be made uniform.

[0045] Furthermore, when the wavelength of the signal for which the SPDT 1 is applied is λ, the length of the transmission line in the switch unit Ua from the antenna port P4 or the circuit port P5 to the connection point on the transmission line 7a is λ / 4. With such a configuration, when the transistor 13 is turned on, the connection with the circuit port P5 side can be blocked in a high-frequency manner when viewed from the antenna port P4 side, and when the transistor 13 is turned off, the connection with the circuit port P5 side can be turned on in a high-frequency manner when viewed from the antenna port P4 side.

[0046] Although the principles of the present invention have been shown and described in the preferred embodiments, it will be appreciated by those skilled in the art that the present invention may be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configurations disclosed in the embodiments. Therefore, all modifications and changes according to the claims and their spirit are claimed.

[0047] In the embodiment, the configurations of the impedance conversion circuits 5a and 9a are exemplified as follows. Fig. 12A The microstrip line shown in FIG. 1 is shown in FIG. 2 , but other configurations may be used. For example, the following impedance transformer may be used: Fig. 12BAn impedance converter using a transmission line with a characteristic impedance Z0 of a stub as shown in; and Fig. 12C . The π-type impedance converter shown in FIG. 1 has a configuration in which two capacitors 23a, 23b are connected between both ends of the inductor 21 and the ground. However, in the case of this configuration, the length of the transmission line 3a must be set so that the impedance of the first port P1 is high when the transistor 13 is turned on.

Claims

1. A single-pole double-throw switch, comprising: First port; Second port; The third port; A first switch unit, wherein the first switch unit is connected between the first port and the second port; The first switch unit comprises: a first antenna port, the first antenna port being connected to the first port, a first circuit port, the first circuit port being connected to the second port, a first transmission line configured to couple the first antenna port to the first circuit port, and A first switch element, wherein the first switch element is connected between the first transmission line and ground, and the first switch element comprises: a first parallel circuit including a first transistor and a first inductor connected in parallel with the first transistor, the first parallel circuit being connected to the ground, and a first capacitor connected between the first transmission line and the first parallel circuit, and A second switch unit, wherein the second switch unit is connected between the first port and the third port; the second switch unit comprises: a second antenna port, the second antenna port being connected to the first port, a second circuit port, the second circuit port being connected to the third port, a second transmission line configured to couple the second antenna port to the second circuit port, and A second switch element, the second switch element is connected between the second transmission line and the ground, and the second switch element includes: a second parallel circuit including a second transistor and a second inductor connected in parallel with the second transistor, the second parallel circuit being connected to the ground, and a second capacitor connected between the second transmission line and the second parallel circuit, wherein a characteristic impedance of the first transmission line is different from each of a first impedance seen from the first antenna port and a second impedance seen from the first circuit port, and wherein a characteristic impedance of the second transmission line is different from each of the first impedance seen from the second antenna port and a third impedance seen from the second circuit port, wherein the first transmission line is configured to perform impedance matching between a first characteristic impedance of the first antenna port and the first circuit port and a second characteristic impedance different from the first characteristic impedance at a connection point of the first switch element, and when the wavelength of the signal for which the single-pole double-throw switch is directed is λ, the length between the first antenna port and the first circuit port and the connection point is a length of λ / 4, and The second transmission line is configured to perform impedance matching between a first characteristic impedance of the second antenna port and the second circuit port and a second characteristic impedance different from the first characteristic impedance at a connection point of the second switch element, and when a wavelength of a signal for which the single-pole double-throw switch is intended is λ, a length between the second antenna port and the second circuit port and the connection point is a length of λ / 4, The first transmission line comprises: a first transmission line portion connected to the first antenna port and having the first characteristic impedance; a first impedance conversion circuit connected to the first transmission line section and configured to perform impedance matching between the second characteristic impedance and the first characteristic impedance of the first transmission line section; a second transmission line section having the second characteristic impedance and connected to the first impedance conversion circuit; and a second impedance conversion circuit connected between the second transmission line portion and the first circuit port and configured to perform impedance matching between the first characteristic impedance and the second characteristic impedance, and The second transmission line comprises: a third transmission line portion connected to the second antenna port and having the first characteristic impedance; a third impedance conversion circuit connected to the third transmission line section and configured to perform impedance matching between the second characteristic impedance and the first characteristic impedance of the third transmission line section; a fourth transmission line section having the second characteristic impedance and connected to the third impedance conversion circuit; and a fourth impedance conversion circuit connected between the fourth transmission line portion and the second circuit port and configured to perform impedance matching between the first characteristic impedance and the second characteristic impedance, and wherein the first switching element is connected to the second transmission line portion, and the second switching element is connected to the fourth transmission line section, wherein the first impedance conversion circuit, the second impedance conversion circuit, the third impedance conversion circuit, and the fourth impedance conversion circuit are set to characteristic impedances that are values ​​of square roots of products of the first characteristic impedance and the second characteristic impedance, The first impedance conversion circuit, the second impedance conversion circuit, the third impedance conversion circuit and the fourth impedance conversion circuit are stub circuits. 2 . The single-pole double-throw switch of claim 1 , wherein a characteristic impedance of each of the first transmission line and the second transmission line is a value of a square root of a product of the first characteristic impedance and the second characteristic impedance.

3. The single-pole double-throw switch according to claim 1, wherein the impedance of the first switching element when the first transistor is conducting and the impedance of the first switching element when the first transistor is non-conducting are arranged at point symmetric positions in the frequency of the signal for which the single-pole double-throw switch is intended on a Smith chart with the second characteristic impedance as a reference, and The impedance of the second switching element when the second transistor is conductive and the impedance of the second switching element when the second transistor is non-conductive are set at point-symmetrical positions in the frequency of the signal to which the single-pole double-throw switch is directed on a Smith chart with the second characteristic impedance as a reference.

4. A single-pole double-throw switch, comprising: First port; Second port; The third port; A first switch unit, wherein the first switch unit is connected between the first port and the second port; The first switch unit comprises: a first antenna port, the first antenna port being connected to the first port, a first circuit port, the first circuit port being connected to the second port, a first transmission line configured to couple the first antenna port to the first circuit port, and A first switch element, wherein the first switch element is connected between the first transmission line and ground, and the first switch element comprises: a first parallel circuit including a first transistor and a first inductor connected in parallel with the first transistor, the first parallel circuit being connected to the ground, and a first capacitor connected between the first transmission line and the first parallel circuit, and A second switch unit, wherein the second switch unit is connected between the first port and the third port; the second switch unit comprises: a second antenna port, the second antenna port being connected to the first port, a second circuit port, the second circuit port being connected to the third port, a second transmission line configured to couple the second antenna port to the second circuit port, and A second switch element, the second switch element is connected between the second transmission line and the ground, and the second switch element includes: a second parallel circuit including a second transistor and a second inductor connected in parallel with the second transistor, the second parallel circuit being connected to the ground, and a second capacitor connected between the second transmission line and the second parallel circuit, wherein a characteristic impedance of the first transmission line is different from each of a first impedance seen from the first antenna port and a second impedance seen from the first circuit port, and wherein a characteristic impedance of the second transmission line is different from each of the first impedance seen from the second antenna port and a third impedance seen from the second circuit port, wherein the first transmission line is configured to perform impedance matching between a first characteristic impedance of the first antenna port and the first circuit port and a second characteristic impedance different from the first characteristic impedance at a connection point of the first switch element, and when the wavelength of the signal for which the single-pole double-throw switch is directed is λ, the length between the first antenna port and the first circuit port and the connection point is a length of λ / 4, and The second transmission line is configured to perform impedance matching between a first characteristic impedance of the second antenna port and the second circuit port and a second characteristic impedance different from the first characteristic impedance at a connection point of the second switch element, and when a wavelength of a signal for which the single-pole double-throw switch is intended is λ, a length between the second antenna port and the second circuit port and the connection point is a length of λ / 4, The first transmission line comprises: a first transmission line portion connected to the first antenna port and having the first characteristic impedance; a first impedance conversion circuit connected to the first transmission line section and configured to perform impedance matching between the second characteristic impedance and the first characteristic impedance of the first transmission line section; a second transmission line section having the second characteristic impedance and connected to the first impedance conversion circuit; and a second impedance conversion circuit connected between the second transmission line portion and the first circuit port and configured to perform impedance matching between the first characteristic impedance and the second characteristic impedance, and The second transmission line comprises: a third transmission line portion connected to the second antenna port and having the first characteristic impedance; a third impedance conversion circuit connected to the third transmission line section and configured to perform impedance matching between the second characteristic impedance and the first characteristic impedance of the third transmission line section; a fourth transmission line section having the second characteristic impedance and connected to the third impedance conversion circuit; and a fourth impedance conversion circuit connected between the fourth transmission line portion and the second circuit port and configured to perform impedance matching between the first characteristic impedance and the second characteristic impedance, and wherein the first switching element is connected to the second transmission line portion, and the second switching element is connected to the fourth transmission line section, wherein the first impedance conversion circuit, the second impedance conversion circuit, the third impedance conversion circuit, and the fourth impedance conversion circuit are set to characteristic impedances that are values ​​of square roots of products of the first characteristic impedance and the second characteristic impedance, The first impedance conversion circuit, the second impedance conversion circuit, the third impedance conversion circuit and the fourth impedance conversion circuit are π-type impedance converters. 5 . The single-pole double-throw switch of claim 4 , wherein a characteristic impedance of each of the first transmission line and the second transmission line is a value of a square root of a product of the first characteristic impedance and the second characteristic impedance.

6. The single-pole double-throw switch according to claim 4, wherein the impedance of the first switching element when the first transistor is conducting and the impedance of the first switching element when the first transistor is non-conducting are arranged at point symmetric positions in the frequency of the signal for which the single-pole double-throw switch is intended on a Smith chart with the second characteristic impedance as a reference, and The impedance of the second switching element when the second transistor is conductive and the impedance of the second switching element when the second transistor is non-conductive are set at point-symmetrical positions in the frequency of the signal to which the single-pole double-throw switch is directed on a Smith chart with the second characteristic impedance as a reference.

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