A clock generating circuit and a clock generator

Abstract

The present invention provides a clock generation circuit and generator. First, the first signal is phase sampled according to a reference signal, and then low-pass filtered to extract a low-frequency clock phase signal; at the same time, the second signal is phase sampled according to the reference signal, and then band-pass filtered to extract an intermediate-frequency clock phase signal. Then, the clock phase signal output by the low-pass filter and the clock phase signal output by the band-pass filter are superimposed and synthesized, and then the synthesized signal is smoothed by a phase-locked loop to output a slowly varying clock signal. Finally, the phase of the clock signal output by the phase-locked loop is adjusted with reference to a long-term frequency stable signal, and its phase is made consistent with the phase of the long-term frequency stable signal by increasing or decreasing the phase, thereby outputting a high-stability clock signal. The circuit provided in this embodiment is simple to implement, requires fewer components to be added, has a small hardware volume, and is low in cost.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a clock generating circuit and a clock generator. Background Art

[0002] 5G communication has faster data transmission rate, lower response delay and higher throughput, and is one of the development trends of future network communication. Currently, operators and equipment manufacturers are intensively deploying 5G communication networks and gradually putting them into commercial use. In 5G communication networks, many links require accurate and stable clocks to ensure efficient and high-quality communication of the network.

[0003] In the prior art, high-stability clocks are mainly generated in the following two ways: (1) Generated directly by atomic clocks. This implementation method has the highest stability, but is bulky and expensive. (2) Provide long-term frequency stability through GPS signals and provide short-term frequency stability and low jitter through OCXO signals. This implementation method has high stability, but is bulky and expensive.

[0004] Therefore, those skilled in the art need to provide a low-cost clock generator. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a clock generation circuit and a clock generator with lower cost.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A clock generation circuit, comprising:

[0008] A first phase sampler, a second phase sampler, a low pass filter, a band pass filter, a synthetic signal generator, a phase locked loop and a phase adjuster;

[0009] The input end of the first phase sampler is used to obtain a first signal with a preset frequency, and perform phase sampling on the first signal based on a reference signal;

[0010] The input end of the second phase sampler is used to obtain a second signal with a preset frequency, and perform phase sampling on the second signal based on a reference signal;

[0011] The input end of the low-pass filter is connected to the output end of the first phase sampler, and is used to perform low-pass filtering on the sampling signal of the first phase sampler;

[0012] The input end of the bandpass filter is connected to the output end of the second phase sampler, and is used to perform bandpass filtering on the sampling signal of the second phase sampler;

[0013] The input end of the synthetic signal generator is connected to the output end of the low-pass filter and the output end of the band-pass filter, and is used to integrate the phase sampling signal of the low-pass filter and the phase sampling signal after the band-pass filter to obtain a clock phase signal;

[0014] The input end of the phase-locked loop is connected to the output end of the synthetic signal generator, and is used to obtain and process the clock phase signal and output a clock signal;

[0015] The first input end of the phase adjuster is used to obtain the first signal, and the second input end of the phase adjuster is connected to the output end of the phase-locked loop, and is used to adjust the phase of the clock signal output by the phase-locked loop based on the phase of the first signal, so that the phase of the clock signal output by the phase-locked loop is consistent with the phase of the first signal.

[0016] Optionally, in the above clock generation circuit, the first signal is a GPS signal, the second signal is a TCXO signal, and the reference signal is an XO signal.

[0017] Optionally, in the above-mentioned clock generation circuit, the reference signal is a reference signal whose jitter value is less than a preset value.

[0018] Optionally, in the above clock generation circuit, the preset value is not greater than 100fs RMS.

[0019] A clock generator, comprising any one of the clock generating circuits described above.

[0020] In the above scheme provided by the embodiment of the present invention, the clock generation circuit first performs phase sampling on the first signal according to the reference signal, and then performs low-pass filtering to extract the low-frequency clock phase signal; at the same time, the second signal is phase sampled according to the reference signal, and then performs band-pass filtering to extract the intermediate frequency clock phase signal. Then, the clock phase signal output by the low-pass filter and the clock phase signal output by the band-pass filter are superimposed and synthesized, and then the synthesized signal is smoothed through the phase-locked loop to output a slowly varying clock signal. Finally, the phase of the clock signal output by the phase-locked loop is adjusted with reference to the long-term frequency stable signal, and its phase is made consistent with the phase of the long-term frequency stable signal by increasing or decreasing the phase, thereby outputting a high-stable clock signal. The circuit provided in this embodiment is simple to implement, requires fewer components to be added, has a small hardware volume, and is low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0022] Figure 1 A schematic diagram of the structure of a clock generation circuit disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Embodiment 1:

[0026] See also Figure 1 , Figure 1 A schematic diagram of the structure of a clock generation circuit disclosed in an embodiment of the present application.

[0027] In the technical solutions disclosed in the embodiments of this application, see Figure 1 The clock generation circuit comprises:

[0028] A first phase sampler 100, a second phase sampler 200, a low pass filter 300, a band pass filter 400, a synthetic signal generator 500, a phase locked loop 600 and a phase adjuster 700;

[0029] The input end of the first phase sampler is used to obtain a first signal with a preset frequency, and the first signal is phase sampled based on the reference signal to obtain a signal V1, that is, the first phase collector samples the first signal when detecting the arrival of a set time in each cycle of the reference signal. The set time may refer to the rising edge, falling edge or other time of the reference signal. In this solution, the first signal may refer to a long-term frequency stable signal, and its type may be selected according to user needs. For example, in this solution, the first signal may be a GPS (Global Positioning System) signal. The reference signal may be a low-jitter signal, for example, an XO signal (oscillation signal) with a jitter value less than a preset value. The size of the preset value may be selected according to user needs. For example, in this solution, the preset value is not greater than 100fs RMS. 。

[0030] The input end of the second phase sampler is used to obtain a second signal with a preset frequency, and the phase of the second signal is sampled based on the reference signal to obtain a signal V3, that is, the second phase collector samples the second signal when detecting the arrival of a set time in each cycle of the reference signal, and the set time may refer to the rising edge, falling edge or other time of the reference signal; in this solution, the second signal may refer to a short-term frequency stable signal, and its type may be selected according to user needs. For example, in this solution, the second signal may be a TCXO (Temperature Compensate X'tal (crystal) Oscillator, temperature compensated quartz crystal resonator) signal.

[0031] The input end of the low-pass filter 300 is connected to the output end of the first phase sampler 100, and is used to perform low-pass filtering on the sampling signal V1 of the first phase sampler 100 to obtain a signal V2, that is, the first phase collector sends the collected first signal to the low-pass filter 300, and the low-pass filter 300 performs low-pass filtering on the sampling signal and then outputs a signal V2, wherein V2 is a low-frequency clock phase signal;

[0032] The input end of the bandpass filter 400 is connected to the output end of the second phase sampler 200, and is used to perform bandpass filtering on the sampling signal of the second phase sampler 200, that is, the second phase collector 200 sends the collected second signal to the bandpass filter 400, and the bandpass filter 400 performs bandpass filtering on the sampling signal and then outputs a signal V4, wherein V4 is an intermediate frequency clock phase signal.

[0033] The input end of the synthetic signal generator 500 is connected to the output end of the low-pass filter 300 and the output end of the band-pass filter 400, and is used to integrate the phase sampling signal of the low-pass filtering and the phase sampling signal after the band-pass filtering to obtain the clock phase signal V5, that is, after obtaining the low-frequency clock phase signal V2 and the intermediate-frequency clock phase signal V4, the synthetic signal generator superimposes and synthesizes the two and outputs the clock phase signal V5;

[0034] The input end of the phase-locked loop 600 is connected to the output end of the synthetic signal generator 500, and is used to obtain and process the clock phase signal, that is, after smoothing the clock phase signal V5, output a slowly varying clock signal V6;

[0035] The first input end of the phase adjuster 700 is used to obtain the first signal, and the second input end of the phase adjuster is connected to the output end of the phase-locked loop, and is used to adjust the phase of the clock signal output by the phase-locked loop based on the phase of the first signal, so that the phase of the clock signal output by the phase-locked loop is consistent with the phase of the first signal, and output the adjusted clock signal, and use the adjusted clock signal as a high-stable clock signal. In the technical solution disclosed in the application embodiment, the phase adjuster can be implemented by a phase interpolator (interpolating between different phase clocks output by the phase-locked loop) or by an adjustable delay device (adjusting the number of levels, load, and drive strength of a multi-stage clock buffer).

[0036] It can be understood that in the above scheme, signal V2 is a clock phase signal with low frequency, long-term stable frequency and low jitter, and signal V4 is a clock phase signal with medium frequency, short-term stable frequency and low jitter. The clock signal V5 synthesized by superimposing V2 and V4 through the synthetic signal generator 500 is a clock phase signal with low medium frequency, long-term and short-term stable frequency and low jitter.

[0037] Using the GPS signal as the first signal to generate the highly stable clock signal ensures the long-term frequency stability of the highly stable clock signal, using the TCXO signal as the second signal to generate the highly stable clock signal ensures the short-term frequency stability of the highly stable clock signal, and generating the highly stable clock signal through a low-jitter XO signal ensures the low jitter of the highly stable clock signal, thereby ensuring that the generated clock signal has both long-term frequency stability and short-term frequency stability and has high stability.

[0038] The clock generation circuit provided in this embodiment first performs phase sampling on the long-term frequency stable signal GPS signal according to the reference signal, and then performs low-pass filtering to extract the low-frequency clock phase signal; at the same time, the short-term frequency stable signal TCXO signal is phase sampled according to the reference signal, and then band-pass filtered to extract the intermediate frequency clock phase signal. Then, the clock phase signal output by the low-pass filter and the clock phase signal output by the band-pass filter are superimposed and synthesized, and then the synthesized signal is smoothed through the phase-locked loop to output a slowly varying clock signal. Finally, the phase of the clock signal output by the phase-locked loop is adjusted with reference to the long-term frequency stable signal, and its phase is made consistent with the phase of the long-term frequency stable signal by increasing or decreasing the phase, thereby outputting a high-stability clock signal. The circuit provided in this embodiment is simple to implement, requires fewer components to be added, has a small hardware volume, and is low in cost.

[0039] Corresponding to the above circuit, the present application also discloses a clock generator, which can be applied with the clock generation circuit described in any one of the above embodiments of the present application.

[0040] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0041] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock generation circuit, characterized in that: include: A first phase sampler, a second phase sampler, a low pass filter, a band pass filter, a synthetic signal generator, a phase locked loop and a phase adjuster; The input end of the first phase sampler is used to obtain a first signal with a preset frequency, and perform phase sampling on the first signal based on a reference signal; The input end of the second phase sampler is used to obtain a second signal with a preset frequency, and perform phase sampling on the second signal based on a reference signal; The input end of the low-pass filter is connected to the output end of the first phase sampler, and is used to perform low-pass filtering on the sampling signal of the first phase sampler; The input end of the bandpass filter is connected to the output end of the second phase sampler, and is used to perform bandpass filtering on the sampling signal of the second phase sampler; The input end of the synthetic signal generator is connected to the output end of the low-pass filter and the output end of the band-pass filter, and is used to integrate the phase sampling signal of the low-pass filter and the phase sampling signal after the band-pass filter to obtain a clock phase signal; The input end of the phase-locked loop is connected to the output end of the synthetic signal generator, and is used to obtain and process the clock phase signal and output a clock signal; The first input end of the phase adjuster is used to obtain the first signal, and the second input end of the phase adjuster is connected to the output end of the phase-locked loop, and is used to adjust the phase of the clock signal output by the phase-locked loop based on the phase of the first signal, so that the phase of the clock signal output by the phase-locked loop is consistent with the phase of the first signal; The first signal is a GPS signal, and the second signal is a TCXO signal.

2. The clock generation circuit according to claim 1, characterized in that: include: The reference signal is an XO signal.

3. The clock generation circuit according to claim 1, characterized in that: The reference signal is a reference signal whose jitter value is less than a preset value.

4. The clock generation circuit according to claim 1, characterized in that: The preset value is no greater than 100 fs RMS.

5. A clock generator, characterized in that: A clock generating circuit comprising the clock generating circuit described in any one of claims 1 to 4.

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