Silicon carbide semiconductor device and method for manufacturing the same

Abstract

The present invention provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, which can efficiently and accurately form a base region having a high concentration region at a portion separated from a trench sidewall. ‑ type channel region (2a), in the lateral direction with p ‑ The p-type high concentration region (2b) is adjacent to the n-type channel region (2a). The impurity concentration of the p-type high concentration region (2b) is in the vertical direction. ++ The peak concentration is shown at the depth where the p-type source region (4) is separated, and decreases as the depth of the peak concentration moves toward the source side and the drain side. The lateral impurity concentration of the p-type high concentration region (2b) is ++ The peak concentration is shown just below the p-type contact region (5), and becomes lower as it moves toward the trench (6). The p-type high concentration region (2b) is used to form a p ++ The ion implantation mask used in the ion implantation of the type contact region (5) is formed by implanting ions with an acceleration energy higher than the acceleration energy of the ion implantation.

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same. Background Art

[0002] Silicon carbide (SiC) has a wider band gap than silicon (Si), so the maximum electric field strength is greater than that of silicon, and therefore it is highly anticipated as a semiconductor material that can sufficiently reduce on-resistance. In addition, in semiconductor devices that use silicon carbide as a semiconductor material (hereinafter referred to as silicon carbide semiconductor devices), low on-resistance is sought, and a trench gate structure is adopted in a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: insulated gate field effect transistor) that is easy to structurally obtain low on-resistance characteristics.

[0003] The trench gate structure is a MOS gate structure in which a MOS gate is buried in a trench formed on the front side of a semiconductor substrate. In the trench gate structure, a channel (n-type inversion layer) is formed in the longitudinal direction (depth direction) along the sidewall of the trench in the p-type base region. By reducing the thickness of the p-type base region, the channel length is shortened, and low on-state resistance can be achieved due to short channelization, but new problems arise due to the increase in short channel effect. Therefore, a structure for improving the problems caused by the increase in short channel effect is proposed (for example, refer to the following patent document 1).

[0004] The following Patent Document 1 discloses the following structure: ++ A p-type source region is disposed directly below the trench source region and is spaced a predetermined distance from the trench sidewall and is adjacent to the portion of the p-type base region where the channel is formed and has an impurity concentration higher than that of the p-type base region. + Type area. + The type region is to suppress the p-type base region and n-type region. ++ The depletion layer extending from the pn junction of the p-type source region and the pn junction of the p-type base region and the n-type current diffusion region into the p-type base region is called the halo region. The halo region is formed by ion implanting p-type impurities from an oblique direction into the sidewall of the trench (hereinafter referred to as oblique ion implantation).

[0005] A conventional silicon carbide semiconductor device without a halo region is shown in FIG. Fig.13 . Fig.13 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. Fig.13 The conventional silicon carbide semiconductor device 110 shown is a vertical MOSFET without a halo region. The semiconductor substrate 130 is formed of silicon carbide. + The n -The silicon carbide epitaxial substrate is formed by forming the silicon carbide epitaxial layers 131 and 132 of the p-type drift region 101 and the p-type base region 102. By reducing the thickness t101 of the p-type silicon carbide epitaxial layer 132, the channel length L is shortened, and a short channel can be achieved.

[0006] A first p-type semiconductor substrate 130 is selectively provided inside the semiconductor substrate 130 at a position deeper from the front surface of the semiconductor substrate 130 and closer to the drain side than the bottom surface of the trench 106. + Type region 121, second p + Type area 122. The first p + The type region 121 is opposite to the bottom surface of the trench 106. + The type region 122 is selectively provided between adjacent trenches 106 (mesa region) in a manner separated from the trenches 106. + Type region 121, second p + The gate insulating film is provided with a gate region 122, thereby suppressing the electric field applied to the gate insulating film during turn-off and improving the withstand voltage. Reference numerals 111 to 113 are metal films constituting the source electrode.

[0007] To this Fig.13 A method for manufacturing the conventional silicon carbide semiconductor device 110 shown will be described. Fig.14 The flowchart is a schematic diagram of a conventional method for manufacturing a silicon carbide semiconductor device. + Type n is accumulated on the starting substrate - The ion implantation is repeated under different conditions. - The n-type current diffusion region 103 and the first p-type silicon carbide epitaxial layer 131 are selectively formed inside. + Type region 121, second p + Type area 122. - The n-type silicon carbide epitaxial layer 131 has n-type current diffusion region 103 and first p-type silicon carbide epitaxial layer 131. + Type region 121, second p + The portion outside the mold area 122 is n - Type drift region 101.

[0008] Next, in n -A p-type silicon carbide epitaxial layer 132 is deposited on top of the p-type silicon carbide epitaxial layer 131 (step S101). Next, n-type impurities or p-type impurities for gate threshold voltage control (hereinafter referred to as channel ion implantation) are ion-implanted into the p-type silicon carbide epitaxial layer 132 (step S102). Next, the outer periphery of the p-type silicon carbide epitaxial layer 132 is removed, and the p-type silicon carbide epitaxial layer 132 is left in the active region in a mesa shape (step S103). Next, the p-type silicon carbide epitaxial layer 132 is subjected to an ion implantation process for forming an n-type impurity. ++ Ion implantation of the type source region 104 is performed (step S104).

[0009] Next, the p-type silicon carbide epitaxial layer 132 is subjected to a process for forming a p ++ In the process of step S105, ion implantation of the type contact region 105 is performed by multi-stage (here, three-stage) ion implantation with different acceleration energies to form a box-shaped profile. ++ The ion implantation conditions of the third stage are to use monovalent aluminum (Al + ) are dopants, and their acceleration energies are set to 160keV, 90keV, and 40keV, respectively. ++ Type source region 104 and p ++ The portion other than the p-type contact region 105 is the p-type base region 102 .

[0010] Next, a predetermined voltage-resistant structure is formed in the edge termination region surrounding the active region (step S106). Next, a heat treatment is performed to activate all impurities ion-implanted into the semiconductor substrate 130 (step S107). Next, a groove 106 is formed at a predetermined depth from the front surface of the semiconductor substrate 130 (step S108). Next, a gate electrode 108 is formed inside the groove 106 via a gate insulating film 107 (step S109). Then, a source electrode and a drain electrode (not shown) are formed on both sides of the semiconductor substrate 130 as surface electrodes (step S110), thereby completing the process. Fig.13 MOSFET shown.

[0011] Next, a method for manufacturing a conventional silicon carbide semiconductor device including a halo-shaped region will be described. Fig.15 This is a flowchart schematically showing another example of a conventional method for manufacturing a silicon carbide semiconductor device. Fig.15 The conventional method for manufacturing a silicon carbide semiconductor device shown in Fig.14The difference of the manufacturing method of the conventional silicon carbide semiconductor device 110 shown is that a halo region is formed by oblique ion implantation into the trench sidewall (step S118) after forming the trench (step S117) and before forming the gate electrode (step S120). Heat treatment for impurity activation (step S119) is performed after forming the halo region.

[0012] By controlling the acceleration energy of the inclined ion implantation in step S118, a halo-shaped region can be formed at a portion at a predetermined distance from the trench sidewall, and the p-type impurity concentration of the portion of the p-type base region along the trench sidewall can be relatively reduced. The portion of the p-type base region along the trench sidewall is the portion where the channel is formed. Fig.15 The steps S111 to S117 and S119 to S121 of the conventional method for manufacturing a silicon carbide semiconductor device are respectively Fig.14 The steps S101 to S106 , S108 , S107 , S109 , and S110 of the conventional method for manufacturing the silicon carbide semiconductor device 110 are the same.

[0013] As a method of relatively reducing the impurity concentration of the portion of the p-type base region where the channel is formed, the following method has been proposed. - The p-type drift region is formed inside the p-type base region. + At this time, the p-type impurities are + The type area diffuses inward and outward, and the p + The portion adjacent to the p-type region is inverted to p-type to become a p-type region (for example, refer to Patent Document 2 below). In Patent Document 2 below, the portion that is inverted to p-type to become a p-type region is formed in a portion of the p-type base region along the trench sidewall, thereby relatively reducing the impurity concentration of the portion of the p-type base region where the channel is formed.

[0014] Prior art literature

[0015] Patent Literature

[0016] Patent Document 1: Japanese Patent Application Publication No. 2017-168665

[0017] Patent Document 2: Japanese Patent Application Publication No. 2007-281265 Summary of the invention

[0018] Technical issues

[0019] As described above, by providing a halo-shaped region in the MOSFET, even if the channel length is shortened to achieve low on-state resistance, the increase of the short channel effect (the effect of the depletion layer extending from the source side and the drain side to the p-type base region) can be suppressed when the MOSFET is turned on, and the reduction of the gate threshold voltage can be suppressed. Therefore, both low on-state resistance and high gate threshold voltage can be taken into account.

[0020] However, when the halo region is formed by tilted ion implantation into the trench sidewall, the formation position of the halo region is easily deviated, and there is a concern that the characteristics of each unit cell (cell) formed in a semiconductor wafer surface may deviate significantly. The main reasons for the deviation in the formation position of the halo region include the size of the trench, the angle of the trench sidewall, the position of the ion implantation source from the trench sidewall, and the position of the unit cell (component unit of the element) in a single surface of the semiconductor crystal.

[0021] In addition, when the halo-shaped region is formed by oblique ion implantation into the trench sidewall (see Fig.15 ), since the conventional method for manufacturing the silicon carbide semiconductor device 110 which does not have a halo region (refer to Fig.14 ) changes the process sequence, so production management becomes complicated due to changes in production line design. In addition, since it is necessary to perform inclined ion implantation ( Fig.15 Therefore, the pre-processing time for forming the halo-shaped area becomes longer.

[0022] The present invention aims to solve the above-mentioned problems of the prior art and to provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device capable of efficiently and with good dimensional accuracy forming a base region having a high concentration region at a portion separated from a trench sidewall.

[0023] Technical Solution

[0024] In order to solve the above problems and achieve the purpose of the present invention, the silicon carbide semiconductor device of the present invention has the following characteristics. A first semiconductor layer of a first conductivity type is provided on the front surface of a semiconductor substrate composed of silicon carbide. A second semiconductor layer is provided at a position closer to the front surface side of the semiconductor substrate than the first semiconductor layer, forming the front surface of the semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided on the surface of the second semiconductor layer. A second semiconductor region of a second conductivity type is selectively provided on the surface of the second semiconductor layer.

[0025] The third semiconductor region of the second conductivity type is the portion of the second semiconductor layer excluding the first semiconductor region and the second semiconductor region. The impurity concentration of the third semiconductor region is lower than the impurity concentration of the second semiconductor region. The high concentration region of the second conductivity type is a portion of the third semiconductor region. The high concentration region is opposite to the second semiconductor region in the depth direction. The low concentration region of the second conductivity type is the portion of the third semiconductor region excluding the high concentration region. The low concentration region is opposite to the high concentration region in a direction parallel to the front surface of the semiconductor substrate, and is opposite to the first semiconductor region and the first semiconductor layer in the depth direction.

[0026] The trench penetrates the first semiconductor region and the low concentration region from the front surface of the semiconductor substrate and reaches the first semiconductor layer. The gate electrode is arranged inside the trench via a gate insulating film. The first electrode is electrically connected to the first semiconductor region and the second semiconductor region. The second electrode is arranged on the back surface of the semiconductor substrate. The impurity concentration of the high concentration region decreases as it approaches the low concentration region in a direction parallel to the front surface of the semiconductor substrate.

[0027] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, a width of the high concentration region is wider than a width of the second semiconductor region.

[0028] In addition, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the high concentration region is opposed to the first semiconductor region and the second semiconductor region in the depth direction. The impurity concentration of the high concentration region decreases as it moves from the depth position where the impurity concentration becomes maximum toward the front side and the back side of the semiconductor substrate, respectively. The depth position where the impurity concentration of the high concentration region becomes maximum is separated from the first semiconductor region in the depth direction.

[0029] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, a distance from the high concentration region to the trench is not less than 0.04 μm and not more than 0.2 μm.

[0030] Furthermore, in the silicon carbide semiconductor device of the present invention, in the above invention, a distance from the high concentration region to the trench is not less than 0.06 μm and not more than 0.1 μm.

[0031] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the method for manufacturing a silicon carbide semiconductor device of the present invention has the following characteristics. A first step is performed to deposit a first semiconductor layer of the first conductivity type composed of silicon carbide having an impurity concentration lower than the impurity concentration of the above-mentioned starting substrate on the surface of a first conductivity type starting substrate composed of silicon carbide. A second step is performed to form a second semiconductor layer of the second conductivity type composed of silicon carbide on the surface of the above-mentioned first semiconductor layer, thereby forming a semiconductor substrate having the above-mentioned starting substrate on the back and the above-mentioned second semiconductor layer on the front. A third step is performed to selectively form a first semiconductor region of the first conductivity type on the surface of the above-mentioned second semiconductor layer. A fourth step is performed to form an ion implantation mask having an opening at a predetermined position on the surface of the above-mentioned second semiconductor layer. A fifth step is performed to form a second semiconductor region of the second conductivity type having an impurity concentration higher than the impurity concentration of the above-mentioned second semiconductor layer on the surface of the above-mentioned second semiconductor layer by performing a first ion implantation of a second conductivity type impurity using the above-mentioned ion implantation mask.

[0032] A sixth step is performed by performing a second ion implantation of a second conductive type impurity at an acceleration energy higher than that of the first ion implantation using the ion implantation mask, thereby forming a second conductive type high concentration region having an impurity concentration higher than that of the second semiconductor layer and lower than that of the second semiconductor region at a position closer to the back side of the semiconductor substrate than the second semiconductor region inside the second semiconductor layer, and leaving a portion of the second semiconductor layer other than the first semiconductor region, the second semiconductor region, and the high concentration region as a second conductive type low concentration region opposite to the high concentration region in a direction parallel to the front side of the semiconductor substrate, thereby forming a second conductive type third semiconductor region composed of the high concentration region and the low concentration region. A seventh step is performed to form a trench that penetrates the first semiconductor region and the low concentration region from the front side of the semiconductor substrate to reach the first semiconductor layer. An eighth step is performed to form a gate electrode inside the trench via a gate insulating film. A ninth step is performed to form a first electrode electrically connected to the first semiconductor region and the second semiconductor region. A tenth step of forming a second electrode on the back surface of the semiconductor substrate is performed.

[0033] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, the fifth step and the sixth step are performed continuously.

[0034] Furthermore, the method for manufacturing a silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, in the sixth step, a range of the second ion implantation is set to a position deeper than the first semiconductor region.

[0035] In addition, the method for manufacturing a silicon carbide semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the above-mentioned 11th step is further included after the above-mentioned 5th step and before the above-mentioned 6th step, and in the 11th step, the width of the opening portion of the above-mentioned ion implantation mask is widened.

[0036] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above invention, in the sixth step, a distance from the high concentration region to the trench is set to be greater than or equal to 0.04 μm and less than or equal to 0.2 μm.

[0037] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above invention, a distance from the high concentration region to the trench is set to be not less than 0.06 μm and not more than 0.1 μm.

[0038] In addition, the manufacturing method of the silicon carbide semiconductor device of the present invention is characterized in that, in the above-mentioned invention, in the above-mentioned sixth step, the second conductive type impurity injected by the above-mentioned second ion diffuses in a direction parallel to the front surface of the above-mentioned semiconductor substrate, and the impurity concentration of the above-mentioned high concentration region decreases as it approaches the above-mentioned low concentration region in a direction parallel to the front surface of the above-mentioned semiconductor substrate.

[0039] In addition, the method for manufacturing a silicon carbide semiconductor device of the present invention is characterized in that, in the above-mentioned invention, in the above-mentioned sixth step, the second conductive type impurity implanted by the above-mentioned second ion is diffused in a direction parallel to the front surface of the above-mentioned semiconductor substrate, and the width of the above-mentioned high concentration region is wider than the width of the opening portion of the mask for ion implantation.

[0040] According to the above invention, since the p-type high concentration region functions as a HALO region, the increase of the short channel effect is suppressed, and the gate threshold voltage is suppressed from decreasing, so that a high gate threshold voltage and a low on-resistance can be achieved at the same time, and the leakage current during the turn-off period can be suppressed. In addition, according to the above invention, when forming the p-type high concentration region to become the HALO region, the ion implantation is not performed obliquely toward the trench sidewall as in the prior art, so the p-type high concentration region can be formed efficiently and with good dimensional accuracy.

[0041] Effects of the Invention

[0042] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, there is an effect that a base region having a high concentration region in a portion separated from a trench sidewall can be formed efficiently with good dimensional accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0044] Figure 2 Yes means Figure 1 Characteristic diagram of impurity concentration distribution at the cutting line AA'.

[0045] Figure 3 Yes means Figure 1 Characteristic diagram of impurity concentration distribution at cutting line BB'.

[0046] Figure 4 This is a flowchart showing an overview of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0047] Figure 5 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0048] Figure 6 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0049] Figure 7 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0050] Figure 8 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0051] Fig. 9 This is a cross-sectional view showing a state of a silicon carbide semiconductor device according to the second embodiment during manufacturing.

[0052] Fig.10 This is a cross-sectional view showing a state of a silicon carbide semiconductor device according to the second embodiment during manufacturing.

[0053] Fig.11 This is a characteristic diagram schematically showing the distribution of impurities implanted into the silicon carbide epitaxial layer by ion implantation.

[0054] Fig.12 This is a characteristic diagram showing the relationship between the peak concentration of the first portion of the p-type high concentration region and the spacing distance in Example 2.

[0055] Fig.13 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0056] Fig.14 This is a flowchart showing an overview of a conventional method for manufacturing a silicon carbide semiconductor device.

[0057] Fig.15 This is a flowchart schematically showing another example of a conventional method for manufacturing a silicon carbide semiconductor device.

[0058] Explanation of symbols

[0059] 1:n - Drift zone

[0060] 2: p-type base region

[0061] 2a: p - Channel Region

[0062] 2b: p-type high concentration region

[0063] 2c to 2e: The first to third parts of the p-type high concentration region

[0064] 3: n-type current diffusion region

[0065] 4:n ++ Type source region

[0066] 5: p ++ Type contact area

[0067] 6: Groove

[0068] 7: Gate insulation film

[0069] 8: Gate electrode

[0070] 9: Interlayer insulation film

[0071] 9a: Contact hole

[0072] 10: Silicon carbide semiconductor device

[0073] 11: Silicide layer

[0074] 12: Source electrode

[0075] 13, 14: n-type buffer

[0076] 15:n + Type Drain

[0077] 16: Drain

[0078] 21: p of the groove bottom + Type region (first p + Type area)

[0079] 22: P of the countertop area + Type region (second p + Type area)

[0080] 22a, 22b: p + Type Area

[0081] 23: n-type region

[0082] 30: Semiconductor substrate

[0083] 31:n + Type starting substrate

[0084] 32~35, 51: Silicon carbide epitaxial layer

[0085] 41: Mask for ion implantation

[0086] 41a, 41a': openings of the mask for ion implantation

[0087] 42-44: Ion implantation

[0088] 52: Predetermined points for ion implantation into silicon carbide epitaxial layer

[0089] d1:n ++ The depth of the source region

[0090] d2: p ++ Depth of contact area

[0091] d3: The depth from the front surface of the semiconductor substrate to the interface between the p-type base region and the n-type current diffusion region

[0092] d4: Depth position of the peak concentration of the first portion of the p-type high concentration region from the front surface of the semiconductor substrate

[0093] L: Channel length

[0094] Tch: The distance between the first part of the p-type high concentration region and the trench (separation distance)

[0095] w1:p ++ Width of contact area

[0096] w2: width of the p-type high concentration region

[0097] w11, w12: Width of the opening of the ion implantation mask

[0098] x2a, x2b: Length of the p-type impurity to diffuse laterally from the end of the opening of the ion implantation mask DETAILED DESCRIPTION

[0099] Hereinafter, preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, the layers and regions prefixed with n or p respectively indicate that electrons or holes are majority carriers. In addition, the + and - marked on n and p respectively indicate that the impurity concentration is higher and lower than that of the unmarked layers and regions. It should be noted that in the following descriptions of the embodiments and the accompanying drawings, the same symbols are marked for the same configurations, and repeated descriptions are omitted.

[0100] (Implementation Method 1)

[0101] The structure of the silicon carbide semiconductor device according to the first embodiment will be described. Figure 1 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 1 2 shows two adjacent unit cells (component units) of a vertical MOSFET using silicon carbide as a semiconductor material. Figure 1 Only a portion of the unit cells arranged in the active region are illustrated, and the edge termination region surrounding the active region is omitted (in Figures 5 to 10 The active region refers to a region where current flows when the semiconductor device is in the on state.

[0102] The edge termination region is the region between the active region and the side of the chip (the end of the semiconductor substrate 30), and is n - The drift region 1 is a region that relaxes the electric field on the front side of the semiconductor substrate 30 and maintains a withstand voltage (voltage resistance). The edge termination region is configured with a withstand voltage structure such as a guard ring, a p-type region constituting a junction termination extension (JTE) structure, a field plate, and a surface field reduction. The withstand voltage refers to the limit voltage at which a semiconductor device will not malfunction or be destroyed.

[0103] Figure 2 , Figure 3 It means respectively Figure 1 Characteristic diagram of the impurity concentration distribution at the cutting line A-A' and the cutting line B-B'. Figure 2 2 shows the impurity concentration distribution of the p-type high concentration region 2b of the p-type base region 2 in the depth direction (vertical direction) from the front surface of the semiconductor substrate 30. Figure 3 2 shows the effective impurity concentration distribution of the p-type high concentration region 2 b of the p-type base region 2 in the direction parallel to the front surface of the semiconductor substrate 30 (lateral direction). Figure 2 , Figure 3 The impurity concentration distribution of the p-type high concentration region 2b is obtained by the first ion implantation 43 (see Figure 7 ) is obtained by the longitudinal and lateral diffusion of the p-type impurities produced.

[0104] Figure 1 to Figure 3 The silicon carbide semiconductor device 10 of the first embodiment shown is a vertical MOSFET having a trench gate structure in an active region of a semiconductor substrate 30, and has a p-type base region (third semiconductor region) 2 composed of portions 2a and 2b having different impurity concentrations. The semiconductor substrate 30 is formed on an n-type substrate. + The n-type drain region 15 + The front surface of the n-type starting substrate (third semiconductor layer) 31 is sequentially formed into n-type buffer regions 14, 13, and n- -A silicon carbide epitaxial substrate (semiconductor chip) is obtained by epitaxially growing each of silicon carbide epitaxial layers 32 to 35 of the p-type drift region 1 and the p-type base region 2.

[0105] On the front side (p - A MOS gate having a trench gate structure is provided on the main surface of the silicon carbide epitaxial layer (second semiconductor layer) 35. The MOS gate is composed of a p-type base region 2, an n-type ++ Type source region (first semiconductor region) 4, p ++ The trench 6 penetrates the p-type contact region (second semiconductor region) 5, the trench 6, the gate insulating film 7 and the gate electrode 8. The trench 6 penetrates the p-type contact region (second semiconductor region) 5, the trench 6, the gate insulating film 7 and the gate electrode 8 in the depth direction from the front surface of the semiconductor substrate 30. - type silicon carbide epitaxial layer 35 and reaches n - The silicon carbide epitaxial layer (first semiconductor layer) 34 is formed. The depth direction refers to the direction from the front surface of the semiconductor substrate 30 toward the back surface.

[0106] The trench 6 is provided in a stripe shape extending in a direction parallel to the front surface of the semiconductor substrate 30, for example. Inside the trench 6, a gate insulating film 7 is provided along the inner wall of the trench 6. A gate electrode 8 is provided on the gate insulating film 7 in a manner buried in the trench 6. Between adjacent trenches 6 (mesa regions), as described later, p-type base regions 2, n-type base regions 3, and n-type base regions 4 are selectively provided. ++ Type 4 source region and p ++ Type contact region 5. Each portion between the centers of adjacent mesa regions constitutes one unit cell.

[0107] With p - The contact method of the n-type silicon carbide epitaxial layer 35 (p-type base region 2) is - The surface layer of the source side (source electrode 12 side) of the type silicon carbide epitaxial layer 34 is provided with an n-type current diffusion region 3. The n-type current diffusion region 3 is connected to the n-type silicon carbide epitaxial layer 34. - The conductivity type of drift region 1 is the same, and the impurity concentration is higher than n - The n-type region with a high drift region 1 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. Inside the n-type current spreading region 3, the bottom surface of the trench 6 is closed.

[0108] The n-type current diffusion region 3 reaches the side wall of the trench 6 in a direction parallel to the front surface of the semiconductor substrate 30. In addition, the n-type current diffusion region 3 reaches a position deeper than the bottom surface of the trench 6 closer to the drain (the drain 16 side) from the interface with the p-type base region 2. - The portion of the n-type silicon carbide epitaxial layer 34 other than the n-type current diffusion region 3 and the n-type region 23 described later is n-type. - n-type drift region 1. n-type current diffusion region 3 with n -The contact between the p-type drift region 1 and the p-type base region 2 is arranged in an n - type drift region 1 and the p-type base region 2.

[0109] First p + Type region 21, second p + Type area 22. The first p + The first p-type region 21 is arranged at a position deeper than the interface between the p-type base region 2 and the n-type current diffusion region 3 and closer to the drain side so as to be separated from the p-type base region 2. + The type region 21 is provided at a position closer to the drain side than the trench 6 and is opposed to the bottom surface of the trench 6 in the depth direction. + The depth of the molded area 21 can be varied. + Type region 21 can be connected with n - Type drift region 1 contact.

[0110] Second p + Type region 22 with the first p + The second p-type region 21 is separated from the p-type base region 21 and is arranged between adjacent trenches 6 (mesa region). + The type region 22 can be located closer to the drain side than the bottom surface of the trench 6, and can be connected to the n - The first p-type drift region 1 is contacted by forming a first p-type drift region 1 at a position deeper than the bottom surface of the trench 6 and closer to the drain side. + Type region 21, second p + The n-type region 22 and the n-type current diffusion region 3 (or n - The pn junction of the type drift region 1) can alleviate the electric field concentration on the gate insulating film 7 at the bottom surface of the trench 6.

[0111] Second p + The type region 22 can be arranged, for example, in the central part of the mesa region. + The contact type region 22 is in the second p + An n-type region 23 is selectively provided directly below the n-type region 22. The n-type region 23 has a second p + The withstand voltage near the type region 22 is higher than the first p + By providing the n-type region 23, the withstand voltage near the center of the mesa region can be lower than the withstand voltage near the bottom of the trench 6, and avalanche breakdown is more likely to occur near the center of the mesa region than near the bottom of the trench 6. It should be noted that the second p + type region 22 and n type region 23.

[0112] In a way that they touch each other - The n-type silicon carbide epitaxial layer 35 is selectively provided with n++ Type 4 source region and p ++ Type contact area 5. ++ Type 4 source region and p ++ The type contact region 5 is exposed on the front surface of the semiconductor substrate 30. ++ The type source region 4 is arranged in contact with the side wall of the trench 6 and faces the gate electrode 8 via the gate insulating film 7 on the side wall of the trench 6. ++ The source region 4 reaches a depth d1 of, for example, about 0.45 μm from the front surface of the semiconductor substrate 30. ++ Type contact area 5 and n ++ The type source region 4 is arranged closer to the center side of the mesa region. ++ The width w1 of the type contact region 5 may be, for example, 1.0 μm.

[0113] p ++ The contact region 5 is located at a position closer to the semiconductor substrate 30 than the front surface of the semiconductor substrate 30. ++ The depth d1 of the type source region 4 is shallow, for example, it is terminated at a depth d2 of about 0.4 μm. ++ The contact region 5 may also extend from the front surface of the semiconductor substrate 30 to a depth of about 100 m. ++ The depth of the source region 4 is d1 and the depth is d2. - In addition to n ++ Type 4 source region and p ++ Outside the contact area 5 and n ++ Type 4 source region and p ++ The portion of the p-type contact region 5 on the drain side is the p-type base region 2. A depth d3 from the front surface of the semiconductor substrate 30 to the interface between the p-type base region 2 and the n-type current diffusion region 3 is, for example, about 1.1 μm.

[0114] In the p-type base region 2, the portion along the side wall of the trench 6 (hereinafter referred to as p - Compared with the p-type channel region 2a, the impurity concentration is higher in a portion 2b that is a predetermined distance away from the side wall of the trench 6 in a direction parallel to the front surface of the semiconductor substrate 30 (hereinafter referred to as a p-type high concentration region). - The n-type channel region (low concentration region) 2a is a portion that forms a channel (n-type inversion layer) when the MOSFET is turned on. ++ The p-type source region 4 is provided directly below (on the drain side) along the side wall of the trench 6. - Type channel region 2a and n ++ The n-type source region 4 is in contact with the n-type current diffusion region 3 , and is in contact with the gate insulating film 7 on the side wall of the trench 6 .

[0115] The p-type high concentration region (high concentration region) 2b is provided in the p ++ The contact area 5 is directly below the n ++The p-type high concentration region 2b is located directly below the p-type source region 4. The p-type high concentration region 2b is located parallel to the front surface of the semiconductor substrate 30. - The p-type high concentration region 2b is used to suppress the p-type base region 2 and the n-type channel region 2a. ++ The pn junction of the p-type source region 4 and the pn junction of the p-type base region 2 and the n-type current diffusion region 3 function as a so-called halo region of the depletion layer extending into the p-type base region 2. By providing the p-type high concentration region 2b, even if the p-type is made to have a low on-resistance, - The thickness of the p-type channel region 2a (= channel length L) is reduced, which can also suppress the increase of the short channel effect when the MOSFET is turned on and suppress the decrease of the gate threshold voltage. - If the type channel region 2a is high, an effect as a halo-shaped region is obtained.

[0116] The p-type high concentration region 2b is composed of a first portion 2c to a third portion 2e, which are formed by ion implantation 43 (see Figure 7 ) is formed by diffusion of p-type impurities generated during ion implantation 43 for forming the p-type high concentration region 2b in the depth direction (hereinafter referred to as longitudinal diffusion). The first portion 2c to the third portion 2e of the p-type high concentration region 2b are located at different depths from the front surface of the semiconductor substrate 30. In addition, the first portion 2c to the third portion 2e of the p-type high concentration region 2b are formed by diffusion of p-type impurities generated during ion implantation 43 for forming the p-type high concentration region 2b in a direction parallel to the front surface of the semiconductor substrate 30 (hereinafter referred to as lateral diffusion), thereby extending from the center side of the mesa region to the two trenches 6 and the p-type high concentration region 2b. ++ The contact region 5 extends in a manner separate from the p - type channel region 2a.

[0117] The first portion 2c (shaded portion) of the p-type high concentration region 2b represents the peak value (maximum value: hereinafter referred to as peak concentration) of the impurity concentration of the p-type high concentration region 2b. The second portion 2d and the third portion 2e (shaded portion that is sparser than the first portion 2c) of the p-type high concentration region 2b have lower impurity concentrations than the first portion 2c. The second portion 2d and the third portion 2e of the p-type high concentration region 2b are adjacent to the source side and the drain side of the first portion 2c, respectively. ++ The third portion 2e of the p-type high concentration region 2b is in contact with the n-type current diffusion region 3. Figure 1 In FIG. 1 , different shadows are used to indicate the impurity concentration distribution of the p-type high concentration region 2b generated by the longitudinal diffusion and lateral diffusion of the p-type impurity (in FIG. 1 ). Figure 8 The same is true in ).

[0118] The first portion 2c of the p-type high concentration region 2b is formed from p ++ The two ends of the type contact region 5 are respectively toward the trench 6 side and are connected to the p ++ The lengths x2a and x2b extending in a manner of separating the p-type contact region 5 do not depend on the conditions of the ion implantation 43 for forming the p-type high concentration region 2b, and are, for example, about 0.2 μm. The second portion 2d and the third portion 2e of the p-type high concentration region 2b also extend toward the trench 6 with almost the same length as the first portion 2c of the p-type high concentration region 2b. That is, the width w2 of the p-type high concentration region 2b is greater than that of the p-type high concentration region 2b. ++ The width w1 of the type contact region 5 is about 0.4 μm (=0.2 μm×2).

[0119] The first portion 2c of the p-type high concentration region 2b may be spaced apart from the sidewall of the trench 6 by a distance (hereinafter referred to as a spacing distance) Tch of, for example, 0.04 μm or more and 0.2 μm or less. When the spacing distance Tch between the first portion 2c of the p-type high concentration region 2b and the sidewall of the trench 6 is less than the above lower limit, the p - If the width of the p-type channel region 2a becomes too narrow, it cannot function as a MOSFET. If the spacing distance Tch exceeds the upper limit, the effect of the halo region as the p-type high concentration region 2b cannot be obtained.

[0120] The wider the spacing distance Tch is, the more the process margin for forming the p-type high concentration region 2b can be secured. Therefore, the lateral diffusion of the p-type impurities generated during the ion implantation 43 for forming the p-type high concentration region 2b can be suppressed. - The type channel region 2a is eliminated. By preferably setting the separation distance Tch to, for example, about 0.06 μm or more and 0.1 μm or less, the trade-off relationship between lowering the on-resistance and suppressing the reduction of the gate threshold voltage can be further improved.

[0121] The first portion 2c of the p-type high concentration region 2b is connected to the n ++ The first portion 2c of the p-type high concentration region 2b may be arranged in a manner separated from the n-type source region 4. ++ The p-type source region 4 is separated and arranged in a manner that the ... ++ The first portion 2c of the p-type high concentration region 2b may be located at a depth position where the impurity concentration of the p-type source region 4 does not decrease. ++ Type contact area 5 contact.

[0122] The depth position of the peak concentration of the first portion 2c of the p-type high concentration region 2b may be located inside the p-type high concentration region 2b, for example, at a depth d4 of about 0.4 μm or more and 1.5 μm or less from the front surface of the semiconductor substrate 30. The peak concentration of the first portion 2c of the p-type high concentration region 2b may be, for example, 1×10 17 / cm 3 Above and 1×10 18 / cm 3 The magnitude of the effect of the halo-shaped region generated by the p-type high concentration region 2b is determined by the peak concentration of the first portion 2c of the p-type high concentration region 2b.

[0123] The impurity concentration in the depth direction of the p-type high concentration region 2b shows a peak concentration at the first portion 2c, and decreases as it moves from the depth position of the peak concentration toward the source side and the drain side (see Figure 2 The impurity concentration of the p-type high concentration region 2b in the direction parallel to the front surface of the semiconductor substrate 30 is in the range of p ++ The peak concentration is shown at the part directly below the contact area 5. ++ The contact region 5 is separated and becomes lower toward the groove 6 side (refer to Figure 3 ).

[0124] The first portion 2c of the p-type high concentration region 2b may have an end shape closer to the trench 6 than the second portion 2d and the third portion 2e in a direction parallel to the front surface of the semiconductor substrate 30. Specifically, for example, between the p-type high concentration region 2b and the p - At the interface of the p-type channel region 2a, the p-type high concentration region 2b protrudes toward the groove 6 in a direction parallel to the front surface of the semiconductor substrate 30. At the first part 2c of the p-type high concentration region 2b, it can be bent into a roughly arc shape in which the distance to the side wall of the groove 6 is shortened compared with the second part 2d and the third part 2e (not shown).

[0125] The interlayer insulating film 9 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 8. The interlayer insulating film 9 is, for example, a BPSG (Boro Phospho Silicate Glass) film or an NSG (Non doped Silicate Glass) film. A contact hole 9a is provided in each mesa region, which penetrates the interlayer insulating film 9 in the depth direction and reaches the semiconductor substrate 30. The width of the contact hole 9a can be, for example, 1.5 μm. The n is exposed in the contact hole 9a. ++ Type 4 source region and p ++ Type contact area 5.

[0126] Inside the contact hole 9a, a silicide layer (first electrode) 11 is provided on the front surface of the semiconductor substrate 30 to form an ohmic contact with the semiconductor substrate 30. The silicide layer 11 may be, for example, a nickel silicide (NiSi, NiSi2) layer. A source electrode 12 is provided on the surface of the silicide layer 11 and the interlayer insulating film 9 in such a manner as to bury the contact hole 9a. The source electrode 12 is connected to the n ++ Type 4 source region and p ++ The type contact area 5 is electrically connected.

[0127] The source electrode 12 is, for example, an aluminum alloy layer such as aluminum silicon (AlSi) containing aluminum (Al). The source electrode 12 may be a laminated film obtained by sequentially laminating a barrier metal and an aluminum alloy layer. The barrier metal has the function of preventing atomic diffusion and mutual reaction between regions facing each other across the barrier metal. The barrier metal may be, for example, a titanium (Ti) film and a titanium nitride (TiN) film.

[0128] On the back side of the semiconductor substrate 30 ( + The n-type drain region 15 + The back side of the n-type starting substrate 31 is provided with n-type buffer zones 13, 14 and n- + The n-type buffer region 13 is arranged at a position closer to the back surface of the semiconductor substrate 30 than the n-type buffer region 14 and the n-type buffer region 15. + The n-type buffer region 14 is disposed at a position deep in the n-type buffer region 13 and the n-type buffer region 15. + The n-type buffer regions 13 and 14 may not be provided. + The type drain region 15 is exposed on the back surface of the semiconductor substrate 30 .

[0129] The n-type buffer region 13 is, for example, a recombination promoting layer containing an element that forms a recombination center (hole trapping center). The hole density during bipolar operation can be reduced by recombination in the n-type buffer region 13, thereby preventing the n-type + The basal plane dislocation (BPD) of the type starting substrate 31 becomes a stacking defect and moves toward n - The n-type buffer region 14 is used to suppress the expansion of the n-type drift region 1. + The stacking defect generated by the basal plane dislocation of the type starting substrate 31 is - Type drift region 1 propagates dislocation conversion layer.

[0130] A drain electrode (second electrode) 16 is provided on the entire back surface of the semiconductor substrate 30. The drain electrode 16 is connected to the n +The silicide layer on the back side of the semiconductor substrate 30 may be, for example, a laminated film formed by laminating a molybdenum (Mo) film and a nickel (Ni) film forming an ohmic contact with the semiconductor substrate 30. The thicknesses of the molybdenum film and the nickel film may be 0.7 μm and 0.1 μm, respectively.

[0131] The drain electrode 16 also serves as a drain pad. The drain electrode 16 may be, for example, a laminated film in which a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film are laminated in sequence. The thicknesses of the titanium film, the nickel film, and the gold film may be 0.25 μm, 1.45 μm, and 0.1 μm, respectively.

[0132] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the first embodiment will be described. Figure 4 This is a flowchart showing an overview of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 5 to 8 1 is a cross-sectional view showing a state of the silicon carbide semiconductor device of Embodiment 1 during the manufacturing process. Figures 5 to 8 In the embodiment, n-type buffers 14 and 13 are omitted (refer to Figure 1 ) (in Fig. 9 , Fig.10 Here, n ++ The depth d1 of the source region 4 from the front surface of the semiconductor substrate 30 is greater than p ++ The depth d2 of the type contact region 5 from the front surface of the semiconductor substrate 30 is shallow (refer to Figure 7 ) as an example.

[0133] First, if Figure 5 As shown, ready to become n + The n-type drain region 15 + Next, on n + The front surface of the n-type starting substrate 31 is sequentially formed into the respective silicon carbide epitaxial layers 32 and 33 (see Figure 1 ) epitaxial growth. In addition, on the surface of the n-type silicon carbide epitaxial layer 33, the n-type silicon carbide epitaxial layer 33 is formed by the n-type silicon carbide epitaxial layer 33. - The thickness t1 of the silicon carbide epitaxial layer 34 is made to be n - Type drift region 1 n - The silicon carbide epitaxial layer 34 is epitaxially grown.

[0134] Next, through photolithography and ion implantation of p-type impurities, n - The surface layer of the type silicon carbide epitaxial layer 34 selectively forms a first p + Type 21 and p + Type area 22a. + Type region 22a is the second p +Next, the p-type region 22 is formed by photolithography and ion implantation of n-type impurities. + An n-type region 23 is selectively formed directly below the n-type region 22 a.

[0135] Next, by photolithography and ion implantation of n-type impurities, for example, n-type impurities are implanted throughout the entire active region. - The surface layer of the type silicon carbide epitaxial layer 34 forms an n-type current diffusion region 3. The n-type current diffusion region 3, the first p + Type 21 and p + The formation order of the n-type region 22a and the n-type region 23. - The portion of the n-type silicon carbide epitaxial layer 34 closer to the drain side than the n-type current diffusion region 3 and the n-type region 23 becomes n - Type drift region 1.

[0136] Next, through epitaxial growth, n - The silicon carbide epitaxial layer 34 is thickened to a predetermined thickness t2. Next, by photolithography and ion implantation of p-type impurities, the n-type silicon carbide epitaxial layer 34 is thickened to a predetermined thickness t2. - The thickness of the silicon carbide epitaxial layer 34 is partly to reach p + The depth of the type region 22a selectively forms p + Type area 22b. + The width of the molded area 22b can be larger than p + The width of the molded area 22a is narrow. + Type regions 22a, 22b, thereby forming a second p + Type area 22.

[0137] Next, by photolithography and ion implantation of n-type impurities, n-type impurities are added in a manner such that they are spread over the entire active region. - The portion of the thickness of the first p-type silicon carbide epitaxial layer 34 is formed into an n-type region that becomes the n-type current diffusion region 3, thereby increasing the thickness of the n-type current diffusion region 3. + Type region 21, second p + Type region 22 contacts the first p + Type zone 21 and p + n-type current diffusion region 3 is formed between the p-type region 22. + The n-type region 22 b and the n-type region to become the n-type current diffusion region 3 are formed in this order.

[0138] Next, in n - type silicon carbide epitaxial layer 34, so that the p - The n type silicon carbide epitaxial layer 35 is epitaxially grown (step S1: second step). +A semiconductor substrate (semiconductor wafer) 30 is obtained by sequentially depositing silicon carbide epitaxial layers 32 to 35 on a starting substrate 31 of the type. - The type silicon carbide epitaxial layer 35 can be formed by - Next, ion implantation (channel ion implantation) of n-type impurities or p-type impurities for controlling gate threshold voltage is performed on the p-type silicon carbide epitaxial layer 35 (step S2).

[0139] Next, remove p - The outer periphery of the silicon carbide epitaxial layer 35 is formed by making the p - The n-type silicon carbide epitaxial layer 35 remains in a mesa shape (step S3). As a result, in the edge termination region, n-type silicon carbide epitaxial layer 35 is exposed on the front surface of the semiconductor substrate 30. - Next, by photolithography and ion implantation of n-type impurities, for example, n-type silicon carbide epitaxial layer 34 is formed in the p-type active region. - The surface layer of the type silicon carbide epitaxial layer 35 forms n ++ Type source region 4 (step S4: third process).

[0140] Next, if Figure 6 As shown in p - The surface of the silicon carbide epitaxial layer 35 is formed on the surface of the p ++ The ion implantation mask 41 has an opening 41a at a portion corresponding to the formation region of the p-type contact region 5. Next, the ion implantation mask 41 is used as a mask to perform ion implantation (first ion implantation) 42 of p-type impurities from a direction substantially perpendicular to the front surface of the semiconductor substrate 30. - The surface layer of the type silicon carbide epitaxial layer 35 is formed so as to penetrate the n ++ The depth d2 of the type source region 4 selectively forms p ++ The ion implantation 42 may be performed in multiple stages (multiple times).

[0141] For example, by using multiple stages at different acceleration energies ( Figure 4 The ion implantation 42 is the 2nd to 4th level, forming a box-shaped profile of p ++ The conditions for the third-stage ion implantation 42 may be, for example, monovalent aluminum (Al + ) are dopants, and their acceleration energies are set to 160keV, 90keV and 40keV, respectively. - In addition to the n-type silicon carbide epitaxial layer 35 ++ Type 4 source region and p ++ The portion other than the p-type contact region 5 is the p-type base region 2 .

[0142] In addition, after the above-mentioned ion implantation 42, as Figure 7 As shown, using the same ion implantation mask 41 as a mask, p-type impurity ion implantation (second ion implantation) 43 is performed from a direction substantially perpendicular to the front surface of the semiconductor substrate 30. - The p-type high concentration region 2b is selectively formed inside the p-type silicon carbide epitaxial layer 35 (step S5-2: sixth step). ++ The ion implantation 42 of the contact region 5 is carried out with high acceleration energy (at Figure 4 In the process of step S5, the order of ion implantation 42 and 43 may be changed.

[0143] Due to the use of ++ The ion implantation mask 41 has an opening 41a in a portion corresponding to the formation region of the type contact region 5, so that the ion implantation mask 41 can be formed in the p ++ The p-type impurity is ion-implanted 43 directly below the p-type contact region 5. The p-type impurity is vertically diffused by the ion implantation 43, so that Figure 8 As shown in p ++ A p-type high concentration region 2b having first to third parts 2c to 2e with different impurity concentrations is formed directly below the p-type contact region 5. The first part 2c of the p-type high concentration region 2b is formed near the depth of the range of the ion implantation 43, and the second part 2d and the third part 2e are formed on the source side and the drain side, respectively, from the depth of the range of the ion implantation 43.

[0144] In addition, the p-type impurity injected by ion implantation 43 is injected from the end of the opening 41a of the ion implantation mask 41 with a length x2a and x2b of about 0.2 μm (see Figure 1 ) Start with p ++ Therefore, the p-type high concentration region 2b is diffused laterally from the p-type contact region 5. ++ The contact area 5 extends directly below n ++ The width w2 of the p-type high concentration region 2b is about 0.4 μm (= 0.2 μm × 2) wider than the width w11 of the opening 41a of the ion implantation mask 41. The vertical and horizontal peak concentrations of the impurity concentration of the p-type high concentration region 2b are determined by the dose of the ion implantation 43.

[0145] The conditions for the ion implantation 43 may be, for example, divalent aluminum (Al 2+ ) is a dopant, and its acceleration energy is set to, for example, 700 keV. The ion implantation 43 may be performed in multiple stages (multiple times). The portion of the p-type base region 2 other than the p-type high concentration region 2b is the p-type base region 2. - That is, the p-type base region 2 has a p -The channel region 2a has a p-type channel region 2a without impurities being introduced by ion implantation 42 and 43. - The region of impurity concentration during the epitaxial growth of the silicon carbide epitaxial layer 35. The process of step S4 and the process of step S5 can be interchanged.

[0146] Next, after removing the ion implantation mask 41, a predetermined voltage-resistant structure is formed in the edge termination region (step S6). For the ion implantation mask used in all ion implantations performed in this manufacturing process, a resist film may be used as a mask, or an oxide film may be used as a mask. Next, a heat treatment is performed to activate all impurities implanted into the semiconductor substrate 30 in an ion manner (step S7). Next, a through-n structure is formed. ++ The p-type source region 4 and the p-type base region 2 - The first p-type channel region 2a reaches the inside of the n-type current diffusion region 3 + The groove 6 of the mold area 21 (step S8: seventh process).

[0147] Next, by a conventional method, polysilicon (poly-Si) is buried inside the trench 6 via the gate insulating film 7, thereby forming the gate electrode 8 (step S9: the eighth process). Thereafter, a silicide layer 11 and a source electrode 12 are formed on the front surface of the semiconductor substrate 30 as surface electrodes. A silicide layer (not shown) and a drain 16 are formed on the back surface of the semiconductor substrate 30 as surface electrodes (step S10: the ninth and tenth processes). Thereafter, the semiconductor substrate 30 is singulated (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10 having a p-type base region having a p-type high concentration region 2b.

[0148] As described above, according to Embodiment 1, the p-type base region is separated from the trench sidewall by a portion thereof. - The p-type channel region has a p-type high concentration region adjacent to the p-type channel region. The impurity concentration of the p-type high concentration region is ++ The peak concentration is shown directly below the p-type contact region, and in the direction parallel to the front surface of the semiconductor substrate, the concentration decreases as the p - Since the p-type high concentration region functions as a HALO region, the increase of the short channel effect is suppressed and the gate threshold voltage is suppressed from decreasing. Therefore, a high gate threshold voltage and a low on-resistance can be achieved at the same time, and the leakage current during shutdown can be suppressed.

[0149] In addition, according to Embodiment 1, by using the ++The ion implantation mask used in the ion implantation of the p-type contact region can form a p-type high concentration region having the above-mentioned impurity concentration distribution by ion implanting p-type impurities from a direction substantially perpendicular to the front surface of the semiconductor substrate. When forming the p-type high concentration region to become the HALO region, since the ion implantation is not performed obliquely toward the side wall of the trench as in the prior art, the p-type high concentration region can be formed with good dimensional accuracy. Therefore, the characteristic deviation of each unit cell formed within the surface of one semiconductor wafer can be suppressed.

[0150] In addition, according to Embodiment 1, by only increasing the number of ++ The p-type high concentration region can be formed by increasing the number of ion implantation stages (number of times) in the ion implantation process of the p-type contact region. Therefore, the method for manufacturing a silicon carbide semiconductor device without a halo region is equivalent to the conventional method (refer to Fig.14 ) There is almost no change in the number of processes and the order of processes. There is no need to change the design of the production line, and the pre-processing time can be shortened compared to the case where the p-type high concentration region is formed by oblique ion implantation into the trench sidewall. Therefore, the p-type high concentration region of the p-type base region can be effectively formed.

[0151] (Implementation Method 2)

[0152] Next, refer to Figures 4 to 6 , Figure 8 to Figure 10 A method for manufacturing a silicon carbide semiconductor device according to the second embodiment will be described. Fig. 9 , Fig.10 1 is a cross-sectional view showing a state of the silicon carbide semiconductor device of the second embodiment during the manufacturing process. The method for manufacturing the silicon carbide semiconductor device of the second embodiment is to apply the method for manufacturing the silicon carbide semiconductor device 10 of the first embodiment, and further shorten the spacing distance Tch between the first portion 2c of the p-type high concentration region 2b and the side wall of the trench 6 (see Figure 1 ) is a method for manufacturing a silicon carbide semiconductor device.

[0153] In the method for manufacturing a silicon carbide semiconductor device according to the second embodiment, first, the processes of steps S1 to S4 are sequentially performed in the same manner as in the first embodiment (see Figure 4 , Figure 5 ). Next, similarly to the first embodiment, a ++ An ion implantation mask 41 having an opening 41a is formed in a portion corresponding to the formation region of the p-type contact region 5. The ion implantation mask 41 is used as a mask to perform ion implantation 42 of p-type impurities, thereby selectively forming a p-type contact region 5. ++ Type contact area 5 (refer to Figure 6 ).

[0154] Next, if Fig. 9As shown in FIG. 1 , the width w12 of the opening 41a′ of the ion implantation mask 41 is widened by photolithography and etching. Fig.10 As shown, it will form p ++ The ion implantation mask 41 having an opening 41a' wider than the width w12 is used as a mask, and ion implantation (second ion implantation) 44 of p-type impurities is performed from a direction substantially perpendicular to the front surface of the semiconductor substrate 30. - A p-type high concentration region 2 b is selectively formed inside the p-type silicon carbide epitaxial layer 35 (step S5 ).

[0155] The conditions of the ion implantation 44 are, for example, the same as those of the ion implantation 43 in the first embodiment. By the ion implantation 44, as in the first embodiment, ++ The p-type high concentration region 2b of the p-type base region 2 is formed directly below the p-type contact region 5. The p-type impurity implanted by ion implantation 44 diffuses laterally by about 0.2 μm from the end of the opening 41a′ of the ion implantation mask 41 expanded by the width w12.

[0156] In the second embodiment, as described above, during the ion implantation 44 for forming the p-type high concentration region 2b, the ion implantation 44 is performed in the same manner as that for forming the p-type high concentration region 2b. ++ The ion implantation mask 41 having a wider width w12 of the opening 41a' is used compared to the ion implantation 42 of the p-type contact region 5. As a result, since the width w2 of the p-type high concentration region 2b is wider than that in the case where the p-type high concentration region 2b is formed in the first embodiment, the spacing distance Tch between the first portion 2c of the p-type high concentration region 2b and the side wall of the trench 6 can be further shortened.

[0157] Instead of the ion implantation mask 41, an ion implantation mask having an opening of width w12 may be newly formed, and the newly formed ion implantation mask may be used as a mask to perform ion implantation 44. Thereafter, the processes of steps S6 to S10 are sequentially performed in the same manner as in the first embodiment (see Figure 4 ), thereby completing a silicon carbide semiconductor device in which the spacing distance Tch between the first portion 2c of the p-type high concentration region 2b and the side wall of the trench 6 is further shortened.

[0158] As described above, according to Embodiment 2, the same effects as those of Embodiment 1 can be obtained. According to Embodiment 2, by increasing the opening width of the ion implantation mask used for ion implantation to form the p-type high concentration region, the spacing distance of the first portion of the p-type high concentration region can be further shortened.

[0159] (Example 1)

[0160] Next, the lateral diffusion of the p-type impurities ion-implanted into the silicon carbide epitaxial layer was verified. Fig.11 FIG. 1 is a characteristic diagram schematically showing the distribution of impurities ion-implanted into a silicon carbide epitaxial layer. Fig.11 This is the result of a simulation of the spread of p-type impurities ion-implanted from a predetermined point (1 point) 52 on the surface (ion implantation surface) of the silicon carbide epitaxial layer 51. Fig.11 In FIG. 5 , a range 53 where a large amount of p-type impurities exist is indicated by hatching, and illustration of p-type impurities extending to positions outside the range 53 is omitted. It should be noted that the extension of p-type impurities can be inferred by a scanning capacitance microscope, a scanning nonlinear dielectric microscope, a scanning microwave microscope, or the like.

[0161] Fig.11 The horizontal axis is the depth from the ion implantation surface of the silicon carbide epitaxial layer 51. Fig.11 The vertical axis is the predetermined point of the ion implantation surface of the p-type impurity from the silicon carbide epitaxial layer 51. The length of the lateral diffusion in the direction parallel to the ion implantation surface (lateral direction) is 1 / 2. The cutting line CC' passes through the predetermined point 52 of the ion implantation surface of the silicon carbide epitaxial layer 51 and is perpendicular to the ion implantation surface. The conditions for ion implantation of p-type impurities into the silicon carbide epitaxial layer 51 are to use divalent aluminum (Al 2+ ) is a dopant, and its acceleration energy is set to, for example, 700 keV.

[0162] according to Fig.11 The results shown confirmed that the p-type impurity ion-implanted from a predetermined point 52 on the ion-implanted surface of the silicon carbide epitaxial layer 51 diffused longitudinally from the ion-implanted surface of the silicon carbide epitaxial layer 51 and diffused laterally almost symmetrically around the predetermined point 52. In addition, it was confirmed that the length x2' of the lateral diffusion at a depth of about 0.4 μm from the ion-implanted surface of the silicon carbide epitaxial layer 51 was about 0.2 μm.

[0163] (Example 2)

[0164] Next, the relationship between the peak concentration of the first portion 2 c of the p-type high concentration region 2 b and the separation distance Tch between the first portion 2 c of the p-type high concentration region 2 b and the side wall of the trench 6 was verified. Fig.12 This is a characteristic diagram showing the relationship between the peak concentration of the first portion of the p-type high concentration region and the spacing distance in Example 2. Fig.12 The horizontal axis of is the peak concentration of the first portion of the p-type high concentration region, and the vertical axis is the gate threshold voltage Vth of the silicon carbide semiconductor device 10 of Embodiment 1. The drain-source voltage applied to the silicon carbide semiconductor device 10 is set to 20V.

[0165] according to Fig.12 The results shown confirm that, when the spacing distance Tch is wider than 0.1 μm, the gate threshold voltage Vth is difficult to change regardless of the peak concentration of the first part 2c of the p-type high concentration region 2b. In addition, it is also confirmed that the narrower the spacing distance Tch, the higher the gate threshold voltage Vth. Therefore, the present invention is beneficial when the spacing distance Tch is less than 0.1 μm. In addition, it is confirmed that the higher the peak concentration of the first part of the p-type high concentration region, the higher the gate threshold voltage Vth can be.

[0166] The present invention is not limited to the above-mentioned embodiments, and various changes can be made without departing from the scope of the present invention. ++ The ion implantation conditions for the p-type contact region and the p-type high concentration region are just examples and can be variously set according to specifications and the like.

[0167] Industrial Applicability

[0168] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like.

Claims

1. A silicon carbide semiconductor device, characterized in that: have: a semiconductor substrate composed of silicon carbide; a first semiconductor layer of a first conductivity type, disposed on the front side of the semiconductor substrate; a second semiconductor layer disposed at a position closer to the front side of the semiconductor substrate than the first semiconductor layer, forming the front side of the semiconductor substrate; a first semiconductor region of a first conductivity type, which is selectively disposed on a surface of the second semiconductor layer; a second semiconductor region of a second conductivity type, which is selectively disposed on the surface of the second semiconductor layer; a third semiconductor region of the second conductivity type, which is a portion of the second semiconductor layer excluding the first semiconductor region and the second semiconductor region, and has an impurity concentration lower than that of the second semiconductor region; a second conductivity type high concentration region which is a part of the third semiconductor region and is opposed to the second semiconductor region in the depth direction; a second conductivity type low concentration region, which is a portion of the third semiconductor region excluding the high concentration region, and is opposed to the high concentration region in a direction parallel to the front surface of the semiconductor substrate and is opposed to the first semiconductor region and the first semiconductor layer in a depth direction; a trench extending from the front surface of the semiconductor substrate through the first semiconductor region and the low concentration region to reach the first semiconductor layer; a gate electrode disposed inside the trench via a gate insulating film; a first electrode electrically connected to the first semiconductor region and the second semiconductor region; and a second electrode disposed on the back surface of the semiconductor substrate, The impurity concentration of the high concentration region decreases as approaching the low concentration region in a direction parallel to the front surface of the semiconductor substrate. The lower surface of the high concentration region is in contact with the upper surface of the first semiconductor layer. The impurity concentration of the high concentration region decreases as it moves from a depth position where the impurity concentration is the highest toward the front side and the back side of the semiconductor substrate, respectively. A depth position where the impurity concentration of the high concentration region is maximum is separated from the first semiconductor region in the depth direction.

2. The silicon carbide semiconductor device according to claim 1, wherein: The width of the high concentration region is wider than that of the second semiconductor region.

3. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that: The distance from the high concentration region to the groove is 0.04 μ m or more and 0.2 μ m or less.

4. The silicon carbide semiconductor device according to claim 3, wherein: The distance from the high concentration region to the groove is 0.06 μ m or more and 0.1 μ m or less.

5. A method for manufacturing a silicon carbide semiconductor device, characterized in that: include: A first step is to deposit a first semiconductor layer of a first conductivity type composed of silicon carbide on a surface of a first conductivity type starting substrate composed of silicon carbide, wherein the impurity concentration of the first semiconductor layer is lower than the impurity concentration of the starting substrate; In a second step, a second semiconductor layer of a second conductivity type composed of silicon carbide is formed on the surface of the first semiconductor layer, and a semiconductor substrate is formed whose back surface is the starting substrate and whose front surface is the second semiconductor layer. A third step is to selectively form a first semiconductor region of the first conductivity type on the surface of the second semiconductor layer; A fourth step is to form an ion implantation mask having an opening at a predetermined position on the surface of the second semiconductor layer; A fifth step is to form a second semiconductor region of the second conductivity type having an impurity concentration higher than that of the second semiconductor layer on the surface of the second semiconductor layer by performing a first ion implantation of a second conductivity type impurity using the ion implantation mask; In a sixth step, by using the ion implantation mask, a second ion implantation of a second conductive type impurity is performed at an acceleration energy higher than that of the first ion implantation, thereby forming a second conductive type high concentration region inside the second semiconductor layer at a position closer to the back side of the semiconductor substrate than the second semiconductor region, the impurity concentration of the high concentration region being higher than the impurity concentration of the second semiconductor layer and lower than the impurity concentration of the second semiconductor region, and the lower surface of the high concentration region being in contact with the upper surface of the first semiconductor layer, Furthermore, a portion of the second semiconductor layer other than the first semiconductor region, the second semiconductor region and the high concentration region is left as a low concentration region of the second conductivity type facing the high concentration region in a direction parallel to the front surface of the semiconductor substrate, thereby forming a third semiconductor region of the second conductivity type composed of the high concentration region and the low concentration region; Step 7: forming a trench from the front surface of the semiconductor substrate through the first semiconductor region and the low concentration region to reach the first semiconductor layer; In an eighth step, a gate electrode is formed inside the trench via a gate insulating film; A ninth step of forming a first electrode electrically connected to the first semiconductor region and the second semiconductor region; and In a tenth step, a second electrode is formed on the back surface of the semiconductor substrate. In the sixth step, the impurity concentration of the high concentration region decreases as it moves from a depth position where the impurity concentration is maximum toward the front side and the back side of the semiconductor substrate, respectively, and the depth position where the impurity concentration of the high concentration region is maximum is separated from the first semiconductor region in the depth direction. In the sixth step, the second conductive type impurity implanted by the second ion diffuses in a direction parallel to the front surface of the semiconductor substrate, and the impurity concentration of the high concentration region decreases as it approaches the low concentration region along the direction parallel to the front surface of the semiconductor substrate.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein: The fifth step and the sixth step are performed continuously.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein: In the sixth step, a range of the second ion implantation is set to a position deeper than the first semiconductor region.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein: The method further includes an eleventh step after the fifth step and before the sixth step, wherein the width of the opening of the ion implantation mask is increased.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein: The distance from the high concentration region to the groove is set to 0.04 μ m or more and 0.2 μ m or less.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein: The distance from the high concentration region to the groove is set to 0.06 μ m or more and 0.1 μ m or less.

11. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 5 to 10, characterized in that: In the sixth step, the second conductivity type impurity implanted by the second ion implantation diffuses in a direction parallel to the front surface of the semiconductor substrate, and the width of the high concentration region is wider than the width of the opening of the ion implantation mask.

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