Storage Devices

Abstract

A novel storage device is provided. The present invention is a storage device including a plurality of storage cells arranged in rows and columns, each storage cell including a transistor and a capacitor. The transistor includes a first gate and a second gate having regions overlapping each other across a semiconductor layer. The storage device has the function of operating in a "write mode", a "read mode", a "refresh mode" and an "NV mode". In the "refresh mode", after the data held by the storage cell is read out, the data is written again to the storage cell at a first time. In the "NV mode", after the data stored in the storage cell is read out, the data is written again to the storage cell at a second time, and then a potential that turns the transistor into an off state is supplied to the second gate. By operating in the "NV mode", data can be stored for a long period of time even if the power supply to the storage cell is stopped. Multi-valued data can be stored in the storage cell.

Description

Technical Field

[0001] One embodiment of the present invention relates to a storage device.

[0002] In addition, one embodiment of the present invention relates to an object, a method or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. One embodiment of the present invention relates to a driving method thereof or a manufacturing method thereof.

[0003] Note that in this specification, etc., a semiconductor device refers to any device that can operate by utilizing semiconductor characteristics. Storage devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic devices sometimes include semiconductor devices. In addition, storage devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic devices may also be referred to as semiconductor devices. Background Art

[0004] As semiconductor thin films that can be used for transistors, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors (OS: Oxide Semiconductor) have attracted attention. As oxide semiconductors, for example, it is known that in addition to single metal oxides such as indium oxide and zinc oxide, there are also multinary metal oxides. Among multinary metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly hot.

[0005] Through the study of IGZO, CAAC (c-axis aligned crystalline) structure and nc (nanocrystalline) structure, which are neither single crystal nor amorphous, were discovered in oxide semiconductors (see non-patent documents 1 to 3). Non-patent documents 1 and 2 disclose a technology for manufacturing transistors using an oxide semiconductor having a CAAC structure. Non-patent documents 4 and 5 disclose that an oxide semiconductor having a lower crystallinity than a CAAC structure and a nc structure also has tiny crystals.

[0006] A transistor using IGZO for an active layer has an extremely small off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] In addition, various semiconductor devices using a transistor including an oxide semiconductor in a channel formation region (hereinafter also referred to as an “OS transistor”) have been proposed.

[0008] Patent Document 1 discloses an example of using OS transistors in DRAM (Dynamic Random Access Memory). Since the leakage current (off-state current) of OS transistors in the off state is extremely small, it is possible to manufacture DRAM with a low refresh frequency and low power consumption.

[0009] In addition, a nonvolatile memory using an OS transistor is disclosed in Patent Document 2. Unlike flash memory, these nonvolatile memories have no limit on the number of times they can be rewritten, so high-speed operation can be achieved more easily and power consumption is low.

[0010] In a memory using the above OS transistor, the off-state current can be reduced by increasing the threshold voltage of the OS transistor, thereby improving the data retention characteristics of the memory. Patent document 2 discloses an example in which a second gate is provided in the OS transistor to control the threshold voltage of the OS transistor, thereby reducing the off-state current.

[0011] In order for the memory to retain data for a long period of time, a predetermined negative potential needs to be constantly supplied to the second gate of the OS transistor. Patent Documents 2 and 3 disclose examples of the configuration of a circuit for driving the second gate of the OS transistor.

[0012] [Prior technical literature]

[0013] [Patent Document]

[0014] [Patent Document 1] Japanese Patent Application Publication No. 2013-168631

[0015] [Patent Document 2] Japanese Patent Application Publication No. 2012-069932

[0016] [Patent Document 3] Japanese Patent Application Publication No. 2012-146965

[0017] [Non-patent literature]

[0018] [Non-patent document 1] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186

[0019] [Non-patent document 2] S. Yamazaki et al., "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10

[0020] [Non-patent document 3] S. Ito et al., "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p.151-154

[0021] [Non-patent document 4] S. Yamazaki et al., "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022

[0022] [Non-patent document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p.155-164

[0023] [Non-patent document 6] K. Kato et al., "Japanese Journal of Applied Physics", 2012, volume 51, p.021201-1-021201-7

[0024] [Non-patent document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217

[0025] [Non-patent document 8] S.Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p.626-629 Summary of the invention

[0026] Technical problem to be solved by the invention

[0027] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. Another purpose of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. Another purpose of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another purpose of one embodiment of the present invention is to provide a novel semiconductor device.

[0028] The description of multiple purposes does not interfere with each other. One mode of the present invention does not necessarily have to achieve all of the above purposes. Purposes other than the above can be naturally known from the description of the specification, drawings, claims, etc., and these purposes can also become the purpose of one mode of the present invention.

[0029] Solutions to technical problems

[0030] One embodiment of the present invention is a memory device, which includes a plurality of memory cells arranged in rows and columns, each of which includes a transistor having a first gate and a second gate and a capacitor, wherein the first gate and the second gate have regions overlapping each other via a semiconductor layer containing a metal oxide. The memory device has a function of writing data to at least one of the plurality of memory cells, a function of reading data from at least one of the plurality of memory cells, a function of writing the first data to the memory cell at a first time after reading the first data held by at least one of the plurality of memory cells, and a function of writing the first data to the memory cell at a second time after reading the first data held by at least one of the plurality of memory cells, supplying a first potential to the second gate of the memory cell, and then stopping the supply of power to the plurality of memory cells, wherein the first data is multi-valued data and the second time is longer than the first time.

[0031] The semiconductor layer of the transistor preferably contains at least one or both of In and Zn. The second time is preferably 1.5 times or more of the first time. The first potential is a potential that turns the transistor into an off state. In addition, when the threshold voltage of the transistor is VthM, the first potential is preferably below -VthM.

[0032] Effects of the Invention

[0033] According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a high operating speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0034] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all of the above effects. One mode of the present invention does not need to have all of the above effects. In addition, the description of the specification, drawings, and claims, etc. clearly has effects other than the above effects, and effects other than the above effects can be obtained from the description of the specification, drawings, and claims, etc.

[0035] BRIEF DESCRIPTION OF THE DRAWINGS

[0036] [ Fig. 1 ] A diagram illustrating a structural example of a semiconductor device.

[0037] [Fig. 2] A diagram illustrating the electrical characteristics of a transistor.

[0038] [Fig. 3] A diagram illustrating a configuration example of a voltage generating circuit.

[0039] [ Fig. 4 ] A diagram illustrating a configuration example of a voltage holding circuit.

[0040] [ Figure 5 ]A diagram illustrating a structural example of a temperature detection circuit.

[0041] [ Fig. 6 ] A diagram illustrating an example of changes in voltage VBias with respect to temperature changes.

[0042] [ Figure 7 ]A timing diagram illustrating an example of the operation of a semiconductor device.

[0043] [ Figure 8 ]A diagram illustrating an example structure of a storage device.

[0044] [ Fig. 9 ]A diagram illustrating an example structure of a memory cell array.

[0045] [Fig. 10] A circuit diagram illustrating a structural example of a memory cell.

[0046] [ Fig.11 ]A diagram illustrating a structural example of a memory cell array and a bit line driver circuit.

[0047] [ Fig.12 ]A diagram illustrating an example of a circuit configuration.

[0048] [ Fig.13 ]A timing diagram illustrating an example of the operation of a storage device.

[0049] [ Fig.14 ]A timing diagram illustrating an example of the operation of a storage device.

[0050] [ Fig.15 ]A timing diagram illustrating an example of the operation of a storage device.

[0051] [ Fig.16 ]A timing diagram illustrating an example of the operation of a storage device.

[0052] [ Fig.17 ]A diagram illustrating an example structure of a storage device.

[0053] [ Fig.18 ]A diagram illustrating a structural example of a memory cell array and a bit line driver circuit.

[0054] [ Fig.19 ]A diagram illustrating a structural example of a memory cell array and a bit line driver circuit.

[0055] [ Fig. 20 ]A timing diagram illustrating an example of the operation of a storage device.

[0056] [ Fig.21 ]A timing diagram illustrating an example of the operation of a storage device.

[0057] [ Fig. 22 ]A timing diagram illustrating an example of the operation of a storage device.

[0058] [ Fig.23 ]A diagram illustrating an example structure of a storage device.

[0059] [ Fig.24 ]A diagram illustrating a structural example of a memory cell array and a bit line driver circuit.

[0060] [ Fig.25 ]A timing diagram illustrating an example of the operation of a storage device.

[0061] [ Fig.26 ]A timing diagram illustrating an example of the operation of a storage device.

[0062] [ Fig. 27 ]A timing diagram illustrating an example of the operation of a storage device.

[0063] [ Fig.28 ]A diagram illustrating an example structure of a storage device.

[0064] [ Fig.29 ]A diagram illustrating an example structure of a storage device.

[0065] [Fig. 30] A diagram illustrating a structural example of a transistor.

[0066] [Fig. 31] A diagram illustrating a structural example of a transistor.

[0067] [Fig. 32] A diagram illustrating a structural example of a transistor.

[0068] [Fig. 33] A diagram illustrating a structural example of a transistor.

[0069] [Fig. 34] A diagram illustrating a structural example of a transistor.

[0070] [Fig. 35] A diagram illustrating an example of an electronic component.

[0071] [ Fig.36 ]A diagram illustrating an example of an electronic device.

[0072] [Figure 37] A diagram illustrating an application example of a storage device.

[0073] Modes for Carrying Out the Invention

[0074] The embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments and examples shown below.

[0075] Note that in the invention structure described below, the same reference numerals are used in common in different drawings to represent the same parts or parts with the same function, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a reference numeral.

[0076] Note that in each of the drawings described in this specification, the size of each component, the thickness of a layer, and a region may be exaggerated for the sake of clarity. Therefore, the present invention is not limited to the sizes in the drawings.

[0077] In this specification, a high power supply voltage is sometimes referred to as an “H level” (also referred to as “VDD” or “H potential”), and a low power supply voltage is sometimes referred to as an “L level” (also referred to as “GND” or “L potential”).

[0078] Note that voltage refers to the potential difference between two points, while potential refers to the electrostatic energy (potential energy) of a unit charge in an electrostatic field at a certain point. Note that, in general, the potential difference between the potential of a certain point and a reference potential (e.g., ground potential) is simply referred to as potential or voltage, and potential and voltage are usually synonymous. Therefore, in this specification, "potential" may be referred to as "voltage", and "voltage" may be referred to as "potential", except for special cases.

[0079] In addition, the following embodiments and examples in this specification can be combined as appropriate. In addition, when a plurality of configuration examples are shown in one embodiment, these configuration examples can be combined as appropriate.

[0080] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, etc. For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In addition, an OS transistor may be referred to as a transistor comprising a metal oxide or an oxide semiconductor. In this specification, etc., a metal oxide comprising nitrogen is sometimes also referred to as a metal oxide.

[0081] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally off) n-channel field effect transistors, and therefore, their threshold voltage (also referred to as "Vth") is greater than 0V.

[0082] (Implementation Method 1)

[0083] <Semiconductor Device 100>

[0084] 1 is a circuit diagram showing a configuration example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a voltage generating circuit 110, a voltage holding circuit 120, a temperature detecting circuit 130, and a voltage control circuit 140. The node between the voltage holding circuit 120 and the voltage control circuit 140 is referred to as a node ND. The voltage holding circuit 120 and the voltage control circuit 140 are electrically connected to an output terminal OUT of the semiconductor device 100 via the node ND.

[0085] In addition, the semiconductor device 100 is electrically connected to the second gates of the plurality of transistors M11 through the output terminal OUT. The transistor M11 is a transistor including a first gate (also referred to as a "front gate" or simply referred to as a "gate") and a second gate (also referred to as a "back gate"). The first gate and the second gate have a region overlapping each other across the semiconductor layer. The second gate has a function of controlling the threshold voltage of the transistor M11, for example.

[0086] The transistor M11 represents a transistor used in various circuits included in a storage device, a display device, a computing device, etc. For example, it represents a transistor included in a NOR type or NAND type storage device. In addition, for example, it represents a transistor included in a display device such as a liquid crystal display device or an EL display device. In addition, for example, it represents a transistor included in a CPU (Central Processing Unit), a GPU (Graphics Processing Unit) or an FPGA (Field Programmable Gate Array).

[0087] Although three transistors M11 are shown in FIG. 1 , one embodiment of the present invention is not limited thereto, and more transistors M11 may be connected to the semiconductor device 100 .

[0088] Here, the temperature dependency of Id-Vg characteristics, which is one of the electrical characteristics of a transistor, will be described. Figure 2A and Figure 2B An example of Id-Vg characteristics, which are one of the electrical characteristics of a transistor, is shown. The Id-Vg characteristics represent changes in drain current (Id) with respect to changes in gate voltage (Vg). Figure 2A and Figure 2B The horizontal axis of shows Vg on a linear scale. Figure 2A and Figure 2B The vertical axis shows Id in a logarithmic scale.

[0089] Figure 2A The Id-Vg characteristics of the OS transistor are shown. Figure 2B Id-Vg characteristics of a transistor using silicon for a semiconductor layer in which a channel is formed (also referred to as a “Si transistor”) are shown. Figure 2A and Figure 2B Both are Id-Vg characteristics of n-channel transistors.

[0090] like Figure 2A As shown in Figure 1, the off-state current of the OS transistor is not easy to increase even when it is operated at high temperature. As the operating temperature of the OS transistor increases, the Vth drifts in the negative direction and the on-state current increases. Figure 2B As shown in Figure 1, as the temperature of the Si transistor increases, the off-state current increases. As the temperature of the Si transistor increases, the Vth drifts in the positive direction and the on-state current decreases.

[0091] Therefore, by using an OS transistor as the transistor M11, the power consumption of the entire semiconductor device including the transistor M11 can be reduced even when operating at a high temperature.

[0092] In addition, the semiconductor device 100 has a function of writing a voltage VBG to the second gate of the transistor M11 through the output terminal OUT and maintaining the voltage. For example, when a negative potential is supplied as the voltage VBG, the transistor M11 can drift the Vth in the positive direction while maintaining the negative potential of the second gate. Even when operating at a high temperature, a high Vth can be maintained. For example, when the transistor M11 is used as a selection transistor of a memory cell, the charge of a capacitor used as a memory can be maintained for a long period of time.

[0093] [Voltage generating circuit 110]

[0094] Figure 3A and Figure 3B1 shows an example of a circuit configuration of the voltage generating circuit 110. The above circuit diagram is a step-down charge pump, where GND is input to the input terminal IN and a voltage VBG0 is output from the output terminal OUT of the voltage generating circuit 110. Here, as an example, the number of stages of the basic circuit of the charge pump circuit is 4, but one embodiment of the present invention is not limited to this, and a charge pump circuit having any number of stages can also be configured.

[0095] Figure 3A The voltage generating circuit 110 a shown includes transistors M21 to M24 and capacitors C21 to C24 .

[0096] The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT, and are connected so that the gates and the first electrodes thereof function as diodes. The gates of the transistors M21 to M24 are connected to the capacitors C21 to C24, respectively.

[0097] CLK is input to the first electrodes of the capacitors C21 and C23 of the odd-numbered stages, and CLKB is input to the first electrodes of the capacitors C22 and C24 of the even-numbered stages. CLKB is an inverted clock signal obtained by inverting the phase of CLK.

[0098] The voltage generating circuit 110a has a function of generating a voltage VBG0 by stepping down the GND input to the input terminal IN. The voltage generating circuit 110a can generate a negative potential only by receiving CLK and CLKB.

[0099] The transistors M21 to M24 may be formed using OS transistors. The use of OS transistors is preferred because the reverse current of the diode-connected transistors M21 to M24 can be reduced.

[0100] Figure 3B The voltage generating circuit 110b shown in the figure is composed of transistors M31 to M34 which are p-channel transistors. For other components, refer to the description of the voltage generating circuit 110a.

[0101] The voltage generating circuit 110 may use not only a step-down charge pump but also a step-up charge pump. Alternatively, the voltage generating circuit 110 may include both a step-down charge pump and a step-up charge pump.

[0102] [Voltage holding circuit 120]

[0103] The voltage holding circuit 120 includes a transistor M12 (see Figure 1A ). A first terminal (one of the source and the drain) of the transistor M12 is electrically connected to the voltage generating circuit 110, and a second terminal (the other of the source and the drain) of the transistor M12 is electrically connected to the node ND.

[0104] The voltage holding circuit 120 has a function of supplying the voltage VBG0 generated by the voltage generating circuit 110 to the node ND by turning on the transistor M12. When the threshold voltage of the transistor M12 is set to Vth1 and the transistor M12 is turned on, a voltage of VBG0+Vth1 or higher is preferably supplied to the gate of the transistor M12. In addition, the voltage holding circuit 120 has a function of turning off the transistor M12 and holding the voltage of the node ND.

[0105] When a negative potential is supplied as the voltage VBG0, a transistor having a first gate and a second gate can be used as the transistor M12, and the first gate and the second gate can be electrically connected to the second terminal (see Figure 4A ). At this time, the transistor M12 has a diode function. In addition, when the voltage output from the transistor M12 is recorded as voltage VBG1, the following relationship holds: VBG1=VBG0+Vth1. The negative potential of the write node ND can be maintained by setting the first terminal of the transistor M12 to GND.

[0106] exist Figure 4A In the transistor M12 shown, after supplying a negative potential to the node ND, the first terminal is set to GND, and Vg becomes 0 V. Therefore, it is preferable that Id (also called "cutoff current") is small when Vg is 0 V. By making the cutoff current sufficiently small, the negative potential written to the node ND can be maintained for a long time.

[0107] The channel length of transistor M12 is preferably greater than the channel length of transistor M11. For example, when the channel length of transistor M11 is less than 1 μm, the channel length of transistor M12 is greater than 1 μm, more preferably greater than 3 μm, further preferably greater than 5 μm, and further preferably greater than 10 μm. By extending the channel length of transistor M12, transistor M12 is not affected by the short channel effect and the cut-off current can be suppressed. In addition, the withstand voltage between the source and drain of transistor M12 can be increased. When the withstand voltage between the source and drain of transistor M12 is high, the connection between the voltage generating circuit 110 that generates a high voltage and transistor M11 can be facilitated.

[0108] As the transistor M12, it is preferred to use an OS transistor or a transistor using a wide bandgap semiconductor in the channel formation region. The OS transistor or the transistor using a wide bandgap semiconductor has a small cutoff current and a high withstand voltage between the source and the drain. Note that in this specification, a wide bandgap semiconductor refers to a semiconductor with a bandgap of 2.2 eV or more. For example, silicon carbide, gallium nitride, diamond, etc. can be cited.

[0109] The transistor M12 is required to have a cut-off current smaller than that of the transistor M11. On the other hand, the transistor M11 is required to have an on-state current larger than that of the transistor M12. In this way, when transistors with different required properties are formed on the same substrate, different semiconductors can be used to form each transistor. The transistor M12 preferably uses a semiconductor having a band gap larger than that of the transistor M11 for the channel formation region. In addition, the transistor M11 preferably uses a semiconductor having a higher electron mobility than that of the transistor M12 for the channel formation region.

[0110] In addition, the voltage holding circuit 120 may be composed of a plurality of transistors M12 connected in series (see Figure 4B and Figure 4C ).

[0111] [Temperature detection circuit 130]

[0112] The temperature detection circuit 130 includes a temperature sensor 131 and an analog-to-digital conversion circuit (also referred to as “ADC”) 132 (see Figure 5 ).

[0113] The temperature sensor 131 has a function of sensing the temperature of the semiconductor device 100 and outputting an analog signal VA corresponding to the temperature. The temperature sensor 131 may be, for example, a temperature measuring resistor made of platinum, nickel or copper, a thermistor, a thermocouple, an IC temperature sensor or the like.

[0114] The analog-to-digital conversion circuit 132 has a function of converting the analog signal VA into an n-bit (n is an integer greater than or equal to 1) digital signal VD. The digital signal VD is output from the temperature detection circuit 130 and supplied to the voltage control circuit 140 .

[0115] By converting the temperature information of the analog signal measured by the temperature detection circuit 130 into a digital signal and outputting it, the signal attenuation and noise caused by wiring resistance and parasitic capacitance can be reduced. Therefore, even if the temperature detection circuit 130 is set at a position far away from the voltage control circuit 140, the temperature information can be accurately transmitted to the voltage control circuit 140.

[0116] [Voltage control circuit 140]

[0117] As reference Figure 2AAs described, the lower the temperature of the OS transistor, the more Vth drifts in the positive direction, and the on-state current decreases. As a result, the operating speed of the circuit decreases. In addition, the higher the temperature, the more Vth drifts in the negative direction, and the cut-off current increases. This is the main reason for the narrowing of the temperature range in which the circuit can operate. By using the voltage control circuit 140 to supply a correction voltage corresponding to the operating temperature to the node ND, the voltage output by the output terminal OUT of the semiconductor device 100 can be corrected, thereby expanding the temperature range in which the circuit electrically connected to the output terminal OUT can operate.

[0118] The voltage control circuit 140 includes a logic circuit 145 and a voltage generating circuit 146 (see Figure 1B ). The logic circuit 145 has a function of supplying the digital signal (temperature information) supplied by the temperature detection circuit 130 to the voltage generation circuit 146. For example, the serial signal supplied by the temperature detection circuit 130 is converted into a parallel signal and supplied to the voltage generation circuit 146. In addition, the logic circuit 145 has a function of converting the n-bit digital signal supplied by the temperature detection circuit 130 into an m-bit (m is an integer greater than 1) digital signal and supplying it to the voltage generation circuit 146.

[0119] The voltage generating circuit 146 has a function of converting the m-bit digital signal supplied from the logic circuit 145 into a 2-bit digital signal. m level voltage and output function. Figure 1B An example in which m is 4 is shown. Figure 1B The medium voltage generating circuit 146 includes a buffer BF1 , a buffer BF2 , a buffer BF3 , a buffer BF4 , a capacitor C1 , a capacitor C2 , a capacitor C4 , and a capacitor C8 .

[0120] The 4-bit digital signal output by the logic circuit 145 is supplied to the input terminals of the buffers BF1 to BF4. Specifically, the first bit of the 4-bit digital signal is input to the buffer BF1, the second bit is input to the buffer BF2, the third bit is input to the buffer BF3, and the fourth bit is input to the buffer BF4.

[0121] One electrode of capacitor C1 is electrically connected to the output terminal of buffer BF1, and the other electrode is electrically connected to the output terminal OUT. One electrode of capacitor C2 is electrically connected to the output terminal of buffer BF2, and the other electrode is electrically connected to the output terminal OUT. One electrode of capacitor C4 is electrically connected to the output terminal of buffer BF3, and the other electrode is electrically connected to the output terminal OUT. One electrode of capacitor C8 is electrically connected to the output of buffer BF4, and the other electrode is electrically connected to the output terminal OUT.

[0122] The voltage outputted from the output terminal OUT of the voltage control circuit 140 is referred to as “voltage VBias.” The output terminal OUT of the voltage control circuit 140 is electrically connected to the node ND of the semiconductor device 100 .

[0123] The voltage supplied to the node ND by the voltage control circuit 140 is determined by the ratio of the combined capacitance of the capacitors C1, C2, C4, and C8 to the parasitic capacitance generated at the node ND. The capacitance value of the capacitor C1 is preferably sufficiently greater than the capacitance value of the parasitic capacitance. Specifically, the capacitance value of the capacitor C1 is preferably 5 times or more, and more preferably 10 times or more, the capacitance value of the parasitic capacitance.

[0124] In addition, the capacitance values ​​of capacitor C1, capacitor C2, capacitor C4, and capacitor C8 may all be the same capacitance value, but preferably, the capacitance values ​​of at least some of the capacitors are different or the capacitance values ​​of all the capacitors are different. In this embodiment, the capacitance value of capacitor C2 is twice the capacitance value of capacitor C1, the capacitance value of capacitor C4 is four times the capacitance value of capacitor C1, and the capacitance value of capacitor C8 is eight times the capacitance value of capacitor C1. Thus, 16 levels of voltage can be supplied to node ND by voltage control circuit 140.

[0125] FIG. 6A to FIG. 6C An example of voltage change of voltage VBias with respect to temperature change is shown. FIG. 6A to FIG. 6C The horizontal axis shows temperature on a linear scale. FIG. 6A to FIG. 6C The vertical axis of VBias shows the voltage VBias in a linear scale. When the transistor M11 is an OS transistor, the magnitude of the voltage VBias preferably decreases as the operating temperature of the transistor M11 increases (see Fig. 6A ). In addition, depending on the purpose or application, the voltage VBias can be increased as the operating temperature increases (refer to Figure 6B ). In addition, the magnitude of the voltage VBias may also change nonlinearly with respect to temperature changes (see Figure 6C ). The voltage change of the voltage VBias with respect to the temperature change can be set by the logic circuit 145 .

[0126] <Operation Example of Semiconductor Device 100>

[0127] Figure 7 1 is a timing chart for explaining an operation example of the semiconductor device 100. In this embodiment, an operation example under the following conditions is explained: the transistor M11 is an OS transistor, and the voltage VBias changes linearly in the range of 0V to 7.5V when the operating temperature changes in the range of 100°C to -50°C. In addition, the voltage VBG is -3V when the operating temperature is 20°C.

[0128] The temperature detection circuit 130 outputs a 4-bit digital signal VD. In the present embodiment, when the operating temperature is 100°C, "0000" is output as the digital signal VD, and when the operating temperature is -50°C, "1111" is output.

[0129] In addition, when the output of the buffer BF1 connected to one electrode of the capacitor C1 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C1 rises by 0.5 V. In addition, when the output of the buffer BF2 connected to one electrode of the capacitor C2 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C2 rises by 1.0 V. In addition, when the output of the buffer BF3 connected to one electrode of the capacitor C4 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C4 rises by 2.0 V. In addition, when the output of the buffer BF4 connected to one electrode of the capacitor C8 changes from the L potential to the H potential, the potential of the other electrode of the capacitor C8 rises by 4.0 V.

[0130] [Period T0]

[0131] Period T0 is a reset period. During period T0, each output terminal of buffers BF1 to BF4 outputs an L potential (0V). In addition, voltage VBG0 is set to -7V, and transistor M12 is turned on. As a result, voltage VBG becomes -7V. During period T0, temperature detection circuit 130 can stop outputting digital signal VD. In addition, the operation of temperature detection circuit 130 can also be stopped.

[0132] [Period T1]

[0133] During the period T1, the transistor M12 is turned off, and the voltage of the node ND is maintained at -7 V. Thus, the voltage VBG is maintained at -7 V.

[0134] [Period T2]

[0135] During the period T2, the temperature detection circuit 130 supplies the digital signal VD (temperature information) to the voltage control circuit 140. For example, "1000" is supplied to the voltage control circuit 140 as the digital signal VD indicating 20°C.

[0136] The logic circuit 145 inputs a potential corresponding to the digital signal VD to the buffers BF1 to BF4. Specifically, when the digital signal VD is "1000", the buffers BF1 to BF3 are controlled so that the outputs are at an L potential and the outputs of the buffers BF4 are at an H potential.

[0137] Then, the potential of the output terminal OUT of the voltage control circuit 140 rises by 4 V. As a result, the voltage of the node ND changes from -7 V to -3 V, and the voltage VBG changes to -3 V.

[0138] [Period T3]

[0139] During the period T3, the temperature detection circuit 130 supplies the digital signal VD (temperature information) to the voltage control circuit 140. For example, "0101" is supplied to the voltage control circuit 140 as the digital signal VD indicating 50°C.

[0140] As in period T2, logic circuit 145 inputs a potential corresponding to digital signal VD to buffers BF1 to BF4. When digital signal VD is "0101", the output of buffer BF1 becomes H potential, the output of buffer BF2 becomes L potential, the output of buffer BF3 becomes H potential, and the output of buffer BF4 becomes L potential. As a result, voltage VBG becomes -4.5V.

[0141] [Period T4]

[0142] During the period T4, the temperature detection circuit 130 supplies the digital signal VD (temperature information) to the voltage control circuit 140. For example, "1100" is supplied to the voltage control circuit 140 as the digital signal VD indicating -20°C.

[0143] As in the period T2 and the period T3, the logic circuit 145 inputs a potential corresponding to the digital signal VD to the buffers BF1 to BF4. When the digital signal VD is "1100", the output of the buffer BF1 becomes an L potential, the output of the buffer BF2 becomes an L potential, the output of the buffer BF3 becomes an H potential, and the output of the buffer BF4 becomes an H potential. As a result, the voltage VBG becomes -1.0V.

[0144] In this way, the voltage VBG can be changed in response to temperature changes. In addition, without considering the temperature change of the electrical characteristics of the transistor M11, the second gate of the transistor M11 is supplied with a larger voltage than required. When the second gate of the transistor M11 is supplied with a larger voltage than required for a long time, the electrical characteristics of the transistor M11 deteriorate and the reliability may be reduced. Through one method of the present invention, the voltage supplied to the second gate of the transistor M11 can be changed in response to temperature changes. Thus, only the minimum voltage required can be supplied to the second gate of the transistor M11. Through one method of the present invention, the reliability of a semiconductor device including the transistor M11 can be improved.

[0145] Alternatively, a reset period (period T0 ) may be provided at regular intervals to refresh the voltage of the node ND.

[0146] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0147] (Implementation Method 2)

[0148] In this embodiment, a memory device using the semiconductor device 100 described in Embodiment 1 will be described.

[0149] <Storage Device>

[0150] Figure 8 The memory device 300 includes a peripheral circuit 311, a cell array 401, and a semiconductor device 100. The peripheral circuit 311 includes a row decoder 321, a word line driver circuit 322, a column decoder 331, a bit line driver circuit 330, an output circuit 340, and a control logic circuit 360.

[0151] The word line driving circuit 322 has a function of supplying a potential to the wiring WL. The bit line driving circuit 330 includes a precharge circuit 332, an amplifier circuit 333, and an input / output circuit 334. The precharge circuit 332 has a function of precharging the wiring SL (not shown), the wiring BIL, or the wiring RBL. The amplifier circuit 333 has a function of amplifying the data signal read out by the wiring BIL or the wiring RBL. In addition, the wiring WL, the wiring SL, the wiring BIL, and the wiring RBL are wirings connected to the memory cell (Memory Cell) 411 in the cell array 401, and will be described in detail later. The amplified data signal is output to the outside of the storage device 300 as a digital data signal RDATA through the output circuit 340.

[0152] The memory device 300 is supplied from the outside with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 311 , and a high power supply voltage (VIL) for the cell array 401 .

[0153] Control signals (CE, WE, RE), address signal ADDR, and data signal WDATA are also input from the outside to the memory device 300. The address signal ADDR is input to the row decoder 321 and the column decoder 331, and the data signal WDATA is input to the input / output circuit 334.

[0154] The control logic circuit 360 processes input signals (CE, WE, RE) from the outside to generate control signals for the row decoder 321 and the column decoder 331. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 360 are not limited thereto, and other control signals may be input as needed.

[0155] The above-mentioned circuits and signals can be used appropriately as needed.

[0156] OS transistors can be used as transistors constituting the cell array 401. In addition, OS transistors can be used as transistors constituting the peripheral circuit 311. By using OS transistors as the cell array 401 and the peripheral circuit 311, the cell array 401 and the peripheral circuit 311 can be manufactured using the same manufacturing process, thereby reducing manufacturing costs.

[0157] [Structural example of cell array]

[0158] exist Fig. 9 The details of the cell array 401 are described in . The cell array 401 has m (m is an integer greater than or equal to 1) cells in one column and n (n is an integer greater than or equal to 1) cells in one row, for a total of m×n memory cells 411. The memory cells 411 are arranged in rows and columns. Fig. 9 The address of the memory cell 411 is also indicated. For example, [1,1] shows the memory cell 411 at the address of the first row and the first column, and [i,j] (i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n) shows the memory cell 411 at the address of the i-th row and the j-th column. In addition, the number of wirings connecting the cell array 401 and the word line driving circuit 322 is determined by the structure of the memory cell 411 and the number of memory cells 411 in one column. In addition, the number of wirings connecting the cell array 401 and the bit line driving circuit 330 is determined by the structure of the memory cell 411 and the number of memory cells 411 in one row.

[0159] [Structural example of storage unit]

[0160] FIG. 10 shows a configuration example of storage cells 411A to 411E that can be used for the above-described storage cell 411 .

[0161] [DOSRAM]

[0162] Fig. 10A 1 shows a circuit configuration example of a DRAM type memory cell 411A. In this specification, etc., a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 411A includes a transistor M11 and a capacitor Cs.

[0163] The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the capacitor Cs is connected to the wiring GNDL. The wiring GNDL is a wiring that provides a low-level potential (also called a reference potential).

[0164] The wiring BIL is used as a bit line, and the wiring WL is used as a word line. The wiring BGL is used as a wiring for supplying a potential to the back gate of the transistor M11. In addition, the wiring BGL is electrically connected to the output terminal OUT of the semiconductor device 100. By supplying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0165] Data writing and reading are performed by supplying a high-level potential to the wiring WL to turn on the transistor M11 and electrically connect the wiring BIL and the first terminal of the capacitor Cs.

[0166] In addition, the memory cell in the memory device 300 is not limited to the memory cell 411A, and the circuit structure may be changed.

[0167] When the transistor M11 is used in a memory cell, the transistor M11 is preferably an OS transistor. In addition, the semiconductor layer of the OS transistor is preferably an oxide semiconductor containing any one of indium, element M (element M is aluminum, gallium, yttrium or tin), and zinc. In particular, an oxide semiconductor containing indium, gallium and zinc is preferably used.

[0168] The OS transistor using an oxide semiconductor containing indium, gallium, and zinc has the characteristic of extremely small off-state current. By using an OS transistor as the transistor M11, the leakage current of the transistor M11 can be made very small. In other words, the transistor M11 can be used to maintain the written data for a long time, thereby reducing the refresh frequency of the memory cell. In addition, the refresh work of the memory cell can be omitted. In addition, since the leakage current is very small, multi-value data or analog data can be maintained in the memory cell 411A.

[0169] By using an OS transistor as the transistor M11, a DOSRAM can be configured.

[0170] [NOSRAM]

[0171] Fig. 10B The circuit configuration example of a gain unit type (also referred to as "2Tr1C type") memory cell 411B including two transistors and one capacitor is shown. The memory cell 411B includes a transistor M11, a transistor M3, and a capacitor Cs.

[0172] The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring WBL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring BGL. The second terminal of the capacitor Cs is connected to the wiring RL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor Cs.

[0173] Wiring WBL is used as a write bit line, wiring RBL is used as a read bit line, and wiring WL is used as a word line. Wiring RL is used as wiring for supplying a predetermined potential to the second terminal of capacitor Cs. When data is written or data is retained, wiring RL is preferably supplied with a reference potential.

[0174] The wiring BGL is used as a wiring for supplying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal OUT of the semiconductor device 100. By supplying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0175] Data is written by supplying a high-level potential to the wiring WL to turn on the transistor M11 so that the wiring WBL is electrically connected to the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in the on state, a potential corresponding to the information to be recorded in the wiring WBL is supplied, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M3. Then, a low-level potential is supplied to the wiring WL to turn the transistor M11 into a non-conductive state, thereby maintaining the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M3.

[0176] The data is read out by supplying a predetermined potential to the wiring RL and the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, the potential held by the first terminal of the capacitor Cs (or the gate of the transistor M3) can be read out by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, the information written in the storage cell can be read out from the potential held by the first terminal of the capacitor Cs (or the gate of the transistor M3). Alternatively, it can be known whether the storage cell is written with information.

[0177] In addition, the memory cell in the above-mentioned memory device 300 is not limited to the memory cell 411B, and the circuit structure may be changed appropriately.

[0178] For example, a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL may be employed. Fig. 10C An example of the circuit structure of the memory cell in this case is shown. In the memory cell 411C, the wiring WBL and the wiring RBL of the memory cell 411B are combined into one wiring BIL, and the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. That is, in the memory cell 411C, one wiring BIL is used as a write bit line and a read bit line.

[0179] In addition, the transistor M11 of the memory cell 411B and the memory cell 411C is preferably an OS transistor. A memory device that uses an OS transistor as the transistor M11 and a 2Tr1C type memory cell like the memory cell 411B and the memory cell 411C is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

[0180] In addition, the channel formation region of the transistor M3 preferably contains silicon. In particular, the silicon may be amorphous silicon, polycrystalline silicon, or low temperature polycrystalline silicon (LTPS: Low Temperature Poly-Silicon) (hereinafter, a transistor containing such silicon will be referred to as a Si transistor). Since the field effect mobility of a Si transistor is sometimes higher than that of an OS transistor, a Si transistor is more suitable for use as a readout transistor.

[0181] In addition, when an OS transistor is used as the transistor M3, the memory cell can be formed of a unipolar circuit.

[0182] in addition, Fig. 10D The circuit configuration example of a memory cell 411D of a gain unit type (also referred to as a "3Tr1C type") having three transistors and one capacitor is shown. The memory cell 411D includes a transistor M11, a transistor M5, a transistor M6, and a capacitor Cs.

[0183] The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is electrically connected to the wiring BGL. The second terminal of the capacitor Cs is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor Cs. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RL.

[0184] The wiring BIL serves as a bit line, the wiring WL serves as a write word line, and the wiring RL serves as a read word line.

[0185] The wiring BGL is used as a wiring for supplying a potential to the back gate of the transistor M11. The wiring BGL is electrically connected to the output terminal OUT of the semiconductor device 100. By supplying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M11 can be increased or decreased.

[0186] Data is written by supplying a high-level potential to the wiring WL to turn on the transistor M11 so that the wiring BIL is connected to the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in the on state, a potential corresponding to the information to be recorded in the wiring BIL is supplied, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M5. Then, a low-level potential is supplied to the wiring WL to turn the transistor M11 into a non-conductive state, thereby maintaining the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M5.

[0187] The data is read out by precharging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and supplying a high level potential to the wiring RL. By making the wiring RL a high level potential, the transistor M6 becomes conductive, and the wiring BIL and the second terminal of the transistor M5 become electrically connected. At this time, the second terminal of the transistor M5 is supplied with the potential of the wiring BIL, but the potential of the second terminal of the transistor M5 and the potential of the wiring BIL will change in accordance with the potential maintained by the first terminal of the capacitor Cs (or the gate of the transistor M5). Here, the potential maintained by the first terminal of the capacitor Cs (or the gate of the transistor M5) can be read out by reading out the potential of the wiring BIL. In other words, the information written into the storage cell can be read out from the potential maintained by the first terminal of the capacitor Cs (or the gate of the transistor M5). Alternatively, it can be known whether the storage cell is written with information.

[0188] In addition, the circuit structure of the memory cell in the above-mentioned memory device 300 may be changed appropriately.

[0189] It is also preferable to use an OS transistor as the transistor M11 of the memory cell 411D. The 3Tr1C memory cell 411D using an OS transistor as the transistor M11 is one form of the NOSRAM described above.

[0190] The channel formation regions of the transistors M5 and M6 described in this embodiment preferably contain silicon. In particular, the silicon may be amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon. Since the field effect mobility of Si transistors is sometimes higher than that of OS transistors, Si transistors are more suitable for use as readout transistors.

[0191] In addition, when OS transistors are used as the transistors M5 and M6, the memory cell can be formed of a unipolar circuit.

[0192] [oxSRAM]

[0193] Fig. 10EAn example of a circuit structure of an SRAM (Static Random Access Memory) type memory cell 411E using an OS transistor is shown. In this specification, etc., an SRAM using an OS transistor is referred to as an oxSRAM. Fig. 10E The illustrated memory cell 411E is an SRAM type memory cell capable of backup.

[0194] The memory cell 411E includes transistors M7 to M10, transistors MS1 to MS4, capacitors Cs1 and Cs2. In addition, transistors M7 and M8 are equivalent to transistor M11. Transistors M7 to M10 are transistors including back gates. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0195] The first terminal of the transistor M7 is connected to the wiring BIL, and the second terminal of the transistor M7 is connected to the first terminal of the transistor MS1, the first terminal of the transistor MS3, the gate of the transistor MS2, the gate of the transistor MS4, and the first terminal of the transistor M10. The gate of the transistor M7 is connected to the wiring WL, and the back gate of the transistor M7 is connected to the wiring BGL1.

[0196] The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WL, and the back gate of transistor M8 is connected to wiring BGL2.

[0197] The second terminal of the transistor MS1 is electrically connected to the wiring VDL. The second terminal of the transistor MS2 is electrically connected to the wiring VDL. The second terminal of the transistor MS3 is electrically connected to the wiring GNDL. The second terminal of the transistor MS4 is connected to the wiring GNDL.

[0198] The second terminal of the transistor M9 is connected to the first terminal of the capacitor Cs1, the gate of the transistor M9 is connected to the wiring BRL, and the back gate of the transistor M9 is connected to the wiring BGL3. The second terminal of the transistor M10 is connected to the first terminal of the capacitor Cs2, the gate of the transistor M10 is connected to the wiring BRL, and the back gate of the transistor M10 is connected to the wiring BGL4.

[0199] A second terminal of the capacitor Cs1 is connected to the wiring GNDL, and a second terminal of the capacitor Cs2 is connected to the wiring GNDL.

[0200] The wiring BIL and the wiring BILB are used as bit lines, the wiring WL is used as a word line, and the wiring BRL is a wiring for controlling the conduction state and the non-conduction state of the transistor M9 and the transistor M10.

[0201] The wiring BGL1 to the wiring BGL4 serve as wiring for supplying a potential to the back gates of the transistors M7 to M10 , respectively.

[0202] The wirings BGL1 to BGL4 are electrically connected to the output terminal OUT of the semiconductor device 100. In addition, a plurality of semiconductor devices 100 may be provided for the memory device 300, and the wirings BGL1 to BGL4 may be electrically connected to different semiconductor devices 100. By supplying an arbitrary potential to the wirings BGL1 to BGL4, the threshold voltages of the transistors M7 to M10 may be increased or decreased.

[0203] The wiring VDL is a wiring for supplying a high-level potential, and the wiring GNDL is a wiring for supplying a low-level potential.

[0204] Data is written by supplying a high level potential to the wiring WL and a high level potential to the wiring BRL. Specifically, when the transistor M10 is turned on, a potential corresponding to the information to be recorded in the wiring BIL is supplied and written to the second terminal side of the transistor M10.

[0205] The storage unit 411E uses transistors MS1 and MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to the potential is input to the second terminal side of the transistor M8. Since the transistor M8 is in the on state, the potential supplied to the wiring BIL, that is, the inverted signal of the signal input to the wiring BIL is output to the wiring BILB. In addition, since the transistors M9 and M10 are in the on state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are respectively maintained by the first terminal of the capacitor Cs2 and the first terminal of the capacitor Cs1. Then, by supplying a low-level potential to the wiring WL and supplying a low-level potential to the wiring BRL, the transistors M7 to M10 are turned into a non-conductive state, thereby maintaining the potential of the first terminal of the capacitor Cs1 and the potential of the first terminal of the capacitor Cs2.

[0206] Data is read out by the following method: first, the wiring BIL and the wiring BILB are precharged to a predetermined potential, and then a high-level potential is supplied to the wiring WL and the wiring BRL, whereby the potential of the first terminal of the capacitor Cs1 is refreshed by the inverter loop of the storage unit 411E and output to the wiring BILB. In addition, the potential of the first terminal of the capacitor Cs2 is refreshed by the inverter loop of the storage unit 411E and output to the wiring BIL. Since the wiring BIL and the wiring BILB are changed from the precharged potential to the potential of the first terminal of the capacitor Cs2 and the potential of the first terminal of the capacitor Cs1, respectively, the potential held by the storage unit can be read from the potential of the wiring BIL or the wiring BILB.

[0207] In addition, OS transistors are preferably used as transistors M7 to M10. By using OS transistors as transistors M7 to M10, data written to the memory cell 411E can be retained for a long period of time, thereby reducing the refresh frequency of the memory cell 411E. In addition, the refresh operation of the memory cell 411E can be omitted. In addition, since the leakage current is very small, multi-value data or analog data can be retained in the memory cell 411E.

[0208] In addition, the channel formation regions of transistors MS1 to MS4 preferably contain silicon. In particular, the silicon may be amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon. Since the field effect mobility of Si transistors is sometimes higher than that of OS transistors, Si transistors are suitable for use as transistors in inverters.

[0209] In addition, by using OS transistors in memory cells, information written to the memory cells can be retained for a long time even when power supply to the memory cells is stopped. Thus, power supply to part or all of the peripheral circuit 311 can be stopped during a period when writing and reading of information is not required.

[0210] One semiconductor device 100 may be electrically connected to all the memory cells. Alternatively, a plurality of semiconductor devices 100 may be provided for the memory device 300 so that each column or each plurality of columns of memory cells are electrically connected to one semiconductor device 100. Alternatively, each row or each plurality of rows of memory cells may be electrically connected to one semiconductor device 100. Alternatively, a plurality of memory cells in the cell array may be divided into a plurality of area blocks, and a semiconductor device 100 may be provided in each area block or each plurality of area blocks.

[0211] The storage unit described in this embodiment can be used for storage elements such as registers and cache memories in a CPU, a GPU, or the like.

[0212] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0213] (Implementation 3)

[0214] In this embodiment, a configuration example and an operation example of the cell array 401 included in the memory device 300 are described. In this embodiment, a DRAM type memory cell 411A is used as the memory cell 411.

[0215] Fig.11 Shows different from Fig. 9 An example of a cell array 401. Fig.11 This is a folded bit-line memory cell array. Note that the memory cell 411A can also be used in an open bit-line memory cell array.

[0216] exist Fig.11 In the cell array 401 shown, there are m (m is an integer greater than 1) cells in one column and n (n is an integer greater than 1) cells in one row, for a total of m×n memory cells 411A, and the memory cells 411A are arranged in rows and columns. Fig.11 In FIG. 4 , the address of the storage unit 411A is also indicated. For example, [i, j] represents the storage unit 411A at the i-th row and the j-th column.

[0217] in addition, Fig.11 The cell array 401 shown includes m wirings WL electrically connected to the word line driving circuit 322. The wiring WL[1] is electrically connected to the memory cell 411A in the first row. Similarly, the wiring WL[i] is electrically connected to the memory cell 411A in the i-th row.

[0218] In addition, Fig.11 In the cell array 401 shown in the figure, two wirings BIL (wiring BILa and wiring BILb) are included in one column. Fig.11 In FIG. 1 , the wiring BILa in the first column is represented as wiring BILa[1], and the wiring BILb in the j-th column is represented as wiring BILb[j].

[0219] The memory cells 411A arranged in odd-numbered rows are electrically connected to one of the wiring BILa and the wiring BILb, and the memory cells 411A arranged in even-numbered rows are electrically connected to the other of the wiring BILa and the wiring BILb.

[0220] In addition, the wiring BILa and the wiring BILb are electrically connected to the precharge circuit 332, the amplifier circuit 333, and the input-output circuit 334 provided in each column. In addition, the input-output circuit 334 is electrically connected to the wiring SALa and the wiring SALb in each column. Fig.11In FIG. 1 , the precharge circuit 332 of the first column is represented as precharge circuit 332[1], and the precharge circuit 332 of the jth column is represented as precharge circuit 332[j]. The same is true for the description of the amplifier circuit 333 and the input / output circuit 334. Note that the bit line driving circuit 330 includes a column decoder 331 (see FIG. 1 ). Figure 8 ).

[0221] <Circuit Configuration Example>

[0222] Fig.12 An example of the circuit configuration of the memory cell 411A in the J-th column, the precharge circuit 332 , the amplifier circuit 333 , and the input / output circuit 334 is shown.

[0223] [Precharge circuit 332]

[0224] The precharge circuit 332[j] includes n-channel transistors Tr21 to Tr23. In addition, transistors Tr21 to Tr23 may also be p-channel transistors. One of the source and drain of transistor Tr21 is connected to wiring BILa[j], and the other of the source and drain is connected to wiring PRE. One of the source and drain of transistor Tr22 is connected to wiring BILb[j], and the other of the source and drain is connected to wiring PRE. One of the source and drain of transistor Tr23 is connected to wiring BILa[j], and the other of the source and drain is connected to wiring BILb[j]. The gate of transistor Tr21, the gate of transistor Tr22, and the gate of transistor Tr23 are connected to wiring PL. The precharge circuit 332[j] has a function of initializing the potential of wiring BILa[j] and wiring BILb[j].

[0225] [Amplifier circuit 333]

[0226] The amplifier circuit 333[j] includes a p-channel transistor Tr31 and a transistor Tr32, and an n-channel transistor Tr33 and a transistor Tr34. One of the source and the drain of the transistor Tr31 is connected to the wiring SP, and the other of the source and the drain is connected to the gate of the transistor Tr32, the gate of the transistor Tr34, and the wiring BILa[j]. One of the source and the drain of the transistor Tr33 is connected to the gate of the transistor Tr32, the gate of the transistor Tr34, and the wiring BILa[j], and the other of the source and the drain is connected to the wiring SN. One of the source and the drain of the transistor Tr32 is connected to the wiring SP, and the other of the source and the drain is connected to the gate of the transistor Tr31, the gate of the transistor Tr33, and the wiring BILb[j]. One of the source and the drain of the transistor Tr34 is connected to the gate of the transistor Tr31, the gate of the transistor Tr33, and the wiring BILb[j], and the other of the source and the drain is connected to the wiring SN. The amplifier circuit 333[j] has a function of amplifying the potential of the wirings BILa[j] and BILb[j]. The amplifier circuit 333[j] is used as a latch-type sense amplifier.

[0227] [Input-output circuit 334]

[0228] The input / output circuit 334[j] includes an n-channel transistor Tr41 and a transistor Tr42. In addition, the transistor Tr41 and the transistor Tr42 may also be p-channel transistors. One of the source and the drain of the transistor Tr41 is connected to the wiring BILa[j], and the other of the source and the drain is connected to the wiring SALa[j]. One of the source and the drain of the transistor Tr42 is connected to the wiring BILb[j], and the other of the source and the drain is connected to the wiring SALb[j]. The gate of the transistor Tr41 and the gate of the transistor Tr42 are connected to the wiring CSEL.

[0229] The input / output circuit 334[j] has a function of controlling the conduction state of the wiring BILa[j] and the wiring SALa[j] and the conduction state of the wiring BILb[j] and the wiring SALb[j] according to the potential supplied to the wiring CSEL. That is, the input / output circuit 334[j] can be used to select whether to output a potential to the wiring SALa[j] and the wiring SALb[j].

[0230] The wiring SP, wiring SN, wiring CSEL, wiring PRE, and wiring PL have the function of transmitting signals for controlling the operation of the precharge circuit 332, the amplifier circuit 333, and the input / output circuit 334. The wiring SP, wiring SN, wiring CSEL, wiring PRE, and wiring PL are connected to the wiring SP. Figure 8The wirings SP, SN, CSEL, PRE, and PL are connected to the control logic circuit 360. The control logic circuit 360 has a function of supplying control signals to the wirings SP, SN, CSEL, PRE, and PL.

[0231] <Working Example>

[0232] use Fig.12 The illustrated memory cell 411A[i,j], precharge circuit 332[j], amplifier circuit 333[j], and input / output circuit 334[j] illustrate the operation mode of the memory device 300. The memory device 300 is assumed to operate at 20° C. Therefore, it is assumed that −3 V is supplied from the semiconductor device 100 to the wiring BGL.

[0233] [Read Mode]

[0234] First, use Fig.13 The timing diagram of FIG. 4 illustrates an example of the operation of the amplifier circuit 333[j] when data is read from the memory cell 411A[i,j].

[0235] [Period T11]

[0236] During period T11, the precharge circuit 332[j] is operated to initialize the potentials of the wirings BILa[j] and BILb[j]. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the wirings BILa[j] and BILb[j] are supplied with the potential Vpre of the wiring PRE. In addition, the potential Vpre may be, for example, (VH_SP+VL_SN) / 2.

[0237] During the period T11, the potential of the wiring CSEL is at a low level (VL_CSEL), and the transistors Tr41 and Tr42 in the input / output circuit 334[j] are in an off state. In addition, the potential of the wiring WL[i] is at a low level (VL_WL), and the transistor M11 included in the storage unit 411A[i,j] is in an off state. Similarly, although Fig.13 Although not shown, the potential of the wiring WL[i+1] is low level (VL_WL), and the transistor M11 included in the memory cell 411A[i+1,j] is in the off state. In addition, the potentials of the wirings SP and SN are the potential Vpre, and the amplifier circuit 333[j] is in the stopped state.

[0238] [Period T12]

[0239] During period T12, the potential of wiring PL is set to a low level (VL_PL), and transistors Tr21 to Tr23 are turned off. In addition, wiring WL[i] is selected. Specifically, by changing the potential of wiring WL[i] to a high level (VH_WL), transistor M11 included in storage unit 411A[i,j] is turned on. As a result, in storage unit 411A[i,j], wiring BILa[j] and capacitor Cs are turned on through transistor M11, and the potential of wiring BILa[j] changes according to the amount of charge held by capacitor Cs.

[0240] exist Fig.13 , the case where data "1" is stored in the storage cell 411A[i,j] and the amount of charge stored in the capacitor Cs is large. Specifically, when the amount of charge stored in the capacitor Cs is large, the charge is released from the capacitor Cs to the wiring BILa[j], causing the potential of the wiring BILa[j] to rise by ΔV1 from the potential Vpre. On the other hand, when data "0" is stored in the storage cell 411A[i,j] and the amount of charge stored in the capacitor Cs is small, the charge flows from the wiring BILa[j] into the capacitor Cs, causing the potential of the wiring BILa[j] to drop by ΔV2 (not shown).

[0241] During the period T12, the potential of the wiring CSEL is at a low level (VL_CSEL), and the transistors Tr41 and Tr42 in the input / output circuit 334[j] are in an off state. The potentials of the wiring SP and the wiring SN are at the potential Vpre, and the amplifier circuit 333[j] remains in a stopped state.

[0242] [Period T13]

[0243] During period T13, the potential of wiring SP is changed to a high level (VH_SP), and the potential of wiring SN is changed to a low level (VL_SN). Thus, amplifier circuit 333[j] becomes in an operating state. Amplifier circuit 333[j] has a potential difference (VL_S) between amplifying wiring BILa[j] and wiring BILb[j]. Fig.13 Since the amplifier circuit 333[j] becomes in the operating state, the potential of the wiring BILa[j] approaches the potential of the wiring SP (VH_SP) from Vpre+ΔV1. In addition, the potential of the wiring BILb[j] approaches the potential of the wiring SN (VL_SN) from Vpre.

[0244] Note that at the beginning of the period T13, when the potential of the wiring BILa[j] is Vpre-ΔV2, the amplifier circuit 333[j] is in operation, so the potential of the wiring BILa[j] approaches the potential of the wiring SN (VL_SN) from Vpre-ΔV2. In addition, the potential of the wiring BILb[j] approaches the potential of the wiring SP (VH_SP) from the potential Vpre.

[0245] In addition, during the period T13, the potential of the wiring PL is at a low level (VL_PL), and the transistors Tr21 to Tr23 in the precharge circuit 332[j] are in an off state. In addition, the potential of the wiring CSEL is at a low level (VL_CSEL), and the transistors Tr41 and Tr42 in the input-output circuit 334[j] are in an off state. In addition, the potential of the wiring WL[i] is at a high level (VH_WL), and the transistor M11 included in the storage unit 411A[i,j] is in an on state. Therefore, in the storage unit 411A[i,j], the charge amount corresponding to the potential (VH_SP) of the wiring BILa[j] is stored in the capacitor Cs.

[0246] [Period T14]

[0247] During the period T14, the potential of the wiring CSEL is controlled to turn on the input / output circuit 334[j]. Specifically, the potential of the wiring CSEL is set to a high level (VH_CSEL), so that the transistor Tr41 and the transistor Tr42 are turned on. As a result, the potential of the wiring BILa[j] is supplied to the wiring SALa[j], and the potential of the wiring BILb[j] is supplied to the wiring SALb[j].

[0248] In addition, during the period T14, the potential of the wiring PL is at a low level (VL_PL), and in the precharge circuit 332[j], the transistors Tr21 to Tr23 are turned off. In addition, the potential of the wiring WL[i] is at a high level (VH_WL), and the transistor M11 of the storage unit 411A[i,j] is turned on. In addition, the potential of the wiring SP is at a high level (VH_SP), the potential of the wiring SN is at a low level (VL_SN), and the amplifier circuit 333[j] is in an operating state. As a result, in the storage unit 411A[i,j], the charge corresponding to the potential (VH_SP) of the wiring BILa[j] is stored in the capacitor Cs.

[0249] [Period T15]

[0250] In the period T15, the potential of the wiring CSEL is controlled to turn off the input / output circuit 334[j]. Specifically, the potential of the wiring CSEL is set to a low level (VL_CSEL), so that the transistor Tr41 and the transistor Tr42 are turned off.

[0251] In addition, during period T15, the wiring WL[i] is placed in a non-selected state. Specifically, the potential of the wiring WL[i] is low level (VL_WL). As a result, the transistor of the memory cell 411A[i,j] is turned off. As a result, the charge corresponding to the potential (VH_SP) of the wiring BILa is stored in the capacitor Cs of the memory cell 411A[i,j]. Therefore, even after the data is read, the data is retained in the memory cell 411A[i,j].

[0252] Furthermore, during period T15, even if the input / output circuit 334[j] is turned off, as long as the amplifier circuit 333[j] is in operation, the potentials of the wirings BILa[j] and BILb[j] are held by the amplifier circuit 333[j]. Thus, the amplifier circuit 333[j] has a function of temporarily holding the data read from the memory cell 411A[i,j].

[0253] By performing the above operation, data can be read from the memory cell 411A[i,j]. The read data is supplied to the output circuit 340 (see Figure 8 ). Note that data can also be read from the storage unit 411A[i+1,j] in the same manner as the storage unit 411A[i,j].

[0254] [Write Mode]

[0255] Next, use Fig.14 The timing chart shown illustrates an example of the operation of the amplifier circuit 333[j] when writing data to the memory cell 411A[i,j]. Data can be written to the memory cell 411A[i+1,j] based on the same principle as above.

[0256] [Period T21]

[0257] During the period T21, the transistors Tr21 to Tr23 included in the precharge circuit 332[j] are turned on, and the potentials of the wirings BILa[j] and BILb[j] are initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the wiring BILa[j] and the wiring BILb[j] are supplied with the potential Vpre of the wiring PRE. In addition, the potential Vpre may be, for example, (VH_SP+VL_SN) / 2.

[0258] [Period T22]

[0259] Then, during period T22, the potential of wiring PL is set to a low level (VL_PL), so that transistors Tr21 to Tr23 are turned off. In addition, wiring WL[i] connected to the memory cell 411A[i,j] to which data is written is selected. Specifically, the potential of wiring WL[i] is set to a high level (VH_WL), so that transistor M11 included in memory cell 411A[i,j] is turned on. As a result, in memory cell 411A[i,j], wiring BILa[j] and capacitor Cs are turned on through transistor M11.

[0260] At this time, when data “1” has been stored in the memory cell 411A[i,j], charge is discharged from the capacitor Cs to the wiring BILa[j], so that the potential of the wiring BILa[j] rises from the potential Vpre by ΔV1.

[0261] [Period T23]

[0262] In the period T23 , the potential of the wiring SP is set to a high level (VH_SP), and the potential of the wiring SN is set to a low level (VL_SN), so that the amplifier circuit 333 [j] is in an operating state.

[0263] [Period T24]

[0264] In the period T24, the potential of the wiring CSEL is controlled to turn on the input / output circuit 334[j], thereby bringing the wiring BILa[j] and the wiring SALa[j] into conduction, and bringing the wiring BILb[j] and the wiring SALb[j] into conduction.

[0265] The data signal WDATA is supplied to the input-output circuit 334[j] through the wiring SALa[j] and the wiring SALb[j]. By supplying a write potential corresponding to the data signal WDATA to the wiring SALa[j] and the wiring SALb[j], the write potential is supplied to the wiring BILa[j] and the wiring BILb[j] through the input-output circuit 334[j]. For example, when data "0" is stored in the memory cell 411A[i,j], a low level (VL_SN) is supplied to the wiring SALa[j], and a high level (VH_SP) is supplied to the wiring SALb[j].

[0266] Then, the switching states of the transistors Tr31 to Tr34 included in the amplifier circuit 333[j] are reversed, the potential (VL_SN) of the wiring SN is supplied to the wiring BILa[j], and the potential (VH_SP) of the wiring SP is supplied to the wiring BILb[j]. As a result, the charge amount corresponding to the potential (VL_SN) representing the data "0" is stored in the capacitor Cs. By performing the above operation, data can be written to the memory cell 411A[i,j].

[0267] [Period T25]

[0268] In period T25, the wiring WL[i] is turned into a non-selected state. Thus, the charge written into the memory cell 411A[i,j] is retained. In addition, by setting the potential of the wiring CSEL to a low level (VL_CSEL), the transistor Tr41 and the transistor Tr42 are turned off.

[0269] Furthermore, even if the transistors Tr41 and Tr42 in the input / output circuit 334[j] are turned off after the potential of the wiring SALa[j] is supplied to the wiring BILa[j], the potential of the wiring BILa[j] and the wiring BILb[j] can be maintained by the amplifier circuit 333[j] as long as the amplifier circuit 333[j] is in operation. Thus, the timing at which the transistors Tr41 and Tr42 are turned off from the on state can be either before or after the wiring WL[i] is selected.

[0270] By performing the above operation, data can be written to the memory cell 411A[i,j]. Note that data can also be written to the memory cell 411A[i+1,j] in the same manner as the memory cell 411A[i,j].

[0271] [Refresh Mode]

[0272] In order to maintain the data written to the memory cell 411A[i,j], a refresh operation (rewrite operation) is performed at fixed intervals. Fig.15The timing chart shown illustrates an example of the operation of the amplifier circuit 333[j] in the refresh operation. The refresh operation can be performed based on the same principle as above.

[0273] [Period T31]

[0274] During the period T31, the transistors Tr21 to Tr23 included in the precharge circuit 332[j] are turned on, and the potentials of the wirings BILa[j] and BILb[j] are initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the potential Vpre of the wiring PRE is supplied to the wirings BILa[j] and BILb[j].

[0275] [Period T32]

[0276] During period T32, the potential of wiring PL is set to a low level (VL_PL), so that transistors Tr21 to Tr23 are turned off. In addition, the wiring WL[i] connected to the storage unit 411A[i,j] to which data is written is selected. Specifically, the potential of wiring WL[i] is set to a high level (VH_WL), so that the transistor M11 of the storage unit 411A[i,j] is turned on. As a result, in the storage unit 411A[i,j], the wiring BILa[j] and the capacitor Cs are turned on through the transistor M11.

[0277] At this time, when data “1” has been stored in the memory cell 411A[i,j], charge is discharged from the capacitor Cs to the wiring BILa[j], so that the potential of the wiring BILa[j] rises from the potential Vpre by ΔV1.

[0278] [Period T33]

[0279] During the period T33, the potential of the wiring SP is set to a high level (VH_SP), and the potential of the wiring SN is set to a low level (VL_SN), so that the amplifier circuit 333[j] is in an operating state. By making the amplifier circuit 333[j] in an operating state, the potential of the wiring BILa[j] approaches the potential of the wiring SP (VH_SP) from Vpre+ΔV1. In addition, the potential of the wiring BILb[j] approaches the potential of the wiring SN (VL_SN) from Vpre. Note that in this specification, etc., the time required for the period T33 is referred to as "writing time".

[0280] [Period T34]

[0281] During period T34, the wiring WL[i] is set to a non-selected state. Specifically, the potential of the wiring WL[i] is set to a low level (VL_WL), so that the transistor of the memory cell 411A[i,j] is turned off. As a result, the charge amount corresponding to the potential (VH_SP) of the wiring BILa is stored in the capacitor Cs of the memory cell 411A[i,j].

[0282] In the refresh mode, since data is not read or written, the input / output circuit 334[j] can be kept in the off state. Therefore, the refresh mode can be performed in a shorter time than the read mode and the write mode. Note that the refresh mode of the memory cell 411A[i+1,j] can also be performed in the same manner as the memory cell 411A[i,j].

[0283] [NV mode]

[0284] By using an OS transistor as the transistor M11, power supply to a part or all of the peripheral circuit 311 and the cell array 401 can be stopped during a period when writing and reading of information is not required. In this case, it is preferable to operate the memory device 300 in NV mode (Non-volatile mode). Fig.16 The timing diagram shown illustrates an example of NV mode operation.

[0285] [Period T41]

[0286] During the period T41, the transistors Tr21 to Tr23 included in the precharge circuit 332[j] are turned on, and the potentials of the wirings BILa[j] and BILb[j] are initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the wiring BILa[j] and the wiring BILb[j] are supplied with the potential Vpre of the wiring PRE. The period T41 corresponds to the period T31 in the refresh mode.

[0287] [Period T42]

[0288] During period T42, the potential of wiring PL is set to a low level (VL_PL), so that transistors Tr21 to Tr23 are turned off. In addition, the wiring WL[i] connected to the storage unit 411A[i,j] to which data is written is selected. Specifically, the potential of wiring WL[i] is set to a high level (VH_WL), so that the transistor M11 of the storage unit 411A[i,j] is turned on. As a result, in the storage unit 411A[i,j], wiring BILa[j] and capacitor Cs are turned on through transistor M11.

[0289] At this time, when data "1" is stored in the memory cell 411A[i,j], charge is released from the capacitor Cs to the wiring BILa[j], so that the potential of the wiring BILa[j] rises from the potential Vpre by ΔV1. The period T42 corresponds to the period T32 in the refresh mode.

[0290] [Period T43]

[0291] During period T43, the potential of wiring SP is set to a high level (VH_SP), and the potential of wiring SN is set to a low level (VL_SN), so that amplifier circuit 333[j] is in an operating state. By making amplifier circuit 333[j] in an operating state, the potential of wiring BILa[j] approaches the potential of wiring SP (VH_SP) from Vpre+ΔV1. In addition, the potential of wiring BILb[j] approaches the potential of wiring SN (VL_SN) from Vpre. Period T43 is equivalent to period T33 in refresh mode. Therefore, in NV mode, the time required for period T43 is the "write time".

[0292] Here, in the NV mode, in order to reliably store the charge amount corresponding to the data in the capacitor Cs, the write time is made longer than the write time in the refresh mode. The write time in the NV mode is preferably 1.5 times or more of the write time in the refresh mode, more preferably 2 times or more, and further preferably 5 times or more. By extending the write time, insufficient writing of data can be prevented.

[0293] [Period T44]

[0294] During period T44, the potential of the wiring WL[i] is changed to a low level (VL_WL), and the transistor included in the storage unit 411A[i,j] is turned off. In addition, when the threshold of the transistor M11 is VthM (VthM>0V), regardless of the operating temperature, a potential of -VthM or less, preferably -2×VthM or less, and more preferably -3×VthM or less is supplied to the wiring BGL. For example, when VthM is 2V, regardless of the operating temperature, a potential of -2V or less, preferably -4V or less, and more preferably -6V or less is supplied to the wiring BGL. In this embodiment, during period T44, -7V is supplied to the wiring BGL.

[0295] After the period T44 ends, the power supply to a part or all of the peripheral circuit 311 and the cell array 401 is stopped.

[0296] The write time is made longer than the write time in the refresh mode, and a potential below -VthM, preferably below -2×VthM, and more preferably below -3×VthM is supplied to the wiring BGL. Thus, even if the power supply to the cell array 401 is stopped, the written data can be maintained for more than 10 years in an environment of 85°C.

[0297] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0298] (Implementation 4)

[0299] In this embodiment, a structure example and an operation example of a storage device 300A and a storage device 300B that can hold multiple bits of data (multi-value data) in one storage unit are described. The storage device 300A is a modified example of the above-mentioned storage device 300. In order to reduce repeated descriptions, the differences between the storage device 300A and the storage device 300 are mainly described. For parts not described in this embodiment, reference can be made to other embodiments or technical common sense of ordinary technicians in the field of this technology. In this embodiment, a DRAM type storage unit 411A is used as the storage unit 411.

[0300] <Storage device 300A>

[0301] <Structure example>

[0302] Fig.17 FIG. 2 is a block diagram showing a configuration example of a storage device 300A. The storage device 300A has Figure 8 The memory device 300 shown in the figure has a structure in which a global logic circuit 350 is added. In addition, the memory device 300A includes a bit line driver circuit 330A. The bit line driver circuit 330A has a structure different from that of the bit line driver circuit 330 included in the memory device 300.

[0303] The global logic circuit 350 has a function of holding a data signal WDATA input from the outside. In addition, the global logic circuit 350 has a function of supplying the data signal WDATA to the bit line driver circuit 330A through the wiring SAL.

[0304] The information stored in the memory cell 411A is read by the bit line driver circuit 330A and supplied to the global logic circuit 350. The global logic circuit 350 has a function of holding the information. In addition, the global logic circuit 350 has a function of supplying the information to the output circuit 340. The output circuit 340 has a function of outputting the information to the outside as a digital data signal RDATA.

[0305] The bit line driving circuit 330A included in the memory device 300A includes a precharge circuit 332 , an input / output circuit 334 , and a signal conversion circuit 335 . The signal conversion circuit 335 includes a DAC (Digital to Analog Converter) 337 and an ADC (Analog to Digital Converter) 338 .

[0306] Fig.18 FIG. 4 shows an example of the structure of the cell array 401 and the bit line driving circuit 330A of the memory device 300A. Fig.18 In the cell array 401 shown, there are m memory cells 411A in one column and n memory cells in one row, for a total of m×n memory cells 411A, and the memory cells 411A are arranged in rows and columns.

[0307] in addition, Fig.18 The cell array 401 shown includes m wirings WL electrically connected to the word line driving circuit 322. The wiring WL[1] is electrically connected to the memory cell 411A in the first row. Similarly, the wiring WL[i] is electrically connected to the memory cell 411A in the i-th row.

[0308] in addition, Fig.18 The cell array 401 shown includes n wirings BIL electrically connected to the bit line driver circuit 330A. The wiring BIL[1] is electrically connected to the memory cell 411A in the first column. Similarly, the wiring BIL[j] is electrically connected to the memory cell 411A in the jth column.

[0309] The wiring BIL is electrically connected to the precharge circuit 332, the signal conversion circuit 335 (DAC 337, ADC 338), and the input / output circuit 334 provided in each column. Fig.11 Likewise, in Fig.18 , the precharge circuit 332 of the first column is represented as precharge circuit 332[1], and the precharge circuit 332 of the j-th column is represented as precharge circuit 332[j]. The same is true for the description of the signal conversion circuit 335 and the input / output circuit 334.

[0310] The input / output circuit 334 included in the memory device 300A has a function of determining the operation of the signal conversion circuit 335. The input / output circuit 334 has a function of switching between reading data stored in the memory cell 411A and writing data stored in the memory cell 411A according to the operation mode. The input / output circuit 334 is electrically connected to the global logic circuit 350 via the wiring SAL.

[0311] The control logic circuit 360 can be used to control the operation of the precharge circuit 332, the signal conversion circuit 335, and the input / output circuit 334 (see Fig.17 ).

[0312] Fig.19 A more detailed configuration example of the cell array 401 and the bit line driver circuit 330A is shown. Fig.19 Nine memory cells 411A in row i and column j to row i+2 and column j+2 and a portion of the bit line driver circuit 330A corresponding to columns j to j+2, respectively, are shown.

[0313] The precharge circuit 332[j] is electrically connected to the wiring BIL[j]. The precharge circuit 332[j] has a function of precharging the wiring BIL[j]. The input / output circuit 334[j] has a function of determining the operation of the DAC 337[j] and the ADC 338[j] according to the operation mode. Specifically, when operating in the write mode, the DAC 337[j] is operated and the ADC 338[j] is stopped.

[0314] The input terminal of the DAC 337 [j] is electrically connected to the input-output circuit 334 [j], and the output terminal is electrically connected to the wiring BIL [j]. The input terminal of the ADC 338 [j] is electrically connected to the wiring BIL [j], and the output terminal is electrically connected to the input-output circuit 334 [j].

[0315] Alternatively, an amplifier circuit may be provided between the wiring BIL[j] and the ADC338[j].

[0316] The DAC 337[j] has a function of converting k-bit (k is an integer greater than or equal to 2) digital data supplied from the input / output circuit 334 into multi-valued data (analog data). The ADC 338[j] has a function of converting multi-valued data (analog data) stored in the storage unit 411A[i, j] into k-bit digital data.

[0317] <Working Example>

[0318] Next, the operation mode of the memory device 300A will be described. It is assumed that the memory device 300A operates at 20° C. Therefore, it is assumed that −3 V is supplied from the semiconductor device 100 to the wiring BGL.

[0319] [Read Mode]

[0320] Next, use Fig. 20 The timing chart shown in the figure explains an example of the operation of the bit line driver circuit 330A when data is read from the memory cell 411A[i,j]. In addition, it is assumed that the charge amount corresponding to the data "1010" among the 4-bit (16-value) digital data is held in the capacitor Cs of the memory cell 411A[i,j].

[0321] [Period T51]

[0322] During period T51, the precharge circuit 332[j] is operated to initialize the potential of the wiring BIL[j]. Specifically, the potential Vpre is supplied to the wiring BIL[j]. Note that in this embodiment, the potential Vpre is the average potential of the highest potential (VH_DA) and the lowest potential (VL_DA) output from the DAC 337[j]. That is, the potential Vpre = (VH_DA + VL_DA) / 2.

[0323] During period T51, the potential of wiring WL[i] is low level (VL_WL), and transistor M11 is in the off state. In addition, DAC337[j], ADC338[j], and input / output circuit 334[j] are in the stopped state. Fig. 20 Although not shown in the figure, the potential of the wiring WL other than the wiring WL[i] is also VL_WL.

[0324] [Period T52]

[0325] During period T52, the precharge circuit 332[j] is stopped and the wiring WL[i] is selected. Specifically, by changing the potential of the wiring WL[i] to a high level (VH_WL), the transistor M11 included in the memory cell 411A[i,j] is turned on. As a result, in the memory cell 411A[i,j], the wiring BIL[j] and the capacitor Cs are turned on through the transistor M11, and the potential of the wiring BIL[j] changes according to the amount of charge held by the capacitor Cs.

[0326] exist Fig. 20 In the example, the charge amount corresponding to the data "1010" is held in the capacitor Cs of the storage cell 411A[i,j]. The charge is released from the capacitor Cs to the wiring BIL[j], so that the potential of the wiring BIL[j] rises from the potential Vpre by ΔV1. In addition, depending on the amount of charge held in the capacitor Cs, the potential of the wiring BIL[j] sometimes decreases. Since the transistor M11 becomes turned on, the potential of the capacitor Cs of the storage cell 411A[i,j] is the same as the potential of the wiring BIL[j]. In addition, the operation of the input-output circuit 334[j] is started.

[0327] [Period T53]

[0328] In the period T53, the operation of ADC338[j] is started. In addition, in the period T53, the potential of the wiring WL[i] may be set to VL_WL.

[0329] [Period T54]

[0330] During the period T54, ADC338[j] converts the potential of the wiring BIL[j] into digital data and outputs the digital data to the wiring SAL[j].

[0331] [Period T55]

[0332] In the period T55, the wiring WL[i] is placed in a non-selected state. Specifically, the potential of the wiring WL[i] is changed to a low level (VL_WL). In addition, the operations of the ADC 338[j] and the input / output circuit 334[j] are stopped.

[0333] By performing the above operation, data can be read from the memory cell 411A[i,j]. The read data is supplied to the global logic circuit 350 through the wiring SAL[j]. As described above, the global logic circuit 350 has the function of holding the data and the function of supplying the data to the output circuit 340. The data is output to the outside as the data signal RDATA through the output circuit 340.

[0334] When operating in the read mode, the amount of charge held in the memory cell 411A[i,j] changes. That is, the information stored in the memory cell 411A[i,j] is destroyed.

[0335] To restore the damaged information, the memory device 300A operates in the write mode described below after operating in the read mode. Specifically, when operating in the read mode, the data of the memory cell 411A[i,j] held by the global logic circuit 350 is written again to the memory cell 411A[i,j].

[0336] [Write Mode]

[0337] Next, use Fig.21 The timing chart shown in the figure illustrates an example of the operation of the bit line driver circuit 330A when writing data to the memory cell 411A[i,j]. In this embodiment, it is assumed that the charge amount corresponding to the data "1010" among the 4-bit (16-value) digital data is written to the capacitor Cs of the memory cell 411A[i,j].

[0338] [Period T61]

[0339] During period T61, the precharge circuit 332[j] is operated to initialize the potential of the wiring BIL[j]. Specifically, the potential Vpre is supplied to the wiring BIL[j]. In addition, the wiring WL[i] is selected, and the transistor M11 is turned on. As a result, the potential of the capacitor Cs of the memory cell 411A[i,j] also becomes the potential Vpre.

[0340] During the period T61, the DAC 337[j], the ADC 338[j] and the input / output circuit 334[j] are in a stopped state.

[0341] [Period T62]

[0342] During period T62, the operation of the input / output circuit 334[j] starts.

[0343] [Period T63]

[0344] During period T63, the operation of DAC337[j] starts.

[0345] [Period T64]

[0346] In the period T64, the data signal WDATA input from the outside is supplied to the wiring SAL[j] through the global logic circuit 350. In this embodiment, it is assumed that data "1010" is supplied to the wiring SAL[j] as the data signal WDATA.

[0347] The data "1010" supplied to the wiring SAL[j] is converted by the DAC 337[j] into a potential corresponding to the data "1010" and supplied to the wiring BIL[j]. At this time, since the transistor M11 is in the on state, the capacitor Cs of the memory cell 411A[i,j] is supplied with a charge amount having the same potential as the wiring BIL[j].

[0348] [Period T65]

[0349] In period T65, by making wiring WL[i] non-selected and transistor M11 off, the charge corresponding to data "1010" is retained in memory cell 411A[i,j]. In addition, the operation of ADC338[j] and input / output circuit 334[j] is stopped.

[0350] By performing the above operation, data can be written to the memory cell 411A[i,j]. In the present embodiment, the time required for the period T64 is the "writing time".

[0351] [Refresh Mode]

[0352] In order to maintain the data written to the memory cell 411A[i,j], a refresh operation (re-write operation) is performed at fixed intervals. Specifically, first, the memory device 300A is operated in the read mode, and the data maintained by the memory cell 411A[i,j] is maintained in the global logic circuit 350. Then, the memory device 300A is operated in the write mode, and the data maintained by the global logic circuit 350 is re-written to the memory cell 411A[i,j]. In the refresh mode, the time required for the period T64 is still the "write time".

[0353] In the refresh mode, the data signal WDATA is not input to the global logic circuit 350 and the data signal WDATA is not output from the global logic circuit 350 to the output circuit 340 .

[0354] [NV mode]

[0355] The NV mode is performed after the read mode is executed. Before the NV mode is executed, as a pre-processing, the memory device 300A is operated in the read mode, and the data held in the memory cell 411A[i, j] is stored in the global logic circuit 350. In the read mode performed as the pre-processing of the NV mode, the data signal WDATA input to the global logic circuit 350 and the data signal WDATA output from the global logic circuit 350 to the output circuit 340 may not be performed, as in the case of executing the refresh mode.

[0356] use Fig. 22 The timing chart shown in FIG. 1 illustrates an example of operation in the NV mode in the storage device 300A. The NV mode is an operation mode that is almost the same as the write mode. Fig. 22 In the embodiment, the NV mode is represented by the period T71 to the period T75. In addition, the period T71 to the period T74 correspond to the period T61 to the period T64 of the write mode. Therefore, the description of the period T71 to the period T74 is omitted.

[0357] In the NV mode, in order to store the charge corresponding to the data in the capacitor Cs reliably, the write time is longer than the write time in the refresh mode. The time required for period T74 is the "write time" in the NV mode. The write time in the NV mode is preferably 1.5 times or more of the write time in the refresh mode, more preferably 2 times or more, and further preferably 5 times or more. By extending the write time, insufficient writing of data can be prevented.

[0358] [Period T75]

[0359] In period T75, the potential of wiring WL[i] is changed to low level (VL_WL), and the transistor included in memory cell 411A[i,j] is turned off. By turning transistor M11 off, the charge amount corresponding to data "1010" is retained in memory cell 411A[i,j].

[0360] In addition, when the threshold of the transistor M11 is VthM (VthM>0V), a potential of -VthM or less, preferably -2×VthM or less, and more preferably -3×VthM or less is supplied to the wiring BGL regardless of the operating temperature. For example, when VthM is 2V, a potential of -2V or less, preferably -4V or less, and more preferably -6V or less is supplied to the wiring BGL regardless of the operating temperature. In this embodiment, -7V is supplied to the wiring BGL during period T75. In addition, the operation of ADC338[j] and the input / output circuit 334[j] is stopped.

[0361] After the period T75 ends, the power supply to a part or all of the peripheral circuit 311 and the cell array 401 is stopped.

[0362] The write time in the NV mode is made longer than the write time in the refresh mode, and a potential below -VthM, preferably below -2×VthM, and more preferably below -3×VthM is supplied to the wiring BGL. Thus, even if the power supply to the cell array 401 is stopped, the written data can be maintained for more than 10 years in an environment of 85°C.

[0363] By providing a precharge circuit 332, a signal conversion circuit 335 (DAC 337, ADC 338) and an input / output circuit 334 for a plurality of memory cells 411A included in each column of the cell array 401, data can be read and written at high speed.

[0364] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0365] (Implementation 5)

[0366] When the number of bits of the data signal WDATA increases, the area occupied by the bit line driving circuit 330 increases exponentially. In particular, the area occupied by the signal conversion circuit 335 increases. Therefore, when the precharge circuit 332, the signal conversion circuit 335, and the input / output circuit 334 are provided for each column of memory cells, the memory device 300 itself becomes larger.

[0367] In this embodiment, a memory device 300B having a structure in which the occupied area of ​​the bit line driving circuit 330 is not easily increased even if the number of bits of the data signal WDATA increases is described. Note that the memory device 300B is a modified example of the memory device 300A. The structure example shown in the memory device 300B is particularly effective when the data signal WDATA is digital data of 3 bits or more.

[0368] <Storage device 300B>

[0369] <Structure Example<

[0370] Fig.23 A block diagram illustrating a configuration example of a memory device 300B is shown. The memory device 300B includes a bit line driver circuit 330B instead of the bit line driver circuit 330A. The bit line driver circuit 330B includes a column switching circuit 339 between the cell array 401 and the precharge circuit 332 .

[0371] Fig.24 FIG. 4 shows a configuration example of a portion of the cell array 401 and a bit line driver circuit 330B. Fig.24In FIG. 4 , three columns of memory cells 411A are shown, i row and j column to i+2 row and j+2 column. Fig.24 , a structure in which a column switching circuit 339, a precharge circuit 332, a signal conversion circuit 335, and an input / output circuit 334 are provided for every three columns is shown.

[0372] In addition, Fig.24 In FIG. 1 , the g-th column switching circuit 339 is represented as column switching circuit 339[g] (g is an integer greater than 1). The same is true for the description of the precharge circuit 332, the signal conversion circuit 335, and the input-output circuit 334. When the column switching circuit 339, the precharge circuit 332, the signal conversion circuit 335, and the input-output circuit 334 are provided for every f columns (f is an integer greater than 2), g can be represented as n / f. Therefore, n is preferably a multiple of f.

[0373] The column switching circuit 339 includes f switches SW. In addition, the column switching circuit 339 is electrically connected to f wirings SCL. Fig.24 , the case where f is 3 is shown. Therefore, Fig.24 The column switching circuit 339 shown includes switches SW[1] to SW[3], and is electrically connected to wirings SCL[1] to SCL[3].

[0374] The wiring SCL[1] is electrically connected to the switch SW[1] and has a function of controlling the on state and the off state of the switch SW[1]. The wiring SCL[2] is electrically connected to the switch SW[2] and has a function of controlling the on state and the off state of the switch SW[2]. The wiring SCL[3] is electrically connected to the switch SW[3] and has a function of controlling the on state and the off state of the switch SW[3].

[0375] In addition, an amplifier circuit may be provided between the circuit 339[g] and the ADC 338[g]. In addition, an amplifier circuit may be provided between the wiring BIL[j] and the switch SW[1]. In addition, an amplifier circuit may be provided between the wiring BIL[j+1] and the switch SW[2]. In addition, an amplifier circuit may be provided between the wiring BIL[j+2] and the switch SW[3].

[0376] <Working Example<

[0377] Next, the operation mode of the memory device 300B will be described. It is assumed that the memory device 300B operates at 20° C. Therefore, it is assumed that −3 V is supplied from the semiconductor device 100 to the wiring BGL.

[0378] [Read Mode]

[0379] Next, use Fig.25The timing diagram shown illustrates an example of the operation of the bit line driver circuit 330B when data is read from the memory cell 411A[i,j] to the memory cell 411A[i,j+2]. In addition, it is assumed that the charge amount corresponding to the data "1010" in the 4-bit (16-value) digital data is held in the capacitor Cs of the memory cell 411A[i,j]. In addition, it is assumed that the charge amount corresponding to the data "0010" in the 4-bit (16-value) digital data is held in the capacitor Cs of the memory cell 411A[i+1,j]. In addition, it is assumed that the charge amount corresponding to the data "0111" in the 4-bit (16-value) digital data is held in the capacitor Cs of the memory cell 411A[i+2,j].

[0380] [Period T81]

[0381] During period T81, the precharge circuit 332[g] is operated. In addition, a high level (VH_SCL) potential is supplied to the wiring SCL[1] to the wiring SCL[3], and the switches SW[1] to SW[3] are turned on. As a result, the wiring BIL[j] to the wiring BIL[j+2] (at Fig.25 Specifically, the potential Vpre is supplied to the wiring BIL[j] to the wiring BIL[j+2].

[0382] During the period T81, the potential of the wiring WL[i] is at a low level (VL_WL), and the transistor M11 is in an off state. In addition, the DAC 337[g], the ADC 338[g], and the input / output circuit 334[g] are in a stopped state.

[0383] [Period T82]

[0384] During period T82, the precharge circuit 332[g] is stopped. In addition, a low level (VL_SCL) potential is supplied to the wiring SCL[1] to the wiring SCL[3], and the switches SW[1] to SW[3] are turned off. In addition, the wiring WL[i] is selected. Specifically, by changing the potential of the wiring WL[i] to the high level (VH_WL), the transistor M11 included in the memory cell 411A[i,j] is turned on.

[0385] As a result, in the memory cell 411A[i,j], the wiring BIL[j] and the capacitor Cs are turned on through the transistor M11, and the potential of the wiring BIL[j] changes according to the amount of charge held by the capacitor Cs. The memory cells 411A[i+1,j] and 411A[i+2,j] also operate in the same manner, and the potentials of the wirings BIL[j+1] and BIL[j+2] change.

[0386] In addition, the operation of the input / output circuit 334[g] starts.

[0387] [Period T83]

[0388] In the period T83, the operation of ADC338[g] is started. In addition, in the period T83, the potential of the wiring WL[i] may be set to VL_WL.

[0389] [Period T84]

[0390] In period T84, the potential of the wiring SCL[1] is changed to a high level (VH_SCL[1]), and the wiring BIL[j] and ADC338[g] are electrically connected. ADC338[g] converts the potential of the wiring BIL[j] into digital data and outputs it to the wiring SAL[g].

[0391] [Period T85]

[0392] During period T85, the potential of wiring SCL[1] is changed to a low level (VL_SCL[1]). In addition, the potential of wiring SCL[2] is changed to a high level (VH_SCL[2]), and wiring BIL[j+1] and ADC338[g] are electrically connected. ADC338[g] converts the potential of wiring BIL[j+1] into digital data and outputs it to wiring SAL[g].

[0393] [Period T86]

[0394] During period T86, the potential of wiring SCL[2] is changed to a low level (VL_SCL[2]). In addition, the potential of wiring SCL[3] is changed to a high level (VH_SCL[3]), and wiring BIL[j+2] and ADC338[g] are electrically connected. ADC338[g] converts the potential of wiring BIL[j+2] into digital data and outputs it to wiring SAL[g].

[0395] [Period T87]

[0396] During period T87, the wiring WL[i] is placed in a non-selected state. Specifically, the potential of the wiring WL[i] is changed to a low level (VL_WL). In addition, the potential of the wiring SCL[3] is changed to a low level (VL_SCL[3]). In addition, the operation of ADC338[g] and the input / output circuit 334[g] is stopped.

[0397] By performing the above operation, the data stored in the memory cells 411A[i,j] to 411A[i+2,j] can be sequentially read out. The read data is supplied to the global logic circuit 350 through the wiring SAL[g]. The data is output to the outside as the data signal RDATA through the output circuit 340.

[0398] A switch element such as a transistor can be used as the switch SW included in the column switching circuit 339. In addition, in the memory device 300B, data stored in the memory cells 411A[i,j] to 411A[i+2,j] are sequentially read out. Therefore, as the switch SW (switch SW[1] to switch SW[3]) included in the column switching circuit 339, a transistor with a very small off-state current such as an OS transistor is preferably used.

[0399] When operating in the read mode, the amount of charge held in the memory cells 411A[i,j] to 411A[i+2,j] changes. That is, the information stored in the memory cells 411A[i,j] to 411A[i+2,j] is destroyed.

[0400] In order to restore the damaged information, after operating in the read mode, the storage device 300B is operated in the write mode described below. Specifically, when operating in the read mode, the data of the storage cells 411B[i,j] to the storage cells 411A[i+2,j] held by the global logic circuit 350 are written again to the storage cells 411A[i,j] to the storage cells 411A[i+2,j].

[0401] [Write Mode]

[0402] Next, use Fig.26 The timing diagram shown illustrates an example of the operation of the bit line driver circuit 330B when data is written to the memory cell 411A[i,j]. In this embodiment, it is assumed that the charge amount corresponding to the data "1010" among the 4-bit (16-value) digital data is written to the capacitor Cs of the memory cell 411A[i,j]. In addition, it is assumed that the charge amount corresponding to the data "0010" among the 4-bit (16-value) digital data is written to the capacitor Cs of the memory cell 411A[i,j+1]. In addition, it is assumed that the charge amount corresponding to the data "0111" among the 4-bit (16-value) digital data is written to the capacitor Cs of the memory cell 411A[i,j+2].

[0403] [Period T91]

[0404] During period T91, the precharge circuit 332[g] is operated. In addition, a high level potential (VH_SCL) is supplied to the wiring SCL[1] to the wiring SCL[3], and the switches SW[1] to SW[3] are turned on. As a result, the wiring BIL[j] to the wiring BIL[j+2] (at Fig.26The potential of the capacitor Cs of the memory cell 411A[i,j] to the memory cell 411A[i,j+2] is also initialized.

[0405] During period T91, DAC337[g], ADC338[g] and input / output circuit 334[g] are in a stopped state.

[0406] [Period T92]

[0407] During period T92, the operation of the input / output circuit 334[g] starts.

[0408] [Period T93]

[0409] During period T93, the operation of DAC337[g] starts.

[0410] [Period T94]

[0411] In period T94, the potential of wiring SCL[1] is changed to high level (VH_SCL[1]), and wiring BIL[j] and DAC337[g] are electrically connected. The data signal WDATA input from the outside is supplied to wiring SAL[g] through the global logic circuit 350. Here, it is assumed that data "1010" is supplied to wiring SAL[j] as data signal WDATA.

[0412] The data "1010" supplied to the wiring SAL[j] is converted by the DAC 337[g] into a potential corresponding to the data "1010" and supplied to the wiring BIL[j]. At this time, since the transistor M11 is in the on state, the capacitor Cs of the memory cell 411A[i,j] is supplied with a charge amount having the same potential as the wiring BIL[j].

[0413] [Period T95]

[0414] During period T95, the potential of wiring SCL[1] is changed to a low level (VL_SCL[1]). The potential of wiring SCL[2] is changed to a high level (VH_SCL[2]), and wiring BIL[j+1] and DAC337[g] are electrically connected. The data signal WDATA input from the outside is supplied to wiring SAL[g] through the global logic circuit 350. Here, it is assumed that data "0010" is supplied to wiring SAL[g] as data signal WDATA.

[0415] The data "0010" supplied to the wiring SAL[g] is converted by the DAC 337[g] into a potential corresponding to the data "0010" and supplied to the wiring BIL[j+1]. At this time, since the transistor M11 is in the on state, the capacitor Cs of the memory cell 411A[i,j+1] is supplied with a charge amount having the same potential as the wiring BIL[j+1].

[0416] [Period T96]

[0417] During period T96, the potential of wiring SCL[2] is changed to a low level (VL_SCL[2]). The potential of wiring SCL[3] is changed to a high level (VH_SCL[3]), and wiring BIL[j+2] and DAC337[g] are electrically connected. The data signal WDATA input from the outside is supplied to wiring SAL[g] through the global logic circuit 350. Here, it is assumed that data "0010" is supplied to wiring SAL[g] as data signal WDATA.

[0418] The data "0010" supplied to the wiring SAL[g] is converted by the DAC 337[g] into a potential corresponding to the data "0010" and supplied to the wiring BIL[j+2]. At this time, since the transistor M11 is in the on state, the capacitor Cs of the memory cell 411A[i,j+2] is supplied with a charge amount having the same potential as the wiring BIL[j+2].

[0419] [Period T97]

[0420] During period T97, the wiring WL[i] is turned into a non-selected state and the transistor M11 is turned into an off state, so that the charge amount corresponding to each data is retained in the storage cells 411A[i,j] to 411A[i,j+2]. In addition, the potential of the wiring SCL[3] is turned into a low level (VL_SCL[3]). In addition, the operation of ADC338[g] and the input / output circuit 334[g] is stopped.

[0421] By performing the above operation, data can be written to the memory cell 411A[i,j]. In the present embodiment, the time required from the period T94 to the period T96 is the "writing time".

[0422] [Refresh Mode]

[0423] The refresh mode of the memory device 300B can also operate in the same manner as the memory device 300A, so a detailed description thereof will be omitted here.

[0424] [NV mode]

[0425] In the storage device 300B, similarly to the storage device 300A, the NV mode is performed after the read mode is performed. Fig. 27 2 is a timing chart showing an example of operation in the NV mode in the storage device 300B. The NV mode is an operation mode that is almost the same as the write mode. Fig. 27 In the embodiment, the NV mode is represented by the period T101 to the period T107. In addition, the period T101 to the period T106 correspond to the period T91 to the period T96 of the write mode. Therefore, the description of the period T101 to the period T106 is omitted.

[0426] In the NV mode, in order to store the charge corresponding to the data in the capacitor Cs reliably, the write time is longer than the write time in the refresh mode. The time required from period T104 to period T106 is the "write time" in the NV mode. The write time in the NV mode is preferably 1.5 times or more of the write time in the refresh mode, more preferably 2 times or more, and further preferably 5 times or more. By extending the write time, insufficient writing of data can be prevented.

[0427] [Period T107]

[0428] During the period T107, the potential of the wiring WL[i] is changed to a low level (VL_WL), and the transistors included in the memory cells 411A[i,j] to 411A[i,j+2] are turned off. By turning off the transistor M11, the charge amount corresponding to each data is retained in the memory cells 411A[i,j] to 411A[i,j+2].

[0429] In addition, when the threshold of the transistor M11 is VthM (VthM>0V), a potential of -VthM or less, preferably -2×VthM or less, and more preferably -3×VthM or less is supplied to the wiring BGL regardless of the operating temperature. For example, when VthM is 2V, a potential of -2V or less, preferably -4V or less, and more preferably -6V or less is supplied to the wiring BGL regardless of the operating temperature. In this embodiment, -7V is supplied to the wiring BGL during period T75. In addition, the operation of ADC338[g] and the input / output circuit 334[g] is stopped.

[0430] After the period T75 ends, the power supply to a part or all of the peripheral circuit 311 and the cell array 401 is stopped.

[0431] The write time in the NV mode is made longer than the write time in the refresh mode, and a potential below -VthM, preferably below -2×VthM, and more preferably below -3×VthM is supplied to the wiring BGL. Thus, even if the power supply to the cell array 401 is stopped, the written data can be maintained for more than 10 years in an environment of 85°C.

[0432] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0433] (Implementation method 6)

[0434] In this embodiment, a cross-sectional structure example of a storage device 300 is described with reference to the drawings.

[0435] <Configuration Example of Storage Device<

[0436] Fig.28 A partial cross section of the storage device 300 is shown. Fig.28 The memory device 300 shown includes a layer 310 and a layer 320 stacked on a substrate 231 . Fig.28 The case where a single crystal semiconductor substrate (eg, a single crystal silicon substrate) is used as the substrate 231 is shown.

[0437] [Layer 310]

[0438] exist Fig.28 In FIG. 2 , layer 310 includes transistor 233 a , transistor 233 b , and transistor 233 c on substrate 231 . Fig.28 A cross section of the transistor 233a, the transistor 233b, and the transistor 233c in the channel length direction is shown.

[0439] Channels of the transistor 233a, the transistor 233b, and the transistor 233c are formed in a portion of the substrate 231. When the integrated circuit is required to operate at high speed, a single crystal semiconductor substrate is preferably used as the substrate 231.

[0440] The transistor 233a, the transistor 233b, and the transistor 233c are electrically isolated from each other by the element isolation layer 232. The element isolation layer can be formed by a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

[0441] In addition, an insulating layer 234 is provided on the substrate 231, and insulating layers 235 and 237 are provided on the transistors 233a, 233b, and 233c. An electrode 238 is buried in the insulating layer 237. The electrode 238 is electrically connected to one of the source and the drain of the transistor 233a through a contact plug 236.

[0442] In addition, insulating layers 239 , 240 , and 241 are provided on the electrode 238 and the insulating layer 237 , and an electrode 242 is buried in the insulating layers 239 , 240 , and 241 . The electrode 242 is electrically connected to the electrode 238 .

[0443] In addition, insulating layers 243 and 244 are provided on the electrode 242 and the insulating layer 241 , and an electrode 245 is buried in the insulating layers 243 and 244 . The electrode 245 is electrically connected to the electrode 242 .

[0444] In addition, insulating layers 246 and 247 are provided on the electrode 245 and the insulating layer 244 , and an electrode 249 is buried in the insulating layers 246 and 247 . The electrode 249 is electrically connected to the electrode 245 .

[0445] In addition, insulating layers 248 and 250 are provided on the electrode 249 and the insulating layer 247 , and an electrode 251 is buried in the insulating layers 248 and 250 . The electrode 251 is electrically connected to the electrode 249 .

[0446] [Layer 320]

[0447] Layer 320 is disposed on layer 310. Layer 320 includes a transistor 368a, a transistor 368b, a capacitor 369a, and a capacitor 369b. Fig.28 The cross section of the transistor 368a and the transistor 368b in the channel length direction is shown. The transistor 368a and the transistor 368b are transistors including a back gate.

[0448] The transistor 368a and the transistor 368b correspond to the transistor M11 described in the above embodiment. Therefore, an oxide semiconductor which is a type of metal oxide is preferably used as the semiconductor layer of the transistor 368a and the transistor 368b. That is, the transistor 368a and the transistor 368b are preferably OS transistors.

[0449] The transistor 368a and the transistor 368b are provided on the insulating layer 361 and the insulating layer 362. In addition, the insulating layer 363 and the insulating layer 364 are provided on the insulating layer 362. The back gates of the transistor 368a and the transistor 368b are buried in the insulating layer 363 and the insulating layer 364. The insulating layer 365 and the insulating layer 366 are provided on the insulating layer 364. In addition, the electrode 367 is buried in the insulating layer 361 to the insulating layer 366. The electrode 367 is electrically connected to the electrode 251.

[0450] Insulating layers 371, 372, and 373 are formed over the transistor 368a, the transistor 368b, the capacitor 369a, and the capacitor 369b, and an electrode 375 is formed over the insulating layer 373. The electrode 375 is electrically connected to the electrode 367 through a contact plug 374.

[0451] In addition, insulating layers 376, 377, 378, and 379 are provided on the electrode 375. In addition, an electrode 380 is buried in the insulating layers 376 to 379. The electrode 380 and the electrode 375 are electrically connected.

[0452] In addition, an insulating layer 381 and an insulating layer 382 are provided on the electrode 380 and the insulating layer 379 .

[0453] <Deformation example>

[0454] Fig.29 A cross section of a portion of a memory device 300A is shown. The memory device 300A is a modified example of the memory device 300. The memory device 300A includes a layer 310A and a layer 320. An insulating substrate (eg, a glass substrate) is used as a substrate 231 of the memory device 300A.

[0455] Layer 310A includes transistor 268a, transistor 268b, and capacitor 269a. Thin film transistors (e.g., OS transistors) are used as transistors in layer 310A. Layer 310A can be made into a unipolar integrated circuit by using OS transistors as transistors in layer 310A. By making all transistors in memory device 300A OS transistors, memory device 300A can be made into a unipolar memory device.

[0456] <Constitution Materials<

[0457] [Substrate]

[0458] Although there is no great restriction on the material used for the substrate, the substrate must have at least a sufficiently high heat resistance to withstand the subsequent heat treatment. For example, as a substrate, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, etc., etc. can be used. In addition, an SOI substrate or a substrate having semiconductor elements such as strained transistors or FIN-type transistors arranged on a semiconductor substrate can also be used. In addition, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, etc. that can be used for high electron mobility transistors (HEMT: High Electron Mobility Transistor) can also be used. In other words, the substrate is not only a supporting substrate, but can also be a substrate on which other devices such as transistors are formed.

[0459] In addition, as the substrate, a glass substrate such as barium borosilicate glass and aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. In addition, as the substrate, a flexible substrate can be used. When a flexible substrate is used, transistors and capacitors can be directly manufactured on the flexible substrate, or transistors and capacitors can be manufactured on other manufacturing substrates and then peeled off and transferred to the flexible substrate. In addition, in order to peel off transistors and capacitors from the manufacturing substrate and transfer them to the flexible substrate, it is preferred to provide a peeling layer between the manufacturing substrate and the transistors and capacitors.

[0460] As the flexible substrate, for example, metal, alloy, resin or glass, or fibers thereof can be used. The lower the linear expansion coefficient of the flexible substrate used as the substrate, the more deformation caused by the environment is suppressed, so it is preferred. For example, a flexible substrate with a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less or 1×10 -5 / K or less. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable for flexible substrates.

[0461] [Insulation layer]

[0462] The insulating layer is a single layer or a stack of the following materials, and the material is selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In addition, a material mixed with multiple materials of oxide materials, nitride materials, oxynitride materials, and oxynitride materials can also be used.

[0463] In this specification, etc., nitrogen oxide refers to a compound in which the nitrogen content is greater than the oxygen content. In addition, oxynitride refers to a compound in which the oxygen content is greater than the nitrogen content. In addition, for example, the content of each element can be measured using Rutherford backscattering spectroscopy (RBS: Rutherford Backscattering Spectrometry) or the like.

[0464] In addition, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, in order to prevent the hydrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the hydrogen concentration in the insulating layer. Specifically, the hydrogen concentration in the insulating layer measured by secondary ion mass spectrometry (SIMS) is 2×10 20 atoms / cm 3Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

[0465] In order to prevent the nitrogen concentration in the semiconductor layer from increasing, it is preferable to reduce the nitrogen concentration in the insulating layer. Specifically, the nitrogen concentration in the insulating layer measured by SIMS is 5×10 19 atoms / cm 3 Below, preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0466] The defects in at least the region of the insulating layer that contacts the semiconductor layer and at least the region of the insulating layer that contacts the semiconductor layer are preferably few, and typically the signal observed by the electron spin resonance method (ESR) is preferably few. For example, as the above signal, the E' center observed when the g value is 2.001 can be cited. The E' center is caused by the dangling bond of silicon. For example, when a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, a spin density of 3×10 17 spins / cm 3 Below, preferably 5×10 16 spins / cm 3 The following silicon oxide layer or silicon oxynitride layer.

[0467] Sometimes, in addition to the above signals, a signal caused by nitrogen dioxide (NO2) is observed. This signal is split into three signals due to the nuclear spin of N, each with a g value of 2.037 or more and 2.039 or less (first signal), a g value of 2.001 or more and 2.003 or less (second signal), and a g value of 1.964 or more and 1.966 or less (third signal).

[0468] For example, it is preferable to use a signal derived from nitrogen dioxide (NO2) with a spin density of 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm3 insulation layer.

[0469] Nitrogen dioxide (NO2) and other nitrogen oxides (NO x ) forms an energy level in the insulating layer. This energy level is located in the energy gap of the oxide semiconductor layer. x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, sometimes this energy level captures electrons on the insulating layer side. As a result, the captured electrons remain near the interface between the insulating layer and the oxide semiconductor layer, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, by using a film with a low content of oxynitride as the insulating layer and the insulating layer, the drift of the threshold voltage of the transistor can be reduced.

[0470] As nitrogen oxides (NO x For example, an insulating layer with a low release amount of ammonia can be a silicon oxynitride layer. The silicon oxynitride layer has a lower release amount of ammonia than nitrogen oxides (NO x ) release, typically 1×10 18 Pieces / cm 3 Above and 5×10 19 Pieces / cm 3 Note that the above-mentioned ammonia release amount is the total amount in the range of the heat treatment temperature in TDS being 50° C. to 650° C. or 50° C. to 550° C.

[0471] Since nitrogen oxides (NO x ) reacts with ammonia and oxygen, so by using an insulating layer that releases a lot of ammonia, nitrogen oxides (NO x ).

[0472] At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer that releases oxygen by heating. Specifically, it is preferable to use an insulating layer whose oxygen release amount converted to oxygen atoms when TDS analysis is performed (wherein the layer surface temperature is heated to 100° C. to 700° C., preferably 100° C. to 500° C.) is 1.0×10 18 atoms / cm 3 Above, 1.0×10 19 atoms / cm 3 Above, or 1.0×10 20 atoms / cm 3 Note that oxygen released by heating is also referred to as "excess oxygen" in this specification and the like.

[0473] The insulating layer containing excess oxygen can also be formed by adding oxygen to the insulating layer. As the oxygen addition treatment, heat treatment in an oxygen atmosphere, plasma treatment, etc. can be used. Alternatively, oxygen addition can be performed by ion implantation, ion doping, plasma immersion ion implantation, etc. Examples of the gas used for the oxygen addition treatment include 16 O2 or 18 Oxygen gas such as O2, oxygen-containing gas such as nitrous oxide gas or ozone gas. In this specification, the process of adding oxygen is also referred to as "oxygen doping process". The oxygen doping process can also be performed while heating the substrate.

[0474] As the insulating layer, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. can be used. In addition to the above-mentioned organic materials, low-k materials, siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. In addition, the insulating layer can also be formed by stacking a plurality of insulating layers formed of these materials.

[0475] Siloxane resins are equivalent to resins containing Si-O-Si bonds formed using siloxane materials as starting materials. Siloxane resins may also use organic groups (such as alkyl groups or aryl groups) or fluorine groups as substituents. In addition, the organic groups may also include fluorine groups.

[0476] There is no particular limitation on the method for forming the insulating layer. Note that a baking process may be required depending on the material used for the insulating layer. In this case, the baking process of the insulating layer can be combined with other heat treatment processes to efficiently manufacture the transistor.

[0477] [electrode]

[0478] As the conductive material for forming the electrode, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc. can be used. In addition, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus, a silicide such as nickel silicide, etc. can also be used.

[0479] In addition, a conductive material containing the above-mentioned metal element and oxygen can also be used. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, indium tin oxide (ITO: Indium Tin Oxide), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium gallium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used.

[0480] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked for use. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a conductive material containing nitrogen and a conductive material containing oxygen are combined may also be used.

[0481] In addition, when an oxide semiconductor is used as the semiconductor layer and a stacked structure of a material containing the above-mentioned metal element and a conductive material containing oxygen is used as the gate electrode, it is preferred to provide a conductive material containing oxygen on one side of the semiconductor layer. By providing a conductive material containing oxygen on one side of the semiconductor layer, oxygen released from the conductive material can be easily supplied to the semiconductor layer.

[0482] In addition, as an electrode, for example, a highly embedded conductive material such as tungsten or polysilicon can be used. In addition, a combination of a highly embedded conductive material and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer can also be used. Sometimes the electrode is called a "contact plug".

[0483] In particular, it is preferable to use a conductive material that does not easily allow impurities to pass through as an electrode in contact with the gate insulator. As an example of a conductive material that does not easily allow impurities to pass through, tantalum nitride can be mentioned.

[0484] By using an insulating material that is not easily permeable to impurities as an insulating layer and a conductive material that is not easily permeable to impurities as an electrode, it is possible to further suppress the diffusion of impurities into the transistor. As a result, the reliability of the transistor can be further improved. In other words, the reliability of the storage device can be further improved.

[0485] [Semiconductor layer]

[0486] As the semiconductor layer, one or more of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor can be used. As the semiconductor material, for example, silicon or germanium can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, or organic semiconductors can also be used.

[0487] When an organic semiconductor is used as the semiconductor layer, a low molecular weight organic material having an aromatic ring or a π-electron conjugated conductive polymer can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene, etc. can be used.

[0488] The semiconductor layer may also adopt a stacked structure. When the semiconductor layer adopts a stacked structure, semiconductors with different crystal states or different semiconductor materials may be used.

[0489] In addition, since the band gap of an oxide semiconductor, which is a type of metal oxide, is greater than 2 eV, when an oxide semiconductor is used as a semiconductor layer, a transistor with extremely small off-state current can be realized. Specifically, the off-state current per 1 μm channel width can be less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24 A. That is, the on-off ratio can be more than 20 digits. In addition, in a transistor using an oxide semiconductor as a semiconductor layer (OS transistor), the insulation withstand voltage between the source and the drain is high. Thus, a transistor with good reliability can be provided. In addition, a transistor with a large output voltage and a high withstand voltage can be provided. In addition, a storage device with good reliability can be provided. In addition, a storage device with a large output voltage and a high withstand voltage can be provided.

[0490] In this specification and the like, a transistor using crystalline silicon in a semiconductor layer forming a channel is referred to as a "crystalline Si transistor".

[0491] Compared with OS transistors, crystalline Si transistors can easily obtain higher mobility. On the other hand, it is difficult for crystalline Si transistors to achieve an extremely small off-state current like OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer according to the purpose or use. For example, a combination of OS transistors and crystalline Si transistors, etc., can be used according to the purpose or use.

[0492] When an oxide semiconductor layer is used as a semiconductor layer, it is preferred to form the oxide semiconductor layer by a sputtering method. When the oxide semiconductor layer is formed by a sputtering method, the density of the oxide semiconductor layer can be increased, so it is preferred. In the case of forming the oxide semiconductor layer by a sputtering method, as a sputtering gas, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen can be used. In addition, the sputtering gas needs to be highly purified. For example, as an oxygen gas or a rare gas used as a sputtering gas, a high-purity gas with a dew point of less than -60°C, preferably less than -100°C, is used. By using a high-purity sputtering gas to form a thin film, it is possible to prevent moisture and the like from mixing into the oxide semiconductor layer as much as possible.

[0493] When the oxide semiconductor layer is formed by sputtering, it is preferable to remove as much water as possible from the film forming chamber of the sputtering device. For example, it is preferable to use an adsorption vacuum pump such as a cryopump to evacuate the film forming chamber to a high vacuum (to 5×10 -7 Pa to 1×10 -4 In particular, when the sputtering device is on standby, the partial pressure of the gas molecules corresponding to H2O (the gas molecules corresponding to m / z=18) in the film forming processing chamber is preferably 1×10 -4 Pa or less, more preferably 5×10 -5 Below Pa.

[0494] [Metal oxides]

[0495] The oxide semiconductor, which is a type of metal oxide, preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it is preferred that, in addition to these, it also contains aluminum, gallium, yttrium or tin. In addition, it may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0496] Here, the case where the oxide semiconductor includes indium, element M, and zinc is considered. Note that element M is aluminum, gallium, yttrium, or tin. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that as element M, a plurality of the above elements may be combined.

[0497] In addition, in this specification and the like, a metal oxide containing nitrogen may be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0498] [Composition of Metal Oxides]

[0499] Hereinafter, the configuration of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described.

[0500] In this specification, etc., it may be described as CAAC (c-axis aligned crystal) or CAC (Cloud-Aligned Composite). Note that CAAC is an example of a crystal structure, and CAC is an example of a function or a material configuration.

[0501] CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in another part of the material, and has a semiconductor function as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC-metal oxide can have a switching function (a function of controlling on / off). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0502] In addition, CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated with a nanoparticle level. In addition, the conductive region and the insulating region are sometimes distributed unevenly in the material. In addition, sometimes the conductive region whose edge is fuzzy and connected with a cloud shape is observed.

[0503] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0504] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. In addition, the component with the narrow gap interacts with the component with the narrow gap through the complementary effect with the component with the wide gap, so that the carriers flow through the component with the wide gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on-state of the transistor.

[0505] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).

[0506] [Structure of Metal Oxide]

[0507] Oxide semiconductors, which are a type of metal oxide, are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0508] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has distortion. Note that distortion refers to the part where the lattice arrangement direction changes between the region where the multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0509] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, in the distortion, there is sometimes a lattice arrangement such as a pentagon or a heptagon. In addition, in CAAC-OS, no clear grain boundary is observed even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bonding distance between atoms caused by the substitution of metal elements.

[0510] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be represented as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0511] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. In addition, the crystallinity of metal oxides is sometimes reduced due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is a metal oxide with few impurities or defects (oxygen vacancies, etc.). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

[0512] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0513] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductor. a-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0514] Oxide semiconductors (metal oxides) have various structures and various characteristics. Oxide semiconductors may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0515] [Transistor with metal oxide]

[0516] Next, a case where the above-mentioned metal oxide is used in a channel formation region of a transistor will be described.

[0517] By using the above-mentioned metal oxide in the channel formation region of the transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0518] In addition, metal oxides with low carrier density are preferably used for transistors. When the carrier density of a metal oxide film is to be reduced, the impurity concentration in the metal oxide film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in a metal oxide can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and is 1×10 -9 / cm 3 above.

[0519] Furthermore, high purity intrinsic or substantially high purity intrinsic metal oxide films have a lower defect state density and thus sometimes have a lower trap state density.

[0520] Furthermore, it takes a long time for the charges trapped in the trap states of the metal oxide to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region in a metal oxide with a high trap state density may be unstable.

[0521] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0522] [Impurities]

[0523] Here, the influence of each impurity in the metal oxide is described.

[0524] When the metal oxide contains silicon or carbon, which is one of the elements of Group 14, defect states are formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide or near the interface of the metal oxide (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0525] In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0526] When the metal oxide contains nitrogen, electrons as carriers are easily generated, which increases the carrier density and becomes n-type. As a result, a transistor using a metal oxide containing nitrogen in a channel formation region tends to have a normally-on characteristic. Therefore, in the metal oxide, it is preferred to reduce nitrogen in the channel formation region as much as possible. For example, the nitrogen concentration in the metal oxide measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0527] Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to generate water, thus sometimes forming oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using a metal oxide containing hydrogen as a channel formation region tend to have a normally-on characteristic. Therefore, it is preferred to reduce the hydrogen in the metal oxide as much as possible. Specifically, in the metal oxide, the hydrogen concentration measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0528] By using a metal oxide whose impurity concentration is sufficiently reduced in a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0529] <Film Formation Method>

[0530] The insulating material used to form the insulating layer, the conductive material used to form the electrode, or the semiconductor material used to form the semiconductor layer can be formed by sputtering, spin coating, chemical vapor deposition (CVD: Chemical Vapor Deposition) method (including thermal CVD method, organic metal CVD (MOCVD: Metal Organic Chemical Vapor Deposition) method, plasma enhanced CVD (PECVD: Plasma Enhanced CVD) method, high density plasma CVD (HDPCVD: High density plasma CVD) method, reduced pressure CVD (LPCVD: low pressure CVD) method, atmospheric pressure CVD (APCVD: atmospheric pressure CVD) method, etc.), atomic layer deposition (ALD: Atomic Layer Deposition) method or molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method, dip coating, spraying, droplet jetting method (inkjet method, etc.), printing method (screen printing, offset printing, etc.).

[0531] The plasma CVD method can obtain a high-quality film at a relatively low temperature. In the case of a film forming method that does not use plasma, such as the MOCVD method, the ALD method, or the thermal CVD method, damage is not easily generated on the formed surface. For example, the wiring, electrodes, elements (transistors, capacitors, etc.) included in the storage device sometimes generate charge accumulation (charge up) due to receiving charges from plasma. At this time, the wiring, electrodes, elements, etc. included in the storage device are sometimes damaged due to the accumulated charges. On the other hand, in the case of a film forming method that does not use plasma, since such plasma damage does not occur, the yield of the storage device can be improved. In addition, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.

[0532] Unlike the film-forming method of depositing particles released from a target material, the CVD method and the ALD method are film-forming methods that form a film due to a reaction on the surface of the object to be processed. Therefore, the film formed by the CVD method and the ALD method is not easily affected by the shape of the object to be processed, and has good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the film-forming speed of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other film-forming methods such as the CVD method with a fast film-forming speed.

[0533] The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow ratio of the source gases. For example, when the CVD method and the ALD method are used, a film of any composition can be formed by adjusting the flow ratio of the source gases. In addition, for example, when the CVD method and the ALD method are used, a film whose composition changes continuously can be formed by changing the flow ratio of the source gases while forming the film. When the film is formed while changing the flow ratio of the source gases, since the time required for conveying and adjusting the pressure can be omitted, the time required for film formation can be shortened compared to the case where the film is formed using multiple film forming chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0534] Note that when the film is formed by the ALD method, it is preferable to use a gas that does not contain chlorine as a material gas.

[0535] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0536] (Implementation 7)

[0537] In this embodiment, a structural example of a transistor which can be applied to the semiconductor device or the like described in the above embodiment will be described.

[0538] <Transistor Structure Example 1>

[0539] Reference Fig. 30A , Fig. 30B and Fig. 30C A structural example of the transistor 510A is described. Fig. 30A is a top view of transistor 510A. Fig. 30B is Fig. 30A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 30C is Fig. 30A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig. 30A In the top view, for the sake of clarity, part of the components are omitted and shown.

[0540] exist Fig. 30A , Fig. 30B and Fig. 30C 5 shows a transistor 510A, an insulating layer 511 used as an interlayer film, an insulating layer 512, an insulating layer 514, an insulating layer 516, an insulating layer 580, an insulating layer 582, and an insulating layer 584. In addition, a conductive layer 546 (a conductive layer 546a and a conductive layer 546b) which is electrically connected to the transistor 510A and used as a contact plug, and a conductive layer 503 used as a wiring are shown.

[0541] The transistor 510A includes: a conductive layer 560 (conductive layer 560a and conductive layer 560b) used as a first gate electrode; a conductive layer 505 (conductive layer 505a and conductive layer 505b) used as a second gate electrode; an insulating layer 550 used as a first gate insulator; insulating layers 521, 522, and 524 used as second gate insulators; an oxide 530 (oxide 530a, oxide 530b, and oxide 530c) including a region where a channel is formed; a conductive layer 542a used as one of a source and a drain; a conductive layer 542b used as the other of a source and a drain; and an insulating layer 574.

[0542] 30, an oxide 530c, an insulating layer 550, and a conductive layer 560 are provided in an opening provided in the insulating layer 580 via an insulating layer 574. The oxide 530c, the insulating layer 550, and the conductive layer 560 are provided between the conductive layer 542a and the conductive layer 542b.

[0543] The insulating layer 511 and the insulating layer 512 serve as an interlayer film.

[0544] As the interlayer film, a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide can be added to these insulators. In addition, these insulators can also be nitrided. Silicon oxide, silicon oxynitride or silicon nitride can also be stacked on the above-mentioned insulators.

[0545] For example, the insulating layer 511 is preferably used as a barrier layer for suppressing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, as the insulating layer 511, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In addition, for example, it is preferable to use aluminum oxide or silicon nitride as the insulating layer 511. By adopting this structure, it is possible to suppress impurities such as hydrogen and water from diffusing from the side closer to the substrate than the insulating layer 511 to the side of the transistor 510A.

[0546] For example, the dielectric constant of the insulating layer 512 is preferably lower than that of the insulating layer 511. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0547] The conductive layer 503 is formed in a manner embedded in the insulating layer 512. Here, the height of the top surface of the conductive layer 503 and the height of the top surface of the insulating layer 512 may be substantially the same. The conductive layer 503 has a single-layer structure, but the present invention is not limited thereto. For example, the conductive layer 503 may also have a stacked structure of two or more layers. As the conductive layer 503, a highly conductive conductive material having tungsten, copper or aluminum as a main component is preferably used.

[0548] In transistor 510A, conductive layer 560 is sometimes used as a first gate (also referred to as a top gate) electrode. Conductive layer 505 is used as a second gate (also referred to as a bottom gate) electrode. In this case, by independently changing the potential supplied to conductive layer 505 without interlocking it with the potential supplied to conductive layer 560, the threshold voltage of transistor 510A can be controlled. In particular, by supplying a negative potential to conductive layer 505, the threshold voltage of transistor 510A can be made greater than 0V and the off-state current can be reduced. Therefore, compared to when a negative potential is not supplied to conductive layer 505, when a negative potential is supplied to conductive layer 505, the drain current when the potential supplied to conductive layer 560 is 0V can be reduced.

[0549] In addition, for example, by overlapping the conductive layer 505 with the conductive layer 560 , when a potential is supplied to the conductive layer 560 and the conductive layer 505 , the electric field generated from the conductive layer 560 and the electric field generated from the conductive layer 505 are connected, so that the channel formation region formed in the oxide 530 can be covered.

[0550] That is, the channel formation region can be electrically surrounded by the electric field of the conductive layer 560 used as the first gate electrode and the electric field of the conductive layer 505 used as the second gate electrode. In this specification, the structure of the transistor in which the channel formation region is electrically surrounded by the electric field of the first gate electrode and the electric field of the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0551] The insulating layer 514 and the insulating layer 516 are used as interlayer films, similarly to the insulating layer 511 and the insulating layer 512. For example, the insulating layer 514 is preferably used as a barrier layer for suppressing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. By adopting this structure, it is possible to suppress impurities such as hydrogen and water from diffusing from the side closer to the substrate than the insulating layer 514 to the transistor 510A side. For example, the dielectric constant of the insulating layer 516 is preferably lower than that of the insulating layer 514. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0552] In the conductive layer 505 used as the second gate, a conductive layer 505a is formed in contact with the inner wall of the opening of the insulating layer 514 and the insulating layer 516, and a conductive layer 505b is formed inside. Here, the height of the top surface of the conductive layer 505a and the conductive layer 505b may be substantially the same as the height of the top surface of the insulating layer 516. In addition, in the transistor 510A, the conductive layer 505a and the conductive layer 505b are stacked, but the present invention is not limited to this. For example, the conductive layer 505 may have a single-layer structure or a stacked structure of three or more layers.

[0553] Here, as the conductive layer 505a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In this specification, "the function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0554] For example, by providing the conductive layer 505a with a function of suppressing diffusion of oxygen, a decrease in conductivity due to oxidation of the conductive layer 505b can be suppressed.

[0555] In addition, when the conductive layer 505 also has a wiring function, it is preferable to use a highly conductive conductive material with tungsten, copper or aluminum as a main component as the conductive layer 505b. In this case, it is not necessary to provide the conductive layer 503. In the drawings, the conductive layer 505b has a single-layer structure, but it may also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials may be used.

[0556] The insulating layer 521 , the insulating layer 522 , and the insulating layer 524 function as a second gate insulator.

[0557] The insulating layer 522 preferably has a barrier property. When the insulating layer 522 has a barrier property, the insulating layer 522 serves as a layer for suppressing impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A.

[0558] As the insulating layer 522, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium silicate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin filming of the gate insulator. By using a high-k material as an insulator used as a gate insulator, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0559] For example, the insulating layer 521 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulating layer 521 having a stacked structure with thermal stability and a high relative dielectric constant can be formed.

[0560] Note that in Fig. 30, the second gate insulator has a three-layer stacked structure, but may have a single-layer structure or a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials.

[0561] The oxide 530 including the region used as the channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. When the oxide 530a is provided below the oxide 530b, impurities can be prevented from diffusing from the structure formed below the oxide 530a to the oxide 530b. When the oxide 530c is provided above the oxide 530b, impurities can be prevented from diffusing from the structure formed above the oxide 530c to the oxide 530b. As the oxide 530, an oxide semiconductor of one of the metal oxides described in the above embodiment can be used.

[0562] The oxide 530c is preferably provided in the opening provided in the insulating layer 580 via the insulating layer 574. When the insulating layer 574 has a barrier property, diffusion of impurities from the insulating layer 580 into the oxide 530 can be suppressed.

[0563] One of the conductive layers 542 serves as a source electrode, and the other serves as a drain electrode.

[0564] Conductive layer 542a, conductive layer 542b can be made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum or tungsten, or an alloy containing these elements as main components. In particular, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen and oxygen and have high oxidation resistance.

[0565] In addition, although a single-layer structure is shown in FIG. 30 , a stacked structure of two or more layers may be adopted. For example, a tantalum nitride film and a tungsten film are preferably stacked. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be adopted.

[0566] In addition, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0567] Alternatively, a barrier layer may be provided over the conductive layer 542. The barrier layer is preferably made of a substance that has a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductive layer 542 can be suppressed when the insulating layer 574 is formed.

[0568] The barrier layer may be made of, for example, a metal oxide. In particular, it is preferable to use an insulating film having barrier properties to oxygen or hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide. Alternatively, silicon nitride formed by CVD may be used.

[0569] By including the barrier layer, the range of choices for the material of the conductive layer 542 can be expanded. For example, a material with low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used for the conductive layer 542. In addition, for example, a conductor that is easy to deposit or process can be used.

[0570] The insulating layer 550 is used as a first gate insulator. The insulating layer 550 is preferably provided in the opening provided in the insulating layer 580 via the oxide 530 c and the insulating layer 574 .

[0571] When miniaturization and high integration of transistors are performed, leakage current and other problems may occur due to the thin film of the gate insulator. In this case, the insulating layer 550 may also have a laminated structure, similar to the second gate insulator. By making the insulator used as the gate insulator have a laminated structure of a high-k material and a thermally stable material, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a laminated structure with thermal stability and a high relative dielectric constant can be achieved.

[0572] The conductive layer 560 used as the first gate electrode includes a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. As with the conductive layer 505a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used as the conductive layer 560a. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0573] When the conductive layer 560a has a function of suppressing diffusion of oxygen, the selectivity of the material of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, and a decrease in conductivity can be prevented.

[0574] As a conductive material having a function of inhibiting the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, as the conductive layer 560a, an oxide semiconductor that can be used for the oxide 530 can be used. In this case, by forming the conductive layer 560b by sputtering, the resistivity of the oxide semiconductor can be reduced to make it a conductor. The conductor can be called an OC (Oxide Conductor) electrode.

[0575] As the conductive layer 560b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. Since the conductive layer 560 is used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductive layer 560b can also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials can be used.

[0576] An insulating layer 574 is disposed between the insulating layer 580 and the transistor 510A. An insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used as the insulating layer 574. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0577] By including the insulating layer 574, impurities such as water and hydrogen contained in the insulating layer 580 can be prevented from diffusing into the oxide 530b through the oxide 530c and the insulating layer 550. In addition, oxidation of the conductive layer 560 by excess oxygen contained in the insulating layer 580 can be prevented.

[0578] The insulating layer 580 , the insulating layer 582 , and the insulating layer 584 serve as an interlayer film.

[0579] Similar to the insulating layer 514, the insulating layer 582 is preferably used as a block insulating film for preventing impurities such as water and hydrogen from entering the transistor 510A from the outside.

[0580] As with the insulating layer 516, the insulating layer 580 and the insulating layer 584 preferably have a lower dielectric constant than the insulating layer 582. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0581] In addition, the transistor 510A may be electrically connected to other structures through plugs or wiring such as the conductive layer 546 embedded in the insulating layer 580 , the insulating layer 582 , and the insulating layer 584 .

[0582] In addition, as with the conductive layer 505, as the material of the conductive layer 546, a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. For example, a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity is preferably used. Alternatively, a low resistance conductive material such as aluminum or copper is preferably used. By using a low resistance conductive material, wiring resistance can be reduced.

[0583] For example, by using a stacked-layer structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity, as the conductive layer 546, diffusion of impurities from the outside can be suppressed while maintaining the conductivity of the wiring.

[0584] By having the above structure, a semiconductor device having a transistor including an oxide semiconductor with a large on-state current can be provided. Alternatively, a semiconductor device having a transistor including an oxide semiconductor with a small off-state current can be provided. Alternatively, a semiconductor device having improved reliability while suppressing variations in electrical characteristics and having stable electrical characteristics can be provided.

[0585] <Transistor Structure Example 2>

[0586] Reference Fig.31A , Fig.31B and Fig.31C A structural example of the transistor 510B is described. Fig.31A is a top view of transistor 510B. Fig.31B is Fig.31AA cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.31C is Fig.31A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.31A In the top view, part of the components are omitted for clarity.

[0587] The transistor 510B is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0588] The transistor 510B includes a region where the conductive layer 542 (the conductive layer 542a and the conductive layer 542b) overlaps with the oxide 530c, the insulating layer 550, and the conductive layer 560. With this structure, a transistor with a large on-state current can be provided. In addition, a transistor with high controllability can be provided.

[0589] The conductive layer 560 used as the first gate electrode includes a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. As with the conductive layer 505a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used as the conductive layer 560a. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0590] When the conductive layer 560a has a function of suppressing diffusion of oxygen, the selectivity of the material of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, oxidation of the conductive layer 560b can be suppressed, and a decrease in conductivity can be prevented.

[0591] In addition, it is preferable to provide an insulating layer 574 so as to cover the top surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the oxide 530c. As the insulating layer 574, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0592] By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. In addition, by including the insulating layer 574, diffusion of impurities such as water and hydrogen contained in the insulating layer 580 into the transistor 510B can be suppressed.

[0593] Alternatively, an insulating layer 576 (insulating layer 576a and insulating layer 576b) having a barrier property may be provided between the conductive layer 546 and the insulating layer 580. Providing the insulating layer 576 can prevent oxidation of the conductive layer 546 due to reaction of oxygen in the insulating layer 580 with the conductive layer 546.

[0594] Furthermore, by providing the insulating layer 576 having a barrier property, the range of choices for the material of the conductor used for the plug or the wiring can be expanded. For example, as the conductive layer 546, a metal material having a property of absorbing oxygen and having high conductivity can be used.

[0595] <Transistor structure example 3>

[0596] Reference Fig.32A , Fig.32B and Fig.32C A structural example of the transistor 510C is described. Fig.32A is a top view of transistor 510C. Fig.32B is Fig.32A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.32C is Fig.32A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.32A In the top view, part of the components are omitted for clarity.

[0597] The transistor 510C is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0598] In the transistor 510C shown in FIG. 32 , a conductive layer 547a is disposed between the conductive layer 542a and the oxide 530b, and a conductive layer 547b is disposed between the conductive layer 542b and the oxide 530b. Here, the conductive layer 542a (conductive layer 542b) has a region extending beyond the top surface of the conductive layer 547a (conductive layer 547b) and the side surface on one side of the conductive layer 560 and in contact with the top surface of the oxide 530b. Here, as the conductive layer 547, a conductor that can be used for the conductive layer 542 can be used. In addition, the thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 542.

[0599] Since the transistor 510C shown in FIG32 has the above structure, the conductive layer 542 can be closer to the conductive layer 560 than the transistor 510A. Alternatively, the end of the conductive layer 542a and the end of the conductive layer 542b can overlap with the conductive layer 560. Thus, the substantial channel length of the transistor 510C can be reduced, and the on-state current and frequency characteristics can be improved.

[0600] In addition, the conductive layer 547a (conductive layer 547b) preferably overlaps the conductive layer 542a (conductive layer 542b). With this structure, when etching is performed to form an opening to fill the conductive layer 546a (conductive layer 546b), the conductive layer 547a (conductive layer 547b) is used as an etching stopper to prevent overetching of the oxide 530b.

[0601] In the transistor 510C shown in FIG32, an insulating layer 545 may be provided in contact with the insulating layer 544. The insulating layer 544 is preferably used as a blocking insulating film for suppressing impurities such as water or hydrogen or excess oxygen from entering the transistor 510C from the insulating layer 580 side. As the insulating layer 545, an insulator that can be used for the insulating layer 544 can be used. In addition, for example, a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon oxynitride can be used for the insulating layer 544.

[0602] In addition, in the transistor 510C shown in FIG32, unlike the transistor 510A shown in FIG30, the conductive layer 505 may also have a single-layer structure. At this time, an insulating film to become an insulating layer 516 may be formed on the conductive layer 505 that has been formed into a pattern, and the top of the insulating film is removed by using a CMP method or the like until the top surface of the conductive layer 505 is exposed. Here, it is preferred to improve the flatness of the top surface of the conductive layer 505. For example, the average surface roughness (Ra) of the top surface of the conductive layer 505 may be less than 1 nm, preferably less than 0.5 nm, and more preferably less than 0.3 nm. Thus, the flatness of the insulating layer formed on the conductive layer 505 can be improved, and the crystallinity of the oxide 530b and the oxide 530c can be improved.

[0603] <Transistor Structure Example 4>

[0604] Reference Fig.33A , Fig.33B and Fig.33C A structural example of the transistor 510D is described. Fig.33A is a top view of transistor 510D. Fig.33B is Fig.33A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.33C is Fig.33A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.33A In the top view, part of the components are omitted for clarity.

[0605] The transistor 510D is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0606] exist FIG. 33A to FIG. 33C In the embodiment, the conductive layer 505 having the function of the second gate is also used as a wiring without providing the conductive layer 503. In addition, an insulating layer 550 is included on the oxide 530c, and a metal oxide 552 is included on the insulating layer 550. In addition, a conductive layer 560 is included on the metal oxide 552, and an insulating layer 570 is included on the conductive layer 560. In addition, an insulating layer 571 is included on the insulating layer 570.

[0607] The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 that suppresses oxygen diffusion between the insulating layer 550 and the conductive layer 560, oxygen diffusion to the conductive layer 560 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductive layer 560 due to oxygen can be suppressed.

[0608] In addition, the metal oxide 552 may be used as a part of the first gate. For example, an oxide semiconductor that can be used as the oxide 530 may be used as the metal oxide 552. In this case, by forming the conductive layer 560 by sputtering, the resistance value of the metal oxide 552 may be reduced to make it a conductive layer. This may be referred to as an OC (Oxide Conductor) electrode.

[0609] In addition, the metal oxide 552 is sometimes used as a part of the gate insulator. Therefore, in the case where silicon oxide or silicon oxynitride is used for the insulating layer 550, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide 552. By adopting this stacked structure, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential supplied when the transistor is operating can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulator can be reduced.

[0610] Although the metal oxide 552 in the transistor 510D is shown as a single-layer structure, a stacked structure of two or more layers may be adopted. For example, a metal oxide used as a part of the gate electrode and a metal oxide used as a part of the gate insulator may be stacked.

[0611] When the metal oxide 552 is used as a gate electrode, the on-state current of the transistor 510D can be increased without weakening the influence of the electric field from the conductive layer 560. In addition, when the metal oxide 552 is used as a gate insulator, the leakage current between the conductive layer 560 and the oxide 530 can be suppressed by maintaining the distance between the conductive layer 560 and the oxide 530 using the physical thickness of the insulating layer 550 and the metal oxide 552. Thus, by providing a stacked structure of the insulating layer 550 and the metal oxide 552, the physical distance between the conductive layer 560 and the oxide 530 and the electric field strength applied from the conductive layer 560 to the oxide 530 can be easily adjusted.

[0612] Specifically, an oxide semiconductor that can be used for the oxide 530 can be used as the metal oxide 552 by reducing its resistance. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0613] In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as an insulating layer containing an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. Note that the metal oxide 552 is not an essential component and can be appropriately designed according to the desired transistor characteristics.

[0614] An insulating material having a function of inhibiting the permeation of impurities such as water or hydrogen and oxygen is preferably used as the insulating layer 570. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxidation of the conductive layer 560 due to oxygen from above the insulating layer 570 can be prevented. In addition, impurities such as water or hydrogen from above the insulating layer 570 can be inhibited from entering the oxide 230 through the conductive layer 560 and the insulating layer 550.

[0615] The insulating layer 571 is used as a hard mask. By providing the insulating layer 571, the conductive layer 560 can be processed in such a way that the side surface of the conductive layer 560 is approximately perpendicular to the substrate surface. Specifically, the angle formed by the side surface of the conductive layer 560 and the substrate surface can be made greater than 75 degrees and less than 100 degrees, preferably greater than 80 degrees and less than 95 degrees.

[0616] Alternatively, the insulating layer 571 may also function as a barrier layer by using an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. In this case, the insulating layer 570 may not be provided.

[0617] By using the insulating layer 571 as a hard mask, the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and part of the oxide 530c are selectively removed, so that their side surfaces can be roughly aligned and part of the surface of the oxide 530b can be exposed.

[0618] In addition, the transistor 510D includes a region 531a and a region 531b in a portion of the surface of the exposed oxide 530b. One of the region 531a and the region 531b is used as a source region, and the other is used as a drain region.

[0619] For example, the regions 531a and 531b can be formed by introducing an impurity element such as phosphorus or boron into the surface of the exposed oxide 530b by ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. Note that in this embodiment mode, "impurity element" refers to an element other than a main component element.

[0620] Alternatively, after a portion of the surface of the oxide 530 b is exposed, a metal film may be formed, and then heat treatment may be performed to diffuse elements included in the metal film into the oxide 530 b , thereby forming the regions 531 a and 531 b .

[0621] The resistivity of the region into which the impurity element is introduced in the oxide 530b decreases. Therefore, the region 531a and the region 531b are sometimes referred to as “impurity regions” or “low resistance regions”.

[0622] By using the insulating layer 571 and / or the conductive layer 560 as a mask, the region 531a and the region 531b can be formed in a self-aligned manner. Therefore, the region 531a and / or the region 531b do not overlap with the conductive layer 560, and the parasitic capacitance can be reduced. In addition, the bias region is not formed between the channel formation region and the source and drain region (region 531a or region 531b). By forming the region 531a and the region 531b in a self-aligned manner, an increase in on-state current, a decrease in threshold voltage, an increase in operating frequency, etc. can be achieved.

[0623] In addition, in order to further reduce the off-state current, a bias region may be provided between the channel formation region and the source / drain region. The bias region is a region with high resistivity and is a region where the above-mentioned impurity elements are not introduced. The bias region can be formed by introducing the above-mentioned impurity elements after forming the insulating layer 575. In this case, the insulating layer 575 is also used as a mask as in the case of the insulating layer 571. Therefore, the region of the oxide 530b overlapping with the insulating layer 575 is not introduced with impurity elements, thereby maintaining the resistivity of the region high.

[0624] The transistor 510D includes an insulating layer 575 on the side of the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and the oxide 530c. The insulating layer 575 is preferably an insulator with a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin is preferably used. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide with pores is used for the insulating layer 575, it is preferred because an excess oxygen region can be easily formed in the insulating layer 575 in the subsequent process. In addition, silicon oxide and silicon oxynitride are thermally stable and are therefore preferred. In addition, the insulating layer 575 preferably has a function of diffusing oxygen.

[0625] The transistor 510D includes an insulating layer 574 over the insulating layer 575 and the oxide 530. The insulating layer 574 is preferably formed by a sputtering method. By using a sputtering method, an insulator with less impurities such as water and hydrogen can be formed. For example, aluminum oxide is preferably used as the insulating layer 574.

[0626] An oxide film formed by sputtering may extract hydrogen from a structure. Therefore, the insulating layer 574 extracts hydrogen and water from the oxide 230 and the insulating layer 575 to reduce the hydrogen concentration of the oxide 230 and the insulating layer 575.

[0627] <Transistor Structure Example 5>

[0628] Reference Fig.34A , Fig.34B and Fig.34C A structural example of the transistor 510E is described. Fig.34A is a top view of transistor 510E. Fig.34B is Fig.34A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.34C is Fig.34A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.34A In the top view, part of the components are omitted for clarity.

[0629] The transistor 510E is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0630] exist FIG. 34A to FIG. 34C In the embodiment, a portion of the surface of the exposed oxide 530b includes a region 531a and a region 531b without providing a conductive layer 542. One of the region 531a and the region 531b is used as a source region, and the other is used as a drain region. In addition, an insulating layer 573 is included between the oxide 530b and the insulating layer 574.

[0631] The region 531 (region 531a and region 531b) shown in Fig. 34 is a region in which the above-mentioned elements are added to the oxide 530b. The region 531 can be formed by using a dummy gate, for example.

[0632] Specifically, it is preferable to set a dummy gate on the oxide 530b, use the dummy gate as a mask, and add an element that makes the oxide 530b low in resistance. That is, the element is added to the region of the oxide 530 that does not overlap with the dummy gate, thereby forming a region 531. As a method for adding the element, an ion implantation method in which the ionized source gas is mass-separated and added; an ion doping method in which the ionized source gas is not mass-separated and added; and a plasma immersion ion implantation method, etc. can be used.

[0633] In addition, as an element that reduces the resistance of the oxide 530, boron or phosphorus is typical. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. can also be used. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. The concentration of the element can be measured by secondary ion mass spectrometry (SIMS) or the like.

[0634] In particular, boron and phosphorus are preferred because they can be produced using equipment in amorphous silicon or low-temperature polysilicon production lines. Existing equipment can be used, thereby reducing equipment investment.

[0635] Next, an insulating film serving as an insulating layer 573 and an insulating film serving as an insulating layer 574 may be formed over the oxide 530b and the dummy gate. By providing a stack of the insulating film serving as the insulating layer 573 and the insulating film serving as the insulating layer 574, a region where the region 531 overlaps with the oxide 530c and the insulating layer 550 can be provided.

[0636] Specifically, an insulating film that becomes the insulating layer 580 is provided on the insulating film that becomes the insulating layer 574, and then the insulating film that becomes the insulating layer 580 is subjected to CMP (Chemical Mechanical Polishing) treatment to remove a portion of the insulating film that becomes the insulating layer 580, so that the dummy gate is exposed. Next, when removing the dummy gate, it is preferable to also remove a portion of the insulating layer 573 that is in contact with the dummy gate. As a result, the insulating layer 574 and the insulating layer 573 are exposed on the side of the opening provided in the insulating layer 580, and a portion of the region 531 provided in the oxide 530b is exposed on the bottom surface of the opening. Next, an oxide film that becomes the oxide 530c, an insulating film that becomes the insulating layer 550, and a conductive film that becomes the conductive layer 560 are sequentially formed in the opening, and then a portion of the oxide film that becomes the oxide 530c, the insulating film that becomes the insulating layer 550, and the conductive film that becomes the conductive layer 560 are removed by CMP treatment or the like until the insulating layer 580 is exposed, thereby forming the transistor shown in FIG. 34.

[0637] Note that the insulating layer 573 and the insulating layer 574 are not necessarily provided and may be appropriately designed depending on required transistor characteristics.

[0638] The transistor shown in FIG 34 can utilize existing equipment and does not provide a conductive layer 542, thereby reducing costs.

[0639] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0640] (Implementation 8)

[0641] This embodiment mode describes an example of an electronic component and an electronic device in which the storage device described in the above embodiment mode and the like are mounted.

[0642] <Electronic components>

[0643] First, refer to Fig.35A and Fig.35B An example of an electronic component in which the storage device 300 is incorporated will be described.

[0644] Fig.35A The electronic component 700 and a substrate (circuit board 704 ) on which the electronic component 700 is mounted are shown in a perspective view. Fig.35A The electronic component 700 shown is an IC chip, and includes leads and a circuit portion. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of these IC chips are combined and electrically connected to each other on the printed circuit board 702, thereby completing a circuit board 704.

[0645] The storage device 300 described in the above embodiment is provided as a circuit portion of the electronic component 700. Fig.35A In the embodiment, a QFP (Quad Flat Package) is used as a package of the electronic component 700, but the packaging method is not limited to this.

[0646] Fig.35B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 300 are provided on the interposer 731.

[0647] The electronic component 730 shows an example in which the storage device 300 is used as a high bandwidth memory (HBM: High Bandwidth Memory). In addition, the semiconductor device 735 can use an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0648] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0649] The plug board 731 has a function of electrically connecting a plurality of wirings to a plurality of integrated circuits having different terminal pitches. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has a function of electrically connecting an integrated circuit disposed on the plug board 731 to an electrode disposed on the package substrate 732. Therefore, the plug board is sometimes referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon plug board is used, TSV (Through Silicon Via) can also be used as a through electrode.

[0650] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring formation of a silicon interposer can be performed in a semiconductor process, and a resin interposer is easier to form fine wiring.

[0651] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0652] In addition, in SiP or MCM using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0653] Alternatively, a heat sink (heat sink plate) may be provided so as to overlap the electronic component 730. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 are aligned. For example, in the electronic component 730 shown in this embodiment, it is preferable that the heights of the storage device 300 and the semiconductor device 735 are aligned.

[0654] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the packaging substrate 732 . Fig.35B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0655] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP, QFJ (Quad Flat J-leaded package) or QFN (QuadFlat Non-leaded package) and other mounting methods can be used.

[0656] <Electronic equipment>

[0657] Next, refer to Fig.36 An example of an electronic device in which the above-mentioned electronic components are mounted will be described.

[0658] The robot 7100 includes an illumination sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezoelectric sensor, optical sensor, gyro sensor, etc.), a moving mechanism, etc. The electronic component 730 includes a processor, etc. and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data measured by the sensor.

[0659] The microphone has the function of detecting audio signals such as the user's voice and surrounding sounds. In addition, the speaker has the function of emitting audio signals such as sounds and warning sounds. The robot 7100 can analyze the audio signals input through the microphone and emit the required audio signals from the speaker. The robot 7100 can communicate with the user by using the microphone and the speaker.

[0660] The camera has a function of capturing images of the surroundings of the robot 7100. In addition, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture images of the surroundings using the camera and analyze the images to determine the presence or absence of obstacles during movement.

[0661] The flying object 7120 includes propellers, a camera, a battery, etc., and has an autonomous flight function. The electronic component 730 has a function of controlling the above peripheral devices.

[0662] For example, image data captured by a camera is stored in the electronic component 700. The electronic component 730 can analyze the image data to determine the presence or absence of obstacles during movement, etc. In addition, the electronic component 730 can estimate the remaining power of the battery by the change in the storage capacity of the battery.

[0663] The cleaning robot 7140 includes a display configured on the top surface, multiple cameras configured on the side, a brush, operation buttons, and various sensors, etc. Although not shown in the figure, the cleaning robot 7300 is equipped with tires, a suction port, etc. The cleaning robot 7300 can walk automatically, detect garbage, and suck garbage from the suction port on the bottom surface.

[0664] For example, the electronic component 730 can determine the presence or absence of obstacles such as walls, furniture or steps by analyzing the images taken by the camera. In addition, when objects such as wiring that may be wrapped around the brush are detected through image analysis, the rotation of the brush can be stopped.

[0665] The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 730 performs control to optimize the driving state of the automobile 7160 based on data such as navigation information, speed, engine status, gear selection status, brake usage frequency, etc. For example, image data captured by a camera is stored in the electronic component 700.

[0666] The electronic component 700 and / or the electronic component 730 can be installed in a TV set 7200 (television receiving device), a smartphone 7210 , a PC 7220 (personal computer), a PC 7230 , a game console 7240 , a game console 7260 , or the like.

[0667] For example, the electronic component 730 provided in the TV set 7200 may be used as an image engine. For example, the electronic component 730 performs image processing such as noise removal and up-conversion of resolution.

[0668] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. The electronic component 730 controls the above peripheral devices.

[0669] PC 7220 and PC 7230 are examples of a notebook PC and a desktop PC, respectively. Keyboard 7232 and display device 7233 can be connected to PC 7230 wirelessly or by wire. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a fixed game console. Game console 7260 is connected to controller 7262 wirelessly or by wire. Electronic component 700 and / or electronic component 730 can be installed in controller 7262.

[0670] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0671] (Implementation method 9)

[0672] In this embodiment, an application example of a storage device using the semiconductor device shown in the above embodiment is described. The semiconductor device shown in the above embodiment can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smart phone, an e-book reader terminal, a digital camera (including a video camera), a video playback device, a navigation system, etc.). Note that here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). Figure 37 schematically shows several structural examples of a removable storage device. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices or removable memories.

[0673] Fig.37A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device described in the above embodiment can be assembled to the memory chip 1105 of the substrate 1104.

[0674] Fig.37B This is a schematic diagram of the appearance of an SD card. Fig.37C 11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1114 of the substrate 1113, etc.

[0675] Fig.37D This is a schematic diagram of the appearance of SSD. Fig.37E 1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1154 of the substrate 1153, etc.

[0676] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0677] [Explanation of symbols]

[0678] 100 : semiconductor device, 110 : voltage generating circuit, 120 : voltage holding circuit, 130 : temperature detecting circuit, 131 : temperature sensor, 132 : analog-digital conversion circuit, 140 : voltage control circuit, 145 : logic circuit, 146 : voltage generating circuit.

Claims

1. A storage device, comprising: A plurality of memory cells arranged in rows and columns, each of the plurality of memory cells comprising: a transistor having a first gate and a second gate and a capacitor, the first gate and the second gate having a region overlapping each other via a semiconductor layer containing a metal oxide; a function of writing data to at least one of the plurality of storage units; a function to read data from at least one of the plurality of storage cells; A function of writing the first data to at least one of the plurality of storage cells at a first time after reading the first data held by the storage cell; A function of writing the first data to at least one of the plurality of storage cells at a second time after reading the first data held by the storage cell; and a function of supplying a first potential to the second gate of the memory cell and then stopping power supply to the plurality of memory cells, wherein the first data is multi-valued data, Furthermore, the second time is longer than the first time.

2. The storage device according to claim 1, The semiconductor layer contains at least one or both of In and Zn.

3. The storage device according to claim 1 or 2, The second time is more than 1.5 times the first time.

4. The storage device according to claim 1 or 2, The first potential is a potential that turns the transistor into an off state.

5. The storage device according to claim 4, When the threshold voltage of the transistor is VthM, the first potential is lower than -VthM.

6. A storage device, comprising: A plurality of memory cells arranged in rows and columns, each of the plurality of memory cells comprising: a transistor having a first gate and a second gate and a capacitor, the first gate and the second gate having a region overlapping each other via a semiconductor layer containing a metal oxide; a function of writing data to at least one of the plurality of storage units; a function to read data from at least one of the plurality of storage cells; A function of writing the first data to at least one of the plurality of storage cells at a first time after reading the first data held by the storage cell; A function of writing the first data to at least one of the plurality of storage cells at a second time after reading the first data held by the storage cell; and a function of supplying a first potential to the second gate of the memory cell and then stopping power supply to the plurality of memory cells, The second time is longer than the first time.

7. The storage device according to claim 6, The semiconductor layer contains at least one or both of In and Zn.

8. The storage device according to claim 6 or 7, The second time is more than 1.5 times the first time.

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