Fuse structure and storage unit
By using programmable transistors and fuse contact holes in the fuse structure, polysilicon resistors are eliminated, enabling a reduction in the size and cost of memory cells.
Patent Information
- Application Number
- CN202010526137.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-06-09
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2040-06-09
AI Technical Summary
Existing contact hole fuse structures still require polysilicon resistors, which affects the size of memory cells and results in higher costs.
A fuse structure is adopted, including a programming transistor and a fuse contact hole, which realizes programming and reading with a single transistor, eliminating the need for polysilicon resistors.
The reduced path impedance during programming further shrinks the size of the programming transistor, thereby reducing the overall area of the memory cell.
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Figure CN111627912B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and more particularly to a fuse structure and a storage unit. Background Art
[0002] OTP (One-time Programmable Memory Cell) is a commonly used technology in integrated circuits. This technology does not require additional layers or process manufacturing steps to achieve precision adjustment or customer customization of chips after they leave the factory. Its basic principle is to adjust the chip by destroying metal fuses, polysilicon fuses, breaking through oxide layers, or capturing charges through floating gates.
[0003] In the prior art, destroying polysilicon fuses or metal fuses is the most commonly used technical means. However, since destroying polysilicon fuses or metal fuses requires a large current, each bit of storage unit requires a larger size of burning MOS tube. Therefore, the size of the chip will increase and the cost will become higher.
[0004] In recent years, contact hole fuses or through-hole fuses have been proposed, and the current required for programming can be much smaller than that of polysilicon fuses or metal fuses (about one order of magnitude smaller under the same process). Therefore, the size of the MOS tube required for programming each bit storage unit will also be much smaller, and the chip size can be reduced.
[0005] refer to Figure 1 , Figure 1 This is a schematic diagram of the layout of a conventional contact hole fuse structure. Figure 2 for Figure 1 A cross-sectional schematic diagram of a contact hole fuse structure is shown.
[0006] like Figure 1 , 2 As shown, the contact hole fuse structure includes a MOS tube 110 and a polysilicon resistor structure 120. The MOS tube 110 includes a drain 111, a source 112 (N+), a body terminal P+, and a gate 113, wherein the source 112 constitutes the cathode of the contact hole fuse structure; the polysilicon resistor structure 120 includes a polysilicon resistor 121, a contact hole W1, and an anode 122, wherein one end of the polysilicon resistor 121 is connected to the drain 111 and the other end is connected to the anode 122, and the contact hole W1 is located on the side of the polysilicon resistor 121 close to the drain 111.
[0007] During the programming process, a higher voltage is biased between the anode 122 and the cathode, and the left MOS tube 110 is turned on by controlling the potential of the gate 113 so that a large current passes through the contact hole W1 to burn it, making the impedance of this path larger, which will make W1 have the weakest current capacity. After such a programming, during the reading process, the left MOS tube 110 is also turned on, and a smaller voltage is biased between the anode and the cathode to achieve reading.
[0008] However, for Figure 1 The contact hole fuse structure shown still requires a polysilicon resistor, which will inevitably affect the size of the memory cell.
[0009] Therefore, providing a contact hole fuse structure and a storage unit to further reduce the size is an urgent problem to be solved in the art. Summary of the invention
[0010] In view of this, the present invention provides a fuse structure and a storage unit, which solve the technical problem of fuse structure size in the prior art.
[0011] In one aspect, the present invention provides a fuse structure, comprising:
[0012] a programming transistor, the programming transistor comprising:
[0013] a substrate;
[0014] A first well region is disposed on the substrate
[0015] a first electrode region, disposed on the first well region;
[0016] a second electrode region, disposed on the first well region and arranged opposite to the first electrode region;
[0017] a control electrode, disposed between the first electrode region and the second electrode region, for receiving a control signal to control the electrical connection between the first electrode region and the second electrode region; and
[0018] A first contact hole, configured as a fuse contact hole, is disposed on the first electrode region of the programming transistor.
[0019] Optionally, the first electrode region is configured as an anode terminal, and the second electrode region is configured as a cathode terminal.
[0020] Optionally, the cathode terminal is provided with one or more second contact holes, and the control electrode is provided with one or more third contact holes;
[0021] The first contact hole is configured to receive a first voltage signal, the second contact hole is configured to receive a second voltage signal, and the third contact hole is configured to receive the control signal.
[0022] Optionally, the anode terminal and the cathode terminal are configured as a first bias voltage, and the control electrode controls the first electrode region to be electrically connected to the second electrode region to burn out the first contact hole.
[0023] Optionally, the anode terminal and the cathode terminal are configured as a second bias voltage, and the control electrode controls the first electrode region and the second electrode region to be electrically connected to read the current between the anode terminal and the cathode terminal.
[0024] Optionally, the programming transistor is an NMOS transistor.
[0025] Optionally, the substrate is configured as a P-type substrate;
[0026] The first well region is configured as a P-type well region;
[0027] The first electrode region is configured to be N-type heavily doped;
[0028] The second electrode region is configured to be N-type heavily doped or P-type heavily doped; and
[0029] The control electrode is made of polysilicon.
[0030] Optionally, the first electrode region is configured as a drain region, and the second electrode region is configured as a source region and a body terminal.
[0031] Optionally, the programming transistor is a PMOS transistor.
[0032] On the other hand, a storage unit includes any of the fuse structures described above.
[0033] The fuse structure and storage unit of the present invention can realize programming and reading because the fuse structure only needs one transistor and does not need polysilicon resistors. Since there is no polysilicon resistor, not only the impedance of the path during programming is reduced, but also the size of the programming transistor can be further reduced, while reducing the overall area of the storage unit.
[0034] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
[0036] Figure 1 It is a schematic diagram of the layout of a conventional contact hole fuse structure;
[0037] Figure 2 for Figure 1 A cross-sectional schematic diagram of a contact hole fuse structure shown;
[0038] Figure 3 A schematic diagram of a layout of a fuse structure according to an embodiment of the present invention;
[0039] Figure 4 for Figure 3 A cross-sectional schematic diagram of a fuse structure shown;
[0040] Figure 5 FIG. 4 is a schematic diagram of the structure of a storage unit according to an embodiment of the present invention. DETAILED DESCRIPTION
[0041] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.
[0042] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
[0043] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.
[0044] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.
[0045] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.
[0046] refer to Figure 3 , Figure 4 , Figure 3 is a schematic diagram of a fuse structure according to an embodiment of the present invention, Figure 4 for Figure 3 The cross-sectional diagram of the fuse structure is shown.
[0047] like Figure 3 , 4As shown, the fuse structure includes a programming transistor 210 and a first contact hole 220 . The programming transistor 210 includes a substrate 211 , a first well region 215 , a first electrode region 212 , a second electrode region 213 , and a control electrode 214 .
[0048] In this embodiment, the first well region 215 is configured on the substrate 211; the first electrode region 212 is configured on the first well region 215; the second electrode region 213 is configured on the first well region 215 and is arranged opposite to the first electrode region 212; the control electrode 214 is configured between the first electrode region 212 and the second electrode region 213, and is used to receive a control signal to control the electrical connection between the first electrode region 212 and the second electrode region 213; the first contact hole 220 is used to be configured as a fuse contact hole, that is, a fuse is provided in the contact hole, which is set on the first electrode region 212 of the programming transistor 210.
[0049] In this embodiment, the programming transistor 210 may be an NMOS transistor or a PMOS transistor. Of course, it may also be other transistors. In this embodiment, an NMOS transistor is taken as an example for description.
[0050] In this embodiment, the substrate 211 can be a P-type substrate (P-sub), the first well region 215 is configured as a P-type well region, the first electrode region 212 is configured as an N-type heavily doped (N+), the second electrode region 213 is configured as an N-type heavily doped (N+) and a P-type heavily doped (P+), and the control electrode 214, i.e., the gate, is configured as a polysilicon material (Poly).
[0051] In this embodiment, the first electrode region 212 is configured as an anode terminal, the second electrode region 213 is configured as a cathode terminal, one or more second contact holes 213W are set at the cathode terminal, and one or more third contact holes 214W are set at the control electrode 214. The first contact hole 220 is configured to receive a first voltage signal V1, that is, the anode terminal receives the first voltage signal V1 through the first contact hole 220, the second contact hole 213W is configured to receive a second voltage signal V2, that is, the cathode terminal receives the second voltage signal V2 through the second contact hole 213W, and the third contact hole 214W is configured to receive a control signal Vc, that is, the gate terminal receives the control signal Vc through the third contact hole 214W.
[0052] In this embodiment, the anode terminal and the cathode terminal can be configured as a first bias voltage, and the first bias voltage can be a high bias voltage, that is, the first voltage signal V1 and the second voltage signal V2 constitute a high bias voltage, and the control electrode 214 receives the control signal Vc to control the electrical connection between the first electrode area 212 and the second electrode area 213. At this time, the anode terminal and the cathode terminal will form a large current, which can burn the first contact hole 220, that is, burn the fuse contact hole, so that the programming operation can be achieved.
[0053] In this embodiment, the anode terminal and the cathode terminal can be configured as a second bias voltage, and the second bias voltage can be a low bias voltage, that is, the first voltage signal V1 and the second voltage signal V2 constitute a low bias voltage, and the control electrode 214 receives the control signal Vc to control the electrical connection between the first electrode area 212 and the second electrode area 213. At this time, the current between the anode terminal and the cathode terminal can be read, thereby achieving a reading operation.
[0054] The fuse structure of this embodiment only requires one NMOS transistor and does not require a polysilicon resistor, so that programming and reading can be achieved. Since there is no polysilicon resistor, the impedance of the path during programming (burning) is reduced; and since there is no polysilicon, the first electrode region 212 no longer has a partial area connected to the contact hole of the polysilicon resistor in the prior art, thereby further reducing the size of the NMOS programming tube.
[0055] In this embodiment, the first electrode region 212 can be configured as a drain region, and the second electrode region 213 can be configured as a source region (N+) and a body terminal (P+).
[0056] In one embodiment, for Figure 3 , Figure 4 The fuse structure shown can be manufactured as follows:
[0057] First, a P-well (Pwell) is fabricated on a P-type substrate (P-sub) 211;
[0058] Then, a control electrode 214, a first electrode region 212, and a second electrode region 213 are made in the P well. The control electrode 214 is configured as polysilicon material (Poly), the first electrode region 212 is configured as N-type heavy doping (N+), and the second electrode region 213 is configured as N-type heavy doping (N+) and P-type heavy doping (P+). Specifically, they can be formed by etching through a corresponding mask (MASK) and performing corresponding doping, which will not be repeated here.
[0059] Afterwards, a first contact hole 220, one or more second contact holes 213W, and one or more third contact holes 214W are made, wherein the first contact hole 220 is made in the first electrode region 212 as an anode terminal, and the second contact hole 213W is made in the second electrode region 213 as a cathode terminal, wherein the first contact hole 220 is configured to receive a first voltage signal V1, that is, the anode terminal receives the first voltage signal V1 through the first contact hole 220, the second contact hole 213W is configured to receive a second voltage signal V2, that is, the cathode terminal receives the second voltage signal V2 through the second contact hole 213W, and the third contact hole 214W is configured to receive a control signal Vc, that is, the gate terminal receives the control signal Vc through the third contact hole 214W, thereby forming Figure 3 , Figure 4 The fuse structure is shown.
[0060] In other embodiments, the programming transistor of the fuse structure may also be a PMOS transistor. Figure 3 , Figure 4 Basically the same, except that the substrate, doping, etc. of the programming transistor are adjusted accordingly. For the sake of brevity, they will not be elaborated here.
[0061] refer to Figure 5 , Figure 5 FIG. 4 is a schematic diagram of the structure of a storage unit according to an embodiment of the present invention.
[0062] like Figure 5 As shown, the storage unit 500 includes a fuse structure 200, which may be Figure 3 , Figure 4 The fuse structure is shown.
[0063] The fuse structure 200 may include a programming transistor 210 and a first contact hole 220 . The programming transistor 210 includes a substrate 211 , a first well region 215 , a first electrode region 212 , a second electrode region 213 , and a control electrode 214 .
[0064] In this embodiment, the first well region 215 is configured on the substrate 211, and the first electrode region 212 is configured on the first well region 215; the second electrode region 213 is configured on the first well region 215 and is arranged opposite to the first electrode region 212; the control electrode 214 is configured between the first electrode region 212 and the second electrode region 213, and is used to receive a control signal to control the electrical connection between the first electrode region 212 and the second electrode region 213; the first contact hole 220 is configured as a fuse contact hole and is set on the first electrode region 212 of the programming transistor 210.
[0065] In this embodiment, the programming transistor 210 may be Figure 3 , Figure 4 The NMOS transistor shown in the figure can also be a PMOS transistor, of course, it can also be other transistors. In this embodiment, the NMOS transistor will be taken as an example for description.
[0066] In this embodiment, the substrate 211 can be a P-type substrate (P-sub), the first well region 215 is configured as a P-type well region, the first electrode region 212 is configured as an N-type heavily doped (N+), the second electrode region 213 is configured as an N-type heavily doped (N+) and a P-type heavily doped (P+), and the control electrode 214, i.e., the gate, is configured as a polysilicon material (Poly).
[0067] In this embodiment, the first electrode region 212 is configured as an anode terminal, the second electrode region 213 is configured as a cathode terminal, one or more second contact holes 213W are set at the cathode terminal, and one or more third contact holes 214W are set at the control electrode 214. The first contact hole 220 is configured to receive a first voltage signal V1, that is, the anode terminal receives the first voltage signal V1 through the first contact hole 220, the second contact hole 213W is configured to receive a second voltage signal V2, that is, the cathode terminal receives the second voltage signal V2 through the second contact hole 213W, and the third contact hole 214W is configured to receive a control signal Vc, that is, the gate terminal receives the control signal Vc through the third contact hole 214W.
[0068] In this embodiment, in the storage unit 500, when the first voltage signal V1 and the second voltage signal V2 form a high bias voltage, a programming operation is performed, and when the first voltage signal V1 and the second voltage signal V2 form a low bias voltage, a reading operation is performed. Please refer to the above for details and will not be repeated here.
[0069] It should also be pointed out that, in this embodiment, the fuse structure 200 may also be the fuse structure of any of the above-mentioned embodiments.
[0070] The memory cell of this embodiment can realize programming and reading because the fuse structure only needs one transistor and does not need a polysilicon resistor. The impedance of the path during programming (burning) is reduced because there is no polysilicon resistor. Moreover, because there is no polysilicon, the first electrode region does not have a partial area connected to the contact hole of the polysilicon resistor in the prior art, thereby further reducing the size of the programming tube. In addition, the memory cell of this embodiment must reduce the overall area of the memory cell because there is no polysilicon resistor in the fuse structure.
[0071] The fuse structure and storage unit of the above-mentioned embodiment of the present invention can realize programming and reading because the fuse structure only needs one transistor and does not need polysilicon resistor. The absence of polysilicon resistor not only reduces the impedance of the path during programming, but also can further reduce the size of the programming transistor, while reducing the overall area of the storage unit.
[0072] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims. It should be understood by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention.
Claims
1. A fuse structure, characterized in that: include: a programming transistor, the programming transistor comprising: a substrate; a first well region, disposed on the substrate; a first electrode region, disposed on the first well region; a second electrode region, disposed on the first well region and arranged opposite to the first electrode region; a control electrode, disposed between the first electrode region and the second electrode region, for receiving a control signal to control the electrical connection between the first electrode region and the second electrode region; and a first contact hole configured as a fuse contact hole, disposed on the first electrode region of the programming transistor, wherein a fuse is disposed in the fuse contact hole; in, The first electrode region is configured as an anode terminal, and the second electrode region is configured as a cathode terminal; The anode terminal and the cathode terminal are configured as a first bias voltage, and the control electrode controls the first electrode region to be electrically connected to the second electrode region to burn out the fuse in the first contact hole.
2. The fuse structure according to claim 1, characterized in that: The cathode terminal is provided with one or more second contact holes, and the control electrode is provided with one or more third contact holes; The first contact hole is configured to receive a first voltage signal, the second contact hole is configured to receive a second voltage signal, and the third contact hole is configured to receive the control signal.
3. The fuse structure according to claim 2, characterized in that: The anode terminal and the cathode terminal are configured as a second bias voltage, and the control electrode controls the first electrode region and the second electrode region to be electrically connected so as to read the current between the anode terminal and the cathode terminal.
4. The fuse structure according to claim 1, characterized in that: The programming transistor is an NMOS transistor.
5. The fuse structure according to claim 4, characterized in that: The substrate is configured as a P-type substrate; The first well region is configured as a P-type well region; The first electrode region is configured to be N-type heavily doped; The second electrode region is configured to be N-type heavily doped or P-type heavily doped; and The control electrode is made of polysilicon.
6. The fuse structure according to claim 5, characterized in that: The first electrode region is configured as a drain region, and the second electrode region is configured as a source region and a body terminal.
7. The fuse structure according to claim 1, characterized in that: The programming transistor is a PMOS transistor.
8. A storage unit, characterized in that: The invention comprises the fuse structure as claimed in any one of claims 1 to 7.
Citation Information
Patent Citations
Fuse structure and memory cell
CN212907739U