Chip, electronic equipment and chip manufacturing method

Abstract

The invention discloses a chip, electronic equipment and a chip manufacturing method, and aims to solve the problem that the area of a chip is large. In the chip, an upper pull tube is arranged in a device layer, and the device layer is manufactured by adopting a previous process; the pull-down tube and the gate tube are arranged in the metal interconnection layer, and the metal interconnection layer is manufactured by adopting a subsequent process; compared with the mode that the pull-up tube, the gate tube and the pull-down tube are all manufactured through the previous process, the number of devices manufactured through the previous process can be reduced, the area of a device layer is reduced, and then the area of a chip is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of storage devices, and specifically to a chip, an electronic device, and a chip manufacturing method. Background Art

[0002] Cache is a storage device between the processor (such as Central Processing Unit, referred to as CPU) and the memory in the chip, generally including static random access memory (SRAM); the memory and the logic circuit in the chip are both manufactured using front-end processes, resulting in a larger chip area. Summary of the invention

[0003] The embodiments of the present application provide a chip, an electronic device, and a chip manufacturing method, which can reduce the area of ​​the chip.

[0004] In a first aspect, an embodiment of the present application provides a chip, comprising: a substrate, a device layer and a metal interconnection layer; the device layer is arranged on the substrate, the device layer includes a logic circuit, and the device layer is configured to be manufactured in a front-end process; the metal interconnection layer is stacked on a side of the device layer away from the substrate, and the metal interconnection layer is configured to be manufactured in a back-end process; the chip also includes a static random access memory, the static random access memory includes: a gate tube, a pull-up tube and a pull-down tube, the pull-up tube is arranged in the device layer, and the gate tube and the pull-down tube are arranged in the metal interconnection layer.

[0005] Through the above arrangement, the pull-up tube is arranged in the device layer, and the device layer is manufactured by the front-end process; the pull-down tube and the gate tube are arranged in the metal interconnection layer, and the metal interconnection layer is manufactured by the back-end process; compared with the case where the pull-up tube, the gate tube and the pull-down tube are all manufactured by the front-end process, the number of devices manufactured by the front-end process can be reduced, the area of ​​the device layer is reduced, and thus the area of ​​the chip is reduced.

[0006] In some embodiments that may include the above embodiments, the pull-up tube includes a P-type transistor, and the gate tube and the pull-down tube are N-type transistors. The oxide semiconductor transistors manufactured in the back-end process are more easily made into N-type transistors, and the gate tube and the pull-down tube manufactured in the back-end process are N-type transistors, which can facilitate the manufacture of the gate tube and the pull-down tube.

[0007] In some embodiments that may include the above embodiments, the material of the substrate includes silicon, and the pull-up tube includes a silicon field effect transistor. This arrangement further facilitates the production of the pull-up tube; in addition, the uniformity of the single crystal silicon is high, which can ensure that the pull-up tube has high performance.

[0008] In some embodiments that may include the above embodiments, the metal interconnect layer includes a first metal interconnect layer and a second metal interconnect layer that are stacked, the first metal interconnect layer is located between the second metal interconnect layer and the device layer; the gate tube and the pull-down tube are arranged in the first metal interconnect layer and the second metal interconnect layer. In this arrangement, compared with the case where the gate tube and the pull-down tube are both arranged in the first metal interconnect layer or the second metal interconnect layer, the area of ​​the static random access memory and the chip can be reduced.

[0009] In some embodiments that may include the above embodiments, the gating tube includes a first gating tube and a second gating tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, and the storage unit is a 6T storage unit, and the storage unit includes: a first gating tube, a second gating tube, a first pull-up tube, a second pull-up tube, a first pull-down tube, and a second pull-down tube. Through the above configuration, a total of 6 transistors, including the first gating tube, the second gating tube, the first pull-up tube, the second pull-up tube, the first pull-down tube, and the second pull-down tube, constitute a storage unit for data storage. The first pull-up tube and the first pull-down tube constitute a first inverter, the second pull-up tube and the second pull-down tube constitute a second inverter, the output end of the first inverter is connected to the input of the second inverter to form a first storage node, the output end of the second inverter is electrically connected to the input of the first inverter to form a second storage node, and the first inverter and the second inverter form a latch circuit.

[0010] In some embodiments that may include the above embodiments, one electrode of the first pull-up tube and the second pull-up tube are both connected to the first power line, the other electrode of the first pull-up tube is connected to the gate of the second pull-up tube, and the other electrode of the second pull-up tube is connected to the gate of the first pull-up tube; the gate of the first pull-up tube is also connected to one electrode of the second pull-down tube, the other electrode of the second pull-down tube is connected to the second power line, the gate of the second pull-down tube is also connected to the gate of the second pull-up tube, one electrode of the first pull-down tube is connected to the gate of the second pull-up tube, the other electrode of the first pull-down tube is connected to the second power line, and the gate of the first pull-down tube is connected to the gate of the first pull-up tube; the gate of the first pull-down tube is also connected to one electrode of the second selection tube, the other electrode of the second selection tube is connected to the anti-bit line, and the gate of the second selection tube is connected to the word line; one electrode of the first selection tube is connected to the gate of the second pull-down tube, the other electrode of the first selection tube is connected to the bit line, and the gate of the first selection tube is also connected to the word line.

[0011] In some embodiments that may include the above embodiments, the first gate transistor and the second gate transistor are located in the second metal interconnection layer, and the first pull-down transistor and the second pull-down transistor are located in the first metal interconnection layer. This arrangement can ensure that the number of transistors in the first metal interconnection layer and the second metal interconnection layer is not too large, thereby avoiding the structures of the first metal interconnection layer and the second metal interconnection layer from being too complicated.

[0012] In some embodiments that may include the above embodiments, in the same storage unit, the gate of the first pull-up tube and the gate of the second pull-up tube are arranged in parallel and spaced apart, the gate of the first pull-up tube extends toward the second pull-up tube, and the gate of the first pull-up tube is connected to the electrode of the second pull-up tube through a first contact structure; the gate of the second pull-up tube extends toward the first pull-up tube, and the gate of the second pull-up tube is connected to the electrode of the first pull-up tube through a second contact structure. Through the above arrangement, the first pull-up tube and the second pull-up tube form a structure that is substantially rotationally symmetrical about the center, and the center of symmetry can be the center of the line connecting the midpoint of the gate of the first pull-up tube and the midpoint of the gate of the second pull-up tube.

[0013] In some embodiments that may include the above embodiments, the gate of the first pull-down tube and the gate of the second pull-down tube are arranged in parallel and spaced apart, the gate of the first pull-down tube is connected to the electrode of the second pull-down tube at one end close to the second pull-down tube through the third contact structure, and the gate of the second pull-down tube is connected to the electrode of the second pull-down tube at one end close to the first pull-down tube through the fourth contact structure. In this way, the first pull-down tube and the second pull-down tube form a substantially central rotationally symmetrical structure, and the center of symmetry can be the center of the line connecting the midpoint of the gate of the first pull-down tube and the midpoint of the gate of the second pull-down tube.

[0014] In some embodiments that may include the above embodiments, the electrode of the first selection tube is connected to the fourth contact structure through the sixth contact structure, the fourth contact structure is also connected to the second contact structure, and the first storage node includes: the sixth contact structure, the fourth contact structure and the second contact structure; the electrode of the second selection tube is connected to the third contact structure through the seventh contact structure, the third contact structure is also connected to the first contact structure, and the second storage node includes: the seventh contact structure, the third contact structure and the first contact structure.

[0015] In some embodiments that may include the above embodiments, in each storage unit, the gate of the first gate tube and the gate of the second gate tube extend in the same direction in the second metal interconnect layer, so that the gate of the first gate tube and the gate of the second gate tube are arranged in parallel and spaced apart, so that the first gate tube and the second gate tube form a roughly centrally symmetrical structure, and the center of symmetry can be the center of a line connecting the midpoint of the gate of the first gate tube and the midpoint of the gate of the second gate tube.

[0016] In some embodiments that may include the above embodiments, the gates of the first gate tubes in the plurality of storage cells are an integrated structure, the gates of the second gate tubes in the plurality of storage cells are an integrated structure, the gate of at least one first gate tube in the plurality of storage cells is connected to the gate of at least one second gate tube, and is connected to a word line. In this way, the gates of the first gate tubes and the second gate tubes of the plurality of storage cells are connected to the word line, which can simplify the connection structure.

[0017] In some embodiments that may include the above embodiments, in the same memory cell, the gates of the first gate tube and the second gate tube are arranged in parallel and spaced apart, a first connection portion is further arranged in the second metal interconnection layer, and an end of the gate of the first gate tube close to the second gate tube is connected to an end of the gate of the second gate tube close to the first gate tube through the first connection portion, and the first connection portion is connected to the word line. In this arrangement, the gate of the first gate tube and the gate of the second gate tube in each memory cell are connected to the word line through the corresponding first connection portion, which can reduce the parasitic resistance of the word line and improve the signal transmission response speed of the word line compared to the case where the gates of the first gate tube and the second gate tube in multiple memory cells are connected to the word line through the same fifth contact structure.

[0018] In some embodiments that may include the above embodiments, in the same memory cell, the gate of the first gate tube and the gate of the second gate tube are an integrated structure, a second connection portion is further provided in the second metal interconnection layer, the second connection portion is located between the first gate tube and the second gate tube, the second connection portion is connected to the gate of the first gate tube, and the second connection portion is connected to the word line. In this way, the gates of the first gate tube and the second gate tube are an integrated structure, which can simplify the structure of the chip and facilitate the manufacture of the chip; in addition, the gates of the first gate tube and the second gate tube in each memory cell are connected to the word line through a second connection portion, which can reduce parasitic resistance.

[0019] In some embodiments that may include the above embodiments, the word line is arranged on a side of the second metal interconnect layer away from the substrate, so as to facilitate the connection between the word line and the first gate tube and the second gate tube.

[0020] In some embodiments that may include the above embodiments, the first gate tube and the first pull-down tube are located in the first metal interconnection layer, and the second gate tube and the second pull-down tube are located in the second metal interconnection layer. This arrangement can also avoid the structures of the first metal interconnection layer and the second metal interconnection layer being too complicated.

[0021] In some embodiments that may include the above-mentioned embodiments, electrodes of the first selection tube and the first pull-down tube that are close to each other are an integral structure, and electrodes of the second selection tube and the second pull-down tube that are close to each other are an integral structure. With such a configuration, there is no need to additionally configure other structures for connecting an electrode of the first selection tube and an electrode of the first pull-down tube, thereby simplifying the structure of the chip; in addition, an electrode of the first selection tube and an electrode of the first pull-down tube are an integral structure, and an electrode of the first selection tube and an electrode of the first pull-down tube can be formed simultaneously using the same process, thereby reducing the difficulty of manufacturing the chip. Similarly, there is no need to additionally configure other structures for connecting an electrode of the second selection tube and an electrode of the second pull-down tube, thereby simplifying the structure of the chip; in addition, an electrode of the second selection tube and an electrode of the second pull-down tube are an integral structure, and an electrode of the second selection tube and an electrode of the second pull-down tube can be formed simultaneously using the same process, thereby reducing the difficulty of manufacturing the chip.

[0022] In some embodiments that may include the above embodiments, the metal interconnect layer includes a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately stacked, and the dielectric constant of the first dielectric layer is less than the dielectric constant of the second dielectric layer. In other words, the first dielectric layer is a low dielectric constant material, and such a configuration can reduce the parasitic capacitance of the chip, thereby improving the performance of the chip. In addition, since the dielectric constant of the first dielectric layer is relatively small, its etching resistance is relatively poor (the etching selectivity is relatively large), and the first dielectric layer and the second dielectric layer are alternately stacked, and the etching selectivity of the first dielectric layer and the second dielectric layer is different, which can facilitate the etching of the metal interconnect layer to reduce the difficulty of chip manufacturing.

[0023] In a second aspect, an embodiment of the present application further provides an electronic device, comprising: a mainboard and the chip as described above, wherein the chip is arranged on the mainboard.

[0024] The electronic device provided in the embodiments of the present application includes the chip in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0025] In a third aspect, the present application also provides a chip manufacturing method, including:

[0026] A device layer and a pull-up tube in the device layer are manufactured on a substrate by a front-end process, and the device layer includes a logic circuit; a metal interconnection layer and a gate tube and a pull-down tube in the metal interconnection layer are formed in a stacked manner on the device layer by a back-end process; a static random access memory includes a gate tube, a pull-up tube and a pull-down tube.

[0027] In some embodiments that may include the above embodiments, forming a metal interconnect layer and a gate tube and a pull-down tube located in the metal interconnect layer in a stacked manner on the device layer using a back-end process includes: forming a first metal interconnect layer and a second metal interconnect layer in a stacked manner on the device layer using a back-end process, the first metal interconnect layer being located between the second metal interconnect layer and the device layer; the gate tube and the pull-down tube being arranged in the first metal interconnect layer and the second metal interconnect layer. In this arrangement, compared with the arrangement of the gate tube and the pull-down tube both being arranged in the first metal interconnect layer or the second metal interconnect layer, the area of ​​the static random access memory and the chip can be reduced.

[0028] In some embodiments that may include the above embodiments, the gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: a first gate tube, a second gate tube, a first pull-up tube, a second pull-up tube, a first pull-down tube, and a second pull-down tube; forming the first metal interconnection layer and the second metal interconnection layer in a stacked manner on the device layer using a back-end process includes: forming the first metal interconnection layer and the first pull-down tube and the second pull-down tube in the first metal interconnection layer in a stacked manner on the device layer using a back-end process; forming the second metal interconnection layer and the first gate tube and the second gate tube in the second metal interconnection layer in a stacked manner on the first metal interconnection layer using a back-end process. With such a configuration, it can be ensured that the number of transistors in the first metal interconnection layer and the second metal interconnection layer is not too large, thereby avoiding the structure of the first metal interconnection layer and the second metal interconnection layer from being too complicated.

[0029] In some embodiments that may include the above embodiments, the gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: a first gate tube, a second gate tube, a first pull-up tube, a second pull-up tube, a first pull-down tube, and a second pull-down tube; forming the first metal interconnection layer and the second metal interconnection layer in a stacked manner on the device layer using a back-end process includes: forming the first metal interconnection layer and the first pull-down tube and the first gate tube in the first metal interconnection layer in a stacked manner on the device layer using a back-end process; forming the second metal interconnection layer and the second pull-down tube and the second gate tube in the second metal interconnection layer in a stacked manner on the first metal interconnection layer using a back-end process. With such a configuration, it can be ensured that the number of transistors in the first metal interconnection layer and the second metal interconnection layer is not too large, thereby avoiding the structure of the first metal interconnection layer and the second metal interconnection layer from being too complicated.

[0030] In the chip manufactured by the chip manufacturing method provided in the embodiment of the present application, the pull-up tube is arranged in the device layer, and the device layer is manufactured by the front-end process; the pull-down tube and the gate tube are arranged in the metal interconnection layer, and the metal interconnection layer is manufactured by the back-end process; compared with the pull-up tube, the gate tube and the pull-down tube are all manufactured by the front-end process, the number of devices manufactured by the front-end process can be reduced, the area of ​​the device layer is reduced, and then the area of ​​the chip is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A cross-sectional view of a chip provided in an embodiment of the present application;

[0032] Figure 2 A circuit diagram of a chip provided in an embodiment of the present application in which a gate tube and a pull-down tube are arranged on the same layer;

[0033] Figure 3 It is a schematic diagram of the connection between a chip and a static random access memory in the related art;

[0034] Figure 4 A top view of a device layer when a gate tube and a pull-down tube are arranged on the same layer in a chip provided in an embodiment of the present application;

[0035] Figure 5 An exploded diagram of the same-layer arrangement of the gate tube and the same-layer arrangement of the pull-down tube in the chip provided in the embodiment of the present application;

[0036] Figure 6 A top view of the first metal interconnect layer when the gate tube and the pull-down tube are arranged on the same layer in the chip provided by the embodiment of the present application;

[0037] Figure 7 for Figure 6 The enlarged image in the middle dashed box;

[0038] Figure 8 A top view of the second metal interconnect layer when the gate tube and the pull-down tube are arranged on the same layer in the chip provided by the embodiment of the present application;

[0039] Fig. 9 for Figure 8 The enlarged image in the middle dashed box;

[0040] Fig.10 for Figure 7 and Fig. 9 Sectional view along AA direction;

[0041] Fig.11 for Figure 8 Cross-sectional view along the BB direction;

[0042] Fig.12 A top view of the second metal interconnect layer when the memory cell in the chip provided in the embodiment of the present application includes 8 transistors;

[0043] Fig.13 A top view of the third metal interconnect layer when the memory cell in the chip provided in the embodiment of the present application includes 8 transistors;

[0044] Fig.14 A circuit diagram of a chip provided in an embodiment of the present application in which a storage unit includes 8 transistors;

[0045] Fig.15 A top view of a second metal interconnect layer when a gate of a first gate tube and a gate of a second gate tube in a chip provided by an embodiment of the present application are connected through a first connecting portion;

[0046] Fig.16 for Fig.15 The enlarged image in the middle dashed box;

[0047] Fig.17 for Fig.16 Sectional view along CC direction;

[0048] Fig.18 for Fig.16 Cross-sectional view along the DD direction;

[0049] Fig.19 A top view of a first metal interconnect layer when the gate of a first gate tube and the gate of a second gate tube in a chip provided by an embodiment of the present application are an integrated structure;

[0050] Fig. 20 A top view of a second metal interconnect layer when the gate of a first gate tube and the gate of a second gate tube in a chip provided by an embodiment of the present application are an integrated structure;

[0051] Fig.21 for Fig. 20 Sectional view along EE direction;

[0052] Fig. 22 A top view of the first metal interconnect layer when the gate tube and the pull-down tube are arranged on the same layer in the chip provided by the embodiment of the present application;

[0053] Fig.23 A top view of the second metal interconnect layer when the gate tube and the pull-down tube are arranged on the same layer in the chip provided by the embodiment of the present application;

[0054] Fig.24 for Fig. 22 and Fig.23 Sectional view along the FF axis;

[0055] Fig.25 A circuit diagram of a chip provided by an embodiment of the present application in which a gate tube and a pull-down tube are arranged on the same layer;

[0056] Fig.26A block diagram of a chip provided in accordance with an embodiment of the present application.

[0057] Description of reference numerals:

[0058] 1: substrate; 10: core area; 20: peripheral area; 30: device layer; 40: metal interconnection layer; 41: first metal interconnection layer; 42: second metal interconnection layer; 43: gate; 110: chip; 120: static random access memory; 130: static random access memory; 140: logic circuit; 302: first conductive structure; 303: first conductive part; 304: second conductive part; 305: third dielectric layer; 306: fourth dielectric layer; 307: first contact structure; 308: second contact structure; 401: first dielectric layer; 402: second dielectric layer; 404: first connecting part; 407: second conductive structure; 408: third contact structure; 409: fourth contact structure; 410: third conductive structure; 411: sixth contact structure; 412: seventh contact structure. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0060] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0061] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to changes in the orientation of the components placed in the drawings.

[0062] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a coupling connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. Among them, coupling can be understood as direct coupling and / or indirect coupling, and "coupled connection" can be understood as direct coupling connection and / or indirect coupling connection.

[0063] The embodiment of the present application provides an electronic device, which may include a computer, a mobile phone, a server, etc. The electronic device includes a mainboard and a chip arranged on the mainboard, the chip is electrically connected to the circuit on the mainboard, the chip can process data, calculate, etc., wherein the chip may be a central processing unit (CPU for short).

[0064] Please refer to Figure 1 In the embodiment of the present application, the chip includes a substrate 1 and a device layer 30 disposed on the substrate 1. The substrate 1 can serve as the basis of the chip and is used to carry a film structure such as the device layer 30. Exemplarily, the material of the substrate 1 may include silicon, germanium, etc., and the embodiment of the present application does not limit the material of the substrate 1. The device layer 30 includes a logic circuit, and the logic circuit can be used for data processing, calculation, etc.

[0065] In the above implementation, the chip further includes a metal interconnect layer 40, which is stacked on the side of the device layer 30 away from the substrate 1. The metal interconnect layer 40 is configured to be manufactured in a back-end process, and the device layer 30 is configured to be manufactured in a front-end process. It can be understood that during the manufacturing process, the device layer 30 and the logic circuit in the device layer 30 can be first manufactured by the front-end process, and then the metal interconnect layer 40 is manufactured on the device layer 30 by the back-end process. Exemplarily, the metal interconnect layer 40 may include a plurality of first dielectric layers 401 and a plurality of second dielectric layers 402 that are alternately stacked, and the materials of the first dielectric layer 401 and the second dielectric layer 402 may include silicon oxide, silicon nitride, etc.

[0066] In some embodiments, the dielectric constant of the first dielectric layer 401 is less than the dielectric constant of the second dielectric layer 402, that is, the first dielectric layer 401 is a low dielectric constant material, and such a configuration can reduce the parasitic capacitance of the chip, thereby improving the performance of the chip. In addition, since the dielectric constant of the first dielectric layer 401 is relatively small, its etching resistance is relatively poor (the etching selectivity is relatively large), and the first dielectric layer 401 and the second dielectric layer 402 are alternately stacked, and the etching selectivity ratios of the first dielectric layer 401 and the second dielectric layer 402 are different, which can facilitate the etching of the metal interconnect layer 40, thereby reducing the difficulty of chip manufacturing.

[0067] In some embodiments, the chip may further include at least one metal layer, which may be disposed on a first dielectric layer 401 or a second dielectric layer 402, and / or the metal may be disposed in the device layer 30, and / or the metal layer may be disposed on a side of the metal interconnect layer 40 away from the substrate 1. By patterning the metal layer, metal traces may be formed to facilitate circuit connection.

[0068] It is understandable that in the embodiment of the present application, logic circuits may also be provided in the metal interconnect layer 40 to avoid the logic circuits being concentrated in the device layer 30. On the other hand, the density of the logic circuits may be increased, thereby improving the data calculation and processing capabilities of the chip.

[0069] like Fig.26 As shown, the chip 110 in the embodiment of the present application also includes a static random access memory 130 (Static Random Access Memory for short SRAM), which can be used as a cache (Cache). The static random access memory 130 is a memory between the logic circuit 140 and the memory, and is used to temporarily store the data of the logic circuit 140. The chip 110 also includes an interface circuit 150 connected to the static random access memory 130 and the logic circuit 140, and the interface circuit 150 is used to connect to an external device; illustratively, in the implementation mode where the chip 110 is a central processing unit, the interface circuit 150 can be electrically connected to the circuit on the motherboard to realize the connection between the chip 110 and the motherboard.

[0070] like Figure 2 As shown, in some embodiments, the static random access memory includes a storage unit, which is used for data storage, wherein the storage unit may include a gate tube PG, a pull-up tube PU and a pull-down tube PD, the gate tube PG may include a first gate tube PG1 and a second gate tube PG2, the pull-up tube PU may include a first pull-up tube PU1 and a second pull-up tube PU2, and the pull-down tube PD may include a first pull-down tube PD1 and a second pull-down tube PD2.

[0071] Exemplarily, one electrode (source or drain) of the first pull-up tube PU1 and the second pull-up tube PU2 are both connected to the first power line VDD, the other electrode (drain or source) of the first pull-up tube PU1 is connected to the gate of the second pull-up tube PU2, and the other electrode (drain or source) of the second pull-up tube PU2 is connected to the gate of the first pull-up tube PU1; the gate of the first pull-up tube PU1 is also connected to one electrode of the second pull-down tube PD2, the other electrode of the second pull-down tube PD2 is connected to the second power line VSS, the gate of the second pull-down tube PD2 is also connected to the gate of the second pull-up tube PU2, and one electrode of the first pull-down tube PD1 is connected to the gate of the second pull-up tube PU2. An electrode of the first pull-up tube PU2 is connected to the gate of the second pull-up tube PU2, another electrode of the first pull-down tube PD1 is connected to the second power line VSS, and the gate of the first pull-down tube PD1 is connected to the gate of the first pull-up tube PU1; the gate of the first pull-down tube PD1 is also connected to an electrode of the second selection tube PG2, another electrode of the second selection tube PG2 is connected to the anti-bit line BLB, and the gate of the second selection tube PG2 is connected to the word line WL; one electrode of the first selection tube PG1 is connected to the gate of the second pull-down tube PD2, another electrode of the first selection tube PG1 is connected to the bit line BL, and the gate of the first selection tube PG1 is also connected to the word line WL. The above-mentioned first selection tube PG1, second selection tube PG2, first pull-up tube PU1, second pull-up tube PU2, first pull-down tube PD1 and second pull-down tube PD2, a total of 6 transistors, constitute a 6T storage unit (6T SRAM) for data storage. The first pull-up tube PU1 and the first pull-down tube PD1 constitute a first inverter, the second pull-up tube PU2 and the second pull-down tube PD2 constitute a second inverter, the output end of the first inverter is connected to the input end of the second inverter to form a first storage node Q, the output end of the second inverter is electrically connected to the input end of the first inverter to form a second storage node QB, and the first inverter and the second inverter form a latch circuit. In the above implementation, the first power line VDD can be configured to have a high level, and accordingly, the second power line VSS is configured to be grounded. It can be understood that the voltage of the first power line VDD can be reasonably set according to different situations so that the static random access memory can work normally.

[0072] When data is written, exemplarily, the data stored in the initial state storage unit is "0", at this time, the second storage node QB can be a high level (storing "1"), the first storage node Q is a low level (storing "0"), the second pull-down tube PD2 and the first pull-up tube PU1 are cut off, the first pull-down tube PD1 and the second pull-up tube PU2 are turned on, and by setting the word line WL and the bit line BL to a high level and the inverted bit line BLB to a low level, the first gate tube PG1 and the second gate tube PG2 are both turned on, the bit line BL charges the first storage node Q through the first gate tube PG1, and the inverted bit line BLB discharges the second storage node QB through the second gate tube PG2, so that the second storage node QB is a low level and the first storage node Q is a high level, thereby completing the writing of "1".

[0073] When reading data, the bit line BL and the inverted bit line BLB are both in a high level state. When the word line WL corresponding to the storage unit is at a high level, the first gate tube PG1 and the second gate tube PG2 are both turned on, which is equivalent to connecting the first storage node Q to the bit line BL, and connecting the second storage node QB to the inverted bit line BLB. When reading "1", assuming that the first storage node Q stores "1", the second pull-down tube PD2 and the first pull-up tube PU1 are turned on, while the first pull-down tube PD1 and the second pull-up tube PU2 are turned off, the bit line BL still maintains the original high level state, and the inverted bit line BLB is discharged through the path formed by the second gate tube PG2 and the second pull-down tube PD2, thereby forming a voltage difference between the bit line BL and the inverted bit line BLB, and completing the reading of data "1".

[0074] It can be understood that the number of transistors in the memory cell in the embodiment of the present application is not limited to 6. For example, the number of transistors in the memory cell may also be 8, 10, etc. The embodiment of the present application does not limit the number of transistors constituting the memory cell.

[0075] It can be understood that in the above implementation, the word line WL, the bit line BL, the anti-bit line BLB, the first power line VDD and the second power line VSS can be set in at least one metal layer, that is, the word line WL, the bit line BL, the anti-bit line BLB, the first power line VDD and the second power line VSS can be obtained by patterning at least one metal layer. The embodiment of the present application does not limit the positions of the word line WL, the bit line BL, the anti-bit line BLB, the first power line VDD and the second power line VSS.

[0076] Continue to refer to Figure 1In some embodiments, the device layer 30 may further include a first metal layer M1, and the first metal layer M1 may be disposed close to the metal interconnect layer 40. The pull-up tube PU is disposed in the device layer 30. For example, the first power line VDD may be disposed in the device layer 30. Accordingly, the first power line VDD may be located in the first metal layer M1. That is, the first power line VDD may be obtained by graphically processing the first metal layer M1, so that the pull-up tube PU is connected to the first power line VDD.

[0077] In some embodiments, the pull-up tube PU includes a P-type transistor, the gate tube PG and the pull-down tube PD are N-type transistors, the oxide semiconductor transistors manufactured in the back-end process are easier to be made into N-type transistors, and the gate tube PG and the pull-down tube PD manufactured in the back-end process are N-type transistors, which can facilitate the manufacture of the gate tube PG and the pull-down tube PD.

[0078] In the implementation mode where the material of the substrate 1 includes silicon, that is, the substrate 1 is a silicon substrate, and accordingly, the pull-up tube PU can be a silicon field effect transistor (Si MOSFET), that is, the active region material of the pull-up tube PU can include single crystal silicon. This arrangement further facilitates the production of the pull-up tube PU; in addition, the uniformity of single crystal silicon is high, which can ensure that the pull-up tube PU has high performance.

[0079] The gate transistor PG and the pull-down transistor PD are arranged in the metal interconnection layer 40. Accordingly, a second power line VSS may be arranged in the metal interconnection layer 40 to facilitate the connection of the pull-down transistor PD to the second power line VSS. In some implementations, the bit line BL, the anti-bit line BLB and the word line WL may be arranged on the side of the metal interconnection layer 40 away from the substrate 1.

[0080] like Figure 1 As shown, in the chip provided by the embodiment of the present application, the device layer 30 is arranged on the substrate 1, the device layer 30 includes a logic circuit, and the device layer 30 is manufactured by the front-end process; the metal interconnection layer 40 is stacked and arranged on the side of the device layer 30 away from the substrate 1, and the metal interconnection layer 40 is manufactured by the back-end process; the static random access memory includes a gate tube PG, a pull-up tube PU and a pull-down tube PD, the pull-up tube PU is arranged in the device layer 30, and the gate tube PG and the pull-down tube PD are arranged in the metal interconnection layer 40. Such a configuration can reduce the number of devices manufactured by the front-end process, reduce the area of ​​the device layer, and thus reduce the area of ​​the chip, compared with the case where the pull-up tube PU, the gate tube PG and the pull-down tube PD are all manufactured by the front-end process.

[0081] like Figure 3In the related art shown in FIG. 1 , the static random access memory 120 is covered on the chip 110, and the static random access memory 120 is connected to the chip 110 through the through silicon via technology. The through silicon via technology requires bonding, resulting in a low yield rate; while the chip (such as Figure 1 As shown in the figure, the static random access memory is set inside the chip, and the static random access memory is connected to the circuit inside the chip without bonding, which improves the chip yield. In addition, the through-hole aperture in the through-silicon via technology is large, which will occupy a large chip area; while in the processor in the embodiment of the present application, the static random access memory is set inside the chip, which can avoid occupying the surface space of the chip.

[0082] like Figure 1 As shown, in some embodiments, the metal interconnection layer 40 includes a first metal interconnection layer 41 and a second metal interconnection layer 42 which are stacked, the first metal interconnection layer 41 is located between the second metal interconnection layer 42 and the device layer 30, and the gate tube PG and the pull-down tube PD are arranged in the first metal interconnection layer 41 and the second metal interconnection layer 42. In this way, compared with the gate tube PG and the pull-down tube PD being arranged in the first metal interconnection layer 41 or the second metal interconnection layer 42, the area of ​​the static random access memory and the chip can be reduced. In addition, the gate tube PG and the pull-down tube PD are arranged in the first metal interconnection layer 41 and the second metal interconnection layer 42, which can reduce the impact on the original back-end interconnection layer structure, and can also reduce the impact on the manufacturing difficulty and chip performance due to the addition of additional devices.

[0083] In the embodiment of the present application, the gate tube PG and the pull-down tube PD are arranged in the first metal interconnection layer 41 and the second metal interconnection layer 42. Accordingly, the position relationship between the gate tube PG and the pull-down tube PD can be various, which will be introduced in multiple scenarios below:

[0084] Scene 1

[0085] Continue to refer to Figure 1 In this scenario, the gate tube PG can be set in the second metal interconnection layer 42, and correspondingly, the pull-down tube PD can be set in the first metal interconnection layer 41 to ensure that the number of transistors in the first metal interconnection layer 41 and the second metal interconnection layer 42 is not too large, thereby avoiding the structure of the first metal interconnection layer 41 and the second metal interconnection layer 42 being too complicated.

[0086] like Figure 1 and Figure 2As shown, in the implementation method in which the storage unit of the static random memory includes 6 transistors, correspondingly, the gate tube PG includes a first gate tube PG1 and a second gate tube PG2, the pull-up tube PU includes a first pull-up tube PU1 and a second pull-up tube PU2, and the pull-down tube PD includes a first pull-down tube PD1 and a second pull-down tube PD2; the first gate tube PG1 and the second gate tube PG2 can be both arranged in the second metal interconnection layer 42, and the first pull-down tube PD1 and the second pull-down tube PD2 are both arranged in the first metal interconnection layer 41.

[0087] Please refer to Figure 4 In this scenario, the first pull-up tube PU1 and the second pull-up tube PU2 are arranged at Figure 1 In the device layer 30 shown, the device layer 30 may include a third dielectric layer 305 , a fourth dielectric layer 306 and a first metal layer M1 which are stacked, wherein the fourth dielectric layer 306 is located between the third dielectric layer 305 and the first metal layer M1 , and the third dielectric layer 305 is disposed close to the substrate 1 . The first pull-up tube PU1 and the second pull-up tube PU2 can be arranged in the third dielectric layer 305, and the first metal layer M1 can include a first power line VDD. Accordingly, the electrode (source or drain) of the first pull-up tube PU1 can be connected to the first power line VDD through the first conductive structure 302; illustratively, a first hole can be provided on the third dielectric layer 305, and the bottom of the first hole extends to the electrode of the first pull-up tube PU1, and a second hole is provided on the fourth dielectric layer 306, and the second hole is connected to the first hole. The first conductive structure 302 may include a first conductive portion 303 and a second conductive portion 304, the first conductive portion 303 is located in the first hole, and the second conductive portion 304 is located in the second hole, and the second conductive portion 304 is in contact with both the first conductive portion 303 and the first power line VDD, and then the connection between the first pull-up tube PU1 and the first power line VDD can be achieved through the first conductive portion 303 and the second conductive portion 304. Similarly, the connection structure between the second pull-up tube PU2 and the first power line VDD is substantially similar to the connection structure between the first pull-up tube PU1 and the first power line VDD, and will not be described in detail herein.

[0088] In some embodiments, the front-end process may include a process before forming the fourth dielectric layer 306. In the implementation method where the substrate 1 includes single crystal silicon, the front-end process may include a process for processing the single crystal silicon to form logic circuits, pull-up tubes PU and other devices; accordingly, the back-end process may include a process for forming the fourth dielectric layer 306 and a process after forming the fourth dielectric layer 306. An exemplary back-end process may include forming the fourth dielectric layer 306, the second conductive portion 304, the first metal layer M1, the pull-up tube PU, the second metal layer M2, the gate tube PG, the third metal layer M3 and the fourth metal layer M4, etc.

[0089] In other embodiments, the front-end process may include forming the fourth dielectric layer 306 and the process before forming the fourth dielectric layer 306. In the implementation method where the substrate 1 includes single crystal silicon, exemplarily, the front-end process may include processing the single crystal silicon to form a logic circuit, a pull-up tube PU, a fourth dielectric layer 306 and a second conductive portion 304, etc.; accordingly, the back-end process may include the process after forming the fourth dielectric layer 306. exemplarily, the back-end process may include forming a first metal layer M1, a pull-up tube PU, a second metal layer M2, a gate tube PG, a third metal layer M3 and a fourth metal layer M4, etc.

[0090] In the same storage unit, the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 extend in the same direction in the device layer 30 ( Figure 4 In the vertical direction), the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 are arranged in parallel and spaced apart, the gate 43 of the first pull-up tube PU1 extends toward the second pull-up tube PU2, and the gate 43 of the first pull-up tube PU1 is connected to the other electrode (drain or source) of the second pull-up tube PU2 through a first contact structure 307; similarly, the gate 43 of the second pull-up tube PU2 extends toward the first pull-up tube PU1, and the gate 43 of the second pull-up tube PU2 is connected to the other electrode of the first pull-up tube PU1 through a second contact structure 308. Among them, the first contact structure 307 and the second contact structure 308 can be arranged in the device layer 30, and the first contact structure 307 can contact the gate 43 of the first pull-up tube PU1 or be connected to the gate 43 of the first pull-up tube PU1 through a conductive hole, and the first contact structure 307 can contact or be connected to the other electrode of the second pull-up tube PU2 through a conductive hole. Of course, part of the first contact structure 307 can also serve as the other electrode of the second pull-up tube PU2 to simplify the structure of the chip. Similarly, the second contact structure 308 can contact the gate 43 of the second pull-up tube PU2 or be connected through a conductive hole, and the second contact structure 308 can contact or be connected to the other electrode of the first pull-up tube PU1 through a conductive hole. Of course, part of the second contact structure 308 can also serve as the other electrode of the first pull-up tube PU1. Through the above arrangement, the first pull-up tube PU1 and the second pull-up tube PU2 constitute a structure that is approximately rotationally symmetrical around the center (such as Figure 5 As shown), the symmetry center may be the center of a line connecting the midpoint of the gate 43 of the first pull-up tube PU1 and the midpoint of the gate 43 of the second pull-up tube PU2.

[0091] In the above implementation, the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 extend along the first direction ( Figure 4 The gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 are along a second direction ( Figure 4 The width L1 of the first pull-up tube PU1 in the horizontal direction is 5nm-100nm (such as 5nm, 50nm, 100nm, etc.), the distance L2 between the gate 43 of the first pull-up tube PU1 and the gate 43 of the second pull-up tube PU2 along the second direction can be 20nm-200nm (such as 20nm, 100nm, 200nm, etc.), the active area AA of the first pull-up tube PU1 and the active area AA of the second pull-up tube PU2 both extend along the second direction, and the active area AA of the first pull-up tube PU1 and the active area AA of the second pull-up tube PU2 The width L4 of AA along the first direction is 5nm-200nm (such as 5nm, 100nm, 200nm, etc.), the gate 43 of the first pull-up tube PU1 extends in a direction away from the second pull-up tube PU2, and the distance L5 beyond the active area of ​​the first pull-up tube PU1 is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), and the gate 43 of the second pull-up tube PU2 extends in a direction away from the first pull-up tube PU1, and the distance L5 beyond the active area of ​​the second pull-up tube PU2 is 5nm-50nm (such as 5nm , 10nm, 50nm, etc.), the width L6 of the first conductive structure 302 along the first direction and along the second direction are 10nm-60nm (such as 10nm, 30nm, 60nm, etc.), the distance L7 between the gate 43 of the first pull-up tube PU1 and the second contact structure 308 along the second direction is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), the distance L8 between the gate 43 of the second pull-up tube PU2 and the first contact structure 307 along the second direction is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.). 10nm, 50nm, etc.), a distance L9 between the first contact structure 307 and the second contact structure 308 along the first direction is 20nm-100nm (such as 20nm, 50nm, 100nm, etc.), a width L10 of the first conductive structure 302 (such as the second conductive portion 304) along the second direction is 10nm-50nm (such as 10nm, 30nm, 50nm, etc.), and a width L6 of the first power line VDD along the second direction is 10nm-60nm (such as 10nm, 30nm, 60nm, etc.).

[0092] Please refer to Figure 1 , Figure 6 and Figure 7 In this scenario, the first pull-down tube PD1 and the second pull-down tube PD2 are located at Figure 1In the first metal interconnection layer 41 shown, for example, the first metal interconnection layer 41 may include at least one first dielectric layer 401 and at least one second dielectric layer 402 alternately stacked, and the first pull-down tube PD1 and the second pull-down tube PD2 may be arranged in the same second dielectric layer 402; that is, the active region, source, drain and gate 43 of the first pull-down tube PD1 and the second pull-down tube PD2 may all be arranged in the same second dielectric layer 402. The first metal interconnection layer 41 may also include a second metal layer M2, and the second metal layer M2 includes a second power line VSS, and the second power line VSS may be connected to an electrode (source or drain such as) of the first pull-down tube PD1 through a second conductive structure 407. Figure 1 The second power line VSS is connected to the S / D in the first metal interconnect layer 407. Similarly, the second power line VSS can be connected to an electrode of the second pull-down tube PD2 through another second conductive structure 407. The gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 extend in the same direction in the first metal interconnect layer 41, and the gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 are arranged in parallel and spaced apart. The end of the gate 43 of the first pull-down tube PD1 close to the second pull-down tube PD2 can be connected to the other electrode of the second pull-down tube PD2 through the third contact structure 408, and the end of the gate 43 of the second pull-down tube PD2 close to the first pull-down tube PD1 can be connected through the fourth contact structure 409. In this way, the first pull-down tube PD1 and the second pull-down tube PD2 form a substantially central rotationally symmetrical structure (such as Figure 5 As shown), the symmetry center can be the center of the line connecting the midpoint of the gate 43 of the first pull-down tube PD1 and the midpoint of the gate 43 of the second pull-down tube PD2.

[0093] Continue to refer to Figure 6 , Figure 7 as well as Fig.10 In some embodiments, the gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 are aligned along the first direction ( Figure 7 The gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 extend in a second direction ( Figure 7The width L11 of the first pull-down tube PD1 in the horizontal direction is 5nm-100nm (such as 5nm, 50nm, 100nm, etc.), the active area AA of the first pull-down tube PD1 and the active area AA of the second pull-down tube PD2 both extend along the second direction, and the width L12 of the active area AA of the first pull-down tube PD1 and the active area AA of the second pull-down tube PD2 along the first direction is 5nm-200nm (such as 5nm, 100nm, 200nm, etc.), the distance L13 between the active area AA of the first pull-down tube PD1 and the active area AA of the second pull-down tube PD2 along the first direction is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), and the gate 43 of the first pull-down tube PD1 is away from the second pull-up tube PU2 The gate 43 of the second pull-down tube PD2 extends in a direction away from the first pull-down tube PD1, and the distance L14 beyond the active area AA of the second pull-down tube PD2 is 5nm-50nm (such as 5nm, 10nm, 50nm, etc.), the distance L15 between the gates 43 of the first pull-down tube PD1 in adjacent storage cells is 5nm-80nm (such as 5nm, 40nm, 80nm, etc.), and the distance L15 between the gates 43 of the second pull-down tube PD2 in adjacent storage cells is 5nm-80nm (such as 5nm, 40nm, 80nm, etc.).

[0094] Please refer to Figure 8-Figure 10 In some implementations, the first gate transistor PG1 and the second gate transistor PG2 are arranged as follows: Figure 1In the second metal interconnection layer 42 shown, a third metal layer M3 and a fourth metal layer M4 are stacked on the side of the second metal interconnection layer 42 facing away from the substrate 1. The third metal layer M3 may be located between the fourth metal layer M4 and the second metal interconnection layer 42. A first dielectric layer 401 and / or a second dielectric layer 402 may be stacked between the third metal layer M3 and the fourth metal layer M4 to achieve insulation between the third metal layer M3 and the fourth metal layer M4. Exemplarily, the third metal layer M3 may include a word line WL, and the fourth metal layer M4 may include a bit line BL and a bit bar BLB arranged at intervals. The gates 43 of the first gate tube PG1 and the second gate tube PG2 are both connected to the word line WL. Exemplarily, the gates 43 of the multiple first gate tubes PG1 in the multiple storage cells may be an integrated structure, and correspondingly, the gates 43 of the second gate tubes PG2 in the multiple storage cells are an integrated structure. The gates 43 of at least one first gate tube PG1 and the gates 43 of at least one second gate tube PG2 in the multiple storage cells are connected via a fifth contact structure 428, and the fifth contact structure 428 is connected to the word line WL. In this way, the multiple storage cells can share one fifth contact structure 428, that is, the gates 43 of the first gate tubes PG1 and the gates 43 of the second gate tubes PG2 of the multiple storage cells are connected to the word line WL via one fifth contact structure 428, which can simplify the connection structure. It can be understood that the fifth contact structure 428 can be an integrated structure with the first gate 43 of the gate tube PG1 and the second gate 43 of the gate tube PG2, that is, the fifth contact structure 428 can be set in the same layer as the first gate 43 of the gate tube PG1 and the second gate 43 of the gate tube PG2 and formed at the same time. In this way, there is no need to additionally set the fifth contact structure 428, which can reduce the difficulty of manufacturing and the complexity of the structure.

[0095] Of course, in some implementations, the second metal interconnect layer 42 may include a third metal layer M3 , and the third metal layer M3 may be disposed away from the first metal interconnect layer 41 .

[0096] In the above implementation, one electrode of the first gate transistor PG1 is connected to the fourth contact structure 409 through the sixth contact structure 411, and the fourth contact structure 409 is also connected to the second contact structure 308, so that the sixth contact structure 411, the fourth contact structure 409 and the second contact structure 308 constitute the first storage node Q; the other electrode of the first gate transistor PG1 can be connected to the bit line BL through the third conductive structure 410. One electrode of the second gate transistor PG2 is connected to the third contact structure 408 through the seventh contact structure 412, and the third contact structure 408 is also connected to the first contact structure 307, so that the seventh contact structure 412, the third contact structure 408 and the first contact structure 307 constitute the second storage node QB; the other electrode of the second gate transistor PG2 is connected to the anti-bit line BLB through another third conductive structure 410.

[0097] In some embodiments, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 are connected along a first direction ( Fig. 9 The gate electrode 43 of the first gate transistor PG1 and the gate electrode 43 of the second gate transistor PG2 extend in a second direction ( Fig. 9 A width L16 of the sixth contact structure 411 along the second direction is 5nm-100nm (such as 5nm, 50nm, 100nm, etc.), a distance L17 between the gate 43 of the first gate tube PG1 and the seventh contact structure 412 along the second direction is 5nm-50nm (such as 5nm, 30nm, 50nm, etc.), a distance L18 between the gate 43 of the second gate tube PG2 and the sixth contact structure 411 along the second direction is 5nm-50nm (such as 5nm, 30nm, 50nm, etc.), and a width L19 of the sixth contact structure 411 and the seventh contact structure 412 along the second direction is 10nm-60nm (such as 10nm, 30nm, 60nm, etc.).

[0098] In some implementations, in each storage unit, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 extend in the same direction in the second metal interconnect layer 42, so that the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 are arranged in parallel and spaced apart, thereby making the first gate transistor PG1 and the second gate transistor PG2 form a substantially centrally symmetrical structure (e.g., Figure 5 As shown in FIG. 1 , the symmetry center may be the center of a line connecting a midpoint of the gate electrode 43 of the first gate transistor PG1 and a midpoint of the gate electrode 43 of the second gate transistor PG2.

[0099] In this scenario, multiple storage units can be arranged in an array, and accordingly, a first repeating unit array consisting of a first pull-up tube PU1 and a second pull-up tube PU2 is arranged in the device layer 30, a second repeating unit array consisting of a first pull-down tube PD1 and a second pull-down tube PD2 is arranged in the first metal interconnection layer 41, and a third repeating unit array consisting of a first gate tube PG1 and a second gate tube PG2 is arranged in the second metal interconnection layer 42. Among them, the first pull-up tube PU1 of each column can be connected to the same first power line VDD (share the first power line VDD), and similarly, the second pull-up tube PU2 of each column can be connected to the same first power line VDD; the first pull-down tube PD1 of each column can be connected to the same second power line VSS (share the second power line VSS), and similarly, the second pull-down tube PD2 of each column can be connected to the same second power line VSS. Such an arrangement can reduce the number of the first power line VDD and the second power line VSS, so as to reduce the structural complexity of the chip and facilitate the manufacture of the chip.

[0100] Please refer to Figure 6, Figure 8 , Fig.11 In this scenario, when reading data, the current on the second power line VSS is relatively large, and the second power line VSS itself has a certain resistance, so as the length of the second power line VSS increases, the voltage drop (voltage drop) on the second power line VSS is more obvious; accordingly, the fourth metal layer M4 can also include an auxiliary power line PVSS, and the second power line VSS corresponding to every certain number of storage cells can be connected to the auxiliary power line PVSS. By setting the auxiliary power line PVSS, the voltage drop on the second power line VSS can be reduced, thereby improving the performance of the chip. It can be understood that, if Figure 6 and Figure 8 As shown, the auxiliary power line PVSS can be connected to the corresponding second power line VSS through the conductive via 429 .

[0101] In this scenario, the first pull-up tube PU1 and the second pull-up tube PU2 can be silicon field effect transistors, and accordingly, the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 can all be oxide semiconductor (Oxide Semiconductor referred to as OS) field effect transistors; that is, the active area AA of the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 all include oxide semiconductor channels. Exemplarily, the first pull-up tube PU1 and the second pull-up tube PU2 can both be fin field effect transistors (Fin Field Effect Transistor referred to as Fin FET) to increase the gate control capability of the gate 43; accordingly, the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 can be planar channel structures (such as Figure 1 As shown), of course, the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 can also be fin field effect transistors or other transistor structures, which is not limited in the embodiment of the present application.

[0102] In the implementation mode in which the first gate tube PG1, the second gate tube PG2, the first pull-down tube PD1 and the second pull-down tube PD2 can all be oxide semiconductor field effect transistors, the gate 43 of the first gate tube PG1 can include a gate metal, an electrode layer covering the outside of the gate metal and a high dielectric constant layer (high k) covering the outside of the electrode layer, and the high dielectric constant layer is in contact with the channel. Exemplarily, the material of the gate metal can include tungsten, the material of the electrode layer can include titanium nitride, tantalum nitride, molybdenum nitride, TiAl-based alloy, etc., and the material of the high dielectric constant layer can include hafnium dioxide. The gate 43 of the second gate tube PG2, the gate 43 of the first pull-down tube PD1 and the gate 43 of the second pull-down tube PD2 can have substantially the same structure as the gate 43 of the first gate tube PG1, which will not be repeated here. Through the above-mentioned configuration, the electrode layer can prevent the gate 43 metal from diffusing outward, thereby avoiding the performance degradation of the oxide semiconductor field effect transistor; in addition, the electrode layer can also have a work function.

[0103] Continue to refer to Figure 1 In some embodiments, the metal interconnect layer 40 may include a plurality of stacked first metal interconnect layers 41 and a plurality of stacked second metal interconnect layers 42, wherein the plurality of first metal interconnect layers 41 are located between the second metal interconnect layers 42 and the device layer 30, and each first metal interconnect layer 41 is provided with a first pull-down tube PD1 and a second pull-down tube PD2 (such as Figure 7 ), and the first pull-down tubes PD1 in each first metal interconnection layer 41 are connected in parallel, and the second pull-down tubes PD2 in each first metal interconnection layer 41 are connected in parallel. Similarly, each second metal interconnection layer 42 is provided with a first gate tube PG1 and a second gate tube PG2 (as shown in FIG. Fig. 9 As shown in FIG. 1 , the first gate transistors PG1 in each second metal interconnection layer 42 are connected in parallel, and the second gate transistors PG2 in each second metal interconnection layer 42 are connected in parallel. By connecting in parallel, the equivalent current of the pull-down tube and the gate tube can be increased, thereby improving the performance of the chip.

[0104] Continue to refer to Figure 1It can be understood that the static random access memory may include a core area 10 and a peripheral area 20 located at the edge of the core area 10. The 6T cell array of the static random access memory is arranged in the core area 10, that is, the core area 10 is mainly used for data storage. Each metal layer can also form an auxiliary circuit. The first power line VDD, the second power line VSS, the word line WL, the bit line BL and the anti-bit line BLB can be led to the peripheral area 20 through the auxiliary circuit. The auxiliary line wheel can be connected to the device layer 30 through the conductive holes V1, V2, V3, and the corresponding part of the metal layer. Correspondingly, the auxiliary circuit can be arranged in the peripheral area 20 to avoid the auxiliary circuit occupying the space of the core area 10; in addition, since the auxiliary circuit is arranged in the peripheral area 20, there is no need to add an additional metal layer to set the auxiliary circuit, which can avoid increasing the number of metal layers to reduce the manufacturing cost.

[0105] In some embodiments, the third contact structure 408 and the fourth contact structure 409 can be made in the same process step and with the same material as the conductive via V1 connecting the second metal layer M2 and the first metal layer M1 in the peripheral region 20, thereby reducing the complexity of the chip manufacturing process. Similarly, the sixth contact structure 411 and the seventh contact structure 412 can be made in the same process step and with the same material as the conductive via V2 connecting the second metal layer M2 and the third metal layer M3 in the peripheral region 20, thereby further reducing the complexity of the chip manufacturing process.

[0106] In this scenario, the conductive hole can form a through hole on the corresponding film layer, and then fill the conductor in the through hole to achieve electrical connection between the two sides of the film layer. Exemplarily, the material of each metal layer can include metals such as copper and tungsten, and the material of the conductor, each contact structure, and each conductive structure can all include copper, tungsten, etc. In some embodiments, a conductive barrier layer is provided on the periphery of each metal layer, the periphery of the conductor, the periphery of each contact structure, and the periphery of each conductive structure. The material of the conductive barrier layer may include titanium nitride, tantalum nitride, ruthenium, cobalt, etc. The conductive barrier layer can prevent the internal conductive material from diffusing outward.

[0107] Scene 2

[0108] Please refer to Figure 12-14, the difference between this scenario and scenario one is that each storage unit includes 8 transistors (8T SRAM), and illustratively, the storage unit may include: a first pull-up tube PU1, a second pull-up tube PU2, a first pull-down tube PD1, a second pull-down tube PD2, a first gate tube PG1, a second gate tube PG2, a first read tube R1, and a second read tube R2. Correspondingly, the metal interconnect layer 40 may include a first metal interconnect layer 41, a second metal interconnect layer 42, and a third metal interconnect layer that are stacked, wherein the second metal interconnect layer 42 may be located between the first metal interconnect layer 41 and the third metal interconnect layer, and the first metal interconnect layer 41 may be disposed close to the device layer 30. The first pull-up tube PU1 and the second pull-up tube PU2 may be disposed in the device layer 30, and the structure and connection method of the first pull-up tube PU1 and the second pull-up tube PU2 may be the same as those in scenario one (such as Figure 4 The first pull-down tube PD1 and the second pull-down tube PD2 are arranged in the first metal interconnection layer 41, and the structure and connection method of the first pull-down tube PD1 and the second pull-down tube PD2 can be the same as those in scenario 1 (as shown in FIG. Figure 7 as shown); Fig.12 As shown, the first read transistor R1 and the second read transistor R2 can be arranged in the second metal interconnection layer 42, the gate 43 of the first read transistor R1 is connected to the first word line RWL, one electrode of the first read transistor R1 is connected to one electrode of the second read transistor R2, the other electrode of the first read transistor R1 is connected to the first bit line RBL through the fourth conductive structure 415, the gate 43 of the second read transistor R2 can be connected to the third contact structure 408 through the eighth contact structure 413, and the other electrode of the second read transistor R2 is connected to the second power line VSS through another fourth conductive structure 415; the first selection transistor PG1 and the second selection transistor PG2 can be arranged in the third metal interconnection layer, the first selection transistor PG1 and the second selection transistor PG2 are connected to the first word line RWL, the first electrode of the first read transistor R1 is connected to the first bit line RBL through the fourth conductive structure 415, the gate 43 of the second read transistor R2 can be connected to the third contact structure 408 through the eighth contact structure 413, and the other electrode of the second read transistor R2 is connected to the second power line VSS through another fourth conductive structure 415; The structure of the pass tube PG2 can be roughly the same as that in scenario 1. The gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 can both be connected to the second word line WWL, one electrode of the first gate tube PG1 is connected to the ninth contact structure 414 in the second metal interconnection layer 42 through the sixth contact structure 411, the ninth contact structure 414 is connected to the fourth contact structure 409, the other electrode of the first gate tube PG1 is connected to the third bit line WBL through the third conductive structure 410, one electrode of the second gate tube PG2 is connected to the eighth contact structure 413 through the seventh contact structure 412, and the other electrode of the second gate tube PG2 is connected to the second bit line WBLB through another third conductive structure 410.

[0109] In the above implementation, a first metal layer M1 may be provided in the device layer 30, and the first power line VDD may be located in the first metal layer M1; a second metal layer M2 may be provided in the first metal interconnection layer 41, and the second power line VSS may be provided in the second metal layer M2; a third metal layer M3, a fourth metal layer M4 and a fifth metal layer may be provided in the second metal interconnection layer 42, and the first word line RWL and the first bit line RBL may be provided in any one or more of the third metal layer M3, the fourth metal layer M4 and the fifth metal layer; a sixth metal layer and a seventh metal layer may be provided in the third metal interconnection layer, and the second bit line WBLB, the second word line WWL and the third bit line WBL may be provided in the sixth metal layer and / or the seventh metal layer.

[0110] It is understandable that the first power line VDD, the second power line VSS, the first word line RWL, the first bit line RBL, the second bit line WBLB, the second word line WWL and the third bit line WBL can also be individually wired through other metal layers of the chip, and this scenario does not limit this.

[0111] Scene 3

[0112] Please refer to Figure 15-18 The difference between this scenario and scenario 1 is that the connection structure of the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 is different. In this scenario, the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 are connected on the second metal interconnection layer 42 (such as Figure 1 The first metal interconnection layer 42 is provided with a first connection portion 404, and the end of the gate 43 of the first gate tube PG1 close to the second gate tube PG2 and the end of the gate 43 of the second gate tube PG2 close to the first gate tube PG1 are connected through the first connection portion 404. The first connection portion 404 can be arranged between the first gate tube PG1 and the second gate tube PG2, and the first connection portion 404 is connected to the word line WL. In this way, the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 in each storage unit are connected to the word line WL through the corresponding first connection portion 404. Compared with the case where the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 in multiple storage units are connected to the word line WL through the same fifth contact structure, the parasitic resistance of the word line WL can be reduced and the signal transmission response speed of the word line WL can be improved.

[0113] It can be understood that the first connection portion 404 can be arranged on the side of the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 away from the device layer, and the first connection portion 404 is located on the side of the third metal layer M3 close to the device layer, so that the gate 43 corresponding to the first connection portion 404 is connected to the word line WL.

[0114] Please refer to Fig.16 and Fig.17 In this scenario, the first connection portion 404 is located between the first gate tube PG1 and the second gate tube PG2. This configuration allows the gate 43 of the first gate tube PG1 to extend only to the first connection portion 404 toward the second gate tube PG2, which can reduce the extension length of the gate 43 of the first gate tube PG1, thereby allowing the seventh contact structure 412 to extend toward the gate 43 of the first gate tube PG1 in a direction perpendicular to the gate 43 of the first gate tube PG1, so as to increase the volume of the seventh contact structure 412, so as to facilitate the connection between the seventh contact structure 412 and the third contact structure 408; in addition, the contact area between the seventh contact structure 412 and the third contact structure 408 can also be increased, thereby reducing the connection resistance between the seventh contact structure 412 and the third contact structure 408. Similarly, the gate 43 of the second gate tube PG2 only extends toward the first gate tube PG1 to the first connecting portion 404, which can reduce the extension length of the gate 43 of the second gate tube PG2, and thus the sixth contact structure 411 can be extended toward the gate 43 of the second gate tube PG2 in a direction perpendicular to the gate 43 of the first gate tube PG1, so as to increase the volume of the sixth contact structure 411, so as to facilitate the connection between the sixth contact structure 411 and the fourth contact structure 409; in addition, the contact area between the sixth contact structure 411 and the fourth contact structure 409 can also be increased, thereby reducing the connection resistance between the sixth contact structure 411 and the fourth contact structure 409.

[0115] Exemplarily, the gate 43 of the first gate transistor PG1 and the gate 43 of the second gate transistor PG2 are connected along the first direction ( Fig.16 The distance L20 between the active area AA of the first gate tube PG1 and the first connection portion 404 along the first direction is 5nm-50nm (such as 5nm, 30nm, 50nm, etc.), and the distance L20 between the active area AA of the second gate tube PG2 and the first connection portion along the first direction is 5nm-50nm (such as 5nm, 30nm, 50nm, etc.).

[0116] like Fig.15 and Fig.19 As shown, in this scenario, the fourth metal layer M4 may also include an auxiliary power line PVSS, and the second power line VSS corresponding to every certain number of storage cells may be connected to the auxiliary power line PVSS. By setting the auxiliary power line PVSS, the voltage drop on the second power line VSS may be reduced, thereby improving the performance of the chip. It is understandable that the auxiliary power line PVSS may be connected to the corresponding second power line VSS through the conductive hole 429.

[0117] Scene 4

[0118] Please refer to Fig. 20 and Fig.21 The difference between this scenario and scenario 1 is that in the same storage unit, the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 are an integrated structure, that is, the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 are short-circuited in their extension direction; a second connection portion 416 is also provided in the second metal interconnect layer 42, the second connection portion 416 is located between the first gate tube PG1 and the second gate tube PG2, the second connection portion 416 is connected to the gate 43 of the first gate tube PG1, and the second connection portion 416 is connected to the word line WL. In this way, the gate 43 of the first gate tube PG1 and the second gate tube PG2 are an integrated structure, which can simplify the structure of the static random access memory and facilitate the manufacture of the chip; in addition, the gate 43 of the first gate tube PG1 and the second gate tube PG2 in each storage unit are connected to the word line WL through a second connection portion 416, which can reduce the parasitic resistance.

[0119] In the above implementation, the gate 43 of the first gate tube PG1 and the gate 43 of the second gate tube PG2 extend along the same straight line. This arrangement can reduce the width of the first gate tube PG1 and the second gate tube PG2 in a direction perpendicular to the straight line, and can reduce the size occupied by the first gate tube PG1 and the second gate tube PG2 in a direction perpendicular to the straight line, thereby improving the compactness of the chip structure. In addition, the seventh contact structure 412 can be extended in a direction perpendicular to the gate 43 of the second gate tube PG2 away from the gate 43 of the second gate tube PG2 to increase the volume of the seventh contact structure 412, so that the seventh contact structure 412 and the third contact structure 408 (such as Figure 7 In addition, the contact area between the seventh contact structure 412 and the third contact structure 408 can be increased, thereby reducing the connection resistance between the seventh contact structure 412 and the third contact structure 408. Similarly, the sixth contact structure 411 can be extended away from the first gate tube PG1 in a direction perpendicular to the gate 43 of the first gate tube PG1 to increase the volume of the sixth contact structure 411, so as to facilitate the sixth contact structure 411 to connect with the fourth contact structure 409 (as shown in FIG. Figure 7 in addition, the contact area between the sixth contact structure 411 and the fourth contact structure 409 can also be increased, thereby reducing the connection resistance between the sixth contact structure 411 and the fourth contact structure 409.

[0120] In this scenario, the projection of the word line WL on the second metal interconnect layer 42 can cover the corresponding first gate tube PG1 gate 43 and second gate tube PG2 gate 43. Accordingly, the second connection portion 416 can be located between the first gate tube PG1 and the second gate tube PG2, and approximately located in the middle position between the first gate tube PG1 and the second gate tube PG2, so that the current paths between the first gate tube PG1 and the second gate tube PG2 and the word line WL are the same, so as to ensure that the voltages of the gates 43 of the first gate tube PG1 and the second gate tube PG2 are approximately equal.

[0121] Scene 5

[0122] Please refer to Figure 22-Figure 24 The difference between this scenario and scenario one is that the first gate tube PG1 and the first pull-down tube PD1 are located in the first metal interconnection layer 41, and correspondingly, the second gate tube PG2 and the second pull-down tube PD2 are located in the second metal interconnection layer 42; or, the first gate tube PG1 and the first pull-down tube PD1 are located in the second metal interconnection layer 42, and correspondingly, the second gate tube PG2 and the second pull-down tube PD2 are located in the first metal interconnection layer 41.

[0123] In the implementation mode where the first gate tube PG1 and the first pull-down tube PD1 are located in the first metal interconnection layer 41, and the second gate tube PG2 and the second pull-down tube PD2 are located in the second metal interconnection layer 42, one electrode of the first pull-up tube PU1 and the second pull-up tube PU2 are both connected to the first power line VDD (such as Fig.25The first pull-up tube PU1 is connected to the gate 43 of the second pull-up tube PU2, and the other electrode of the second pull-up tube PU2 is connected to the gate 43 of the first pull-up tube PU1; the gate 43 of the first pull-up tube PU1 is also connected to an electrode of the second pull-down tube PD2, and the other electrode of the second pull-down tube PD2 is connected to a second power line VSS, the gate 43 of the second pull-down tube PD2 is connected to the gate 43 of the second pull-up tube PU2, one electrode of the first pull-down tube PD1 is connected to the gate 43 of the second pull-up tube PU2, and the other electrode of the first pull-down tube PD1 is connected to the gate 43 of the second pull-up tube PU2. The electrode of the first pull-down tube PD1 is connected to another second power line VSS, the gate 43 of the first pull-up tube PU1 is connected, one electrode of the first selection tube PG1 is connected to the gate 43 of the second pull-down tube PD2, the other electrode of the first selection tube PG1 is connected to the bit line BL, the gate 43 of the first selection tube PG1 is connected to a word line WL, one electrode of the second selection tube PG2 is connected to the gate 43 of the first pull-down tube PD1, the other electrode of the second selection tube PG2 is connected to the anti-bit line BLB, and the gate 43 of the second selection tube PG2 is connected to another word line WL. The six transistors of the first selection tube PG1, the second selection tube PG2, the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1 and the second pull-down tube PD2 constitute a storage unit for data storage.

[0124] In the above implementation, an electrode of the first selection tube PG1, an electrode of the first pull-down tube PD1, the gate 43 of the second pull-down tube PD2, and the gate 43 of the second pull-up tube PU2 are connected to form a first storage node Q; an electrode of the second selection tube PG2, an electrode of the second pull-down tube PD2, the gate 43 of the first pull-down tube PD1, and the gate 43 of the first pull-up tube PU1 are connected to form a second storage node QB.

[0125] like Fig. 22 and Fig.24 As shown, the first gate tube PG1 and the first pull-down tube PD1 are located in the first metal interconnect layer 41, and one electrode of the first gate tube PG1 is connected to one electrode of the first pull-down tube PD1. Accordingly, the electrodes of the first gate tube PG1 and the first pull-down tube PD1 that are close to each other can be set as an integral structure. With this arrangement, there is no need to set up other additional structures for connecting one electrode of the first gate tube PG1 and one electrode of the first pull-down tube PD1, which simplifies the structure of the chip; in addition, one electrode of the first gate tube PG1 and one electrode of the first pull-down tube PD1 are an integral structure, and one electrode of the first gate tube PG1 and one electrode of the first pull-down tube PD1 can be formed simultaneously using the same process, thereby reducing the difficulty of chip manufacturing. It can be understood that one electrode of the first gate tube PG1 and one electrode of the first pull-down tube PD1 can be connected to each other through the tenth contact structure 417. Figure 4 The second contact structure 308 is connected, the other electrode of the first gate transistor PG1 is connected to the bit line through the sixth conductive structure 419, the other electrode of the first pull-down transistor PD1 is connected to the second source line VSS through the fifth conductive structure 418, and the gate 43 of the first pull-down transistor PD1 is connected to the second source line VSS through the eleventh contact structure 420. Figure 4 The first contact structure 307 is shown, and the gate 43 of the first gate transistor PG1 is connected to the word line WL. Exemplarily, the second power line VSS is located in the second metal layer M2 to reduce the distance between the second power line VSS and the first gate transistor PG1 and the first pull-down transistor PD1 for easy connection.

[0126] In some embodiments, the active areas AA of the first gate tube PG1 and the first pull-down tube PD1 may also be an integrated structure, that is, the active areas AA of the first gate tube PG1 and the active areas AA of the second gate tube PG2 may be formed simultaneously using the same process to further reduce the difficulty of chip manufacturing.

[0127] Please refer to Fig.23 and Fig.24 Similarly, the second gate tube PG2 and the second pull-down tube PD2 are located in the second metal interconnection layer 42, and one electrode of the second gate tube PG2 is connected to one electrode of the second pull-down tube PD2. Accordingly, the electrodes of the second gate tube PG2 and the second pull-down tube PD2 that are close to each other can be set as an integrated structure. In this way, there is no need to set up other structures for connecting one electrode of the second gate tube PG2 and one electrode of the second pull-down tube PD2, which simplifies the structure of the chip; in addition, one electrode of the second gate tube PG2 and one electrode of the second pull-down tube PD2 are an integrated structure, and one electrode of the second gate tube PG2 and one electrode of the second pull-down tube PD2 can be formed simultaneously using the same process, thereby reducing the difficulty of chip manufacturing. It can be understood that one electrode of the second gate tube PG2 and one electrode of the second pull-down tube PD2 are connected to the eleventh contact structure 420 through the thirteenth contact structure 423, the gate 43 of the second gate tube PG2 is connected to the word line, and the other electrode of the second gate tube PG2 is connected to the anti-bit line BLB through the eighth conductive structure 424; the gate 43 of the second pull-down tube PD2 can be connected to the tenth contact structure 417 through the twelfth contact structure 421, and the other electrode of the second pull-down tube PD2 can be connected to the second power line VSS through the seventh conductive structure 422. Exemplarily, the second power line VSS is located in the fourth metal layer M4 to reduce the distance between the second power line VSS and the second gate tube PG2 and the second pull-down tube PD2, so as to facilitate the connection.

[0128] In some embodiments, the active area AA of the second gate tube PG2 and the second pull-down tube PD2 may also be an integrated structure, that is, the active area AA of the second gate tube PG2 and the active area AA of the second pull-down tube PD2 may be formed simultaneously using the same process to further reduce the difficulty of chip manufacturing.

[0129] In this scenario, the gate 43 of the first gate tube PG1 is connected to a word line WL. For example, the word line WL may be located in the third metal layer M3. This arrangement can reduce the distance between the word line WL and the gate 43 of the first gate tube PG1 to facilitate connection. The gate 43 of the second gate tube PG2 is connected to another word line WL. The word line WL may be located in the fourth metal layer M4 to reduce the distance between the word line WL and the gate 43 of the second gate tube PG2 to facilitate connection.

[0130] The present application also provides a chip manufacturing method, including:

[0131] S101: a device layer and a pull-up tube located in the device layer are manufactured on a substrate by using a front-end process, wherein the device layer includes a logic circuit.

[0132] like Figure 1 As shown, for example, a pull-up tube PU and a logic circuit can be manufactured on a substrate 1 using a front-end process, and then a third dielectric layer 305 is formed on the substrate 1 , and the third dielectric layer 305 covers the substrate 1 and the logic circuit and the pull-up tube PU located on the substrate 1 .

[0133] In some embodiments, after forming the third dielectric layer 305, a fourth dielectric layer 306 may be formed on the third dielectric layer 305, and a first metal layer M1 may be formed on the fourth dielectric layer 306. Exemplarily, the first metal layer M1 and the first power line VDD may be formed by patterning, etching, deposition, and other processes.

[0134] In the above implementation, before forming the first metal layer M1, a first hole can be formed on the third dielectric layer 305 by etching, and a second hole can be formed on the fourth dielectric layer 306, the first hole is in contact with an electrode of the pull-up tube PU, and the second hole is connected to the first hole. After that, a first conductive part 303 is formed in the first hole, and a second conductive part 304 is formed in the second hole, the first conductive part 303 is in contact with an electrode of the pull-up tube PU, and the first conductive part 303 is also in contact with the second conductive part 304; after forming the first power line VDD, the first power line VDD covers at least part of the second conductive part 304, so as to realize the connection between the first power line VDD and an electrode of the pull-up tube PU through the first conductive part 303 and the second conductive part 304.

[0135] In the embodiment of the present application, after forming the device layer 30, the method further includes:

[0136] S102: forming a metal interconnect layer and a gate tube and a pull-down tube located in the metal interconnect layer in a stacked manner on the device layer by adopting a back-end process.

[0137] It is understandable that the metal interconnection layer 40 and the gate tube and the pull-down tube PD located in the metal interconnection layer 40 are formed by the back-end process. Accordingly, in the static random access memory including the gate tube, the pull-up tube PU and the pull-down tube PD, the pull-up tube PU is located in the device layer 30, and the gate tube and the pull-down tube PD are located in the metal interconnection layer 40, so that the static random access memory is located inside the chip.

[0138] In some embodiments, the pull-up tube PU is a P-type transistor, the gate tube and the pull-down tube PD are N-type transistors, the oxide semiconductor transistors manufactured in the back-end process are easier to make into N-type transistors, and the gate tube PG and the pull-down tube PD manufactured in the back-end process are N-type transistors, which can facilitate the manufacture of the gate tube PG and the pull-down tube PD.

[0139] In some embodiments, the material of the substrate 1 may include silicon, that is, the substrate 1 is a silicon substrate, and accordingly, the pull-up tube PU may be a silicon field effect transistor, that is, the active region material of the pull-up tube PU may include single crystal silicon. This arrangement further facilitates the production of the pull-up tube PU.

[0140] In the above implementation, the metal interconnection layer 40 and the gate transistor PG and the pull-down transistor PD located in the metal interconnection layer 40 are formed on the device layer 30 by using the back-end process in a stacked manner, including:

[0141] A first metal interconnection layer 41 and a second metal interconnection layer 42 are stacked on the device layer 30 by adopting a back-end process, and the first metal interconnection layer 41 is located between the second metal interconnection layer 42 and the device layer 30; the gate tube PG and the pull-down tube PD are arranged in the first metal interconnection layer 41 and the second metal interconnection layer 42. Such an arrangement can reduce the area of ​​the static random access memory and the chip compared with the arrangement in which the gate tube PG and the pull-down tube PD are both arranged in the first metal interconnection layer 41 or the second metal interconnection layer 42.

[0142] In the implementation method in which the storage unit of the static random memory includes 6 transistors, correspondingly, the gate tube PG includes a first gate tube PG1 and a second gate tube PG2, the pull-up tube PU includes a first pull-up tube PU1 and a second pull-up tube PU2, and the pull-down tube PD includes a first pull-down tube PD1 and a second pull-down tube PD2.

[0143] In some embodiments, forming the first metal interconnection layer 41 and the second metal interconnection layer 42 in a stacked manner on the device layer 30 by using a back-end process includes: forming the first metal interconnection layer 41 and the first pull-down tube PD1 and the second pull-down tube PD2 in the first metal interconnection layer 41 by using a back-end process. Thereafter, forming the second metal interconnection layer 42 and the first gate tube PG1 and the second gate tube PG2 in the second metal interconnection layer 42 by using a back-end process on the first metal interconnection layer 41. That is, the first gate tube PG1 and the second gate tube PG2 are both arranged in the second metal interconnection layer 42, and the first pull-down tube PD1 and the second pull-down tube PD2 are both arranged in the first metal interconnection layer 41. Such a configuration can ensure that the number of transistors in the first metal interconnection layer 41 and the second metal interconnection layer 42 is not too large, thereby avoiding the structure of the first metal interconnection layer 41 and the second metal interconnection layer 42 from being too complicated.

[0144] In other embodiments, forming the first metal interconnection layer 41 and the second metal interconnection layer 42 in a stacked manner on the device layer 30 by using a back-end process includes: forming the first metal interconnection layer 41 and the first pull-down tube PD1 and the first gate tube PG1 in the first metal interconnection layer 41 in a stacked manner on the device layer 30 by using a back-end process. Thereafter, forming the second metal interconnection layer 42 and the second pull-down tube PD2 and the second gate tube PG2 in the second metal interconnection layer 42 in a stacked manner on the first metal interconnection layer 41 by using a back-end process. Such an arrangement can ensure that the number of transistors in the first metal interconnection layer 41 and the second metal interconnection layer 42 is not too large, thereby preventing the structures of the first metal interconnection layer 41 and the second metal interconnection layer 42 from being too complicated.

[0145] The chip manufactured by the chip manufacturing method provided in the embodiment of the present application, the device layer 30 includes a logic circuit, and the device layer 30 is manufactured by the front-end process; the metal interconnection layer 40 is stacked and arranged on the side of the device layer 30 away from the substrate 1, and the metal interconnection layer 40 is manufactured by the back-end process; the static random access memory includes a gate tube PG, a pull-up tube PU and a pull-down tube PD, the pull-up tube PU is arranged in the device layer 30, and the gate tube PG and the pull-down tube PD are arranged in the metal interconnection layer 40. Such a configuration can reduce the number of devices manufactured by the front-end process, reduce the area of ​​the device layer, and further reduce the area of ​​the chip, compared with the pull-up tube PU, the gate tube PG and the pull-down tube PD all being manufactured by the front-end process.

[0146] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized in that: include: substrate; A device layer, the device layer is disposed on the substrate, the device layer includes a logic circuit, and the device layer is configured to be manufactured in a front-end process; A metal interconnection layer, the metal interconnection layer is stacked and arranged on a side of the device layer away from the substrate, and the metal interconnection layer is configured to be manufactured in a back-end process; A static random access memory comprises: a gate tube, a pull-up tube and a pull-down tube, wherein the pull-up tube is arranged in the device layer, and the gate tube and the pull-down tube are arranged in the metal interconnection layer.

2. The chip according to claim 1, characterized in that: The metal interconnection layer includes a first metal interconnection layer and a second metal interconnection layer which are stacked, wherein the first metal interconnection layer is located between the second metal interconnection layer and the device layer; the gate tube and the pull-down tube are arranged in the first metal interconnection layer and the second metal interconnection layer.

3. The chip according to claim 2, characterized in that: The gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: the first gate tube, the second gate tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube.

4. The chip according to claim 3, characterized in that: The first gate tube and the second gate tube are located in the second metal interconnection layer, and the first pull-down tube and the second pull-down tube are located in the first metal interconnection layer.

5. The chip according to claim 4, characterized in that: In the same storage unit, the gate of the first pull-up tube and the gate of the second pull-up tube are arranged in parallel and spaced apart, the gate of the first pull-up tube extends toward the second pull-up tube, and the gate of the first pull-up tube is connected to the electrode of the second pull-up tube through a first contact structure; the gate of the second pull-up tube extends toward the first pull-up tube, and the gate of the second pull-up tube is connected to the electrode of the first pull-up tube through a second contact structure.

6. The chip according to claim 5, characterized in that: The gate of the first pull-down tube and the gate of the second pull-down tube are arranged in parallel and at intervals, the gate of the first pull-down tube is connected to the electrode of the second pull-down tube at one end close to the second pull-down tube through a third contact structure, and the gate of the second pull-down tube is connected to the electrode of the second pull-down tube at one end close to the first pull-down tube through a fourth contact structure.

7. The chip according to claim 6, characterized in that: The electrode of the first gate tube is connected to the fourth contact structure through a sixth contact structure, and the fourth contact structure is also connected to the second contact structure. The first storage node includes: the sixth contact structure, the fourth contact structure and the second contact structure; the electrode of the second gate tube is connected to the third contact structure through a seventh contact structure, and the third contact structure is also connected to the first contact structure. The second storage node includes: the seventh contact structure, the third contact structure and the first contact structure.

8. The chip according to claim 4, characterized in that: The gates of the first gate tubes in the plurality of storage cells are an integrated structure, the gates of the second gate tubes in the plurality of storage cells are an integrated structure, the gate of at least one of the first gate tubes in the plurality of storage cells is connected to the gate of at least one of the second gate tubes, and is connected to the word line.

9. The chip according to claim 4, characterized in that: In the same storage unit, the gates of the first gate tube and the second gate tube are arranged in parallel and at intervals, and a first connecting portion is also arranged in the second metal interconnection layer, and an end of the gate of the first gate tube close to the second gate tube is connected to an end of the gate of the second gate tube close to the first gate tube through the first connecting portion, and the first connecting portion is connected to the word line.

10. The chip according to claim 4, characterized in that: In the same storage unit, the gate of the first gate tube and the gate of the second gate tube are an integrated structure, and a second connecting portion is also provided in the second metal interconnection layer, the second connecting portion is located between the first gate tube and the second gate tube, the second connecting portion is connected to the gate of the first gate tube, and the second connecting portion is connected to the word line.

11. The chip according to any one of claims 8 to 10, characterized in that: The word line is arranged on a side of the second metal interconnection layer away from the substrate.

12. The chip according to claim 3, characterized in that: The first gate tube and the first pull-down tube are located in the first metal interconnection layer, and the second gate tube and the second pull-down tube are located in the second metal interconnection layer.

13. The chip according to claim 12, characterized in that: The electrodes of the first gate tube and the first pull-down tube close to each other are an integral structure, and the electrodes of the second gate tube and the second pull-down tube close to each other are an integral structure.

14. The chip according to any one of claims 3 to 13, characterized in that: One electrode of the first pull-up tube and the second pull-up tube are both connected to the first power line, the other electrode of the first pull-up tube is connected to the gate of the second pull-up tube, and the other electrode of the second pull-up tube is connected to the gate of the first pull-up tube; the gate of the first pull-up tube is also connected to one electrode of the second pull-down tube, the other electrode of the second pull-down tube is connected to the second power line, the gate of the second pull-down tube is also connected to the gate of the second pull-up tube, one electrode of the first pull-down tube is connected to the gate of the second pull-up tube, the other electrode of the first pull-down tube is connected to the second power line, and the gate of the first pull-down tube is connected to the gate of the first pull-up tube; the gate of the first pull-down tube is also connected to one electrode of the second selection tube, the other electrode of the second selection tube is connected to the anti-bit line, and the gate of the second selection tube is connected to the word line; one electrode of the first selection tube is connected to the gate of the second pull-down tube, the other electrode of the first selection tube is connected to the bit line, and the gate of the first selection tube is also connected to the word line.

15. The chip according to any one of claims 1 to 14, characterized in that: The metal interconnection layer includes a plurality of first dielectric layers and a plurality of second dielectric layers which are alternately stacked, and the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the second dielectric layer.

16. The chip according to any one of claims 1 to 15, characterized in that: The pull-up tube includes a P-type transistor, and the gate tube and the pull-down tube include N-type transistors.

17. The chip according to any one of claims 1 to 16, characterized in that: The material of the substrate includes silicon, and the pull-up tube includes a silicon field effect transistor.

18. An electronic device, characterized in that: include: A mainboard and a chip as described in any one of claims 1 to 17, wherein the chip is arranged on the mainboard.

19. A chip manufacturing method, characterized in that: include: A device layer and a pull-up tube located in the device layer are manufactured on a substrate by using a front-end process, wherein the device layer includes a logic circuit; A metal interconnection layer and a gate tube and a pull-down tube located in the metal interconnection layer are stacked on the device layer by adopting a back-end process; the static random access memory includes the gate tube, the pull-up tube and the pull-down tube.

20. The chip manufacturing method according to claim 19, characterized in that: The metal interconnection layer and the gate tube and the pull-down tube located in the metal interconnection layer are formed on the device layer by stacking by adopting the back-end process, including: A first metal interconnection layer and a second metal interconnection layer are stacked on the device layer by a back-end process, wherein the first metal interconnection layer is located between the second metal interconnection layer and the device layer; the gate tube and the pull-down tube are arranged in the first metal interconnection layer and the second metal interconnection layer.

21. The chip manufacturing method according to claim 20, characterized in that: The gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: the first gate tube, the second gate tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube; Forming a first metal interconnection layer and a second metal interconnection layer in a stacked manner on the device layer by a back-end process includes: Forming a first metal interconnect layer and the first pull-down tube and the second pull-down tube located in the first metal interconnect layer in a stacked manner on the device layer by a back-end process; A second metal interconnection layer and the first gate tube and the second gate tube located in the second metal interconnection layer are stacked on the first metal interconnection layer by adopting a back-end process.

22. The chip manufacturing method according to claim 20, characterized in that: The gate tube includes a first gate tube and a second gate tube, the pull-up tube includes a first pull-up tube and a second pull-up tube, and the pull-down tube includes a first pull-down tube and a second pull-down tube; the static random access memory includes a storage unit, the storage unit is used to store data, the storage unit is a 6T storage unit, and the storage unit includes: the first gate tube, the second gate tube, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube; Forming a first metal interconnection layer and a second metal interconnection layer in a stacked manner on the device layer by a back-end process includes: Forming a first metal interconnection layer and the first pull-down tube and the first gating tube located in the first metal interconnection layer in a stacked manner on the device layer by adopting a back-end process; A second metal interconnection layer and the second pull-down tube and the second gate tube located in the second metal interconnection layer are stacked on the first metal interconnection layer by adopting a back-end process.

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