A Synchronous Multi-Channel Digital Lock-in Amplifier

Abstract

The present invention relates to the technical field of weak signal detection equipment, and specifically to a multi-channel digital phase-locked amplifier. It includes a signal conditioning channel, a reference channel, a serial-to-parallel converter, a phase-sensitive detector and a communication output module; the number of the signal conditioning channels is at least three and the structures are exactly the same; the output ends of the signal conditioning channels are all connected to the serial-to-parallel converter; the signal conditioning channels include a DC isolation filter, an amplifier, a low-pass filter, and an A / D converter. By integrating multiple signal conditioning channels, space is saved, and all A / D converters are sampled at the same time to ensure synchronization, achieving synchronization and consistency that could not be achieved by multiple independent phase-locked amplifiers in the past; the phase-sensitive detector, phase shift module, phase-locked loop, and sine-cosine generator are all transferred to the internal processing of the digital chip, eliminating the influence of noise, temperature drift, DC bias, etc. of the analog signal, improving the stability of the output result, and saving the volume of the instrument.

Description

Technical Field

[0001] The invention relates to the technical field of weak signal detection equipment, and in particular to a multi-channel digital lock-in amplifier. Background Art

[0002] With the deepening of the exploration of the microscopic field, in the research of natural sciences and the practice of measurement engineering, there is an increasing need to detect extremely weak signals, such as measuring fluorescence intensity in material analysis, infrared detection, and electrical signal measurement in biomedical testing. This involves converting non-electrical physical quantities in the real world into voltage or current signals and performing signal processing. However, in these measurement practices, the intensity of these measured signals converted into digital signals is very weak and can be easily submerged by external noise, making detection often very difficult. The lock-in amplifier is an instrument for detecting signals submerged in noise.

[0003] The phase-locked amplifier is a weak signal detection instrument based on the cross-correlation method. Its core is the phase-sensitive detection technology. It uses a reference signal with the same frequency and fixed phase relationship as the signal to be measured as a reference, extracts the signal components related to the reference signal, and filters out the noise components outside the reference frequency.

[0004] In recent years, with the emergence of multi-element photosensitive array detectors such as silicon photodiode arrays, charge-coupled device arrays, InAs arrays, and pyroelectric arrays, there is an increasing demand for multi-channel lock-in amplifiers. The traditional method of parallel measurement of multiple single-channel lock-in amplifiers makes the circuit very complex and large, with poor consistency among channels and high cost. Summary of the invention

[0005] To solve the above problems, the present invention provides a synchronous multi-channel digital lock-in amplifier to realize a multi-channel lock-in amplifier with excellent synchronization, high performance and low cost.

[0006] A synchronous multi-channel digital phase-locked amplifier, characterized in that it includes a signal conditioning channel, a reference channel, a serial-to-parallel converter, a phase-sensitive detector and a communication output module; the number of the signal conditioning channels is at least three and the structures are exactly the same; the output ends of the signal conditioning channels are all connected to the serial-to-parallel converter; the output end of the serial-to-parallel converter and the output end of the reference channel are both connected to the phase-sensitive detector; the output end of the phase-sensitive detector is connected to the communication output module.

[0007] A further improvement is that: the signal conditioning channel includes a DC isolation filter, an amplifier, a low-pass filter, and an A / D converter; the DC isolation filter, the amplifier, the low-pass filter, and the A / D converter are connected in sequence.

[0008] A further improvement is that the output ends of all the A / D converters are connected to a serial-to-parallel converter to convert the parallel data streams of multiple signal conditioning channels into serial data streams.

[0009] A further improvement is that the reference channel includes a square wave shaping circuit, a phase shift module, a digital phase locked loop, and a sine and cosine generator; the square wave shaping circuit, the phase shift module, the digital phase locked loop, and the sine and cosine generator are connected in sequence.

[0010] A further improvement is that the phase shift module, digital phase-locked loop and sine-cosine generator are all pure digital processing units and can be independently implemented inside the FPGA.

[0011] A further improvement is that the digital phase-locked loop includes a frequency measurement module, a phase detector module, a filter module, and a voltage-controlled oscillator module, all of which are generated inside the FPGA.

[0012] A further improvement is that the phase-sensitive detector includes two multipliers and a low-pass filter; the multiplier multiplies the output signal of the serial-to-parallel converter and the output signal of the reference channel.

[0013] A further improvement is that after the output signal of the serial-to-parallel converter and the output signal of the reference channel are multiplied by the multiplier, the multiplier inputs the output result into a low-pass filter for processing.

[0014] A further improvement is that the model of the A / D converter is AD7984.

[0015] A further improvement is that the model of the FPGA is EP4CE115.

[0016] Beneficial effects of the present invention:

[0017] (1) Compared with the existing lock-in amplifier, the synchronous multi-channel digital lock-in amplifier provided by the present invention saves space by integrating multiple signal conditioning channels, and all A / D converters perform sampling at the same time, ensuring synchronization, and achieving synchronization and consistency that cannot be achieved by multiple independent lock-in amplifiers in the past. In addition, the serial-to-parallel converter converts the parallel multi-channel digital signals into serial signals, greatly reducing the demand for FPGA resources, and completing the functions of multiple chips in the past with one chip.

[0018] (2) Compared with the existing multi-channel phase-locked amplifier, the present invention transfers the phase-sensitive detector, phase shift module, phase-locked loop, and sine and cosine generator to the internal processing of the digital chip, which not only eliminates the influence of noise, temperature drift, DC bias, etc. of the analog signal, greatly improves the stability of the output result, but also saves the volume of the instrument. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the structure of a synchronous multi-channel lock-in amplifier according to an embodiment of the present invention;

[0020] Figure 2 The present invention is a schematic diagram of a data conversion format of a serial-to-parallel converter in a synchronous multi-channel lock-in amplifier according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with the accompanying drawings. It is necessary to point out here that the following specific implementation methods are only used to further illustrate the present invention and cannot be understood as limiting the scope of protection of the present invention. Technicians in this field can make some non-essential improvements and adjustments to the present invention based on the above application content.

[0022] Please refer to Figure 1 , Figure 1 It is a schematic diagram of the structure of a synchronous multi-channel phase-locked amplifier according to an embodiment of the present invention, which includes: at least three signal conditioning channels with completely identical structures, a reference channel, a serial-to-parallel converter, a phase-sensitive detector and a communication output module; the output ends of the signal conditioning channels are all connected to the serial-to-parallel converter; the output ends of the serial-to-parallel converter and the output ends of the reference channel are all connected to the phase-sensitive detector; the output end of the phase-sensitive detector is connected to the communication output module.

[0023] The signal conditioning channel is used to receive the input signal to be tested. The signal conditioning channel includes a DC isolation filter, an amplifier, a low-pass filter, and an A / D converter; the input signal first passes through the DC isolation filter to filter out the DC signal and retain only the AC signal; then passes through the amplifier, which is a program-controlled adjustable amplification factor, and amplifies to a degree that can be quantized and converted according to the approximate amplitude of the input signal; then passes through a low-pass filter to filter out high-frequency harmonic components and noise signals to meet the requirements of the Nyquist theorem and prevent the high-frequency signal from being mixed into the low-frequency band during subsequent quantization of the A / D converter, affecting the measurement; finally, the input signal after amplification and filtering is quantized and converted into a digital signal through the A / D converter to facilitate subsequent processing. Each signal conditioning channel is the same, and the A / D converter samples at the same time to ensure synchronization.

[0024] In this embodiment, the A / D converter is AD7984, and the A / D converter of each signal conditioning channel is connected to the subsequent serial-to-parallel converter, such as Figure 2 As shown, the A / D quantized data of N channels at the same sampling moment, after entering the serial-to-parallel converter, are merged into a serial data stream arranged in sequence, arranged in the order of channel 1, channel 2, channel 3...channel N, and then to channel 1, channel 2, channel 3...channel N at the next sampling moment, and so on.

[0025] The reference channel is used to shape the reference signal. The reference channel includes a square wave shaping circuit, a phase shift module, a digital phase-locked loop, and a sine-cosine generator; the square wave shaping circuit, the phase shift module, the digital phase-locked loop, and the sine-cosine generator are connected in sequence. First, the reference signal enters the square wave shaping circuit, and the reference signal is amplified and shaped to meet the acquisition requirements of the FPGA; then it enters the phase shift module inside the FPGA, and the reference signal is phase-shifted according to the required phase shift value.

[0026] The digital phase-locked loop is used to generate an internal signal with the same frequency and phase as the reference signal. The digital phase-locked loop in this embodiment is a complete all-digital phase-locked loop, including a frequency measurement module, a phase detector module, a filter module, and a voltage-controlled oscillator module, all of which are generated inside the FPGA, are not subject to external interference, and will not interfere with other modules of the phase-locked amplifier; the model of the FPGA in this embodiment is EP4CE115.

[0027] The sine and cosine generator is used to receive the signal output by the digital phase-locked loop and generate the sine waveform and cosine waveform required by the phase-sensitive detector.

[0028] The phase-sensitive detector comprises two multipliers and a low-pass filter. The multiplier multiplies the output signal of the serial-to-parallel converter and the output signal of the sine-cosine generator, and the specific expression is:

[0029] Define the signal to be tested as:

[0030] The reference signal is: S R (t) = A R sin(ωt+δ) and S R (t) = A R cos(ωt+δ)

[0031] After the two are multiplied by the multiplier, the output signals are:

[0032]

[0033]

[0034] The multiplier outputs the result S o1 (t) and S o2 (t) are input to the low-pass filter respectively. The low-pass filter ensures that the frequency components of ω and 2ω are filtered out. Therefore, S o1 (t) and S o2 (t) Only the DC component remains:

[0035] and

[0036] From this we can deduce:

[0037]

[0038]

[0039]

[0040]

[0041] Through the demodulation process of the phase-sensitive detector, the amplitude and phase information of the input signal can be restored.

[0042] The communication output module converts the above X, R, A I、 The result of θ can be output to other devices through interfaces such as USB and RS232.

[0043] Compared with the existing lock-in amplifier, the synchronous multi-channel digital lock-in amplifier provided in this embodiment saves space by integrating multiple signal conditioning channels, and all A / D converters perform sampling at the same time, thereby ensuring synchronization and achieving synchronization and consistency that could not be achieved by multiple independent lock-in amplifiers in the past. In addition, the serial-to-parallel converter converts parallel multi-channel digital signals into serial signals, greatly reducing the demand for FPGA resources, and completing the functions of multiple chips in the past with one chip.

[0044] Compared with the existing multi-channel phase-locked amplifier, this embodiment transfers the phase-sensitive detector, phase shift module, phase-locked loop, and sine and cosine generator to the internal processing of the digital chip, which not only eliminates the influence of noise, temperature drift, DC bias, etc. of the analog signal, greatly improves the stability of the output result, but also saves the volume of the instrument.

[0045] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A synchronous multi-channel digital lock-in amplifier, characterized in that: It includes a signal conditioning channel, a reference channel, a serial-to-parallel converter, a phase-sensitive detector and a communication output module; the number of the signal conditioning channels is at least three and the structures are completely the same; the output ends of the signal conditioning channels are all connected to the serial-to-parallel converter; the output ends of the serial-to-parallel converter and the output ends of the reference channel are all connected to the phase-sensitive detector; the output end of the phase-sensitive detector is connected to the communication output module; The signal conditioning channel includes a DC blocking filter, an amplifier, a low-pass filter, and an A / D converter; the DC blocking filter, the amplifier, the low-pass filter, and the A / D converter are connected in sequence; the output ends of all the A / D converters are connected to a serial-to-parallel converter to convert the parallel data streams of multiple signal conditioning channels into serial data streams, thereby reducing the demand for FPGA resources; the input signal first passes through a DC blocking filter to filter out the DC signal and retain only the AC signal; then passes through an amplifier, which is a program-controlled adjustable amplification factor, and amplifies the input signal to a level that can be quantized and converted according to the approximate amplitude of the input signal; and then passes through a low-pass filter to filter the input signal. High-frequency harmonic components and noise signals are removed to meet the requirements of the Nyquist theorem and prevent high-frequency signals from being mixed into the low-frequency band during subsequent A / D converter quantization, which affects the measurement. Finally, the input signal after amplification and filtering is quantized and converted into a digital signal through the A / D converter. All A / D converters are sampled at the same time to ensure synchronization. The N-channel A / D quantized data at the same sampling time enter the serial-to-parallel converter and are merged into a serial data stream arranged in sequence, in the order of channel 1, channel 2, channel 3...channel N, and then to channel 1, channel 2, channel 3...channel N at the next sampling time, and so on. The reference channel includes a square wave shaping circuit, a phase shift module, a digital phase-locked loop, and a sine and cosine generator; the square wave shaping circuit, the phase shift module, the digital phase-locked loop, and the sine and cosine generator are connected in sequence; the phase shift module, the digital phase-locked loop, and the sine and cosine generator are all pure digital processing units, which are independently implemented inside the FPGA; the digital phase-locked loop includes a frequency measurement module, a phase detector module, a filter module, and a voltage-controlled oscillator module, all of which are generated inside the FPGA; first, the reference signal enters the square wave shaping circuit, and the reference signal is amplified and shaped to meet the acquisition requirements of the FPGA; then it enters the phase shift module inside the FPGA, and the reference signal is phase-shifted according to the required phase shift value. The digital phase-locked loop is used to generate an internal signal with the same frequency and phase as the reference signal, and the sine and cosine generator is used to receive the signal output by the digital phase-locked loop to generate the sine waveform and cosine waveform required by the phase-sensitive detector.

2. A synchronous multi-channel digital lock-in amplifier according to claim 1, characterized in that: The phase-sensitive detector comprises two-way multipliers and a low-pass filter; the multiplier multiplies the output signal of the serial-to-parallel converter and the output signal of the reference channel.

3. A synchronous multi-channel digital lock-in amplifier according to claim 2, characterized in that: After the output signal of the serial-to-parallel converter and the output signal of the reference channel are multiplied by the multiplier, the multiplier inputs the output result into the low-pass filter for processing.

4. A synchronous multi-channel digital lock-in amplifier according to claim 1, characterized in that: The model of the A / D converter is AD7984.

5. The synchronous multi-channel digital lock-in amplifier according to claim 1, characterized in that: The model of the FPGA is EP4CE115.

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