A high-power GaN device heat dissipation and integrated integrated structure and manufacturing method

Abstract

The present invention discloses a high-power GaN device heat dissipation and integrated integrated structure, including a TSV adapter board, a GaN device, a housing and a circuit board, wherein the TSV adapter board is provided with an input microchannel, an output microchannel and a guide structure, the GaN device is mounted on the TSV adapter board and a first open microchannel is provided on the back, and the two sides of the first open microchannel in the horizontal direction are respectively connected to the input microchannel and the output microchannel through the guide structure; the TSV adapter board is mounted in the housing and is provided with a flow channel connected to the input microchannel and the output microchannel, and the circuit board is arranged on the top of the side wall of the housing and is electrically connected to the TSV adapter board. The present invention improves the heat dissipation efficiency of the microchannel of the GaN device substrate without reducing the mechanical strength of the GaN device body, and solves the problems of electrical grounding and heterogeneous integration of the GaN device. In addition, the present invention also proposes a manufacturing method for realizing the above structure.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic packaging, and more specifically to a high-power GaN device heat dissipation and integration integrated structure and a manufacturing method thereof. Background Art

[0002] GaN materials have the characteristics of high power density, wide bandgap, high thermal conductivity, high breakdown field strength and high electron saturation velocity, and are suitable for high-power and high-frequency applications. They are widely used in military and commercial fields such as radar systems, communication systems, 5G, and new energy vehicles. With the development of GaN device applications, the local heat flux density of GaN HEMT devices will exceed 1000W / cm 2 If the heat generated in these chips cannot be dissipated in time, it will affect the performance of the chips and make them ineffective.

[0003] At present, the heat dissipation of GaN devices is mainly achieved by placing the chip on a high thermal conductivity carrier such as a copper-molybdenum carrier or a diamond carrier, and then loading it onto a cold plate radiator for heat dissipation. This method is passive heat dissipation, and the thermal resistance of the heat conduction path between the heat source and the radiator is large, which limits the heat dissipation capacity of the terminal radiator. In recent years, the academic community has proposed to optimize heat dissipation by making graphene on the surface of the active area of ​​the GaN HEMT device, or by completely or partially replacing the substrate of the GaN device with a high thermal conductivity substrate such as diamond. This method is also passive heat dissipation. Compared with the former, the thermal resistance of the heat conduction path is greatly reduced, and local hot spots are suppressed, but it still faces the problem of how to efficiently dissipate the high-density heat flow confined to the chip body scale range. The distance from the short terminal radiator to the GaN device body must be shortened.

[0004] Microfluidic heat dissipation technology is an active heat dissipation method with high heat dissipation efficiency and extremely low thermal resistance. It is expected to become a key way to solve the heat dissipation needs of high-power GaN devices. In 2006, the U.S. Naval Laboratory proposed a heat dissipation solution for high-power GaN devices using microfluidic heat sinks. The GaN device is assembled on the bottom surface of a substrate (the side opposite to the open groove) made of open parallel grooves such as Si, AlN, and copper using conductive glue or eutectic bonding technology, and a fixture is attached to close the open surface of the microfluidic heat sink. The microfluidic width is 500±25μm, the height is 1.4±0.025mm, and the spacing is 1mm. The active layer of the GaN device is used to make a simulated heat source to test and analyze the heat dissipation efficiency of the microfluidic device, verifying the heat dissipation efficiency of the parallel groove microfluidic device. However, this solution essentially dissipates heat from discrete GaN devices through a module fixture and a microchannel heat sink consisting of open parallel groove microchannels. The distance between the heat source and the heat dissipation microchannel includes the GaN device substrate layer, the distance from the bottom of the open parallel grooves of the Si, AlN, copper and other substrates to the bottom surface, and the bonding layer between the two. The heat conduction path is long and the integration requirements of GaN devices are not taken into consideration.

[0005] In recent years, the industry has proposed to embed microchannels in high-performance packaging substrates to dissipate heat for high-power GaN devices mounted thereon. For example, Peking University has developed LTCC substrate technology with embedded heat dissipation microchannels, and demonstrated the heat transfer performance of three microchannel structures embedded in LTCC substrates; the Sichuan Institute of Piezoelectric and Acousto-Optical Technology proposed the technology of embedding microchannels in microwave printed circuit boards, and demonstrated the packaging of S-band 10W continuous wave power amplifier modules, solving the problem of GaN device integration and dissipating heat at the same time. In terms of high-frequency electrical performance, LTCC has excellent high-frequency, high-Q characteristics and high-speed transmission characteristics, can withstand high temperatures and adapt to high currents, and is an excellent multi-chip RF packaging substrate material. However, the thermal conductivity of LTCC is only 2-5W / m·K, while that of Si is 150W / m·K, and that of SiC is 490W / m·K, which is similar to the aforementioned parallel channel microfluidic heat dissipation technology solutions such as Si. This results in a large thermal resistance in the heat source area of ​​the GaN device mounted thereon - that is, the path between the active layer of the device and the embedded microchannels in the LTCC, making it difficult to improve the heat dissipation efficiency and to fully utilize the advantages of the microfluidic heat dissipation technology. Moreover, it is difficult to further reduce the size, aspect ratio, and minimum spacing of the embedded microchannels in the LTCC substrate to fully utilize the advantages of the microfluidic heat dissipation technology. In 2018, Ma Shenglin and others from Xiamen University proposed a TSV adapter board with embedded microchannels for 2.5D integration and heat dissipation of GaN devices, and demonstrated a 2-6GHz GaN power amplifier module based on an embedded microchannel TSV adapter board, showing 400W / cm 2 Compared with the embedded microchannel technology of LTCC, the embedded microchannel of TSV adapter board has greatly improved the thermal resistance between the heat source of GaN device and the heat dissipation microfluid and the characteristic size of the microchannel.

[0006] However, with the development of GaN device application level, the heat flux density increases, and the thermal resistance from the heat source area to the heat dissipation microfluid path urgently needs to be further reduced. In 2015, the Raytheon research team in the United States proposed a technical route to close the open microchannels embedded in the diamond substrate of the GaN device and the microchannels embedded in the silicon substrate by bonding process, further reducing the thermal resistance from the active area of ​​the GaN device to the heat dissipation microfluid and improving the heat dissipation efficiency of the microfluid. However, this solution first needs to solve the GaN-On-Diamond process problem. Whether it is to grow the GaN device layer directly on the diamond substrate or to transfer the GaN device layer to the diamond substrate through transfer technology, compared with SiC-based GaN devices or Si-based GaN devices, this technical route itself is difficult and immature. Secondly, the production of microgrooves on the diamond substrate and its bonding process with the silicon microfluidic substrate, whether it is direct bonding or solder bonding, all face thermal stress problems, which are technically complex and difficult. In 2016, the Lockheed Martin R&D team proposed to locally thin the SiC substrate in the active area of ​​the GaN device. The thickness of the SiC substrate is 100μm, and the active area is etched and thinned to 30μm. A split manifold heat sink is installed underneath. When working, the manifold heat sink sprays cooling fluid directly on the suspended SiC substrate. Demonstration tests show that the gain of the GaN monolithic microwave integrated circuit amplifier can be increased by more than 4dB, its maximum output power is increased by more than 8dB, and the power is increased by 3% to 5%. In this solution, the active layer substrate of the GaN device is locally thinned, and the surrounding frame is bonded to the manifold heat sink. The bonding process is less difficult, but the locally thinned active layer of the GaN device is suspended. When working, the cooling fluid is sprayed vertically on the suspended surface. The active area of ​​the GaN device on the suspended film will face performance degradation and reliability risks. It is necessary to coordinate the design between the thickness of the suspended film, the cooling fluid spray speed, and the device performance. It is difficult to further reduce the distance between the active layer of the GaN device and the cooling fluid. Moreover, similar to the aforementioned solution, this solution is only suitable for heat dissipation of monolithic GaN devices and cannot meet the requirements of GaN device integration, especially integration with heterogeneous microelectronic chips. Summary of the invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a high-power GaN device heat dissipation and integration integrated structure and a manufacturing method.

[0008] In order to achieve the above purpose, the technical solution of the present invention is:

[0009] A high-power GaN device heat dissipation and integration integrated structure, the integrated structure includes

[0010] A TSV adapter board, wherein the upper and lower surfaces of the TSV adapter board are respectively provided with metal wiring layers, the upper surface is provided with a flow guide structure, and the body is provided with an interconnection structure, an input microchannel and an output microchannel respectively extending in the thickness direction, the input microchannel is respectively provided with a first outlet and a first inlet on the upper and lower surfaces of the TSV adapter board, the output microchannel is respectively provided with a second inlet and a second outlet on the upper and lower surfaces of the TSV adapter board, and the first inlet and the second outlet are respectively located outside the first outlet and the second inlet;

[0011] A GaN device is disposed on the TSV adapter plate, a first open microchannel is disposed on the back side of the substrate of the GaN device, and two sides of the first open microchannel in a horizontal direction are respectively connected to the first outlet and the second inlet through the guide structure;

[0012] A housing, wherein the housing is provided with a flow channel, wherein the flow channel includes a third inlet and a third outlet provided on the bottom upper surface of the housing, wherein the TSV adapter plate is assembled in the housing, wherein the third inlet is in communication with the first inlet, and the third outlet is in communication with the second outlet;

[0013] The circuit board is arranged on the top of the side wall of the housing and is electrically connected to the TSV adapter board.

[0014] Optionally, the distance between the bottom surface of the first open microchannel and the active layer of the device is less than 100 micrometers, and the characteristic size of the first open microchannel is 10-100 micrometers.

[0015] Optionally, the first open microchannel is a parallel groove type, a spoiler column type or a fin type.

[0016] Optionally, the apertures of the input microchannel and the output microchannel are gradually enlarged in a step-by-step manner from the upper surface to the lower surface of the TSV adapter plate, and are offset outward at the step change location.

[0017] Optionally, the interconnect structure includes an interconnect line in the form of a CPW, microstrip line or TSV interconnected transmission line arranged outside the GaN device assembly area, and a conformal and continuous insulating layer is provided between the interconnect line and the substrate of the TSV adapter plate.

[0018] Optionally, the upper surface of the TSV adapter board is also provided with at least one area for arranging other microelectronic chips and pads for wire bonding or flip-chip bonding.

[0019] Optionally, a second open microchannel corresponding to the first open microchannel is further provided on the upper surface of the TSV adapter plate.

[0020] The method for manufacturing the above-mentioned high-power GaN device heat dissipation and integrated integrated structure comprises the following steps:

[0021] 1) etching a first open microchannel on the back side of the substrate of the GaN device;

[0022] 2) Providing a high-resistance silicon wafer as the substrate of the TSV adapter plate, and making interconnection structures, input microchannels, output microchannels, flow guide structures, and metal wiring layers;

[0023] 3) A corresponding patterned adhesive sealing layer is formed on the substrate surface of the GaN device and the upper surface of the TSV adapter plate, and the substrate of the GaN device is bonded to the TSV adapter plate through the patterned adhesive sealing layer. The patterned adhesive sealing layer seals the first open microchannel and the first outlet and the second inlet, and the electrical signal of the GaN device is led out through bonding;

[0024] 4) Assemble other microelectronic chips on the TSV adapter board by bonding;

[0025] 5) Assemble the TSV adapter board on the bottom of the shell through low-temperature solder, nano silver paste or conductive glue, and make the third inlet sealed and connected with the first inlet, and the third outlet sealed and connected with the second outlet, and assemble the circuit board on the top of the shell side wall to lead out the electrical signal of the TSV adapter board.

[0026] Optionally, in step 2), the steps of making the input microfluidic channel and the output microfluidic channel include: (1) providing a first high-resistance silicon wafer, forming a pair of first holes with a certain depth on the upper surface of the first high-resistance silicon wafer, and forming a pair of second holes connected one-to-one with the first holes on the lower surface of the first high-resistance silicon wafer; (2) providing a second high-resistance silicon wafer, forming a pair of third holes with a certain depth on the upper surface of the second high-resistance silicon wafer, and forming a pair of fourth holes connected one-to-one with the third holes on the lower surface of the second high-resistance silicon wafer; (3) aligning and bonding the first high-resistance silicon wafer and the second high-resistance silicon wafer so that the third holes and the second holes correspond to each other and fit together, wherein the first holes form the first outlet and the second inlet, and the fourth holes form the first inlet and the second outlet.

[0027] Optionally, step 2) further includes manufacturing a second open microchannel on the upper surface of the TSV adapter plate, wherein the second open microchannel corresponds to the first open microchannel.

[0028] Compared with the disclosed technical solutions, the technical solution of the present invention has the following beneficial effects:

[0029] (1) A first open microchannel is fabricated on a GaN device SiC substrate or Si substrate and assembled on a TSV adapter board with an embedded microchannel. The two together constitute a closed microchannel system. The TSV adapter board also provides electrical grounding for the GaN device and a wiring layer for interconnection with other chips. The path between the active layer of the GaN device and the embedded microchannel can be reduced to less than 70 microns without reducing the mechanical strength of the device body. The size of the microchannel can be reduced to the order of 10 microns, which effectively improves the heat dissipation efficiency while solving the problems of electrical grounding and heterogeneous integration of GaN devices.

[0030] (2) Embedding microfluidic heat dissipation in the active layer of GaN devices while achieving heterogeneous integration with other chips;

[0031] (3) Direct RIE etching of GaN device SiC substrate or Si substrate to produce microchannels can be embedded in the current GaN device wafer manufacturing process, which greatly reduces the difficulty and has good compatibility;

[0032] (4) The cooling medium in the microchannel of the GaN device SiC substrate or Si substrate flows in a direction parallel to the device active layer, rather than vertically in the currently disclosed technology, which avoids the mechanical impact and electrical performance of the cooling medium on the active layer of the GaN device. According to the previous simulation test, the heat flux density can reach up to 1000W / cm 2 The heat dissipation capacity of hot spots. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the overall structure of a high-power GaN device heat dissipation and integrated integrated structure of Example 1;

[0034] Figure 2 is a schematic diagram of a GaN device having a first open microchannel formed on the back side of Example 1;

[0035] Figure 3 is a schematic structural diagram of a TSV adapter board of Example 1;

[0036] Figure 4 yes Figure 3 A top cross-sectional view along the directions a-a', b-b', c-c', and d-d';

[0037] Figure 5 is a top view schematically showing the connection relationship of the flow channels of the TSV adapter plate of Example 1;

[0038] Figure 6 is a schematic diagram of the manufacturing process of the TSV adapter board of Example 1;

[0039] Figure 7The high-power GaN device heat dissipation and integrated structure of Example 1 has a flow rate of 80 ml / min and a heat flux density of 865.24 W / cm 2 FLIR image of the test structure surface under;

[0040] Figure 8 Schematic diagram of the relationship between the heat source surface temperature and the heat flux density at a flow rate of 80 ml / min for the high-power GaN device heat dissipation and integrated integrated structure of Example 1;

[0041] Fig. 9 is a schematic diagram of a GaN device with a first open microchannel fabricated on the back side of Example 2;

[0042] Fig.10 is a schematic structural diagram of a TSV adapter board of Example 3;

[0043] Fig.11 yes Fig.10 A top cross-sectional view along the a-a' direction;

[0044] Fig.12 It is a schematic diagram of the overall structure of a high-power GaN device heat dissipation and integrated integrated structure according to Example 3. DETAILED DESCRIPTION

[0045] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The various drawings of the present invention are only for illustration to make it easier to understand the present invention, and the specific proportions can be adjusted according to design requirements. The upper and lower relationships of the relative elements and the definitions of the front / back in the figures described in the text should be understood by those skilled in the art to refer to the relative positions of the components, so they can all be flipped to present the same components, which should all fall within the scope disclosed in this specification.

[0046] Example 1

[0047] A high-power GaN device heat dissipation and integrated integrated structure 1 Figure 1 As shown, it mainly includes a GaN device 000 , a TSV adapter plate 130 , a housing 210 , a circuit board 400 and other microelectronic chips 300 .

[0048] refer to Figure 2 The GaN device 000 includes a SiC or Si substrate, on which a first open microchannel 011 of a parallel groove type is provided. The minimum path between the active layer of the GaN device and the first open microchannel 011 of the substrate, that is, the thickness of the suspended GaN device layer is less than 100 microns, for example, 50 microns. The characteristic size of the parallel groove is 10-100 microns, and the characteristic size mentioned here refers to the width of the parallel groove. Preferably, the parallel groove is located directly below the gate finger of the GaN device 000, and the two are arranged in parallel.

[0049] refer to Figures 3 to 5 The TSV adapter board 130 is a high-resistance silicon substrate with a resistivity of ≥1000Ω·Cm. The upper and lower surfaces are provided with metal wiring layers 134, respectively. The upper surface is provided with a flow guide structure 137 and a pad 135 for wire bonding or flip-chip bonding. The body is provided with an interconnection structure extending in the thickness direction, an input microchannel 113 and an output microchannel 114. The input microchannel 113 is provided with a first outlet 113a and a first inlet 113b on the upper and lower surfaces of the TSV adapter board, respectively. The output microchannel 114 is provided with a second inlet 114a and a second outlet 114b on the upper and lower surfaces of the TSV adapter board, respectively, and the first inlet 113b and the second outlet 114b are located on the outside of the first outlet 113a and the second inlet 114a, respectively. More specifically, the calibers of the input microchannel 113 and the output microchannel 114 are gradually expanded in a step-by-step manner from the upper surface to the lower surface of the TSV adapter board, and are offset to the outside at the mutation point. In this embodiment, four layers of flow channels 111, 112, 121 and 122 are formed, and the first inlet 113b and the second outlet 114b are respectively located outside the first outlet 113a and the second inlet 114a by shifting the layers. The interconnection structure includes a through hole 131 penetrating the upper and lower surfaces of the high-resistance silicon substrate, a metal interconnection line 132 arranged in the through hole 131 and on the top and bottom surfaces, and a conformal cover insulating layer 133 located between the through hole 131 and the interconnection line 132.

[0050] Combination Figures 1 to 5 The GaN device 000 is disposed on the TSV adapter plate 130 , and both ends of the parallel grooves of the first open microchannel 011 are respectively connected to the first outlet 113 a and the second inlet 114 a through the guide structure 137 . The shell 210 is provided with a flow channel, which includes a third inlet 210a and a third outlet 210b provided on the bottom upper surface of the shell 210. The TSV adapter plate 130 is assembled in the shell 210 and the third inlet 210a is connected to the first inlet 113b, and the third outlet 210b is connected to the second outlet 114b, so that the fluid enters the input microchannel 113 through the third inlet 210a of the shell 210 through the first inlet 113b, and then enters the parallel groove of the first open microchannel 011 through the first outlet 113a through the guide structure 137, flows in the horizontal direction, and then flows through the guide structure 137 through the second inlet 114a to the output microchannel 114, and then flows from the second outlet 114b to the third outlet 210b back to the shell 210, forming a connected microchannel system.

[0051] The circuit board 400 is disposed on the top of the side wall of the housing 210 and is electrically connected to the TSV adapter board 130. Other microelectronic chips 300 or passive components are assembled on the TSV adapter board 130 by flip chip bonding or wire bonding technology.

[0052] refer to Figures 1 to 6 , the preparation method is described in detail below.

[0053] 1)GaN device 000

[0054] refer to Figure 2 , using photolithography and RIE etching processes to etch the first open microchannel 011 on the SiC or Si substrate on the back of the GaN device 000. The microchannel structure on the back substrate of the GaN device 000 is fabricated by photolithography in the form of a wafer, or the GaN device 000 can be temporarily bonded to an auxiliary wafer, and the reassembled GaN device wafer thus formed can be processed. Preferably, the steps for fabricating the microchannel structure on the back substrate of the GaN device 000 can also be directly embedded in the back thinning of the GaN device wafer, the etching of the grounding hole and the metallization process, and the inside of the microchannel can be metallized at the same time to form a metal layer 012, or it can be covered and protected during the metallization process without metallization.

[0055] 2) TSV adapter board 130: reference Figure 6 Combined with Figures 3 to 5 ,

[0056] 2.1) Provide a first high-resistance silicon wafer 110 and a second high-resistance silicon wafer 120 polished on both sides, with a resistivity of ≥1000Ω·cm, such as Figure 2 As shown, a pair of first holes 111 with a certain depth are made on the upper surface of the first high-resistance silicon wafer 110 by photolithography, deep silicon etching (DRIE), laser and other processes, serving as the microchannel outlet / inlet on the upper surface of the TSV adapter plate 110; a guide structure 137 is made on the upper surface of the first high-resistance silicon wafer 110 by the same process, corresponding to the first holes 111; a pair of second holes 112 are made on the lower surface of the first high-resistance silicon wafer 110, and the second holes 112 are connected to the first holes 111 in a one-to-one correspondence; a pair of third holes 121 with a certain depth are made on the upper surface of the second high-resistance silicon wafer 120, and a pair of fourth holes 122 are made on the lower surface of the second high-resistance silicon wafer 120, and the third holes 121 and the fourth holes 122 are connected in a one-to-one correspondence.

[0057] 2.2) The lower surface of the first high-resistance silicon wafer 110 and the upper surface of the second high-resistance silicon wafer 120 are connected by a wafer-level bonding process to form a TSV adapter plate 130, so that the second hole groove 112 of the first high-resistance silicon wafer 110 and the third hole groove 121 of the second high-resistance silicon wafer 120 are matched one by one, thereby forming an input microchannel 113 and an output microchannel 114, and the bonding process is silicon-silicon bonding, polymer bonding, gold-gold bonding, gold-tin bonding, copper-tin bonding, etc. The calibers of the first hole groove 111, the second hole groove 112, the third hole groove 121 and the fourth hole groove 122 are successively enlarged and successively offset to the outside, the first hole groove 111 forms the first outlet 113a and the second inlet 114a, and the fourth hole groove forms the first inlet 113b and the second outlet 114b.

[0058] 2.3) The TSV adapter plate 130 is thinned by mechanical thinning, grinding, chemical polishing and other processes to reduce the overall thickness of the substrate and reduce the process difficulty for the subsequent metallization of the interconnection through hole 131.

[0059] 2.4) The interconnection through hole 131 and the metal interconnection line 132 in and on the surface of the through hole 131 are made on the TSV adapter plate 130 by using photolithography and DRIE etching process or laser drilling technology; the interconnection through hole 131 can be embedded in the process of step 1 to step 3, or it can be made separately after completing the above steps; before the through hole 131 and the interconnection line 132, a conformal covering insulating layer 133 can be made on the inner surface and both surfaces of the through hole 131 by oxidation, LPCVD or PECVD and other technical means; the interconnection line 131 can be made by double-sided photoresist The method comprises the following steps: the copper electroplating process under protective conditions, specifically including the deposition of barrier layer and seed layer, the preparation of photoresist mask, copper electroplating, etc., and the copper electroplating on both sides can also be realized by combining photolithography wet etching process, specifically including the steps of deposition of barrier layer and seed layer, copper electroplating, the preparation of photoresist mask, wet etching, etc.; wherein the insulating layer 133 is one of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide, glass, polypropylene or polyparaxylene, the diffusion barrier layer is at least one of Ta, TaN and TiW, and the conductive metal layer is at least one of Cu, Al, Au and W;

[0060] The interconnection line 132 provides an electrical interconnection path that runs through the two surfaces of the TSV adapter board 130. The interconnection line 132 provides a planar wiring for electrical signal transmission. The through hole 131 and / or the interconnection line 132 can form a low-frequency electrical transmission path for transmitting power, and can also form a high-frequency transmission line such as a CPW line or a microstrip line.

[0061] Preferably, a gold layer is locally fabricated on the TSV adapter plate 130 to form a metal wiring layer 134 and a pad 135 of the same form as the area of ​​the chip to be assembled, so as to provide an assembly substrate for other microelectronic chips or passive components.

[0062] 3) At least a corresponding first patterned adhesive sealing layer 013 and a second patterned adhesive sealing layer 136 are made on the surface of the back substrate of the GaN device 000 and the surface of the TSV adapter plate 130, which can be achieved by patterned electroplating of Cu / Sn, Au / Sn, Ag / Sn solder or coating of organic materials such as BCB, or printing of glass paste, etc. The patterned adhesive sealing layer at least surrounds and closes the first outlet 113a and the second inlet 114a of the TSV adapter plate 130 and the first open microchannel 011 of the back substrate of the GaN device 000, forming a closed flow channel system.

[0063] 4) The GaN device 000 is aligned with its back side and mounted on the TSV adapter board 130 using the first patterned adhesive sealing layer 013 and the second patterned adhesive sealing layer 136 . The electrical signal of the GaN device 000 is wire-bonded to the pad 135 on the interconnection line 132 .

[0064] 5) assembling other microelectronic chips 300 in a part of the TSV adapter plate 134 by eutectic bonding or flip-chip bonding;

[0065] 6) Use conductive glue, solder, nano silver paste, etc. to assemble one side of the bonding body of the TSV adapter board 130 to the aluminum alloy shell 210, and make the third inlet 210a and the first inlet 113b sealed and connected, and the third outlet 210b and the second outlet 114b sealed and connected, and assemble the PCB circuit board 400 on the top of the side wall of the shell 210 to lead out the electrical signal of the TSV adapter board 130.

[0066] refer to Figures 7 and 8 The high-power GaN device heat dissipation and integrated integrated structure obtained in this embodiment is expected to achieve a heat flux density of up to 1000W / cm 2 The heat dissipation capacity of hot spots.

[0067] The assembly order of the GaN device 000 , the TSV adapter plate 130 , other microelectronic chips 300 or passive components, and the housing 210 may be adjusted according to the process temperature.

[0068] Example 2

[0069] refer to Fig. 9 In this embodiment, the first open microchannel 011 is a spoiler column type, and the characteristic size of the spoiler column is 10-100 microns, and the characteristic size here refers to the diameter of the spoiler column. The rest is referred to in Example 1.

[0070] Example 3

[0071] refer to Figures 10 to 12 The difference between this embodiment and embodiment 1 is that in step 2.2), in addition to making the first hole groove 111 and the guide structure 137 on the upper surface of the first high-resistance silicon wafer 110, a second open microchannel 118 with a certain depth is also made, and the second open microchannel 118 corresponds to the first open microchannel 011 of the GaN device 000 one by one; the cross-section of the microchannel bonding area on the surface of the second open microchannel 118 is larger than that of the first open microchannel 011 corresponding to the back substrate of the GaN device 000, so as to reduce the bonding difficulty between the back substrate of the GaN device 000 and the surface of the TSV adapter plate 130, and further improve the depth-to-width ratio of the microchannel.

[0072] Example 4

[0073] The difference between this embodiment and embodiment 1 is that in step 2.2), only one high-resistance silicon wafer is provided, and holes with a certain depth and connected are made on both sides of the high-resistance silicon wafer by double-sided photolithography, deep silicon etching (DRIE), laser and other processes as microchannel inlets / outlets, and the high-resistance silicon wafer constitutes a TSV adapter plate 130 to form a two-layer channel structure. That is, in this embodiment, only the first high-resistance silicon wafer 110 or the second high-resistance silicon wafer 120 is used to form the TSV adapter plate 130.

[0074] In addition, other multi-layer flow channel structures with more than 2 layers can also be set according to actual needs.

[0075] The above embodiments are only used to further illustrate a high-power GaN device heat dissipation and integrated integrated structure and manufacturing method of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention fall within the protection scope of the technical solution of the present invention.

Claims

1. A high-power GaN device heat dissipation and integrated integrated structure, characterized by: include A TSV adapter board, wherein the upper and lower surfaces of the TSV adapter board are respectively provided with metal wiring layers, the upper surface is provided with a flow guide structure, and the body is provided with an interconnection structure, an input microchannel and an output microchannel respectively extending in the thickness direction, the input microchannel is respectively provided with a first outlet and a first inlet on the upper and lower surfaces of the TSV adapter board, the output microchannel is respectively provided with a second inlet and a second outlet on the upper and lower surfaces of the TSV adapter board, and the first inlet and the second outlet are respectively located outside the first outlet and the second inlet; A GaN device is disposed on the TSV adapter plate, a first open microchannel is disposed on the back side of the substrate of the GaN device, and two sides of the first open microchannel in a horizontal direction are respectively connected to the first outlet and the second inlet through the guide structure; A housing, wherein the housing is provided with a flow channel, wherein the flow channel includes a third inlet and a third outlet provided on the bottom upper surface of the housing, wherein the TSV adapter plate is assembled in the housing, wherein the third inlet is in communication with the first inlet, and the third outlet is in communication with the second outlet; The circuit board is arranged on the top of the side wall of the housing and is electrically connected to the TSV adapter board.

2. The high-power GaN device heat dissipation and integration integrated structure according to claim 1, characterized in that: The distance between the bottom surface of the first open microchannel and the active layer of the device is less than 100 micrometers, and the characteristic size of the first open microchannel is 10-100 micrometers.

3. The high-power GaN device heat dissipation and integration integrated structure according to claim 1, characterized in that: The first open microchannel is of parallel groove type, spoiler column type or fin type.

4. The high-power GaN device heat dissipation and integrated integrated structure according to claim 1, characterized in that: The apertures of the input microchannel and the output microchannel are gradually enlarged in a step-by-step manner from the upper surface to the lower surface of the TSV adapter plate, and are offset to the outside at the step change position.

5. The high-power GaN device heat dissipation and integration integrated structure according to claim 1, characterized in that: The interconnection structure includes an interconnection line in the form of a CPW, microstrip line or TSV interconnection transmission line arranged outside the GaN device assembly area, and a conformal and continuous insulating layer is arranged between the interconnection line and the substrate of the TSV adapter plate.

6. The high-power GaN device heat dissipation and integration integrated structure according to claim 1, characterized in that: The upper surface of the TSV adapter board is also provided with at least one area for arranging other microelectronic chips and pads for wire bonding or flip-chip bonding.

7. The high-power GaN device heat dissipation and integration integrated structure according to claim 1, characterized in that: The upper surface of the TSV adapter plate is also provided with a second open microchannel corresponding to the first open microchannel.

8. The method for manufacturing the high-power GaN device heat dissipation and integrated integrated structure according to any one of claims 1 to 7, characterized in that The following steps are involved: 1) Etching a first open microchannel on the back side of the substrate of the GaN device; 2) Providing high-resistance silicon wafers as the substrate of the TSV adapter plate, making interconnection structures, input microchannels, output microchannels, flow guide structures and metal wiring layers; 3) A corresponding patterned adhesive sealing layer is formed on the substrate surface of the GaN device and the upper surface of the TSV adapter board, and the substrate of the GaN device is bonded to the TSV adapter board through the patterned adhesive sealing layer. The patterned adhesive sealing layer seals the first open microchannel and the first outlet and the second inlet, and the electrical signal of the GaN device is led out through bonding; 4) Assemble other microelectronic chips on the TSV adapter board through bonding; 5) Assemble the TSV adapter board on the bottom of the shell through low-temperature solder, nano silver paste or conductive glue, and make the third inlet sealed and connected with the first inlet, and the third outlet sealed and connected with the second outlet, and assemble the circuit board on the top of the shell side wall to lead out the electrical signal of the TSV adapter board.

9. The production method according to claim 8, characterized in that: In step 2), the steps of making the input microfluidic channel and the output microfluidic channel include: (1) providing a first high-resistance silicon wafer, forming a pair of first holes with a certain depth on the upper surface of the first high-resistance silicon wafer, and forming a pair of second holes connected to the first holes on the lower surface of the first high-resistance silicon wafer; (2) providing a second high-resistance silicon wafer, forming a pair of third holes with a certain depth on the upper surface of the second high-resistance silicon wafer, and forming a pair of fourth holes connected to the third holes on the lower surface of the second high-resistance silicon wafer; (3) aligning and bonding the first high-resistance silicon wafer and the second high-resistance silicon wafer so that the third holes and the second holes correspond to each other and fit together, wherein the first holes form the first outlet and the second inlet, and the fourth holes form the first inlet and the second outlet.

10. The production method according to claim 8, characterized in that: Step 2) further includes manufacturing a second open microchannel on the upper surface of the TSV adapter plate, wherein the second open microchannel corresponds to the first open microchannel.

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