Display device

Abstract

A display device comprises: a substrate, a metal layer arranged on the substrate, a first conductive layer including a lower pattern arranged on the metal layer, an active layer arranged on the first conductive layer, a second conductive layer arranged on the active layer and including a first gate electrode, a pixel electrode arranged on the second conductive layer, and an emission layer and a common electrode arranged on the pixel electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all the benefits of Korean Patent Application No. 10-2019-0040194, filed on April 5, 2019, and Korean Patent Application No. 10-2019-0076536, filed on June 26, 2019, which are hereby incorporated by reference in their entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a display device. Background Art

[0004] The display device displays images, and recently, light emitting diode displays have attracted attention as self-luminous displays.

[0005] The light emitting diode display has a self-emitting characteristic. Unlike a liquid crystal display ("LCD"), the light emitting diode display does not require a separate light source, so the light emitting diode display can have a reduced thickness and reduced weight. In addition, the light emitting diode display exhibits high quality characteristics such as low power consumption, high brightness, and high response speed.

[0006] Typically, a light emitting diode display includes a plurality of pixels, and each pixel includes a plurality of transistors and a light emitting element. The plurality of transistors are connected to a signal line and can transmit a driving current to the light emitting element. Each transistor can include an active pattern, and the active pattern includes a channel region and a conductive region.

[0007] The light emitting element includes an anode and a cathode, and the anode is connected to the transistor of the pixel so as to receive a driving current. Summary of the invention

[0008] Exemplary embodiments provide a display device having improved image quality by reducing the resistance of a predetermined signal passing through a metal layer while maintaining a thickness of a lower pattern less than a predetermined level.

[0009] Furthermore, exemplary embodiments provide a display device having a reduced non-display area in the display panel and having improved reliability in the non-display area.

[0010] An exemplary embodiment of the display device includes: a substrate; a metal layer disposed on the substrate; a first conductive layer disposed on the metal layer and including a lower pattern; an active layer disposed on the first conductive layer; a second conductive layer disposed on the active layer and including a first gate electrode; a pixel electrode disposed on the second conductive layer, and an emission layer and a common electrode disposed on the pixel electrode.

[0011] In exemplary embodiments, the metal layer may overlap the entire surface of the substrate.

[0012] In exemplary embodiments, an opening overlapping the active layer may be defined in the metal layer.

[0013] In an exemplary embodiment, a third conductive layer may be further included, the third conductive layer being disposed between the second conductive layer and the pixel electrode and including a common voltage line, a driving voltage line, and a data line.

[0014] In exemplary embodiments, the metal layer may include at least one of a first voltage metal layer connected to the driving voltage line and a second voltage metal layer connected to the common voltage line.

[0015] In exemplary embodiments, the metal layer may include the first voltage metal layer and the second voltage metal layer, and the first voltage metal layer and the second voltage metal layer may be spaced apart from each other.

[0016] In exemplary embodiments, openings overlapping the active layer may be defined in the first voltage metal layer and the second voltage metal layer.

[0017] In an exemplary embodiment, the data line may include a first data line, a second data line and a third data line, and the metal layer may include at least one of a first sub-metal layer connected to the first data line, a second sub-metal layer connected to the second data line, and a third sub-metal layer connected to the third data line.

[0018] In exemplary embodiments, the metal layer may include the first sub-metal layer, the second sub-metal layer, and the third sub-metal layer, and an opening overlapping the active layer may be defined in the first sub-metal layer, the second sub-metal layer, and the third sub-metal layer.

[0019] In exemplary embodiments, the first sub-metal layer, the second sub-metal layer, and the third sub-metal layer may be spaced apart from each other.

[0020] In an exemplary embodiment, the display device in the exemplary embodiment includes: a substrate; a metal layer disposed on the substrate; a first conductive layer disposed on the metal layer and including a lower pattern; an active layer disposed on the first conductive layer; a second active layer disposed on the active layer and including a first gate electrode; a pixel electrode disposed on the second conductive layer; and an emission layer and a common electrode disposed on the pixel electrode, wherein the thickness of the metal layer is approximately 6000 angstroms to approximately 10000 angstroms.

[0021] An exemplary embodiment of a display device includes: a substrate including a display area and a non-display area; a light emitting element disposed in the display area; a gate driver disposed in the non-display area and including a plurality of transistors; and a first metal layer overlapping the plurality of transistors.

[0022] In an exemplary embodiment, the display device may further include a second metal layer overlapping the display area and disposed in the same layer as the first metal layer.

[0023] In exemplary embodiments, the first metal layer may have an overall plate shape overlapping the plurality of transistors arranged in a matrix direction.

[0024] In exemplary embodiments, each of the plurality of transistors may include a semiconductor layer, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer.

[0025] In an exemplary embodiment, the display device may include: a gate line including the gate electrode; a first signal line including the source electrode; and a second signal line including the drain electrode, the gate line, the first signal line and the second signal line extending in a first direction, and the semiconductor layer may extend in a second direction different from the first direction.

[0026] In an exemplary embodiment, the display device may include a plurality of semiconductor layers repeatedly disposed along the first direction, and the first metal layer may overlap the plurality of semiconductor layers.

[0027] In an exemplary embodiment, the display device may include a plurality of semiconductor layers repeatedly disposed along the first direction, and the first metal layer may include a plurality of first auxiliary metal layers respectively overlapping the plurality of semiconductor layers.

[0028] In exemplary embodiments, each of the plurality of first auxiliary metal layers may extend in the second direction in a plan view.

[0029] In exemplary embodiments, the plurality of first auxiliary metal layers may be repeatedly disposed along the first direction.

[0030] In exemplary embodiments, the plurality of auxiliary metal layers may be spaced apart from each other.

[0031] In exemplary embodiments, a width of one of the plurality of first auxiliary metal layers may be greater than a width of one of the plurality of semiconductor layers.

[0032] An exemplary embodiment of a display device includes: a substrate, which includes a display area and a non-display area; a light-emitting element, which is arranged in the display area; a gate driver, which includes a plurality of first transistors arranged in the non-display area; and a first metal layer overlapping with at least some of the plurality of first transistors, each of the plurality of first transistors includes a gate electrode, a semiconductor layer, a source electrode and a drain electrode, and a width of the first metal layer is greater than a width of the semiconductor layer.

[0033] In exemplary embodiments, the first metal layer may be electrically connected to the gate electrode.

[0034] In an exemplary embodiment, the first metal layer may have a thickness of about 1000 angstroms to about 4000 angstroms.

[0035] In exemplary embodiments, a planar area of ​​the first metal layer may be greater than a planar area of ​​the semiconductor layer.

[0036] In exemplary embodiments, the semiconductor layer may completely overlap the first metal layer.

[0037] In an exemplary embodiment, a second transistor disposed on the display area and a second metal layer overlapping the second transistor may be further included.

[0038] In exemplary embodiments, a width of the second metal layer may be greater than a width of the semiconductor layer included in the second transistor.

[0039] In exemplary embodiments, the plurality of first transistors may be electrically connected to each other.

[0040] In an exemplary embodiment, the first metal layer may include a plurality of first auxiliary metal layers extending along the second direction while being disposed to be spaced apart along the first direction, and the plurality of auxiliary metal layers may be applied at the same voltage.

[0041] In exemplary embodiments, a display device having improved image quality may be provided by reducing resistance of a signal passing through a metal layer while maintaining a thickness of a lower pattern less than a predetermined level.

[0042] Furthermore, in exemplary embodiments, a display device in which the non-display area is reduced in the display panel and reliability is improved in the non-display area may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other exemplary embodiments, advantages, and features of the present disclosure will become more apparent by describing exemplary embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0044] Figure 1 is a circuit diagram of an exemplary embodiment of one pixel of a display device according to the present invention.

[0045] Figure 2 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0046] Figure 3 is a plan view of an exemplary embodiment of a pixel electrode layer and a plurality of data lines of a display device according to the present invention.

[0047] Figure 4 It is taken along line IVa-IVb Figure 2 A cross-sectional view of a display device shown in FIG.

[0048] Figure 5 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0049] Fig. 6A is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, and Figure 6B yes Fig. 6A Cross-sectional view of a local area.

[0050] Figure 7 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0051] Figure 8 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0052] Fig. 9 It is taken along line XIIIa-XIIIb Figure 8 A cross-sectional view of a display device shown in FIG.

[0053] Fig.10 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0054] Fig.11 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0055] Fig.12 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0056] Fig.13 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0057] Fig.14 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0058] Fig.15 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0059] Fig.16 is a view schematically showing an exemplary embodiment of a configuration of a display device according to the present invention.

[0060] Fig.17 is a block diagram of an exemplary embodiment of a gate driver of a display device according to the present invention.

[0061] Fig.18 is a circuit diagram of an exemplary embodiment of one stage of a gate driver of a display device according to the present invention.

[0062] Fig.19 is a schematic top view of an exemplary embodiment of a display device.

[0063] Fig. 20A , Fig. 20B and Fig. 20C Cross-sectional views of exemplary embodiments of a display area and a non-display area, respectively.

[0064] Fig.21 It is a partial top view of the non-display area.

[0065] Fig.22A , Fig. 22B and Fig. 22C Cross-sectional views of exemplary embodiments of a display area and a non-display area, respectively.

[0066] Fig.23 is a partial top view of an exemplary embodiment of a non-display area. DETAILED DESCRIPTION

[0067] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention.

[0068] Description of parts not related to the present invention is omitted, and the same reference numerals denote the same elements throughout the specification.

[0069] In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present invention is not limited to the sizes and thicknesses shown in the drawings. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0070] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in this specification, the term "on..." or "above" refers to being located on or below an object part, and does not necessarily mean being located on the upper side of the object part based on the direction of gravity.

[0071] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0072] Furthermore, in this specification, the phrase "in a plan view" means observing an object portion from the top, and the phrase "in a cross section" means a cross section cutting the object portion vertically from the side.

[0073] As used herein, the terms "about" or "approximately" include the stated value and an average value determined by one of ordinary skill in the art to be within an acceptable range of deviation for the particular value, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0074] Throughout the specification and the appended claims, a plan view refers to a view when observing a surface parallel to two directions intersecting each other (e.g., direction DR1 and direction DR2), and a cross-sectional view is a view when observing a surface cut in a direction perpendicular to the surface parallel to direction DR1 and direction DR2 (e.g., direction DR3). In addition, overlapping two constituent elements means that the two constituent elements overlap in direction DR3 (e.g., a direction perpendicular to the upper surface of the substrate) unless otherwise specified.

[0075] Now, refer to Figure 1 One pixel of a display device in the exemplary embodiment is described. Figure 1 is a circuit diagram showing an exemplary embodiment of one pixel PX of a display device according to the present invention.

[0076] The display device in the exemplary embodiment according to the present invention may include a plurality of pixels PX, and one pixel PX may include a plurality of transistors T1, T2 and T3, a capacitor Cst and at least one light emitting diode ("LED") ED as a light emitting element. In the illustrated exemplary embodiment, an example in which the pixel PX includes a single LED ED is mainly described.

[0077] The plurality of transistors T1, T2 and T3 include a first transistor T1, a second transistor T2 and a third transistor T3. A source electrode and a drain electrode described below are used to distinguish two electrodes provided on opposite sides of a channel of each transistor T1, T2 and T3, and the two terms may be interchanged.

[0078] A gate electrode G1 of the first transistor T1 is connected to one end of the capacitor Cst, a source electrode S1 of the first transistor T1 is connected to a driving voltage line transmitting a driving voltage ELVDD, and a drain electrode D1 of the first transistor T1 is connected to an anode of the LED ED and the other end of the capacitor Cst. The first transistor T1 receives the data voltage DAT according to a switching operation of the second transistor T2, and can provide a driving current to the LED ED depending on a voltage stored in the capacitor Cst.

[0079] The gate electrode G2 of the second transistor T2 is connected to the first scan line transmitting the first scan signal SC, the source electrode S2 of the second transistor T2 is connected to the data line transmitting the data voltage DAT or the reference voltage, and the drain electrode D2 of the second transistor T2 is connected to one end of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 can be turned on depending on the first scan signal SC to transmit the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 and one end of the capacitor Cst.

[0080] The gate electrode G3 of the third transistor T3 is connected to the second scan line transmitting the second scan signal SS, the source electrode S3 of the third transistor T3 is connected to the other end of the capacitor Cst, the drain electrode D1 of the first transistor T1 and the anode of the LED ED, and the drain electrode D3 of the third transistor T3 is connected to the initialization voltage line transmitting the initialization voltage INIT. The third transistor T3 can be turned on depending on the second scan signal SS to transmit the initialization voltage INIT to the anode of the LED ED and the other end of the capacitor Cst, thereby initializing the voltage of the anode of the LED ED.

[0081] One end of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other end is connected to the source electrode S3 of the third transistor T3 and the anode of the LED ED. The cathode of the LED ED is connected to a common voltage line transmitting a common voltage ELVSS.

[0082] The LED ED may emit light depending on the driving current generated by the first transistor T1.

[0083] We will now describe Figure 1An exemplary embodiment of the operation of the circuit shown in , in particular, an exemplary embodiment of the operation during one frame will be described. In this example, it is described that the first transistor T1, the second transistor T2, and the third transistor T3 are N-channel transistors, but they are not limited thereto.

[0084] If a frame starts, in the initialization period, a high-level first scan signal SC and a high-level second scan signal SS are provided to turn on the second transistor T2 and the third transistor T3. The reference voltage from the data line is provided to the gate electrode G1 of the first transistor T1 and one end of the capacitor Cst through the turned-on second transistor T2, and the initialization voltage INIT is provided to the drain electrode D1 of the first transistor T1 and the anode of the LED ED through the turned-on third transistor T3. Therefore, during the initialization period, the drain electrode D1 of the first transistor T1 and the anode of the LED ED are initialized to the initialization voltage INIT. At this time, the capacitor Cst stores the voltage difference between the reference voltage and the initialization voltage INIT.

[0085] Next, in the sensing period, when the second scanning signal SS becomes a low level in the state where the first scanning signal SC of the high level is maintained, the second transistor T2 maintains the on state, and the third transistor T3 is turned off. The gate electrode G1 of the first transistor T1 and one end of the capacitor Cst maintain the reference voltage through the turned-on second transistor T2, and the drain electrode D1 of the first transistor T1 and the anode of the LED ED are disconnected from the initialization voltage INIT through the turned-off third transistor T3. Therefore, when the current flows from the source electrode S1 to the drain electrode D1, the first transistor T1 is turned off, and then the voltage of the drain electrode D1 becomes the "reference voltage Vth". Vth represents the threshold voltage of the first transistor T1. At this time, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the capacitor Cst, and the sensing of the threshold voltage Vth of the first transistor T1 is completed. By generating a data signal compensated by reflecting the sensed characteristic information during the sensing period, the characteristic deviation of the first transistor T1 that may be different for each pixel can be externally compensated.

[0086] Next, in the data input period, when the first scan signal SC of a high level is provided and the second scan signal SS of a low level is provided, the second transistor T2 is turned on and the third transistor T3 is turned off. The data voltage DAT from the data line is provided to one end of the capacitor Cst and the gate electrode G1 of the first transistor T1 via the turned-on second transistor T2. In this case, the anode of the LED ED and the drain electrode D1 of the first transistor T1 can substantially maintain the potential in the sensing period through the first transistor T1 in the turned-off state.

[0087] Next, in the light emitting period, the first transistor T1 turned on by the data voltage DAT transmitted to the gate electrode G1 generates a driving current according to the data voltage DAT, and the LED ED may emit light by the driving current.

[0088] Now refer to Figures 2 to 4 and Figure 1 A detailed structure of a display device according to an exemplary embodiment of the present invention is described together. Figure 2 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, Figure 3 is a plan view of an exemplary embodiment of a pixel electrode layer and a plurality of data lines of a display device according to the present invention, and Figure 4 It is taken along line IVa-IVb Figure 2 A cross-sectional view of the display device shown.

[0089] like Figure 2 As shown in FIG. 1 , each of the plurality of pixels PX1, PX2, and PX3 may be represented by a pixel having a Figure 1 Parts or regions of a plurality of transistors T1 , T2 , and T3 and a capacitor Cst among constituent elements included in one pixel PX shown in FIG.

[0090] like Figure 4 As shown in , the display device in an exemplary embodiment may include a substrate 110. In an exemplary embodiment, the substrate 110 may include an insulating material such as glass, plastic, etc., and may have flexibility.

[0091] The metal layer 111 may be disposed on the substrate 110. In an exemplary embodiment, the metal layer 111 may overlap the entire surface of the substrate 110.

[0092] In an exemplary embodiment, for example, the metal layer 111 may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys of these metals or metal-like materials. The metal layer 111 may include a single layer or multiple layers.

[0093] In an exemplary embodiment, for example, the thickness of the metal layer 111 may be about 6000 angstroms to about 10000 angstroms. The metal layer 111 may have a considerable thickness. As the thickness of the metal layer 111 increases, the performance of the transistor included in the pixel may be better improved and the image quality may be improved. Even when the thickness of the metal layer 111 increases, the metal layer 111 does not have a step, so that the formation of other conductive layers may be facilitated and the reliability may be improved.

[0094] The insulating layer 112 may be disposed on the metal layer 111. The insulating layer 112 may include an inorganic insulating material, an organic insulating material, or both. The insulating layer 112 may control the formation of capacitance between the metal layer 111 and another conductive layer.

[0095] Next, see Figure 2 , on the insulating layer 112, a first conductive layer (115, 170a) including a lower pattern 115 and a transverse common voltage line 170a may be disposed. Each lower pattern 115 may be disposed in each pixel PX1, PX2, and PX3. The transverse common voltage line 170a may extend substantially in the first direction DR1. The lower pattern 115 may include various conductive metal or semiconductor materials having equivalent conductive properties.

[0096] like Figure 4 As shown in FIG. 1 , the buffer layer 120 of the insulating layer may be disposed on the first conductive layer ( 115 , 170 a ).

[0097] An active layer (130a, 130b, and 130c) (also referred to as "multiple active layers") including a plurality of active patterns 130a, 130b, and 130c may be disposed on the buffer layer 120. The active patterns 130a, 130b, and 130c disposed in the respective pixels PX1, PX2, and PX3 may include channel regions 134a, 134b, and 134c forming channels of the plurality of transistors T1, T2, and T3 and conductive regions connected thereto. The conductive region of each of the active patterns 130a, 130b, and 130c may include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c of the respective transistors T1, T2, and T3.

[0098] In each of the pixels PX1, PX2, and PX3, the plurality of active patterns 130a, 130b, and 130c may be spaced apart from each other, but are not limited thereto. In an exemplary embodiment, for example, the active pattern 130a and the active pattern 130c may be connected to each other. Figure 2 An example is shown in which the active pattern 130 a and the active pattern 130 c are connected to each other.

[0099] In exemplary embodiments, the active layer may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

[0100] The insulating pattern 144 of the first insulating layer may be disposed on the active layer. The insulating pattern 144 may overlap with the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c, and may be disposed on the channel regions 134a, 134b, and 134c. The insulating pattern 144 may not substantially overlap with the conductive regions of the active patterns 130a, 130b, and 130c.

[0101] The second conductive layer ( 151 , 152 , 155 , 154 b , and 154 c ) may be disposed on the insulating pattern 144 .

[0102] The second conductive layer (151, 152, 155, 154b and 154c) may include a first scan line 151 for transmitting the above-mentioned first scan signal SC, a second scan line 152 for transmitting the second scan signal SS, a driving gate electrode 155, a second gate electrode 154b and a third gate electrode 154c. The gate electrode G1, the gate electrode G2 and the gate electrode G3 in the above-mentioned circuit diagram may respectively correspond to the first gate electrode 154a, the second gate electrode 154b and the third gate electrode 154c included in the driving gate electrode 155. The driving gate electrode 155 may also be referred to as a first gate electrode.

[0103] The first scan line 151 and the second scan line 152 may extend in the first direction DR1. The first scan line 151 and the second scan line 152 may be disposed at the top and the bottom of a group of the plurality of pixels PX1, PX2, and PX3, respectively.

[0104] Each driving gate electrode 155 may be disposed corresponding to each pixel PX1, PX2, and PX3. The driving gate electrode 155 disposed at each pixel PX1, PX2, and PX3 may include a first gate electrode 154a protruding upward or downward and a protrusion 155a protruding downward or upward. The first gate electrode 154a intersects the active pattern 130a and overlaps the channel region 134a of the active pattern 130a.

[0105] A plurality of second gate electrodes 154b corresponding to the plurality of pixels PX1, PX2, and PX3 are connected to each other to integrally extend in the second direction DR2, and are connected to the first scan line 151. The second gate electrode 154b intersects the active pattern 130b of each pixel PX1, PX2, and PX3, and overlaps the channel region 134b of the active pattern 130b.

[0106] A plurality of third gate electrodes 154c corresponding to the plurality of pixels PX1, PX2, and PX3 are connected to each other to integrally extend in the second direction DR2, and are connected to the second scan line 152. The third gate electrode 154c intersects the active pattern 130c of each pixel PX1, PX2, and PX3, and overlaps the channel region 134c of the active pattern 130c.

[0107] The second conductive layer ( 151 , 152 , 155 , 154 b , and 154 c ) may further include a conductive pattern 150 a overlapping a common voltage line 170 to be described later.

[0108] The second insulating layer 160 may be disposed on the second conductive layer ( 151 , 152 , 155 , 154 b , and 154 c ). A plurality of contact holes ( 60 , 61 , 62 , 63 a , 63 b , 64 , 65 , 66 , and 68 ) may be defined in the buffer layer 120 and / or the second insulating layer 160 .

[0109] The third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178) may be disposed on the second insulating layer 160. The third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178) may include a plurality of data lines 171a, 171b, and 171c, a driving voltage line 172, a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175, and a plurality of connection members 178 based on a group of a plurality of pixels PX1, PX2, and PX3.

[0110] The common voltage line 170 may be electrically connected to the lateral common voltage line 170a through the contact hole 60 of the second insulating layer 160. The conductive pattern 150a of the second conductive layer (151, 152, 155, 154b, and 154c) is electrically connected to the common voltage line 170 through the contact hole 60a of the second insulating layer 160, thereby reducing the resistance of the common voltage line 170. In another exemplary embodiment, the conductive pattern 150a may be omitted.

[0111] The driving voltage line 172 is electrically connected to the source region 133 a of the active pattern 130 a through the contact hole 61 of the second insulating layer 160 .

[0112] In addition, the driving voltage line 172 can be electrically connected to the metal layer 111 through the contact hole 59 penetrating the second insulating layer 160, the buffer layer 120 and the insulating layer 112. That is, the metal layer 111 can reduce the signal resistance caused by the driving voltage line 172 while being electrically connected to the driving voltage line 172.

[0113] Moreover, since the metal layer 111 is provided on the entire surface of the substrate 110, it can have a considerable thickness without the burden of a step. As the thickness increases, the signal resistance due to the metal layer 111 can be easily reduced. In addition, since the metal layer 111 can be provided without a separate mask, the manufacturing process can be simplified and the cost and time required for the process can be reduced.

[0114] The initialization voltage line 173 is electrically connected to the drain region 135 c of the active pattern 130 c through the contact hole 63 a of the second insulating layer 160 .

[0115] The plurality of data lines 171a, 171b, and 171c may be arranged adjacent to each other in the first direction DR1. Other configurations of the third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178) may not be disposed between the plurality of data lines 171a, 171b, and 171c. Each of the data lines 171a, 171b, and 171c is electrically connected to the source region 133b of the active pattern 130b through the contact hole 64 of the second insulating layer 160. Figure 2 and Figure 3 As shown in FIG. 1 , each of the data lines 171 a , 171 b , and 171 c may be bent at least one.

[0116] One capacitor electrode 175 may be provided at each pixel PX1, PX2, and PX3. In a plan view, the capacitor electrode 175 may be provided between the driving voltage line 172 and each of the data lines 171a, 171b, and 171c. The capacitor electrode 175 may overlap with the corresponding driving gate electrode 155, and the second insulating layer 160 is located therebetween to form a capacitor Cst. The driving gate electrode 155 may also be referred to as a first capacitor electrode, and the capacitor electrode 175 may also be referred to as a second capacitor electrode.

[0117] The capacitor electrode 175 is electrically connected to the drain region 135a of the active pattern 130a through the contact hole 62 of the second insulating layer 160, and is electrically connected to the source region 133c and the active pattern 130c through the contact hole 63b of the second insulating layer 160. In addition, the capacitor electrode 175 is electrically connected to the lower pattern 115 through the contact hole 68 of the second insulating layer 160 and the buffer layer 120. For contact between the capacitor electrode 175 and the drain region 135a of the active pattern 130a, an opening 55a overlapping the contact hole 62 is defined in the driving gate electrode 155, so that the driving gate electrode 155 may have a shape surrounding the periphery of the contact hole 62, but is not limited thereto.

[0118] The connection member 178 is electrically connected to the drain region 135b of the active pattern 130b through the contact hole 65 in each of the pixels PX1, PX2 and PX3, and is electrically connected to the protrusion 155a of the driving gate electrode 155 through the contact hole 66, and as a result, the drain region 135b of the active pattern 130b and the protrusion 155a of the driving gate electrode 155 can be electrically connected to each other.

[0119] In a plan view, the data lines 171a, 171b, and 171c, the driving voltage line 172, the common voltage line 170, and the initialization voltage line 173 may respectively extend substantially along the second direction DR2 so as to intersect the first scan line 151 and the second scan line 152. A plurality of data lines 171a, 171b, and 171c, the driving voltage line 172, and the initialization voltage line 173 may be disposed between two adjacent common voltage lines 170.

[0120] Figure 2 A plurality of pixels PX1, PX2, and PX3 of a group shown in FIG. 1 may be arranged adjacent to each other in the second direction DR2, and may be repeatedly disposed in the first direction DR1 and the second direction DR2. A common voltage line 170 may be disposed on both left and right sides of the plurality of pixels PX1, PX2, and PX3, and a first scan line 151 and a second scan line 152 may be disposed on upper and lower sides, respectively.

[0121] When one repetition group of the plurality of pixels PX1 , PX2 , and PX3 includes three pixels PX1 , PX2 , and PX3 , three data lines 171 a , 171 b , and 171 c , one driving voltage line 172 , and one initialization voltage line 173 may be disposed between two adjacent common voltage lines 170 .

[0122] In an exemplary embodiment, at least one of the first conductive layer (115 and 170a), the second conductive layer (151, 152, 155, 154b and 154c) and the third conductive layer (171a, 171b, 171c, 172, 170, 173, 175 and 178) may include at least one of a metal such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta) and alloys thereof. Each of the first conductive layer (115 and 170a), the second conductive layer (151, 152, 155, 154b and 154c), and the third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178) may include a single layer or multiple layers. In an exemplary embodiment, the third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178) may have a multi-layer structure including, for example, a lower layer including titanium and an upper layer including copper.

[0123] The first transistor T1 includes a channel region 134a, source and drain regions 133a and 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 is electrically connected to the driving voltage line 172 to receive the driving voltage.

[0124] The lower pattern 115 corresponding to the first transistor T1 overlaps the channel region 134a of the first transistor T1 between the channel region 134a and the substrate 110 to prevent external light from reaching the channel region 134a, thereby reducing leakage current and characteristic degradation. The lower pattern 115 is electrically connected to the drain region 135a of the first transistor T1 through the capacitor electrode 175.

[0125] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 of each pixel PX1, PX2, and PX3 is electrically connected to the data lines 171a, 171b, and 171c to receive a data voltage or a reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a through the driving gate electrode 155.

[0126] The third transistor T3 includes a channel region 134 c , a source region 133 c , a drain region 135 c , and a third gate electrode 154 c . The drain region 135 c of the third transistor T3 may receive an initialization voltage from the lateral initialization voltage line 153 .

[0127] A third insulating layer 180 may be disposed on the third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178). A plurality of contact holes (71a, 72a, 73a, 74a, 75a, 76a, and 77a) are defined in the third insulating layer 180 on the third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178).

[0128] The fourth conductive layer may be disposed on the third insulating layer 180. The fourth conductive layer may include a plurality of conductive patterns having a planar shape substantially similar to the conductive patterns of the third conductive layers (171a, 171b, 171c, 172, 170, 173, 175, and 178) (e.g., data lines 171a, 171b, and 171c, driving voltage lines 172, common voltage lines 170, initialization voltage lines 173, capacitor electrodes 175, and connection members 178) disposed below the fourth conductive layer and may be electrically connected to the conductive patterns of the corresponding third conductive layers (171a, 171b, 171c, 172, 170, 173, 175, and 178).

[0129] In an exemplary embodiment, for example, the data lines 171a, 171b and 171c can be electrically connected to the corresponding conductive patterns set in the fourth conductive layer through the contact holes 74a, 75a and 76a, respectively, the driving voltage line 172 can be electrically connected to the corresponding conductive pattern 183a set in the sixth conductive layer through the contact hole 71a, the common voltage line 170 can be electrically connected to the corresponding conductive pattern set in the fourth conductive layer through the contact hole 72a, the initialization voltage line 173 can be electrically connected to the corresponding conductive pattern set in the fourth conductive layer through the contact hole 73a, and the capacitor electrode 175 can be electrically connected to the corresponding conductive pattern 183b set in the fourth conductive layer through the contact hole 77a.

[0130] The conductive pattern of the fourth conductive layer transmits the same voltage as that of the connected third conductive layer (171a, 171b, 171c, 172, 170, 173, 175, and 178), thereby reducing resistance. In another exemplary embodiment, the fourth conductive layer may be omitted.

[0131] The fourth insulating layer 181 may be disposed on the fourth conductive layer. A contact hole 80 may be defined in the fourth insulating layer 181 on the conductive pattern 183 b connected to the capacitor electrode 175 , and a contact hole 81 may be defined in the fourth insulating layer 181 on the common voltage line 170 .

[0132] A fifth conductive layer (190a, 190b, 190c, and 190d) including a plurality of ohmic contacts 190a, 190b, 190c, and 190d may be disposed on the fourth insulating layer 181. In an exemplary embodiment, the fifth conductive layer (190a, 190b, 190c, and 190d) may be omitted.

[0133] Each ohmic contact (or each contact member) 190a, 190b, and 190c may be provided in each pixel PX1, PX2, and PX3, and contact and be electrically connected to the corresponding conductive pattern 183b through the contact hole 80. Therefore, each ohmic contact (or each contact member) 190a, 190b, and 190c may be electrically connected to the capacitor electrode 175, and the capacitor electrode 175 is electrically connected to the conductive pattern 183b.

[0134] The ohmic contact (or contact member) 190 d may make contact with and be electrically connected to the common voltage line 170 through the contact hole 81 .

[0135] Ohmic contacts 190a, 190b, 190c, and 190d can improve the adhesion between the conductive pattern of the fourth conductive layer in contact and another conductive layer, respectively, and prevent oxidation of the fourth conductive layer. In particular, when the fourth conductive layer includes copper, oxidation of copper can be prevented. To this end, the fifth conductive layer (190a, 190b, 190c, and 190d) may include a conductive material that can prevent corrosion of the fourth conductive layer, for example, when the fourth conductive layer includes copper, a conductive material that prevents corrosion of copper by covering the fourth conductive layer. In an exemplary embodiment, the fifth conductive layer (190a, 190b, 190c, and 190d) may include a conductive material, such as a metal oxide, such as indium tin oxide ("ITO") or indium zinc oxide ("IZO").

[0136] The fifth insulating layer 182 may be disposed on the fifth conductive layer (190a, 190b, 190c, and 190d). A contact hole 83 may be defined in the fifth insulating layer 182 on each of the ohmic contacts (or contact members) 190a, 190b, and 190c.

[0137] In the plan view and the cross-sectional view, the center of the contact hole 83 may not match the center of the contact hole 80. In the plan view, the contact hole 83 and the contact hole 80 may not overlap each other or may partially overlap each other.

[0138] The contact hole 83 and the contact hole 80 each overlap the corresponding ohmic contact 190 a , 190 b , and 190 c of each pixel PX1 , PX2 , and PX3 .

[0139] In an exemplary embodiment, for example, the insulating layer 112, the buffer layer 120, the first insulating layer 121 including the insulating pattern 144 (refer to Fig.15 ), at least one of the second insulating layer 160, the third insulating layer 180, the fourth insulating layer 181 and the fifth insulating layer 182 may include silicon nitride (SiN x ), silicon oxide (SiO x In an exemplary embodiment, the fifth insulating layer 182 may include an inorganic insulating material such as polyimide, an acrylic-based polymer, a siloxane-based polymer, etc., and may have a substantially flat upper surface.

[0140] On the fifth insulating layer 182, a pixel electrode layer (191a, 191b, and 191c) including a plurality of pixel electrodes 191a, 191b, and 191c may be disposed as a sixth conductive layer.

[0141] Reference Figure 2 and Figure 3, a plurality of pixels PX1, PX2 and PX3 (or the first transistors T1 of the plurality of pixels PX1, PX2 and PX3) repeated in a plan view are arranged along the second direction DR2, and a plurality of pixel electrodes 191a, 191b and 191c corresponding to the pixels PX1, PX2 and PX3, respectively, may be arranged to be substantially adjacent to each other in the first direction DR1. The arrangement and structure of the pixels PX1, PX2 and PX3 and the pixel electrodes 191a, 191b and 191c corresponding thereto are not limited thereto. The plane size and shape of the pixel electrodes 191a, 191b and 191c may vary, but are not limited thereto.

[0142] A plurality of pixel electrodes 191a, 191b, and 191c may be electrically connected to ohmic contacts (or contact members) 190a, 190b, and 190c electrically connected to the capacitor electrode 175, respectively, through the contact holes 83 of the fifth insulating layer 182. Each pixel electrode 191a, 191b, and 191c is electrically connected to the drain region 135a of the first transistor T1 via the ohmic contacts (or contact members) 190a, 190b, and 190c, the conductive pattern 183b, and the capacitor electrode 175, thereby receiving a voltage from the first transistor T1.

[0143] In an exemplary embodiment, for example, the pixel electrode 191 a may be connected to the first transistor T1 of the pixel PX1 , the pixel electrode 191 b may be connected to the first transistor T1 of the pixel PX2 , and the pixel electrode 191 c may be connected to the first transistor T1 of the pixel PX3 .

[0144] The pixel electrodes 191a, 191b, and 191c may include a semi-transmissive conductive material or a reflective conductive material.

[0145] The sixth insulating layer 350 may be disposed on the fifth insulating layer 182. Openings 355a, 355b, and 355c are defined in the sixth insulating layer 350 on the pixel electrodes 191a, 191b, and 191c, respectively.

[0146] The sixth insulating layer 350 may include an organic insulating material such as a polyacrylate-based resin, a polyimide-based resin, or the like.

[0147] The emission layer 370 may be disposed in the sixth insulating layer 350 and the pixel electrode layer. The emission layer 370 may include a portion disposed in the openings 355a, 355b, and 355c of the sixth insulating layer 350. The emission layer 370 may include an organic emission material or an inorganic emission material. As shown, the emission layer 370 may include a portion disposed above the sixth insulating layer 350, and the portion on at least a portion of the sixth insulating layer 350 may not be covered by the emission layer 370.

[0148] A contact hole 82 may be defined in the sixth insulating layer 350 and the emission layer 370 on the ohmic contact 190 d .

[0149] The common electrode 270 is disposed over the emission layer 370. The common electrode 270 may be continuously disposed over the plurality of pixels PX1, PX2, and PX3. The common electrode 270 may be electrically connected to the common voltage line 170 by contacting the ohmic contact 190d through the contact hole 82, thereby receiving a common voltage.

[0150] The common electrode 270 may include a conductive transparent material.

[0151] The pixel electrodes 191a, 191b and 191c of each pixel PX1, PX2 and PX3, the emission layer 370 and the common electrode 270 together form an LED ED, and one of the pixel electrodes 191a, 191b and 191c and the common electrode 270 becomes a cathode and the other becomes an anode. Previously, an example in which the pixel electrodes 191a, 191b and 191c are anodes was described.

[0152] In a plan view, a region defining the openings 355 a , 355 b , and 355 c of the sixth insulating layer 350 may define an emission region of each of the pixels PX1 , PX2 , and PX3 .

[0153] Reference Figure 2 and Figure 3 , a plurality of openings 355a, 355b, and 355c respectively corresponding to a plurality of pixel electrodes 191a, 191b, and 191c respectively connected to a group of a plurality of pixels PX1, PX2, and PX3 may be arranged adjacent to each other in the first direction DR1.

[0154] Next, refer to Figures 5 to 7 A display device in an exemplary embodiment is described. Figure 5 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, Fig. 6A is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, Figure 6B yes Fig. 6A A cross-sectional view of a local area, and Figure 7 2 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention. Descriptions of constituent elements that are the same as those described above are omitted.

[0155] Reference Figure 5In an exemplary embodiment, openings 111-1, 111-2, and 111-3 overlapping the active layer may be defined in the metal layer 111. In detail, a first opening 111-1 overlapping the first active pattern 130a, a second opening 111-2 overlapping the second active pattern 130b, and a third opening 111-3 overlapping the third active pattern 130a may be defined in the metal layer 111.

[0156] The metal layer 111 in the exemplary embodiment may be electrically connected to the driving voltage line 172 , but it does not overlap the active patterns 130 a , 130 b , and 130 c through the openings 111 - 1 , 111 - 2 , and 111 - 3 defined in the metal layer 111 , and thus may not affect transistor performance.

[0157] Next, refer to Fig. 6A and Figure 6B , the metal layer 111 in the exemplary embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

[0158] In a plan view, the first voltage metal layer 111d may have a first width Wd, and the second voltage metal layer 111s may have a second width Ws. At this time, the first width Wd and the second width Ws may be substantially the same. However, the present invention is not limited thereto and may be changed depending on the pixel width and structure, etc.

[0159] The first voltage metal layer 111d may be connected to the driving voltage line 172 through the contact hole 11d. The first voltage metal layer 111d may be provided with a driving voltage. The second voltage metal layer 111s may be connected to the common voltage line 170, the lateral common voltage line 170a, or the conductive pattern 150a through the contact hole 11s. The second voltage metal layer 111s may receive a common voltage.

[0160] The first voltage metal layer 111 d may have any stack structure for applying a driving voltage, and the second voltage metal layer 111 s may have any stack structure for receiving a common voltage.

[0161] In an exemplary embodiment, if Figure 6BAs shown in, for example, the driving voltage line 172 may be connected to the connection member 115a included in the first conductive layer through the contact hole 11d passing through the second insulating layer 160 and the buffer layer 120, and the connection member 115a may be connected to the first voltage metal layer 111d through the contact hole passing through the insulating layer 112. The first voltage metal layer 111d and the driving voltage line 172 may be connected through the connection member 115a provided in the same layer as the lower pattern 115. However, not limited thereto, the driving voltage line 172 may be directly connected to the first voltage metal layer 111d through the contact hole 11d.

[0162] Similarly, the common voltage line 170 may be connected to the connection member 115b included in the first conductive layer through a contact hole 11s passing through the second insulating layer 160 and the buffer layer 120, and the connection member 115b may be connected to the second voltage metal layer 111s through a contact hole passing through the insulating layer 112. The second voltage metal layer 111s and the common voltage line 170 may be connected through a connection member provided in the same layer as the lower pattern 115. However, it is not limited thereto, and the common voltage line 170 may be directly connected to the second voltage metal layer 111s through the contact hole 11s.

[0163] Next, refer to Figure 7 , the metal layer 111 in the exemplary embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

[0164] In a plan view, the first voltage metal layer 111d may have a first width Wd, and the second voltage metal layer 111s may have a second width Ws. At this time, the first width Wd and the second width Ws may be substantially the same. However, the present invention is not limited thereto and may be changed depending on the pixel width and structure, etc.

[0165] The first voltage metal layer 111d may be connected to the driving voltage line 172 through the contact hole 11d. The first voltage metal layer 111d may be provided with a driving voltage. The second voltage metal layer 111s may be connected to the common voltage line 170, the lateral common voltage line 170a, or the conductive pattern 150a through the contact hole 11s. The second voltage metal layer 111s may receive a common voltage.

[0166] In an exemplary embodiment, openings 111-1, 111-2, and 111-3 overlapping the active layer may be defined in the metal layer 111. In detail, a first opening 111-1 overlapping the first active pattern 130a, a second opening 111-2 overlapping the second active pattern 130b, and a third opening 111-3 overlapping the third active pattern 130a may be defined in the metal layer 111.

[0167] The metal layer 111 may receive a predetermined voltage. The metal layer 111 in the exemplary embodiment does not overlap the active layer through the openings 111-1, 111-2, and 111-3, and thus may not affect transistor performance.

[0168] Next, refer to Figures 8 to 9 A display device in an exemplary embodiment is described. Figure 8 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, and Fig. 9 It is taken along line XIIIa-XIIIb Figure 8 A cross-sectional view of a display device shown in FIG. Description of the same configurations as the above-described constituent elements may be omitted.

[0169] The display device in an exemplary embodiment may include a substrate 110. In an exemplary embodiment, the substrate 110 may include an insulating material such as glass, plastic, etc., and may have flexibility.

[0170] The metal layer 111 may be disposed on the substrate 110. The metal layer 111 in an exemplary embodiment may overlap the entire surface of the substrate 110.

[0171] In an exemplary embodiment, for example, the metal layer 111 may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys of these metals or metal-like materials. The metal layer 111 may include a single layer or multiple layers.

[0172] The thickness of the metal layer 111 may be about 6000 angstroms to about 10000 angstroms. The metal layer 111 may have a considerable thickness. As the thickness of the metal layer 111 increases, the performance of the transistor included in the pixel may be better improved and the image quality may be improved. Even when the thickness of the metal layer 111 increases, the step of the metal layer 111 does not occur, so that the formation of other conductive layers may be facilitated and the reliability may be improved.

[0173] The insulating layer 112 may be disposed on the metal layer 111. The insulating layer 112 may include an inorganic insulating material, an organic insulating material, or both. The insulating layer 112 may control the formation of capacitance between the metal layer 111 and another conductive layer.

[0174] Next, a first conductive layer including a plurality of lower patterns 115 may be disposed on the insulating layer 112. The lower patterns 115 may also be referred to as conductive patterns. The first conductive layer may include a plurality of conductive metals or semiconductor materials having equivalent conductive properties.

[0175] The buffer layer 120 is disposed on the lower pattern 115 and the insulating layer 112 .

[0176] On the buffer layer 120, an active layer (130a, 130b, and 130c) including a plurality of active patterns 130a, 130b, and 130c is disposed. That is, the lower pattern 115 may be disposed between the substrate 110 and the active layer (130a, 130b, and 130c). The active patterns 130a, 130b, and 130c disposed in each pixel PX1, PX2, and PX3 may include channel regions 134a, 134b, and 134c forming channels of the plurality of transistors T1, T2, and T3, and conductive regions connected thereto. The conductive region of each of the active patterns 130a, 130b, and 130c may include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c of each transistor T1, T2, and T3.

[0177] In each of the pixels PX1 , PX2 , and PX3 , the active pattern 130 a and the active pattern 130 c may be connected to each other or spaced apart from each other. Figure 8 An example is shown in which the active pattern 130a and the active pattern 130c are connected to each other. In this case, the drain region 135a of the active pattern 130a may be the source region 133c of the active pattern 130c.

[0178] In exemplary embodiments, the active layers ( 130 a , 130 b , and 130 c ) may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

[0179] The insulating pattern 144 of the first insulating layer may be disposed on the active layer (130a, 130b, and 130c). The insulating pattern 144 may overlap with the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c, and may be disposed on the channel regions 134a, 134b, and 134c. The insulating pattern 144 may not substantially overlap with the conductive regions of the active patterns 130a, 130b, and 130c.

[0180] The second conductive layer (151, 152, 153, 172b, 155, 154b, and 154c) may be disposed on the insulating pattern 144. The second conductive layer (151, 152, 153, 172b, 155, 154b, and 154c) may include a first scan line 151 capable of transmitting a first scan signal SC as described above, a second scan line 152 capable of transmitting a second scan signal SS, a horizontal initialization voltage line 153 capable of transmitting an initialization voltage INIT, a horizontal driving voltage line 172b capable of transmitting a driving voltage ELVDD, a driving gate electrode 155, a second gate electrode 154b, and a third gate electrode 154c, etc. The gate electrode G1, the gate electrode G2, and the gate electrode G3 in the above circuit diagram may correspond to the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c included in the driving gate electrode 155, respectively.

[0181] The first and second scan lines 151 and 152 , the transverse initialization voltage line 153 , and the transverse driving voltage line 172 b may extend in the first direction DR1 , respectively.

[0182] In a plan view, the driving gate electrode 155 may be disposed between the first scan line 151 and the second scan line 152 .

[0183] The second gate electrode 154b is spaced apart from the first scan line 151 and may extend substantially in the second direction DR2. In an alternative exemplary embodiment, the second gate electrode 154b may be directly connected to the first scan line 151.

[0184] The third gate electrode 154c is spaced apart from the second scan line 152 and may extend substantially in the second direction DR2. In an alternative exemplary embodiment, the third gate electrode 154c may be directly connected to the second scan line 152.

[0185] The driving gate electrode 155 disposed at each pixel PX1 , PX2 , and PX3 may include a protrusion 155 a protruding upward and a first gate electrode 154 a protruding downward and extending generally in the second direction DR2 .

[0186] The first gate electrode 154a intersects the active pattern 130a and overlaps the channel region 134a of the active pattern 130a. The second gate electrode 154b intersects the active pattern 130b and overlaps the channel region 134b of the active pattern 130b. The third gate electrode 154c intersects the active pattern 130c and overlaps the channel region 134c of the active pattern 130c.

[0187] The lateral driving voltage line 172 b may be connected to the first metal layer 111 through the contact hole 59 .

[0188] The second insulating layer 160 may be disposed on the second conductive layer ( 151 , 152 , 153 , 172 b , 155 , 154 b , and 154 c ). A plurality of contact holes 24 , 26 , 60 , 61 , 62 , 63 , 64 , 65 , 66 , 67 , 68 , and 69 may be defined in the buffer layer 120 and / or the second insulating layer 160 .

[0189] The third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, and 178) may be disposed on the second insulating layer 160. The third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, and 178) may include a plurality of data lines 171a, 171b, and 171c, a plurality of driving voltage lines 172a, 172c, and 172d, a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175, and a plurality of connection members 174, 176, 177, and 178.

[0190] In a plan view, the data lines 171 a , 171 b , and 171 c , the driving voltage lines 172 a , 172 c , and 172 d , the common voltage line 170 , and the initialization voltage line 173 may extend substantially in the second direction DR2 and intersect the first and second scan lines 151 and 152 , respectively.

[0191] Figure 8 The plurality of pixels PX1, PX2, and PX3 of a group shown in FIG. 1 may be arranged adjacent to each other in the first direction DR1, and may also be repeatedly arranged in the first direction DR1 and the second direction DR2. A common voltage line 170 may be provided on both the left and right sides of the plurality of pixels PX1, PX2, and PX3, respectively. When the plurality of pixels PX1, PX2, and PX3 in the repeated group include three pixels PX1, PX2, and PX3, three data lines 171a, 171b, and 171c, three driving voltage lines 172a, 172c, and 172d, and at least one initialization voltage line 173 may be provided between two adjacent common voltage lines 170.

[0192] Each of the data lines 171a, 171b, and 171c is electrically connected to the source region 133b (at the Figure 8 , two contact holes 64 are shown in each of the pixels PX1, PX2 and PX3).

[0193] Each of the driving voltage lines 172 a , 172 c , and 172 d may be provided corresponding to each of the pixels PX1 , PX2 , and PX3 .

[0194] The driving voltage lines 172a, 172c and 172d are electrically connected to the source region 133a of the active pattern 130a through the contact hole 61 of the second insulating layer 160 (at Figure 8 , two contact holes 61 are shown in pixels PX1 and PX2 and one contact hole 61 is shown in pixel PX3). In addition, the driving voltage lines 172a, 172c, and 172d are electrically connected to the transverse driving voltage line 172b through the contact hole 60 of the second insulating layer 160. Therefore, the transverse driving voltage line 172b can transmit the driving voltage together with the driving voltage lines 172a, 172c, and 172d, and transmit the driving voltage across the entire display device in the first direction DR1 and the second direction DR2 in a grid shape.

[0195] The initialization voltage line 173 is electrically connected to the transverse initialization voltage line 153 through the contact hole 69 of the second insulating layer 160. Therefore, the transverse initialization voltage line 153 can transmit the initialization voltage together with the initialization voltage line 173, and even when one initialization voltage line 173 is provided for three pixels PX1, PX2, and PX3, the initialization voltage can be transmitted to all three pixels PX1, PX2, and PX3 through the transverse initialization voltage line 153.

[0196] One capacitor electrode 175 may be disposed at each pixel PX1, PX2, and PX3. The capacitor electrode 175 may overlap the corresponding driving gate electrode 155 via the second insulating layer 160 therebetween, thereby forming a capacitor Cst.

[0197] The capacitor electrode 175 may include a protrusion 175a extending downward. The protrusion 175a is electrically connected to the drain region 135a of the active pattern 130a (or the source region 133c of the active pattern 130c) through the contact hole 62 of the second insulating layer 160 (at Figure 8 Two contact holes 62 are shown at each pixel PX1, PX2, and PX3 in FIG. 1 . In addition, the capacitor electrode 175 is electrically connected to the lower pattern 115 through the contact hole 68 of the second insulating layer 160 and the buffer layer 120.

[0198] The connection member 174 may be electrically connected to the second scan line 152 and the third gate electrode 154 c through the contact hole 24 of the second insulating layer 160 to electrically connect the second scan line 152 and the third gate electrode 154 c to each other.

[0199] The connection member 176 may be electrically connected to the first scan line 151 and the second gate electrode 154 b through the contact hole 26 of the second insulating layer 160 to electrically connect the first scan line 151 and the second gate electrode 154 b to each other.

[0200] In each of the pixels PX1, PX2, and PX3, the connection member 177 is electrically connected to the drain region 135c of the active pattern 130c through the contact hole 63 of the second insulating layer 160 (at Figure 8 Two contact holes 63 are shown at each pixel PX1, PX2 and PX3 in the active pattern 130c and are electrically connected to the horizontal initialization voltage line 153 through the contact hole 67 of the second insulating layer 160, so that the drain region 135c of the active pattern 130c can be electrically connected to the horizontal initialization voltage line 153.

[0201] The transverse initialization voltage line 153 extends across the three pixels PX1, PX2, and PX3 in the first direction DR1, but may be disposed between two adjacent common voltage lines 170, and thus may not intersect the two common voltage lines 170. The transverse initialization voltage line 153 intersects the three adjacent data lines 171a, 171b, and 171c, and may extend only to the initialization voltage line 173.

[0202] The connection member 178 is electrically connected to the drain region 135b of the active pattern 130b in each of the pixels PX1, PX2, and PX3 through the contact hole 65 of the second insulating layer 160 (at Figure 8 In the figure, two contact holes 65 are shown in each of the pixels PX1, PX2 and PX3, and are electrically connected to the protrusion 155a of the driving gate electrode 155 through the contact hole 66 of the second insulating layer 160, so that the drain region 135b of the active pattern 130b and the protrusion 155a of the driving gate electrode 155 can be electrically connected to each other.

[0203] In an exemplary embodiment, at least one of the first conductive layer, the second conductive layer (151, 152, 153, 172b, 155, 154b and 154c) and the third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177 and 178) including the lower pattern 115 may include at least one of metals such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta) and alloys thereof. Each of the first conductive layer, the second conductive layer and the third conductive layer may include a single layer or multiple layers. In an exemplary embodiment, for example, the third conductive layer may have a multilayer structure including a bottom layer including titanium and an upper layer including copper.

[0204] The first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 is electrically connected to the driving voltage lines 172a, 172c, and 172d to receive the driving voltage.

[0205] The lower pattern 115 corresponding to the first transistor T1 overlaps the channel region 134a of the first transistor T1 in a region between the channel region 134a and the substrate 110 to prevent external light from reaching the channel region 134a, thereby reducing leakage current and characteristic deterioration. The lower pattern 115 is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 175.

[0206] The lateral driving voltage line 172b is electrically connected to the metal layer 111 through the contact hole 59 passing through the buffer layer 120 and the insulating layer 112. That is, the metal layer 111 may reduce the resistance of the driving voltage line 172b while being electrically connected to the driving voltage line 172b.

[0207] In addition, since the metal layer 111 is provided on the entire surface of the substrate 110, it can have a relatively thick thickness without any burden of a step. As the thickness increases, the signal resistance due to the metal layer 111 can be easily reduced. In addition, since the metal layer 111 can be provided without a separate mask, the manufacturing process can be simplified and the cost and time required for the process can be reduced.

[0208] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 is electrically connected to the data lines 171a, 171b, and 171c to receive a data voltage or a reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a through the driving gate electrode 155.

[0209] The third transistor T3 includes a channel region 134 c , a source region 133 c , a drain region 135 c , and a third gate electrode 154 c . The drain region 135 c of the third transistor T3 may receive an initialization voltage from the lateral initialization voltage line 153 .

[0210] The third insulating layer 181 may be disposed on the second insulating layer 160 and the third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, and 178). A contact hole 83a may be defined in the third insulating layer 181 on the capacitor electrode 175, and a contact hole 81 may be defined in the third insulating layer 181 on the common voltage line 170.

[0211] A fourth conductive layer (190a, 190b, 190c, and 190d) including a plurality of ohmic contacts (or contact members) 190a, 190b, 190c, and 190d may be disposed on the third insulating layer 181. In another exemplary embodiment, the fourth conductive layer (190a, 190b, 190c, and 190d) may be omitted.

[0212] Each of the ohmic contacts (or contact members) 190 a , 190 b , and 190 c is disposed in each of the pixels PX1 , PX2 , and PX3 , and may make contact with the capacitor electrode 175 through the contact hole 83 a to be electrically connected.

[0213] The ohmic contact 190 d may be electrically connected to the common voltage line 170 through the contact hole 81 .

[0214] The ohmic contacts (or contact members) 190a, 190b, 190c, and 190d can improve the adhesion of the capacitor electrode 175 and the third conductive layers (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, and 178) respectively contacting therewith and the common voltage line 170 of other conductive layers, and can prevent oxidation of the third conductive layer. In an exemplary embodiment, when the upper layer of the third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, and 178) includes copper, oxidation of copper may be prevented. To this end, the fourth conductive layer (190a, 190b, 190c and 190d) may include a conductive material that can prevent corrosion of the upper layer of the third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177 and 178). For example, when the third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177 and 178) includes copper, the conductive material can prevent corrosion of copper by covering the upper layer of the third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177 and 178). In an exemplary embodiment, the fourth conductive layer ( 190 a , 190 b , 190 c , and 190 d ) may include a conductive material such as a metal oxide such as ITO or IZO.

[0215] The fourth insulating layer 182 may be disposed on the third insulating layer 181 and the fourth conductive layer (190a, 190b, 190c, and 190d). Figure 8 and Fig. 9, a contact hole 83b may be defined in the fourth insulating layer 182 on each of the ohmic contacts (or contact members) 190a, 190b, and 190c, and may overlap with the contact hole 83a.

[0216] At least one of the insulating layer 112, the buffer layer 120, the first insulating layer including the insulating pattern 144, the second insulating layer 160, the third insulating layer 181, and the fourth insulating layer 182 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiON) and the like. In exemplary embodiments, the fourth insulating layer 182 may include an inorganic insulating material such as polyimide, an acrylic-based polymer, or a siloxane-based polymer, and may have a substantially flat upper surface.

[0217] On the fourth insulating layer 182, a pixel electrode layer (191a, 191b, and 191c) including a plurality of pixel electrodes 191a, 191b, and 191c may be disposed as a fifth conductive layer (191a, 191b, and 191c). Figure 8 As shown in , each pixel electrode 191a, 191b and 191c can be arranged corresponding to each pixel PX1, PX2 and PX3. The sizes and shapes of the pixel electrodes 191a, 191b and 191c arranged on the three pixels PX1, PX2 and PX3 can be different in a plan view, but are not limited thereto. In an exemplary embodiment, the pixel PX2 represents green, the pixel PX1 represents red, and the pixel PX3 represents blue, but they are not limited thereto.

[0218] Each of the pixel electrodes 191a, 191b, and 191c may make contact with the corresponding ohmic contacts (or contact members) 190a, 190b, and 190c through the contact hole 83b of the fourth insulating layer 182, and may be electrically connected to the capacitor electrode 175 through the ohmic contacts (or contact members) 190a, 190b, and 190c. Therefore, each of the pixel electrodes 191a, 191b, and 191c may be electrically connected to the drain region 135a of the first transistor T1 to receive a voltage from the first transistor T1.

[0219] The pixel electrode layer (191a, 191b, and 191c) may include a semi-transmissive and semi-reflective conductive material or a reflective conductive material.

[0220] The fifth insulating layer 350 may be disposed on the fourth insulating layer 182. An opening 355 may be defined in the fifth insulating layer 350 above the pixel electrodes 191a, 191b, and 191c. In an exemplary embodiment, the fifth insulating layer 350 may include an organic insulating material such as a polyacrylate-based resin or a polyimide resin.

[0221] The emission layer 370 is disposed on the fifth insulating layer 350 and the pixel electrode layer (191a, 191b, and 191c). The emission layer 370 may include a portion disposed within the opening 355 of the fifth insulating layer 350. The emission layer 370 may include an organic light emitting material or an inorganic light emitting material. In an alternative exemplary embodiment, at least a portion of the fifth insulating layer 350 may not be covered by the emission layer 370.

[0222] A contact hole 82 may be defined in the fifth insulating layer 350 and the emission layer 370 on the ohmic contact (or contact member) 190 d .

[0223] The common electrode 270 is disposed on the emission layer 370. The common electrode 270 may be continuously disposed over the plurality of pixels PX1, PX2, and PX3. The common electrode 270 may be electrically connected to the common voltage line 170 to receive a common voltage by contacting the ohmic contact (or contact member) 190d through the contact hole 82.

[0224] The common electrode 270 may include a conductive transparent material.

[0225] The pixel electrodes 191a, 191b and 191c, the emission layer 370 and the common electrode 270 of each pixel PX1, PX2 and PX3 together form an LED ED, and one of the pixel electrodes 191a, 191b and 191c and the common electrode 270 becomes a cathode and the other becomes an anode. In the above exemplary example, the pixel electrodes 191a, 191b and 191c become anodes.

[0226] Next, refer to Figures 10 to 14 A display device in an exemplary embodiment is described. Fig.10 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, Fig.11 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, Fig.12 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, Fig.13 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention, and Fig.14 2 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention. Descriptions of constituent elements that are the same as those described above are omitted.

[0227] First, refer to Fig.10 In an exemplary embodiment, openings 111-1 and 111-2 overlapping the active layer may be defined in the metal layer 111. Specifically, a first opening 111-1 overlapping the first and third active patterns 130a and 130c and a second opening 111-2 overlapping the second active pattern 130b may be defined in the metal layer 111.

[0228] The metal layer 111 is connected to the lateral driving voltage line 172b through the contact hole 59 to receive a predetermined voltage. In an exemplary embodiment, the metal layer 111 does not overlap the active layer through the openings 111-1 and 111-2, so that transistor performance may not be affected.

[0229] Next, refer to Fig.11 , the metal layer 111 in the exemplary embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

[0230] In a plan view, the first voltage metal layer 111d has a first width Wd, and the second voltage metal layer 111s has a second width Ws. At this time, the first width Wd and the second width Ws may be substantially the same. However, the present invention is not limited thereto and may be changed depending on pixel width, structure, etc.

[0231] The first voltage metal layer 111d may be connected to the lateral driving voltage line 172b through the contact hole 11d. The first voltage metal layer 111d may be provided with a driving voltage. The second voltage metal layer 111s may be connected to the common voltage line 170 through the contact hole 11s. The second voltage metal layer 111s may receive a common voltage.

[0232] Next, refer to Fig.12 , the metal layer 111 in the exemplary embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

[0233] In an exemplary embodiment, openings 111-1 and 111-2 overlapping the active layer may be defined in the metal layer 111. In detail, a first opening 111-1 overlapping the first active pattern 130a and the third active pattern 130c and a second opening 111-2 overlapping the second active pattern 130b may be defined in the metal layer 111. In an exemplary embodiment, an opening overlapping a portion of the active patterns 130a, 130b, and 130c may be defined in the metal layer 111.

[0234] The metal layer 111 may receive a predetermined voltage such as a driving voltage or a common voltage. The metal layer 111 in the exemplary embodiment does not overlap the active layer through the openings 111-1 and 111-2, so that the transistor performance may not be affected.

[0235] Next, refer to Fig.13 , the metal layer 111 in the exemplary embodiment may include a first sub-metal layer 111d1, a second sub-metal layer 111d2, and a third sub-metal layer 111d3. The first sub-metal layer 111d1 in the exemplary embodiment may be connected to the first data line 171a through the contact hole 11d1, the second sub-metal layer 111d2 may be connected to the second data line 171b through the contact hole 11d2, and the third sub-metal layer 111d3 may be connected to the third data line 171c through the contact hole 11d3. The first sub-metal layer 111d1 may receive a first data voltage transmitted through the first data line 171a. The second sub-metal layer 111d2 may receive a second data voltage transmitted through the second data line 171b. The third sub-metal layer 111d3 may receive a third data voltage transmitted through the third data line 171c. Although not shown, each data line may be connected to the metal layer through a separate conductive layer between the data line and the metal layer.

[0236] The first submetal layer 111d1, the second submetal layer 111d2, and the third submetal layer 111d3 may be spaced apart from each other. The first submetal layer 111d1, the second submetal layer 111d2, and the third submetal layer 111d3 may have a stripe shape extending along the second direction DR2.

[0237] In a plan view, the first sub-metal layer 111d1 may have a first width W1, the second sub-metal layer 111d2 may have a second width W2, and the third sub-metal layer 111d3 may have a third width W3. At this time, the first width W1, the second width W2, and the third width W3 may be substantially the same, but the present invention is not limited thereto and may be changed depending on the width, structure, etc. of each pixel.

[0238] Next, refer to Fig.14 In an exemplary embodiment, openings 111-1 and 111-2 overlapping the active layer may be defined in the metal layer 111. In detail, a first opening 111-1 overlapping the first active pattern 130a and the third active pattern 130c and a second opening 111-2 overlapping the second active pattern 130b may be defined in the metal layer 111. In an exemplary embodiment, an opening overlapping a portion of the active patterns 130a, 130b, and 130c may be defined in the metal layer 111. The shapes of the openings 111-1 and 111-2 defined in the metal layer 111 may be changed by the active patterns 130a, 130b, and 130c.

[0239] The metal layer 111 may receive a predetermined voltage such as a data voltage. The metal layer 111 in the exemplary embodiment does not overlap the active layer through the openings 111-1 and 111-2, so that transistor performance may not be affected.

[0240] Next, refer to Fig.15 A display device in an exemplary embodiment is described. Fig.15 is a plan view of an exemplary embodiment of a plurality of pixels of a display device according to the present invention.

[0241] On the substrate 110, a metal layer 111 and an insulating layer 112 may be provided to overlap the entire surface of the substrate 110. Figure 2 The exemplary embodiments of the metal layer 111 and the insulating layer 112 of the exemplary embodiment are described above, but are not limited thereto, and any of the above-described exemplary embodiments may be applied.

[0242] A first conductive layer including a lower pattern 115 may be disposed on the insulating layer 112 .

[0243] The buffer layer 120 may be disposed on the first conductive layer, and the active layer 130 may be disposed thereon.

[0244] The first insulating layer 121 may be disposed on the active layer 130. The first insulating layer 121 may be the same layer as the above-described insulating pattern 144, but unlike the insulating pattern 144, the first insulating layer 121 may be disposed in the entire region on the substrate 110 and partially removed. That is, unlike the insulating pattern 144, the first insulating layer 121 may also be disposed on the buffer layer 120. In an alternative exemplary embodiment, a structure such as the insulating pattern 144 may be disposed instead of the first insulating layer 121.

[0245] On the first insulating layer 121 , a second conductive layer including a gate electrode 154 is disposed, and a second insulating layer 160 may be disposed thereon.

[0246] On the second insulating layer 160 , a third conductive layer including a capacitor electrode 175 may be disposed, and a third insulating layer 180 may be disposed thereon.

[0247] On the third insulating layer 180, a pixel electrode layer including a plurality of pixel electrodes 191 may be disposed. The pixel electrode 191 may be electrically connected to the capacitor electrode 175 through a contact hole 89 of the third insulating layer 180.

[0248] On the third insulating layer 180, a sixth insulating layer 350 may be disposed, and an emission layer 370 and a common electrode 270 may be sequentially disposed on the pixel electrode layer and the sixth insulating layer 350. In an exemplary embodiment, the emission layer 370 may include an emission material emitting first color light, which may be blue light, for example.

[0249] An encapsulation layer 380 including a plurality of insulating layers 381, 382, ​​and 383 may be disposed on the common electrode 270. The insulating layers 381 and 383 may include an inorganic insulating material, and the insulating layer 382 disposed between the insulating layers 381 and 383 may include an organic insulating material.

[0250] On the encapsulation layer 380 , a filling layer 390 including a filler may be disposed. A cover layer 401 including an insulating material and a plurality of color conversion layers 430 a and 430 b and a transmission layer 430 c may be disposed on the filling layer 390 .

[0251] The transmission layer 430c may pass incident light. That is, the transmission layer 430c may transmit the first color light, which may be blue light. The transmission layer 430c may include a polymer material that transmits the first color light. In an exemplary embodiment, the region in which the transmission layer 430c is disposed may correspond to, for example, a light emitting region that emits blue light, and the transmission layer 430c may pass the incident first color light as is without including separate semiconductor nanocrystals.

[0252] Color conversion layers 430a and 430b may include semiconductor nanocrystals different from each other. In an exemplary embodiment, for example, first color light incident on color conversion layer 430a may be converted into second color light by semiconductor nanocrystals included in color conversion layer 430b and then emitted. First color light incident on color conversion layer 430b may be converted into third color light by semiconductor nanocrystals included in color conversion layer 430b and then emitted.

[0253] The semiconductor nanocrystal may include at least one of a phosphor and a quantum dot material, which converts incident first color light into second color light or third color light.

[0254] The core of the quantum dot may be one of a II-VI compound, a III-V compound, a IV-VI compound, a IV element, a IV compound, and a combination thereof.

[0255] In an exemplary embodiment, the II-VI compound may be at least one of the following: a binary compound including CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and combinations thereof, including CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdS Ternary compounds including CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and combinations thereof, and quaternary compounds including HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and combinations thereof.

[0256] In an exemplary embodiment, the III-V compound may be at least one of the following: a binary compound including GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and combinations thereof, a ternary compound including GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb and combinations thereof, and a quaternary compound including GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and combinations thereof.

[0257] In an exemplary embodiment, the IV-VI compound may be at least one of the following: a binary compound including SnS, SnSe, SnTe, PbS, PbSe, PbTe and combinations thereof, a ternary compound including SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and combinations thereof, and a quaternary compound including SnPbSSe, SnPbSeTe, SnPbSTe and combinations thereof. The IV group element may include one of Si, Ge and combinations thereof. The IV group compound may be a binary compound including SiC, SiGe and combinations thereof.

[0258] In this case, the binary compound, ternary compound or quaternary compound may exist in the particle at a uniform concentration, or may exist in the same particle divided into a state where the concentration distribution is partially different. In addition, the color conversion medium layer may have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient so that the concentration of the element present in the shell gradually decreases toward the center thereof.

[0259] In some exemplary embodiments, the quantum dot may have a core-shell structure comprising a core comprising the above-mentioned nanocrystals and a shell surrounding the core. The shell of the quantum dot is used as a protective layer to prevent chemical denaturation of the core and / or as a charge layer to give the quantum dot electrophoretic properties. The shell can be a single layer or multiple layers. The interface between the core and the shell may have a concentration gradient, wherein the concentration of the element present in the shell decreases toward the center. Examples of the shell of the quantum dot include metal or non-metal oxides, semiconductor compounds, or combinations thereof.

[0260] In an exemplary embodiment, for example, the metal or non-metal oxide may be a 2 、Al2O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 and NiO, or binary compounds such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 and CoMn 2 O 4 ternary compound, but the present invention is not limited thereto.

[0261] In an exemplary embodiment, for example, the semiconductor compound may be CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP or AlSb, but the present invention is not limited thereto.

[0262] In an exemplary embodiment, the quantum dots may have a full width at half maximum ("FWHM") of an emission wavelength spectrum of about 45 nanometers (nm) or less, preferably about 40 nm or less, and more preferably about 30 nm or less, for example, within this range, color purity or color reproducibility may be improved. In addition, since light emitted by the quantum dots is emitted in all directions, the light viewing angle may be improved.

[0263] In addition, the form of quantum dots is a form commonly used in the art without particular limitation, but more specifically, forms such as spherical, pyramidal, multi-armed or cubic nanoparticles, nanotubes, nanowires, nanofibers and nanoplate particles can be used.

[0264] Quantum dots can adjust the color of emitted light depending on the particle size, so quantum dots can have various emission colors such as blue, red, and green.

[0265] The insulating layer 440 may be disposed on the plurality of color conversion layers 430a and 430b and the transmission layer 430c, and the plurality of color filters 450a, 450b, and 450c and the light blocking member 461 may be disposed thereon. In another exemplary embodiment, the plurality of color filters 450a, 450b, and 450c may be omitted.

[0266] Color filter 450a may represent the second color light, color filter 450b may represent the third color light, and color filter 450c may represent the first color light.

[0267] The light blocking member 461 may be disposed between adjacent color filters 450 a , 450 b , and 450 c .

[0268] The substrate 210 may be disposed on the plurality of color filters 450a, 450b, and 450c and the light blocking member 461. That is, the plurality of color conversion layers 430a and 430b and the plurality of color filters 450a, 450b, and 450c may be disposed between the substrate 110 and the substrate 210.

[0269] In another exemplary embodiment of the present invention, the emission layer 370 may include quantum dots instead of the plurality of color conversion layers 430a and 430b and the transmission layer 430c.

[0270] Next, refer to Figures 16 to 18 A display device in an exemplary embodiment is described. Fig.16 is a view schematically showing a configuration of an exemplary embodiment of a display device according to the present invention, Fig.17 is a block diagram of an exemplary embodiment of a gate driver of a display device according to the present invention, and Fig.18 is a circuit diagram of an exemplary embodiment of one stage of a gate driver of a display device according to the present invention.

[0271] First, refer to Fig.16 , the display device includes a display panel 300 , a data driver 460 , a gate driver 500 and a signal controller 600 .

[0272] The display panel 300 includes a display area DA displaying an image and a non-display area NA in which a gate driver 500 applies a gate voltage to gate lines G1 to Gn, where n is a natural number greater than 1, and the non-display area NA is disposed around the display area DA.

[0273] The data lines D1 to Dm (where m is a natural number greater than 1) of the display area DA may receive data voltages from a data driver 460, which may be an integrated circuit ("IC") disposed on a flexible printed circuit board ("FPCB") 450 attached to the display panel 300. The data lines D1 to Dm extend from the display area DA to the non-display area NA, thereby forming at least a portion of a fan-out portion (not shown) in the non-display area NA.

[0274] The gate driver 500 and the data driver 460 are controlled by the signal controller 600. A printed circuit board ("PCB") 400 is provided outside the FPCB 450 to transmit signals from the signal controller 600 to the data driver 460 and the gate driver 500. The signals provided to the gate driver 500 through the plurality of signal lines SL from the signal controller 600 may include signals such as a vertical start signal, a clock signal, and a voltage (high voltage and / or low voltage) of a predetermined level. In an exemplary embodiment, the signals provided to the gate driver 500 may include fewer or more types of vertical start signals, clock signals, and / or voltages.

[0275] A plurality of pixels PX are arranged in the display area. The display area DA includes a transistor and a storage capacitor. The storage capacitor stores the charge for a predetermined period of time and maintains the voltage and the voltage applied even after the transistor is turned off. In the case of a liquid crystal display, the display area DA includes a liquid crystal capacitor, and the liquid crystal capacitor includes a pixel electrode, a common electrode and a liquid crystal layer. In the case of a light emitting diode display, the display area DA includes a light emitting element, and the light emitting element includes a pixel electrode, a common electrode and a light emitting layer. A plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm are arranged in the display area DA. The gate lines G1 to Gn and the data lines D1 to Dm may cross and be insulated from each other. A plurality of sensing lines (not shown) may be further arranged in the display area DA.

[0276] For a liquid crystal display, a pixel PX includes a transistor, a liquid crystal capacitor, and a storage capacitor. The control terminal (or gate electrode) of the transistor is connected to the gate line, the input terminal (or source electrode) of the transistor is connected to the data line, and the output terminal (or drain electrode) of the transistor is connected to one end of the liquid crystal capacitor and one end of the storage capacitor. The other end of the liquid crystal capacitor is connected to the common electrode to receive the common voltage, and the other end of the storage capacitor receives the storage voltage. In the case of a light-emitting diode display, the pixel PX may include at least two transistors including a switching transistor and a driving transistor, at least one storage capacitor and a light-emitting element, and may further include at least one compensation transistor.

[0277] The data lines D1 to Dm receive data voltages from the data driver 460 , and the gate lines G1 to Gn receive gate voltages from the gate driver 500 .

[0278] The data driver 460 may be disposed at an upper side or a lower side of the display panel 300 , and may be connected to the data lines D1 to Dm extending in a vertical direction.

[0279] The gate driver 500 receives a vertical start signal, a clock signal, a high voltage corresponding to a gate-on voltage, and a low voltage corresponding to a gate-off voltage to generate a gate signal (a gate-on voltage and a gate-off voltage) to be applied to the gate lines G1 to Gn. The gate driver 500 receives a vertical start signal, a clock signal, a high voltage, and a low voltage to generate a sensing signal to be applied to the sensing line. The gate driver 500 includes a plurality of stages ST1-STn that generate and output gate signals through these signals, and a plurality of signal lines SL that transmit these signals to these stages ST1-STn. The signal lines SL may be disposed outside the display area DA farther than these stages ST1-STn, but are not limited thereto, and some signal lines may be disposed between these stages ST1-STn and the display area DA. Although in Fig.16 , but the signal line SL may include a plurality of signal lines corresponding to the number of signals applied to the gate driver 500, and may include more or less signal lines. The gate driver 500 may be integrated into the non-display area NA of the display panel 300. In an exemplary embodiment, the gate driver 500 may be provided (e.g., mounted) on a PCB or FPCB in the form of an IC chip to be electrically connected to the display panel 300.

[0280] A vertical start signal, a clock signal, a high voltage, and a low voltage may be applied to the gate driver 500 through the FPCB 450 disposed adjacent to the gate driver 500. These signals may be transmitted to the FPCB 450 through the PCB 400 from the outside or the signal controller 600.

[0281] The gate driver 500 may be arranged on the left and / or right side of the display area DA, and may be arranged on the upper and / or lower side thereof. When the gate driver 500 is arranged on the left and right sides of the display panel, the gate driver arranged on the left side of the display panel includes odd-numbered stages ST1, ST3, ..., and the gate driver arranged on the right side of the display panel includes even-numbered stages ST2, ST4, ... or vice versa. However, even if the gate driver 500 is arranged on the left and right sides of the display panel, the left and right gate drivers may include all stages ST1-STn. The stages ST1-STn of the gate driver 500 may include a plurality of transistors and at least one capacitor. These transistors and capacitors may be manufactured with the same process as the transistors included in the pixels PX of the display area DA.

[0282] Next, refer to Fig.17 and Fig.18 A gate driver of a display device in an exemplary embodiment is described.

[0283] First, refer to Fig.17 , the gate driver 500 includes a plurality of stages ST1, ST2, ST3, ... connected interdependently. These stages ST1, ST2, ST3, ... can be connected to a corresponding number of gate lines G1, G2, G3, ..., respectively, to sequentially output gate signals "scan [1]", "scan [2]", "scan [3]", ... to the gate lines G1, G2, G3, .... Moreover, the stages ST1, ST2, ST3, ... can be connected to a corresponding number of sensing lines SS1, SS2, SS3, ..., respectively, to sequentially output sensing signals "sense [1]", "sense [2]", "sense [3]", ... to the sensing lines SS1, SS2, SS3, .... Each stage ST1, ST2, ST3, . . . includes a first input terminal IN1, a second input terminal IN2, voltage terminals VGH, VGL1 and VGL2, a sensing terminal SEN_ON, clock terminals S_CLK, CLK3_SS, CLK1_CR, CLK3_CR and CLK3_SC, a first output terminal OUT1, a second output terminal OUT2 and a carry output terminal CR_OUT.

[0284] Reference Fig.18 and Fig.17, one stage ST among a plurality of stages ST1, ST2, ST3, ... is shown. The first input terminal IN1 is connected to the carry output terminal CR_OUT of the second previous stage, and receives a carry signal output from the carry output terminal CR_OUT of the second previous stage. However, since there is no second previous stage for the first stage ST1 and the second stage ST2, the first vertical start signal SSP1 can be input to the first input terminal IN1 of the first stage ST1, and the second vertical start signal SSP2 can be input to the first input terminal IN1 of the second stage ST2.

[0285] The second input terminal IN2 is connected to the carry output terminal CR_OUT of the second next stage, and receives the carry signal output from the carry output terminal CR_OUT of the second next stage. However, since the second next stage does not exist for the final stage and the previous stage of the final stage, the first vertical start signal SSP1 and the second vertical start signal SSP2 of the next frame can be input to the second input terminal IN2 of the final stage and the previous stage of the final stage, respectively.

[0286] The voltage terminals VGH, VGL1 and VGL2 may include a high voltage terminal VGH, a first low voltage terminal VGL1 and a second low voltage terminal VGL2. A high voltage of a predetermined level may be input to the high voltage terminal VGH, a first low voltage of a predetermined level may be input to the first low voltage terminal VGL1, and a second low voltage lower than the first low voltage may be input to the second low voltage terminal VGL2. In an exemplary embodiment, the first low voltage may correspond to a gate cut-off voltage of a gate signal. In an exemplary embodiment, the first low voltage may correspond to a gate cut-off voltage of a sensing signal. In an exemplary embodiment, the second low voltage may correspond to a gate cut-off voltage of a carry signal. In an exemplary embodiment, the second low voltage may correspond to a discharge level of a first node Q included in the stage.

[0287] The first output terminal OUT1 is electrically connected to the corresponding gate lines G1, G2, G3, ... to output the gate signal. In an exemplary embodiment, for example, the first output terminal OUT1 of the first stage ST1 is electrically connected to the first gate line G1 to output the first gate signal "Scan [1]", and the first output terminal OUT1 of the second stage ST2 is electrically connected to the second gate line G2 to output the second gate signal "Scan [2]". After the first gate signal "Scan [1]" is output, the second gate signal "Scan [2]" is output. Next, the third gate signal "Scan [3]" is sequentially output to the final gate signal.

[0288] The second output terminal OUT2 is electrically connected to the corresponding sensing lines SS1, SS2, SS3, ... to output the sensing signal. In an exemplary embodiment, for example, the second output terminal OUT2 of the first stage ST1 is electrically connected to the first sensing line SS1 to output the first sensing signal "Sensing [1]", and the second output terminal OUT2 of the second stage ST2 is electrically connected to the second sensing line SS2 to output the second sensing signal "Sensing [2]". After the first sensing signal "Sensing [1]" is output, the second sensing signal "Sensing [2]" is output. Next, the third sensing signal "Sensing [3]" is sequentially output to the final sensing signal.

[0289] The carry output terminal CR_OUT outputs a carry signal. The carry output terminal CR_OUT may be connected to the first input terminal IN1 of the second next stage and the second input terminal IN2 of the second previous stage.

[0290] In detail, the stage ST includes a first node charging unit 510, a buffer unit 520, a sensing unit 530, a carry unit 540, a first node holding unit 550, a first node discharging unit 560, an inverter unit 570, and the like.

[0291] The first node charging unit 510 transmits a high voltage to the first node Q according to a carry signal or a vertical start signal input to the first input terminal IN1. The high voltage may be a gate-on voltage. The first node charging unit 510 may include a fourth transistor T4. The fourth transistor T4 includes a control terminal connected to the first input terminal IN1, an input terminal connected to the high voltage terminal VGH, and an output terminal connected to the first node Q.

[0292] The buffer unit 520 may include a first transistor T1 , a second transistor T2 , a third capacitor C3 , a twenty-first transistor T21 , a twenty-second transistor T22 , and a fourth capacitor C4 .

[0293] The third capacitor C3 and the fourth capacitor C4 are charged with a first voltage corresponding to a high voltage in response to a carry signal applied to the first node Q. The third capacitor C3 includes one end connected to the first node Q and the other end connected to the first output terminal OUT1. The fourth capacitor C4 includes one end connected to the first node Q and the other end connected to the second output terminal OUT2.

[0294] The first transistor T1 includes a control terminal connected to a first node Q, an input terminal connected to a clock terminal CLK3_SC, and an output terminal connected to a first output terminal OUT1. The control terminal and the output terminal of the first transistor T1 are respectively connected to one end and the other end of the third capacitor C3. In a state where a first voltage charged by the third capacitor C3 is applied to the control terminal of the first transistor T1, when a high voltage clock signal is received through the clock terminal CLK3_SC, the first transistor T1 is self-bootstrapping. In this case, the first node Q connected to the control terminal of the first transistor T1 is increased from the first voltage to the boost voltage.

[0295] When the boost voltage is applied to the control terminal of the first transistor T1, the first transistor T1 can output the clock signal input to the clock terminal CLK3_SC to the first output terminal OUT1 as a gate signal. The high voltage clock signal can be output as a gate signal of a gate-on voltage through the first output terminal OUT1.

[0296] The twenty-first transistor T21 includes a control terminal connected to the first node Q, an input terminal connected to the clock terminal CLK3_SS, and an output terminal connected to the second output terminal OUT2. The control terminal and the output terminal of the twenty-first transistor T21 are respectively connected to one terminal and the other terminal of the fourth capacitor C4.

[0297] The second transistor T2 pulls down the gate signal. The second transistor T2 includes a control terminal connected to the second node QB, an input terminal connected to the first output terminal OUT1, and an output terminal connected to the first low voltage terminal VGL1. The second transistor T2 pulls down the voltage of the first output terminal OUT1 to the first low voltage applied to the first low voltage terminal VGL1 according to the voltage of the second node QB.

[0298] The 22nd transistor T22 pulls down the sensing signal. The 22nd transistor T22 includes a control terminal connected to the second node QB, an input terminal connected to the second output terminal OUT2, and an output terminal connected to the first low voltage terminal VGL1. The 22nd transistor T22 pulls down the voltage of the second output terminal OUT2 to the first low voltage applied to the first low voltage terminal VGL1 according to the voltage of the second node QB.

[0299] The sensing unit 530 may include a sixteenth transistor ( T16 - 1 and T16 - 2 ), a seventeenth transistor T17 , an eighteenth transistor T18 , and a second capacitor C2 .

[0300] The sixteenth transistor (T16-1 and T16-2) transmits the carry signal applied to the second input terminal IN2 to the third node S according to the signal input to the sensing terminal SEN_ON. The sixteenth transistor (T16-1 and T16-2) may include a sixteenth-first transistor T16-1 and a sixteenth-second transistor T16-2. The sixteenth-first transistor T16-1 includes a control terminal connected to the sensing terminal SEN_ON, an input terminal connected to the second input terminal IN2, and an output terminal connected to the sixteenth-second transistor T16-2. The sixteenth-second transistor T16-2 includes a control terminal connected to the sensing terminal SEN_ON, an input terminal connected to the output terminal of the sixteenth-first transistor T16-1, and an output terminal connected to the third node S.

[0301] The second capacitor C2 includes one end connected to the third node S and the other end connected to the second low voltage terminal VGL2. The second capacitor C2 may be charged using the high voltage of the carry signal applied to the second input terminal IN2.

[0302] The seventeenth transistor T17 includes a control terminal connected to the third node S, an input terminal connected to the eighteenth transistor T18, and an output terminal connected to the first node Q. The eighteenth transistor T18 includes a control terminal connected to the third node S, an input terminal connected to the clock terminal S_CLK, and an output terminal connected to the input terminal of the seventeenth transistor T17. When the voltage of the third node S is charged by a high voltage, the seventeenth transistor T17 and the eighteenth transistor T18 transmit the clock signal input to the clock terminal S_CLK to the first node Q to transmit the high voltage of the clock signal to the first node Q.

[0303] The fourth capacitor C4 of the buffer unit 520 is charged with a first voltage corresponding to a high voltage applied to the first node Q. In a state where the first voltage charged by the fourth capacitor C4 is applied to the control terminal of the twenty-first transistor T21, when the clock terminal CLK3_SS receives a clock signal of a high voltage, the twenty-first transistor T21 is bootstrapped. In this case, the first node Q connected to the control terminal of the twenty-first transistor T21 is increased from the first voltage to the boost voltage. When the boost voltage is applied to the control terminal of the twenty-first transistor T21, the twenty-first transistor T21 can output the clock signal input to the clock terminal CLK3_SS to the second output terminal OUT2 as a sensing signal. The high voltage clock signal can be output as a sensing signal of the gate-on voltage through the second output terminal OUT2.

[0304] The carry unit 540 outputs a carry signal through the carry output terminal CR_OUT. Moreover, the carry unit 540 pulls down the carry signal output to the carry output terminal CR_OUT to the second low voltage applied to the second low voltage terminal VGL2. The carry unit 540 may include a tenth transistor T10, an eleventh transistor T11 and a first capacitor C1. The tenth transistor T10 includes a control terminal connected to the first node Q, an input terminal connected to the clock terminal CLK3_CR, and an output terminal connected to the carry output terminal CR_OUT. The eleventh transistor T11 includes a control terminal connected to the second node QB, an input terminal connected to the carry output terminal CR_OUT, and an output terminal connected to the second low voltage terminal VGL2. The first capacitor C1 includes an end connected to the second node QB and the other end connected to the second low voltage terminal VGL2.

[0305] The first node holding unit 550 holds the voltage of the first node Q. The first node holding unit 550 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 includes a control terminal connected to the clock terminal CLK3_SC, an input terminal connected to the first node Q, and an output terminal connected to the sixth transistor T6. The sixth transistor T6 includes a control terminal connected to the second node QB, an input terminal connected to the output terminal of the fifth transistor T5, and an output terminal connected to the carry output terminal CR_OUT. The first node holding unit 550 may hold the voltage of the first node Q according to the clock signal input to the clock terminal CLK3_SC and the voltage of the second node QB as the second low voltage.

[0306] The first node discharge unit 560 may discharge the high voltage of the first node Q in response to the carry signal input to the second input terminal IN2. The first node discharge unit 560 may include a twentieth transistor T20. The twentieth transistor T20 includes a control terminal connected to the second input terminal IN2, an input terminal connected to the first node Q, and an output terminal connected to the carry output terminal CR_OUT.

[0307] When a high voltage is applied to the first node Q, the inverter unit 570 applies the clock signal of the gate cut-off voltage input to the clock terminal CLK1_CR to the second node QB. Moreover, when the clock signal of the gate on voltage is applied to the clock terminal CLK1_CR, the inverter unit 570 can apply a high voltage to the second node QB. The inverter unit 570 may include a third transistor (T3-1 and T3-2), a seventh transistor T7, and an eighth transistor T8. The third transistor (T3-1 and T3-2) may include a third-first transistor T3-1 and a third-second transistor T3-2. The third-first transistor T3-1 includes a control terminal connected to the first node Q, an input terminal connected to the clock terminal CLK1_CR, and an output terminal connected to the third-second transistor T3-2. The third-second transistor T3-2 includes a control terminal connected to the first node Q, an input terminal connected to the output terminal of the third-first transistor T3-1, and an output terminal connected to the second node QB. The seventh transistor T7 includes a control terminal connected to the clock terminal CLK1-CR, an input terminal connected to the high voltage terminal VGH, and an output terminal connected to the second node QB. The eighth transistor T8 includes a control terminal connected to the second node QB, an input terminal connected to the high voltage terminal VGH, and an output terminal connected to the second node QB. In another exemplary embodiment, the eighth transistor T8 may be omitted.

[0308] Next, refer to Figures 19 to 21 An exemplary embodiment of a structure of a display device is described. Fig.19 is a schematic top view of an exemplary embodiment of a display device, Fig. 20A , Fig. 20B and Fig. 20C sectional views of exemplary embodiments of a display area and a non-display area, respectively, and Fig.21 It is a partial top view of the non-display area.

[0309] Reference Fig.19 The display device 1 includes a display panel 10, and the display panel 10 includes a display area DA and a non-display area NA. The display area DA and the non-display area NA are separate areas in a plan view. Fig.19 , the inner side and the outer side of the dotted quadrilateral correspond to the display area DA and the non-display area NA, respectively.

[0310] In the display panel 10, the display area DA corresponds to a screen on which an image is displayed. In the non-display area NA around the display area DA, circuits and / or signal lines for generating and / or transmitting various signals applied to the display area DA are provided. The non-display area NA may surround the display area DA.

[0311] In the display area DA of the display panel 10, pixels PX are arranged, for example, in a matrix. Signal lines such as gate lines (also referred to as scan lines), data lines, and drive voltage lines are also arranged in the display area DA. The gate lines, data lines, and drive voltage lines are connected to each pixel PX, and a gate signal (also referred to as a scan signal), a data signal, and a drive voltage from these signal lines may be applied to each pixel PX. Each pixel PX in the exemplary embodiment may include a light-emitting element that may be an LED. In the display area DA, signal lines such as sensing lines or light-emitting control lines that may be connected to the pixels PX, or signal lines that transmit signals different from the signals described above may be further arranged.

[0312] In the display area DA, a touch sensor layer for sensing contact or non-contact touch of a user may be provided. Although a rectangular display area DA is shown, the display area DA may have various shapes such as a polygon, a circle, and an ellipse in addition to a quadrilateral, and the edges may be rounded polygons.

[0313] In the non-display area NA of the display panel 10, a pad portion PP is provided in which a pad for receiving a signal from the outside of the display panel 10 is provided. The pad portion PP may be positioned to be elongated in the first direction DR1, for example, along one edge of the display panel 10. The display device 1 may include a flexible printed circuit film bonded to the pad portion PP. The pads of the flexible printed circuit film may be electrically connected to the pads of the pad portion PP. Depending on the size of the display panel 10, the display panel 10 may include a plurality of pad portions PP separated from each other in the first direction DR1, and one flexible printed circuit film may be bonded to each pad portion PP. Fig.19 In the embodiment, the pad portion PP is disposed at the lower end of the display panel 10, but the pad portion PP may be disposed at the upper end of the display panel 10, or may be disposed at both the lower end and the upper end.

[0314] The display device 1 includes a driving unit disposed in the non-display area NA of the display panel 10. The driving unit may generate and / or process various signals for driving the display panel 10. The driving unit may include a data driver for applying data signals to data lines, a gate driver GD for applying gate signals to gate lines, and a signal controller for controlling the data driver and the gate driver.

[0315] The gate driver GD may be integrated in the non-display area NA of the display panel 10, particularly on the first substrate 110, and may be disposed on both sides or one side of the display area DA. The data driver may be provided in the form of an IC chip and may be disposed on a flexible printed circuit film bonded to the pad portion PP or in the non-display area NA of the display panel 10. The signal controller may be provided in the form of an IC chip and may be disposed on a PCB bonded to the flexible printed circuit film. The data driver and the signal controller may be provided in the form of an integrated chip.

[0316] The gate driver GD provided in the non-display area NA is connected to the gate line to apply the gate signal to the pixel PX. The gate driver GD is integrated in the non-display area NA. The gate driver GD receives a driver control signal such as a vertical start signal, a clock signal and a low voltage corresponding to the gate cut-off voltage from the signal controller to generate a gate signal (e.g., a gate on voltage and a gate off voltage) to be applied to the gate line. The gate driver GD includes a drive circuit (also referred to as a shift register) that generates and outputs a gate signal through these signals, and the drive circuit includes stages that are interdependently connected. The gate driver GD also includes a driver control signal line that transmits the driver control signal to these stages. These stages are connected to the gate line one-to-one, thereby allowing the gate signal to be sequentially output to the gate line for each frame. Each stage includes a transistor and may include at least one capacitor. Some of the driver control signals may be provided by a device other than the signal controller.

[0317] The display panel 10 includes an encapsulation layer EN that completely covers the display area DA. The encapsulation layer EN seals the display area DA, especially the light emitting element, to prevent moisture or oxygen from penetrating into the display panel 10, especially in the display area DA. An edge of the encapsulation layer EN may be disposed between an edge of the display panel 10 and the display area DA.

[0318] Next, refer to Fig. 20A A cross-sectional structure of a partial region of the display area DA and a partial region in which a gate driver in the non-display area NA is disposed is described.

[0319] Referring to the cross-sectional structure, the display panel 10 includes a first substrate 110 and various layers, wirings, and elements disposed thereon. The display panel 10 may include a second substrate 210 bonded to the first substrate 110 by a sealant (not shown). In the display area DA of the display panel 10, a large number of pixels are provided, but in order to avoid the complexity of the drawings, only three pixels are briefly described. In addition, although each pixel PX of the display area DA includes a transistor, a capacitor, and a light-emitting element, one transistor TRp and one light-emitting element LD connected thereto are shown and described. Moreover, some transistors TRd in the non-display area NA, which are particularly provided in the gate driver GD, are shown and described.

[0320] In an exemplary embodiment, for example, the first substrate 110 may be a rigid substrate including at least one of glass, quartz, ceramic, etc. In an exemplary embodiment, the first substrate 110 may be a flexible substrate including a polymer such as polyimide.

[0321] The first metal layer LB1 in the non-display area NA and the second metal layer LB2 in the display area DA may be disposed on the first substrate 110. The first metal layer LB1 and the second metal layer LB2 may prevent external light from reaching the semiconductor layers Ad and Ap of the transistors TRd and TRp, thereby preventing the characteristics of the semiconductor layers Ad and Ap from being degraded. The transistors TRd and TRp, in particular, the leakage current of the driving transistor whose current characteristics are important in the light emitting diode display, may be controlled by the first metal layer LB1 and the second metal layer LB2. The first metal layer LB1 and the second metal layer LB2 may include a material that does not transmit light of a wavelength band to be shielded, and may include, for example, a metal, a metal alloy, or a conductive material equivalent to a metal.

[0322] The first metal layer LB1 and the second metal layer LB2 may function as electrodes for receiving a specific voltage on the display panel 10. In this case, the second metal layer LB2 may improve characteristics as a driving transistor by reducing a current change rate in a saturation region of a voltage-current characteristic diagram of the transistor TRp.

[0323] Also, the first metal layer LB1 and the second metal layer LB2 may be electrically connected to other signal lines (eg, gate lines, driving voltage lines, etc.) or may be in a floating state.

[0324] In an exemplary embodiment, for example, the thickness t1 of the first metal layer LB1 and the second metal layer LB2 may be about 1000 angstroms to about 4000 angstroms. The thickness of the first metal layer LB1 and the second metal layer LB2 may be greater than other constituent elements.

[0325] The buffer layer 120 may be disposed on the first metal layer LB1 and the second metal layer LB2. The buffer layer 120 may be used to block impurities that may diffuse from the first substrate 110 to the semiconductor layers Ap and Ad during the formation of the semiconductor layers Ap and Ad, and reduce stress applied to the first substrate 110. In an exemplary embodiment, the buffer layer 120 may include an inorganic insulating material such as silicon oxide and silicon nitride.

[0326] This specification describes an exemplary embodiment in which buffer layer 120 is provided to be flat while covering first and second metal layers LB1 and LB2 , but is not limited thereto, and buffer layer 120 may have steps along first and second metal layers LB1 and LB2 .

[0327] The semiconductor layers Ap and Ad of the transistors TRp and TRd may be disposed on the buffer layer 120. The semiconductor layers Ap and Ad may include a channel region overlapping the gate electrodes Gp and Gd, and a doped source region and a doped drain region on their respective sides. In an exemplary embodiment, the semiconductor layers Ap and Ad may include polysilicon, amorphous silicon, or an oxide semiconductor.

[0328] The semiconductor layers Ad and Ap in the exemplary embodiment may be disposed on the first metal layer LB1 and the second metal layer LB2. In more detail, the semiconductor layer Ad disposed in the gate driver GD may be disposed on the top surface of the first metal layer LB1, and the semiconductor layer Ap disposed in the display area DA may be disposed on the top surface of the second metal layer LB2. Each of the semiconductor layers Ad and Ap may not overlap with the side of the first metal layer LB1 or the second metal layer LB2. That is, in a plan view, the edge of each semiconductor layer Ad and Ap may be disposed on the inner side of the edge of the first metal layer LB1 or the edge of the second metal layer LB2.

[0329] On the semiconductor layers Ap and Ad, a first insulating layer 140 including an inorganic insulating material or an organic insulating material such as silicon oxide and silicon nitride may be disposed. The first insulating layer 140 may also be referred to as a gate insulating layer.

[0330] A gate conductor including a gate line, a driver control signal line, and gate electrodes Gp and Gd of transistors TRp and TRd may be disposed on the first insulating layer 140. In an exemplary embodiment, the gate conductor may include a metal or a metal alloy such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti), or a multilayer such as titanium (Ti) / molybdenum (Mo).

[0331] The second insulating layer 160 may be disposed on the first insulating layer 140 and the gate conductor. In an exemplary embodiment, the second insulating layer 160 may include an inorganic insulating material such as silicon oxide and silicon nitride, or an organic insulating material. The second insulating layer 160 may also be referred to as an interlayer insulating layer.

[0332] On the second insulating layer 160 , data conductors including a data line, a driving voltage line, a common voltage line, and source electrodes Sp and Sd and drain electrodes Dp and Dd of transistors TRp and TRd may be disposed.

[0333] The source electrodes Sp and Sd and the drain electrodes Dp and Dd may be connected to the source region and the drain region of the semiconductor layers Ap and Ad, respectively, via contact holes defined in the second insulating layer 160 and the first insulating layer 140. One of the source electrode Sp and the drain electrode Dp may be connected to the second metal layer through a contact hole defined in the second insulating layer 160, the first insulating layer 140, and the buffer layer 120.

[0334] In exemplary embodiments, the data conductor may include a metal or a metal alloy such as copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), and the like.

[0335] In exemplary embodiments, the data conductor may be a multilayer such as titanium / copper (Ti / Cu), titanium / aluminum (Ti / Al), titanium / copper / titanium (Ti / Cu / Ti), titanium / aluminum / titanium (Ti / Al / Ti), and molybdenum / aluminum / molybdenum (Mo / Al / Mo).

[0336] The gate electrode Gp, the source electrode Sp, and the drain electrode Dp form a transistor TRp together with the semiconductor layer Ap. The gate electrode Gd, the source electrode Sd, and the drain electrode Dd form a transistor TRd together with the semiconductor layer Ad. In the exemplary embodiment shown, the drain electrode Dp is connected to the metal layer LB2 through a contact hole defined in the second insulating layer 160, the first insulating layer 140, and the buffer layer 120. In the transistors TRp and TRd, the gate electrodes Gp and Gd are disposed above the semiconductor layers Ap and Ad, but the structure of the transistor is not limited thereto and various changes may be made.

[0337] A third insulating layer 181 including an inorganic insulating material such as silicon nitride and silicon oxide may be disposed on the data conductor. The third insulating layer 181 of the inorganic insulating layer may also be referred to as a passivation layer. In another exemplary embodiment, the third insulating layer 181 may be omitted.

[0338] An ohmic contact (or contact member) 190 may be disposed on the third insulating layer 181. The ohmic contact (or contact member) 190 may be disposed in the display area DA and connected to the drain electrode Dp through a contact hole. The first electrode E1 and the drain electrode Dp, which will be described later, may be connected through the ohmic contact (or contact member) 190.

[0339] The ohmic contact (or contact member) 190 improves the adhesion of the drain electrode Dp and the first electrode E1, which are in contact with each other, respectively, and can prevent oxidation of the drain electrode Dp. In an exemplary embodiment, when the drain electrode Dp includes copper, it can prevent oxidation of copper. To this end, the ohmic contact (or contact member) 190 may include a conductive material capable of preventing corrosion of the drain electrode Dp by covering the drain electrode Dp, for example, a conductive material that prevents corrosion of copper. In an exemplary embodiment, the ohmic contact (or contact member) 190 may include a conductive material of a metal oxide such as ITO and IZO.

[0340] A fourth insulating layer 182 including an organic insulating material may be disposed on the third insulating layer 181 and the ohmic contact (or contact member) 190. The fourth insulating layer 182 may be an organic insulating layer, for example, it may include polyimide, acrylic polymer, and siloxane polymer. The fourth insulating layer 182 may also be referred to as a planarization layer.

[0341] The first electrode E1 may be disposed on the fourth insulating layer 182. The first electrode E1 in the exemplary embodiment may be connected to the ohmic contact (or contact member) 190 through a contact hole defined in the fourth insulating layer 182. The first electrode E1 may be connected to the drain electrode Dp through the ohmic contact 190.

[0342] In an exemplary embodiment, the first electrode E1 is a metal or a metal alloy such as silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), aluminum-neodymium (AlNd), and aluminum nickel lanthanum (AlNiLa). In an exemplary embodiment, the first electrode E1 may include a transparent conductive material such as ITO and IZO. In an exemplary embodiment, the first electrode E1 may be a multilayer such as ITO / Ag / ITO and ITO / aluminum (Al).

[0343] On the fourth insulating layer 182, a fifth insulating layer 360 may be provided in which an opening overlapping the first electrode E1 is defined. The opening of the fifth insulating layer 360 may define each pixel region and may also be referred to as a pixel defining layer. The fifth insulating layer 360 may include an organic insulating material or an inorganic insulating material.

[0344] The emission layer EL is disposed on the first electrode E1, and the second electrode E2 is disposed on the emission layer EL. The second electrode E2 may be provided with a common voltage ELVSS. In an exemplary embodiment, the second electrode E2 may have light transmittance by forming a thin layer of a metal having a low work function such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), and silver (Ag). In an exemplary embodiment, the second electrode E2 may include a transparent conductive material such as ITO or IZO.

[0345] The first electrode E1, the emission layer EL, and the second electrode E2 of each pixel PX form a light emitting element LD such as an LED. The first electrode E1 may be an anode of the LED, and the second electrode E2 may be a cathode of the LED. The first electrode E1 may also be referred to as a pixel electrode, and the second electrode E2 may also be referred to as a common electrode. The light emitting element LD may be a light emitting element that emits blue light or a light emitting element that emits white light. In an alternative exemplary embodiment, the light emitting element LD may include a light emitting element that emits three primary colors, for example, a light emitting element that emits red light, a light emitting element that emits green light, and a light emitting element that emits blue light.

[0346] The covering layer 371 may be disposed on the second electrode E2, and the functional layer 372 may be disposed on the covering layer 371. The covering layer 371 may improve light efficiency by adjusting the refractive index. When the encapsulation layer EN is formed, the functional layer 372 may be used to prevent damage to the bottom layer and improve optical efficiency. In an exemplary embodiment, the covering layer 371 may include an inorganic insulating material, and the functional layer 372 may include a material such as lithium fluoride (LiF). The covering layer 371 and the functional layer 372 may extend to the non-display area NA. The covering layer 371 and the functional layer 372 may cover a portion of the non-display area NA, or may be arranged to cover the entire area.

[0347] The encapsulation layer EN may be disposed on the capping layer 371 and the functional layer 372. The encapsulation layer EN seals the light emitting element LD to prevent moisture or oxygen from penetrating from the outside. The encapsulation layer EN covers the entire display area DA, and an edge of the encapsulation layer EN may be disposed in the non-display area NA.

[0348] In the encapsulation layer EN, at least one inorganic layer and at least one organic layer are stacked. In the exemplary embodiment shown, the encapsulation layer EN is a thin film encapsulation layer including a first inorganic layer 391, an organic layer 392, and a second inorganic layer 393. In the encapsulation layer EN, the first inorganic layer 391 and the second inorganic layer 393 are mainly used to prevent the penetration of moisture and the like, and the organic layer 392 mainly makes the surface of the second inorganic layer 393 flat in the surface of the encapsulation layer EN, especially in the display area DA. In an exemplary embodiment, the first inorganic layer 391 and the second inorganic layer 393 may include an inorganic insulating material such as silicon oxide and silicon nitride. In an exemplary embodiment, for example, the organic layer 392 may include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, and a perylene resin.

[0349] The first inorganic layer 391 and the second inorganic layer 393 are wider than the organic layer 392, and the first inorganic layer 391 and the second inorganic layer 393 may contact near the edge of the encapsulation layer EN. The edge of the first inorganic layer 391 and the edge of the second inorganic layer 393 may substantially coincide. By widely forming the first inorganic layer 391 and the second inorganic layer 393 in this manner, it is possible to prevent moisture or oxygen from penetrating from the side of the display area DA, and to delay penetration by extending and complicating the penetration path of moisture or oxygen.

[0350] The present specification describes an encapsulation layer in which inorganic layers and organic layers are alternately stacked, but is not limited thereto and may include an encapsulation layer in a flat shape.

[0351] The second substrate 210 bonded to the first substrate 110 via a sealant (not shown) surrounding the edge of the display panel 10 is disposed on the encapsulation layer EN. In order to expose the pad portion PP to the outside for bonding of the printed circuit film, the second substrate 210 is shorter than the first substrate 110 in a region where the pad portion PP is disposed, for example, a lower end of the display panel 10.

[0352] In an exemplary embodiment, the second substrate 210 may include a transparent and rigid material such as glass, quartz, or ceramic, etc. The second substrate 210 may be spaced apart from the encapsulation layer EN by a predetermined distance.

[0353] The light blocking member 220 and the color filters 230R, 230G, and 230B may be disposed on a surface of the second substrate 210 facing the first substrate 110. The color filters 230R, 230G, and 230B may include a red color filter 230R, a green color filter 230G, and a blue color filter 230B. An overcoat layer may be disposed on the color filters 230R, 230G, and 230B.

[0354] The light blocking member 220 is disposed in an area other than the pixel area (e.g., an area overlapping the light emitting layer EL) to prevent light transmission in areas other than the pixel area. The light blocking member 220 may be disposed between the red color filter 230R and the green color filter 230G, between the green color filter 230G and the blue color filter 230B, and between the blue color filter 230B and the red color filter 230R. The light blocking member 220 may define an area in which the red color filter 230R, the green color filter 230G, and the blue color filter 230B are disposed.

[0355] When the plurality of light emitting elements LD provided in the display area DA are light emitting elements emitting blue light, the red color filter 230R may convert the blue light into red light, the green color filter 230G may convert the blue light into green light, and the blue color filter 230B may transmit the blue light as it is. Therefore, the red color filter 230R and the green color filter 230G may also be referred to as a color conversion layer, and the blue color filter 230B may also be referred to as a transmission layer. The red color filter 230R may include at least one of a quantum dot and a phosphor for converting blue light into red light. The green color filter 230G may include at least one of a quantum dot and a phosphor for converting blue light into green light. The blue color filter 230B may include a resin that transmits blue light, and may further include a dye or a pigment. A blue light cut filter (e.g., a yellow color filter) that transmits wavelengths other than the blue wavelength band and blocks the blue wavelength band may be provided between the red color filter 230R and the green color filter 230G and the second substrate 210.

[0356] A touch sensor layer including a touch electrode for sensing a touch may be disposed on the second substrate 210 , and a polarization layer may be disposed to reduce external light reflection.

[0357] Next, refer to Fig. 20B , a cross section of a partial area of ​​the display area DA and a partial area of ​​the non-display area NA where a gate driver is provided will be described. Fig. 20A Description of constituent elements that are the same as the constituent elements in .

[0358] The third-first insulating layer 181a including an inorganic insulating material such as silicon nitride and silicon oxide may be disposed on the data conductor including the source electrode Sp and the drain electrode Dp. The third-first insulating layer 181a of the inorganic insulating layer may also be referred to as a passivation layer.

[0359] An additional conductive layer (Sp2 and Dp2) having a planar shape substantially the same as that of the data conductors Sp and Dp may be disposed on the third-first insulating layer 181a. The additional conductive layers Sp2 and Dp2 may include a plurality of conductive patterns disposed thereunder, the plurality of conductive patterns having a planar shape substantially the same as that of the data conductors including the source electrode Sp and the drain electrode Dp, and being electrically connected to the data conductors including the source electrode Sp and the drain electrode Dp. In an exemplary embodiment, the additional conductive layer (Sp2 and Dp2) may be omitted.

[0360] The same voltage as that of the data conductor including the source electrode Sp and the drain electrode Dp may be applied to the conductive pattern including the additional conductive layer (Sp2 and Dp2), thereby reducing resistance. The additional conductive layer (Sp2 and Dp2) may include a material that is the same as or similar to that of the data conductor including the source electrode Sp and the drain electrode Dp.

[0361] The third-second insulating layer 181b may be disposed on the additional conductive layer (Sp2 and Dp2). In an exemplary embodiment, the third-second insulating layer 181b may include an inorganic insulating material such as silicon nitride or silicon oxide.

[0362] An ohmic contact (or contact member) 190 may be provided on the third-second insulating layer 181b. The ohmic contact (or contact member) 190 may be connected to a drain electrode additional conductive layer Dp2 that is provided in the display area DA and overlaps the drain electrode Dp in the additional conductive layer (Sp2 and Dp2) through a contact hole. The first electrode E1 and the drain electrode Dp, which will be described later, may be connected through the ohmic contact 190.

[0363] The ohmic contact 190 improves the adhesion of the drain electrode additional conductive layer Dp2 and the first electrode E1 that are in contact with each other, and can prevent oxidation of the exposed drain electrode additional conductive layer Dp2. In particular, when the drain electrode additional conductive layer Dp2 includes copper, oxidation of copper can be prevented. To this end, the ohmic contact (or contact member) 190 may include a conductive material that can prevent corrosion of the drain electrode additional conductive layer Dp2 by covering the drain electrode additional conductive layer Dp2, for example, a conductive material that can prevent corrosion of copper. In an exemplary embodiment, the ohmic contact 190 may include a conductive material such as a metal oxide such as ITO or IZO.

[0364] A fourth insulating layer 182 including an organic insulating material may be disposed on the third-second insulating layer 181b and the ohmic contact 190. In an exemplary embodiment, the fourth insulating layer 182 is an organic insulating layer that may include, for example, polyimide, acrylic-based polymer, and siloxane-based polymer, etc. The fourth insulating layer 182 may also be referred to as a planarization layer.

[0365] Next, refer to Fig. 20C The cross section of the partial area of ​​the display area DA and the partial area of ​​the non-display area NA where the gate driver is disposed is described. Fig. 20B Description of constituent elements that are the same as the constituent elements in .

[0366] Reference Fig. 20C , the display device in the exemplary embodiment may not include Fig. 20B The ohmic contact (or contact member) 190 described in the embodiment of the present invention may be formed. The fourth insulating layer 182 may be directly disposed on the third-second insulating layer 181b. The first electrode E1 may contact the drain electrode additional conductive layer Dp2 through the contact hole of the fourth insulating layer 182 and the third-second insulating layer 181b. The first electrode E1 may be connected to the drain electrode Dp through the drain electrode additional conductive layer Dp2. Next, referring to FIG. 20A to FIG. 20C and Fig.21 One of the above describes the planar shape of the plurality of transistors TRd provided in the gate driver GD. In this case, the plurality of transistors TRd may be any transistor included in the gate driver GD, and may be Fig.18 The first transistor T1 shown in FIG. A plurality of transistors TRd provided in the gate driver GD may be electrically connected.

[0367] Reference Fig.21 In an exemplary embodiment, the first metal layer LB1 may be provided in the gate driver GD. The first metal layer LB1 may overlap at least a portion of the plurality of transistors TRd provided in the gate driver GD. As described above, the plurality of transistors TRd may be Fig.18 The first transistor T1 is shown, and the first metal layer LB1 may overlap the plurality of first transistors TRd. In an exemplary embodiment, the first metal layer LB1 may have a plate shape so as to overlap all the plurality of first transistors TRd located in the gate driver GD.

[0368] The first metal layer LB1 can receive a predetermined voltage. When a voltage is applied to the first metal layer LB1, the current flowing compared to the same voltage can be increased by applying a reverse bias voltage. In this case, since the area occupied by the first transistor TRd of the gate driver GD can be reduced, the area of ​​the non-display area NA can be reduced.

[0369] Although not shown in the present specification, the first metal layer LB1 may be connected to the gate electrode or the source electrode through a contact hole outside the display region to receive a predetermined voltage, but is not limited thereto.

[0370] The semiconductor layer Ad may be disposed on the first metal layer LB1 and the buffer layer 120. The gate driver GD may include a plurality of semiconductor layers Ad. The plurality of semiconductor layers Ad may be repeatedly disposed along the first direction DR1. The semiconductor layer Ad may have a stripe shape extending along the second direction DR2, but is not limited thereto.

[0371] A plurality of gate lines G1 including gate electrodes Gd may be disposed on the semiconductor layer Ad and the first insulating layer 140. Each of the plurality of gate lines G1 may have a stripe shape extending along the first direction DR1. The plurality of gate lines G1 may be repeatedly disposed along the second direction DR2.

[0372] Next, a first signal line SL1 including a source electrode Sd and a second signal line SL2 including a drain electrode Dd may be disposed on the gate line G1 and the second insulating layer 160 .

[0373] Each of the first signal line SL1 and the second signal line SL2 may have a form extending along the first direction DR1 and may have, for example, a stripe form. The first signal line SL1 and the second signal line SL2 may be alternately disposed along the second direction DR2.

[0374] The source electrode Sd included in the first signal line SL1 may be connected to the semiconductor layer Ad through the contact hole CNT defined in the first and second insulating layers 140 and 160. The drain electrode Dd included in the second signal line SL2 is connected to the semiconductor layer Ad through the contact hole CNT defined in the first and second insulating layers 140 and 160.

[0375] In an exemplary embodiment, for example, the transistor TRd provided in the gate driver GD may include a gate electrode Gd, a semiconductor layer Ad, a source electrode Sd, and a drain electrode Dd, and may be Fig.18 The first transistor T1 shown in FIG. Fig.18 , a gate electrode Gd provided in the gate driver GD may be connected to the first node Q, a clock signal may be applied to the source electrode Sd, and a predetermined gate signal may be output through the drain electrode Dd.

[0376] In an exemplary embodiment, the first metal layer LB1 may overlap a majority of a region occupied by the transistor TRd corresponding to the first transistor in the gate driver GD. The first metal layer LB1 may have a plate shape overlapping this region.

[0377] The semiconductor layer Ad may be disposed only on the upper surface of the first metal layer LB1. In a plan view, an edge of the semiconductor layer Ad may be disposed inside an edge of the first metal layer LB1. A planar width of the semiconductor layer Ad may be smaller than a planar width of the first metal layer LB1.

[0378] The first metal layer LB1 may have a considerable thickness. In this case, the semiconductor layer Ad included in the gate driver GD in the exemplary embodiment may be disposed only on the first metal layer LB1, and thus may be provided without a step, thereby providing a display device with excellent reliability without disconnecting the semiconductor layer Ad.

[0379] Next, refer to FIG. 22A to FIG. 22C and Fig.23 The display device in the exemplary embodiment is described. FIG. 20A to FIG. 20C and Fig.21 Describe the components.

[0380] First, refer to Fig.22A and Fig.23 , the gate driver GD includes a plurality of semiconductor layers Ad. The gate driver GD in the exemplary embodiment may include n semiconductor layers Ad repeatedly disposed along the first direction DR1.

[0381] The first metal layer LB1 overlapping the non-display area NA (particularly the gate driver GD in the exemplary embodiment) may include a plurality of first auxiliary metal layers LB1-1 to LB1-n. Similar to the semiconductor layer Ad, the gate driver GD may include n first auxiliary metal layers LB1-1 to LB1-n.

[0382] Each first auxiliary metal layer LB1-n may have a stripe shape extending along the second direction DR2 like the semiconductor layer Ad. A plurality of first auxiliary metal layers LB1-1 to LB1-n may be repeatedly disposed along the first direction DR1. In a plan view, a plurality of first auxiliary metal layers LB1-1 to LB1-n may be spaced apart from each other along the first direction DR1. In this case, the interval between adjacent first auxiliary metal layers may be smaller than the interval between adjacent semiconductor layers.

[0383] One first auxiliary metal layer LB1-n may overlap one semiconductor layer Ad. In this case, a width W4 of the first auxiliary metal layer LB1-n may be greater than a width W5 of the semiconductor layer Ad. The semiconductor layer Ad may be disposed on an upper surface of the first auxiliary metal layer LB1-n. The semiconductor layer Ad may completely overlap the first auxiliary metal layer LB1-n. An area occupied by the first auxiliary metal layer LB1-n in the gate driver GD may be greater than an area occupied by the semiconductor layer Ad.

[0384] The specification describes an exemplary embodiment in which one first auxiliary metal layer LB1-n overlaps one semiconductor layer Ad, but is not limited thereto. In an exemplary embodiment, for example, one first auxiliary metal layer LB1-n may overlap two, three or more semiconductor layers Ad, wherein the edge of the semiconductor layer Ad may be disposed within the edge of the first auxiliary metal layer LB1-n.

[0385] When the semiconductor layer has a step while being disposed along the side of the first metal layer LB1, the semiconductor layer may be disconnected as the thickness of the first metal layer LB1 increases, and the reliability of the display device may be reduced.

[0386] In an exemplary embodiment, the first metal layer LB1 may have a considerable thickness. In this case, the semiconductor layer Ad included in the gate driver GD in the exemplary embodiment may be disposed only on the first metal layer LB1 and thus may be provided without a step, thereby providing a display device with excellent reliability without disconnecting the semiconductor layer Ad.

[0387] exist Fig. 22B The non-display area NA in the exemplary embodiment of may be similar to that in Fig.22A The non-display area NA in the exemplary embodiment of Fig. 22B The non-display area NA of the exemplary embodiment may further include a third-second insulating layer 181b disposed between the third-first insulating layer 181a and the fourth insulating layer 182. Also, the display area DA may be Fig. 20B The display area DA is the same as described in .

[0388] according to Fig. 22C The non-display area NA of the exemplary embodiment may be similar to Fig. 22B In the exemplary embodiment of the non-display area NA. Fig. 22C The display area DA of the exemplary embodiment may be Fig. 20C The display area DA is the same as described in .

[0389] While the invention has been described in conjunction with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, wherein: The display device comprises: substrate; a metal layer disposed on the substrate; a first conductive layer disposed on the metal layer and comprising a lower pattern; An active layer, disposed on the first conductive layer; a second conductive layer, disposed on the active layer and comprising a first gate electrode; a pixel electrode, disposed on the second conductive layer; and an emission layer and a common electrode disposed on the pixel electrode, wherein the metal layer overlaps the entire surface of the substrate, An opening is defined in the metal layer overlapping the active layer.

2. The display device according to claim 1, wherein: The display device further includes: The third conductive layer is disposed between the second conductive layer and the pixel electrode and includes a common voltage line, a driving voltage line and a data line.

3. The display device according to claim 2, wherein: The metal layer includes at least one of a first voltage metal layer connected to the driving voltage line and a second voltage metal layer connected to the common voltage line.

4. The display device according to claim 3, wherein: The metal layer includes the first voltage metal layer and the second voltage metal layer, and The first voltage metal layer and the second voltage metal layer are spaced apart from each other.

5. The display device according to claim 4, wherein: Openings overlapping the active layer are defined in the first voltage metal layer and the second voltage metal layer.

6. The display device according to claim 2, wherein: The data lines include a first data line, a second data line and a third data line, and The metal layer includes at least one of a first sub-metal layer connected to the first data line, a second sub-metal layer connected to the second data line, and a third sub-metal layer connected to the third data line.

7. The display device according to claim 6, wherein: The metal layer includes the first sub-metal layer, the second sub-metal layer and the third sub-metal layer, and An opening overlapping the active layer is defined in the first sub-metal layer, the second sub-metal layer, and the third sub-metal layer.

8. The display device according to claim 6, wherein: The first sub-metal layer, the second sub-metal layer, and the third sub-metal layer are spaced apart from each other.

9. A display device, wherein: The display device comprises: substrate; a metal layer disposed on the substrate; a first conductive layer disposed on the metal layer and comprising a lower pattern; An active layer, disposed on the first conductive layer; a second conductive layer, disposed on the active layer and comprising a first gate electrode; a pixel electrode, disposed on the second conductive layer; and an emission layer and a common electrode disposed on the pixel electrode, Wherein, the thickness of the metal layer is 6000 angstroms to 10000 angstroms, The metal layer overlaps the entire surface of the substrate, An opening is defined in the metal layer overlapping the active layer.

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