RF Switch with Compensation

Abstract

Embodiments of the present disclosure generally relate to RF switches with compensation. A radio frequency switch includes a first transistor and a second transistor coupled together to establish a switchable RF path, and a first compensation network coupled between a body terminal of the first transistor and a drain terminal of the second transistor, wherein the first compensation network establishes a path for current flow between the body terminal of the first transistor and the drain terminal of the second transistor, and the first compensation network blocks current flow in a second direction opposite to the first direction.

Description

Technical Field

[0001] The present invention generally relates to a radio frequency (RF) switch having a compensation circuit and a corresponding compensation method. Background Art

[0002] High voltage RF switches are known in the art to be used in various applications (such as tuning of high voltage RF antennas). An RF switch typically includes a stack of multiple transistors in a series configuration between an RF source and ground, and typically includes an accompanying bias circuit for biasing nodes (also referred to herein as "terminals") of the multiple transistors. While the stacked configuration of an RF switch is well suited for many applications, parasitic leakage currents can begin to flow into and out of the multiple transistors at extremely high peak RF voltages (e.g., where the RF switch is coupled between an RF source and ground). The parasitic leakage currents can change the designed bias voltage value of the bias circuit. Summary of the invention

[0003] According to one embodiment, a radio frequency (RF) switching device includes: a first transistor and a second transistor, each transistor including: a gate terminal; a source terminal; a drain terminal and a body (or "body") terminal, wherein the first transistor and the second transistor are coupled together in series to establish a switchable RF path; and a first compensation network coupled between the body terminal of the first transistor and the drain terminal of the second transistor, wherein the first compensation network is configured to establish a path for current flow in a first direction between the body terminal of the first transistor and the drain terminal of the second transistor, and is configured to block current flow in a second direction opposite to the first direction between the body terminal of the first transistor and the drain terminal of the second transistor.

[0004] According to another embodiment, a radio frequency (RF) switching device includes: a plurality of transistors connected in series to form a switchable current path; a plurality of first compensation networks coupled between a body terminal of an Nth transistor of the plurality of transistors and a drain terminal of an (N+1)th transistor of the plurality of transistors, wherein each of the first compensation networks includes a rectifying element.

[0005] According to another embodiment, a method of compensating a radio frequency (RF) switching device, the radio frequency (RF) switching device including a first transistor and a second transistor, the first transistor and the second transistor forming a switchable current path, the method including: generating a first compensation current in a first direction between a body terminal of the first transistor and a drain terminal of the second transistor, and blocking a current flow in a second direction opposite to the first direction between the body terminal of the first transistor and the drain terminal of the second transistor.

[0006] According to another embodiment, a radio frequency (RF) switching device includes a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled in series at a common node to establish a switchable RF path between a load terminal of the second transistor and a load terminal of the first transistor; and a compensation network coupled between a body terminal of the first transistor and a load terminal of the second transistor, wherein the compensation network is configured to establish a path for current flow in a first direction between the body terminal of the first transistor and the load terminal of the second transistor, and the compensation network is configured to block current flow between the body terminal of the first transistor and the load terminal of the second transistor in a second direction opposite to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A block diagram of an RF system embodiment is illustrated, the RF system embodiment comprising: a transceiver, an antenna tuner including a plurality of capacitors and an RF switch, an antenna, and a controller;

[0009] Figure 2A is a circuit diagram of an RF switching device including an exemplary bias network;

[0010] Figure 2B is exposed to high RF voltage Figure 2A A circuit diagram of an RF switching device that creates a leakage current and a corresponding voltage that deviates from a designed bias voltage;

[0011] Figure 3 is Figure 2A and Figure 2B A circuit diagram of an RF switch device embodiment of , but wherein the bias current is removed and includes a leakage current compensation circuit;

[0012] Figure 4 The diagram shows a method according to an embodiment of the present invention. Figure 3 The typical response of the leakage current compensation network shown in IV;

[0013] Figure 5 is a circuit diagram illustrating current distribution in a compensated RF switching device including a bias circuit according to an embodiment;

[0014] Figure 6 illustrates an example of a specific implementation of a compensation network according to an embodiment;

[0015] Figure 7 is a circuit diagram of another embodiment of an RF switch device including a leakage current compensation circuit;

[0016] Fig. 8A and Figure 8B is a circuit diagram of another RF switch device embodiment including a leakage current compensation circuit;

[0017] Fig.9A and Fig. 9B is a circuit diagram of another RF switch device embodiment including a plurality of transistors and a plurality of leakage current compensation circuits;

[0018] Fig. 10A , Fig. 10B and Fig.11 is a circuit diagram of another RF switch device embodiment including a plurality of transistors and at least one leakage current compensation circuit;

[0019] Fig.12 is a circuit diagram of a PMOS-based RF switch device including a leakage current compensation circuit according to an embodiment; and

[0020] Fig.13 is a circuit diagram of an RF switching device including an alternative bias circuit.

[0021] Unless otherwise indicated, corresponding reference numerals and symbols in the different drawings refer to corresponding parts. The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. In order to more clearly illustrate certain embodiments, letters indicating variations of the same structure, material, or processing step may follow the figure numbers. DETAILED DESCRIPTION

[0022] The high voltage RF switch described below can be used as, for example, an antenna tuning switchable element, and in particular can be used in high voltage antenna tuning switches and tunable passive components (e.g., C tuners (capacitance tuners), Z tuners (impedance tuners), etc.). High voltage RF switches are commonly used in cellular handsets to tune the impedance and radiation characteristics of compact antennas. They are typically attached between the feed point or aperture point of the antenna and ground via an external surface mount device (SMD) capacitor or inductor.

[0023] In various embodiments illustrated and described below, one or more leakage current compensation circuits are used to mitigate the effects of leakage currents that flow from the drain and source to the body of a MOS transistor in an RF switch device. In various embodiments, these leakage compensation circuits may include nonlinear elements (such as diodes or other rectifying elements). By compensating for these leakage currents, shifts in the bias voltage of the design of the RF switch caused by leakage currents may be mitigated and / or avoided.

[0024] The leakage current mentioned in this article can include gate-induced drain leakage current and source leakage current (GIDL and GISL). GIDL and GISL are gsA voltage flows from the drain terminal and the source terminal into the body of the RF switch transistor. When GIDL / GISL leakage currents flow out of or into the high impedance bias resistor, these GIDL / GISL leakage currents shift the operating point of the switching transistor in the RF switch. According to an embodiment, when compared to an uncompensated RF switch, the leakage compensation circuit described herein helps to make the operating point of the switching transistor in the RF switch closer to the originally designed operating point despite the presence of significant leakage current. GIDL / GISL leakage currents are caused by quantum mechanical effects and changes in carrier transport within the switching transistor. For example, GIDL leakage currents are caused at least in part by tunneling in a narrow depletion region at the drain below the gate oxide.

[0025] Figure 1 An RF system 100 that can be configured to utilize an RF switch device embodiment is illustrated. As shown, the RF system 100 includes an RF transceiver 102 coupled to an antenna 106 via an antenna tuner 104. The antenna tuner includes parallel capacitors C1, C2, and C3, which can be selectively coupled to the antenna 106 via switches S1, S2, S3, S4, S5, and S6. In various embodiments, the switches S1, S2, S3, S4, S5, and S6 can be implemented using the RF switch device described herein. During operation, the controller 108 provides control signals that selectively turn on and off the switches S1, S2, S3, S4, S5, and S6 according to the antenna settings provided by the transceiver 102. The switch configuration of the antenna tuner can be used to provide RF matching between the antenna 106 and the transceiver 102 at various frequencies. For example, the RF system 100 can be used in multi-band cellular communication applications. It should be understood that RF system 100 is only one example of many applications that may utilize RF switch device embodiments. RF switches may be used in applications requiring signal selection switching (eg, for signal routing between instruments and devices under test in microwave test systems).

[0026] exist Figure 1 , representative RF switch nodes 110, 112, 114, and 116 are also shown to further illustrate the RF voltages applied across the switches. For example, the first switch node 110 of switch S5 is coupled to an RF voltage source provided by antenna 106. The second switch node 112 is coupled to an intermediate RF voltage source provided by the first node of capacitor C3. The first switch node 114 of switch S6 is coupled to another intermediate RF voltage source provided by the second node of capacitor C3. The second switch node 116 of switch S6 is directly coupled to ground. Switches S5 and S6 are switched between an "on" state and an "off" state by the application of transistor gate voltages, which are referred to below as Figure 2A and Figure 2B Detailed description is provided in the drawings and the like. Thus, in an embodiment, the RF switch may be positioned between the first source of the RF voltage and the second source of the RF voltage, or between the RF voltage and ground. For example, other RF voltage sources may be used, including RF voltage sources for providing an AC voltage signal.

[0027] A common challenge in antenna tuning switch design is to achieve high voltage (up to 80V or above peak) handling at RF frequencies while maintaining the same or similar performance as at lower RF voltages. The switches are implemented as stacked MOSFET devices on silicon or other substrates.

[0028] In various embodiments, a MOS transistor used in an RF switch device includes: a gate terminal, a source terminal, a drain terminal, and a body terminal. By using a high-ohmic linear resistor, the MOS transistor is biased to a desired operating point. In some embodiments, a high-resistance DC path is provided for all terminals (including the gate, source, drain, and body terminals). After applying a target DC voltage on each terminal via a high-ohmic bias resistor, the gate-source voltage, the gate-drain voltage, the drain-body voltage, and the source-body voltage define the operating point of the MOS transistor in the switch device.

[0029] Parasitic leakage currents can be generated at high operating voltages and can flow into high ohmic bias resistors, generating significant voltage drops. As a result, the operating point of the desired high voltage RF switch can be shifted from the desired operating point, resulting in a loss of performance and, in extreme cases, signal distortion.

[0030] Figure 2A , Figure 2B , Figure 3 , Figure 4 and Figure 5 The series of circuit diagrams described below are presented to further aid in understanding both the nature and impact of these leakage currents, and the solutions provided by leakage compensation circuit embodiments. Figure 2A is a circuit diagram of a portion of an uncompensated RF switching device including a bias circuit. Figure 2B with Figure 2A The circuit diagram is the same as shown in Figure 2B It is shown that once the RF switching device is exposed to a high voltage RF signal, the gate introduces drain leakage current and source leakage current. Figure 3 is a circuit diagram of the same portion of an RF switch device including a leakage current compensation circuit, but with the bias circuit removed for ease of understanding the operation of the compensation circuit. Figure 4 illustrates the nonlinear nature of the leakage compensation circuit, and Figure 5The same portion of the RF switch arrangement as previously illustrated is shown, but includes both bias circuitry and leakage compensation circuitry.

[0031] Figure 2A An exemplary circuit portion 200 of a high voltage RF switch including a first NMOS transistor M1 connected in series with a second NMOS transistor M2 is shown. In the series connection, the source node of transistor M1 is coupled to the drain node of transistor M2. The drain node of transistor M2 is directly coupled to the RF high voltage source, or the drain node of transistor M2 is indirectly coupled to the RF high voltage source through one or more transistors (also connected in series). The source node of transistor M1 is directly coupled to ground or another RF high voltage source, or the source node of transistor M1 is indirectly coupled to another RF high voltage source through one or more transistors (also connected in series). The gate node of transistor M1 is connected to the ground through a bias resistor R g1 Coupled to the gate bias voltage V g , and the gate node of transistor M2 is biased by resistor R g2 Coupled to the gate bias voltage V g The body node of transistor M1 is connected to the bias resistor R b1 Coupled to the body bias voltage V b , and the body node of transistor M2 is biased by resistor R b2 Coupled to the body bias voltage V b The source-drain node between transistors M1 and M2 is connected via resistor R s1 Coupled to the bias voltage V s The above bias circuit can be repeated and used in Figure 2A Any additional series transistors not shown in the figure. The gate nodes of the first transistor and the second transistor are switched to turn the transistors on and off. In one embodiment, the switchable current path through the switch is the path from the drain node to the source node of the second transistor M2 and the path from the drain node to the source node of the first transistor M1.

[0032] exist Figure 2A The RF switch arrangement shown in FIG. 1 provides a high impedance at the source-drain node. sd1 , and provides high impedance at the body node r b1 , for other RF switch devices described below, r sd1 and r b1 May have different absolute values.

[0033] Figure 2B is a circuit diagram of an RF switch device 200 exposed to a high RF voltage. Therefore, in addition to the additional marker leakage current and marker shift bias voltage, Figure 2B The circuit is Figure 2AThe leakage current generated by exposure to applied high RF voltage and its effect on the bias circuit will be described in further detail below.

[0034] When the RF switch 200 is exposed to high peak voltages at RF frequencies (defined as the peak voltage at which the voltage drop across each individual transistor in the stack approaches the maximum allowed level for a given MOS transistor type), the parasitic leakage current i leakd and i leaks Starts to flow from the drain and source terminals into the body terminals of the corresponding MOS transistor in the RF switch device. This current shifts the operating point of the MOS transistor when flowing into the corresponding high-ohmic bias resistor: the source voltage shift value is ΔV re1 =R s1 (i leakd +i leaks ); and the body voltage shift value is ΔV rb1 =R b1 (i leakd +i leake ). The bias shift effect of parasitic leakage current is illustrated in FIG2 .

[0035] Figure 2A and Figure 2B is a circuit diagram of a bias network in an RF switching device having two MOS transistors. Figure 2A and Figure 2B The circuits of FIG. 1 show two transistors coupled in a series arrangement, but those skilled in the art will appreciate that these circuits may be part of a larger high voltage RF switch including multiple transistors coupled in series (e.g., ten or twenty such transistors in one embodiment). The total number of transistors used in the switch is determined by the breakdown voltage of each transistor in the switch and the maximum peak RF voltage applied to the switch.

[0036] Figure 3 300 is a circuit diagram of an embodiment of an RF switch device including transistors M1 and M2 (the switch device herein is also referred to as an RF switch apparatus and may be a compensated or uncompensated RF switch including a plurality of RF transistors in a series stacked configuration), and a leakage current compensation circuit C1. Figure 3 In order to facilitate understanding of the leakage current compensation circuit C1, the previously described Figure 2A and Figure 2B The bias circuit shown in FIG. 1 can be used with the leakage current compensation circuit C1 in Figure 2A or Figure 2BThe leakage current compensation circuit C1 may also be used with the bias circuit illustrated in FIG. 1 or other bias circuits. One or more leakage compensation circuits may be used in the RF switch to direct the leakage current from the bias resistor into the RF switch in a manner that does not deviate from the design nominal value so that the desired bias voltage is achieved. In an embodiment, one or two compensation circuits are provided for each transistor in the RF switch; however, there does not need to be a one-to-one correspondence between the compensation circuits and the transistors. Multiple compensation circuits (or even one compensation circuit) with fewer than a plurality of transistors in the RF switch will still have a positive effect on maintaining the bias voltage when compared to an uncompensated RF switch.

[0037] As in Figure 3 As shown in FIG. 1 , according to one embodiment, a leakage current compensation circuit C1 including a nonlinear compensation network is coupled between a body terminal of a first transistor M1 and a drain terminal of a second transistor M2 in an RF switch device 300. The nonlinear compensation network of the leakage current compensation circuit C1 is configured to bypass current in a first direction from the body terminal of the first transistor M1 to the drain terminal of the second transistor M2 (large arrow mark 302) across a given voltage on the network, and to block current in a second direction from the drain terminal of the second transistor M2 to the body terminal of the first transistor M1 (small arrow mark 304) if the applied voltage is reversed. In this manner, the leakage current is absorbed back into the RF switch stack through the leakage compensation circuit and is not available for shifting the desired bias voltage as described in further detail below, particularly with respect to FIG. Figure 5 Description.

[0038] In some embodiments, the RF switch device 300, other RF switch devices, and individual switch transistors such as transistors M1 and M2 described herein are symmetrical so that, for example, Figure 3 The source and drain labels shown in are interchangeable. In some embodiments, the individual switch transistors may be physically symmetrical, with the layout and configuration of the source and drain being substantially the same. Thus, the drain may be designated as a load terminal, and the source may also be designated as a load terminal. Thus, in Figure 3In the embodiment, the RF switch device 300 includes a first transistor M1 and a second transistor M2 coupled in series at a common node (the source of transistor M2 and the drain of transistor M1) to establish a switchable RF path between a load terminal of transistor M2 (the drain of transistor M2) and a load terminal of transistor M1 (the source of transistor M1) and a compensation network coupled between a body terminal of transistor M1 and a load terminal of transistor M2, wherein the compensation network is configured to establish a path for current flow between the body terminal of the first transistor and the load terminal of the second transistor in a first direction, and to block current flowing between the body terminal of the first transistor and the load terminal of the second transistor in a second direction opposite to the first direction.

[0039] Figure 4 FIG408 shows a typical response I-V 408 of the leakage current compensation network C1 according to an embodiment. Figure 4 As shown, if the characteristic IV 408 of the compensation network C1 is given by the function I c (V c ) description, where I c is the current flowing through network 400, and V c is the voltage applied to the network, then the following relationship in equation [1] generally applies:

[0040] I c (V c )>-I c (-V c ).[1]

[0041] Equation [1] may not apply under certain abnormal conditions, such as during breakdown conditions of a diode or diode-connected transistor used in the compensation network.

[0042] Figure 5 is a circuit diagram illustrating current distribution in a compensated RF switching device according to an embodiment. Figure 5 shows the previous Figure 1 The RF switch circuit components and bias components are shown in Figure 2A and Figure 2B The leakage current tab shown in Figure 3 In addition, the leakage current compensation circuit shown in Figure 5 Included is a diagram of the "error current" flowing through the bias resistor, which is ideally minimized as described in further detail below.

[0043] As in Figure 5 As shown in FIG. 1 , the characteristics of the compensation network C1 are configured such that for a given RF operating voltage, the average current flowing from the body terminal of the first transistor M1 to the drain terminal of the second transistor M2 is proportional to (i leakd+i leaks ) is similar, so the leakage current from the body terminal is mainly transferred to the drain terminal of the second transistor, and only a part of the leakage current flows into the bias resistor.

[0044] The current in the compensated RF switch arrangement is summarized as follows: Each MOS transistor in the RF switch generates (i leakd +i leaks ) leakage current; the compensation network bypasses the body terminal of the first transistor M1 and the drain terminal of the second transistor M2 i between comp Current; Error current i error ((i leakd +i leaks ) and i comp The difference between the two) flows into the bias resistor; the leakage current compensation network C1 can be optimized to provide |i error <|i leakd +i leaks |, ideally|i error |=0. If the bias resistor R s2 and R b1 If the error current is minimized or reduced, the corresponding voltage drop across the bias resistors is also minimized or reduced, resulting in a smaller shift in the operating point at high power (high RF voltage applied) when compared to an uncompensated RF switch arrangement. The current compensation network can be configured to provide a current in excess of the leakage current (i leakd +i leaks ) of the compensation current i comp , so that i error The polarity is changed and the RF switch becomes overcompensated, which means that the gate-source bias voltage of the RF switching device increases as the applied RF voltage increases.

[0045] therefore, Figure 5 Explained according to Figure 2A and Figure 2B An example of a compensated RF switch device with a shunt portion and a drain / source bias network of the bias circuit shown in FIG. The leakage current compensation circuit C1 can also be used with any other configuration of the bias network if desired.

[0046] Figure 6 An example of a specific implementation of the compensation network C1 according to an embodiment is illustrated.

[0047] Various implementations of the compensation network C1 may be used, providing a response that generally satisfies the relationship shown in equation [1] (except for abnormal operating conditions, such as breakdown conditions). The network may be implemented using components such as passive components (including diodes, multiple diodes, and resistors), transistors in a diode configuration, and combinations of passive and active rectifying elements (including amplifiers, operational amplifiers in feedback loops), and other similar circuits. A list of possible implementations of the compensation network C1 includes, but is not limited to:

[0048] A semiconductor diode circuit 602 including a single diode 620, also referred to as a pn junction;

[0049] a semiconductor circuit 606 including a plurality of semiconductor diodes 620 and 624 coupled in series;

[0050] a semiconductor diode circuit 604 including a semiconductor diode and a resistor 622;

[0051] a semiconductor diode circuit 608 including a plurality of semiconductor diodes 620 and 624 coupled in series with a resistor 622;

[0052] a transistor circuit 610 including a diode-connected transistor 630 (diode-connected to transistor);

[0053] a transistor circuit 612 including a diode-connected transistor 630 coupled in series with a resistor 632;

[0054] a transistor circuit 614 including a diode-connected transistor 630 having a resistor 632 coupled in series with a channel; and

[0055] The circuit includes a diode-connected transistor 630 including a plurality of resistors 632 and 634 connected in series.

[0056] exist Figure 6The diode in can be realized by a diffusion region in silicon or other substrates, and can include a polysilicon diode, a Zener diode, a Schottky diode, or any other type of diode. The diode-connected transistor may include a diode-connected MOSFET, a diode-connected bipolar device (such as a BJT), a junction field effect transistor, and any other type of transistor. In one embodiment, the resistor may include an integrated circuit diffusion resistor or a metal resistor, and the resistor may be sized to match the peak leakage current. For example, for the leakage current circuit 604, the voltage across the resistor 622 is determined by measuring the voltage across the circuit 604 minus the voltage across the diode 620. The remaining voltage across the resistor 622 is divided by the peak leakage current desired to be compensated to determine the value of the resistor 622. Therefore, the resistor 622 generates a matching current less than or equal to the peak leakage current. In the case of an over-compensated RF switch, the resistor 622 generates a matching current that exceeds the peak leakage current.

[0057] There are other implementations of the previously described nonlinear functions with rectification characteristics that can be used that allow larger currents to be bypassed in directions other than the opposite direction.Many integrated and discrete components can be used to implement the rectification characteristics described herein for use in leakage current compensation circuits.

[0058] Figure 7 is a circuit diagram 700 of another RF switch device embodiment, which includes, for example, the aforementioned Figure 3 The leakage current compensation circuit C1 is shown in FIG. Figure 7 The bias circuit is not shown in FIG, but will be implemented in a normal application. The transistors M1 and M2 and the leakage current compensation circuit C1 are Figure 7 and their interconnection has been described previously. Figure 7 In FIG. 1 , note that an additional transistor M3 is inserted in series between transistors M1 and M2. That is, the drain node of transistor M3 is coupled to the source node of transistor M2, and the source node of transistor M3 is coupled to the drain node of transistor M1. Figure 7 In the configuration shown in FIG, the leakage current flowing out of the body node of transistor M1 is bypassed by the action of the leakage current compensation circuit C1 and flows into the drain of transistor M2. Additional transistors (one, two or more such transistors) connected in series, such as transistor M3, may be inserted between transistors M1 and M2.

[0059] Fig. 8A and Figure 8Bis a circuit diagram of another RF switch device embodiment, including a leakage current compensation circuit for compensating for leakage current generated during both the positive half-cycle and the negative half-cycle of a sinusoidal or other periodic RF signal waveform applied to the RF switch device. Fig. 8A and 8B The bias circuit has been omitted for clarity, but would be included in a normal application.

[0060] Fig. 8A A circuit 800A is illustrated that includes transistors M1, M2 and a leakage current compensation circuit C1, all of which are previously described with respect to e.g. Figure 3 described. In addition, Fig. 8A A second leakage current compensation circuit C2 is shown coupled between the source node of transistor M1 and the body node of transistor M2. Fig. 8A In the configuration shown in , the leakage current flowing out of the body node of transistor M1 is bypassed by the action of the leakage current compensation circuit C1 and flows into the drain of transistor M2 in the first half cycle of the applied RF signal waveform. Fig. 8A In the configuration shown in FIG. 1 , the leakage current flowing out of the body node of transistor M2 is bypassed by the action of leakage current compensation circuit C2 and flows into the drain of transistor M1 in the second half cycle of the applied RF signal waveform. Figure 8B The specific example shown in further details explains the operation of the compensation circuits C1 and C2.

[0061] Figure 8B The diagram includes Fig. 8A The transistors M1 and M2 are shown in the circuit 800B. Figure 8B As shown in , the leakage current compensation circuit C1 as a specific implementation includes a diode D1 and a resistor R1 connected in series. Figure 8B As shown in FIG. 8 , the leakage current compensation circuit C2 includes a diode D2 and a resistor R2 connected in series as a specific implementation. During the positive half cycle 802 of the applied RF voltage, the parasitic leakage current i gidl and i gidl The parasitic leakage current i flows out of the body node of transistor M2 via diode D1 and resistor R1 and into the source node of transistor M1. If resistor R1 is sized correctly, the current flowing out of the body node of transistor M2 will be zero. During the negative half cycle 804 of the applied RF voltage, the parasitic leakage current i gidl and i gisl The current flowing out of the body of transistor M1 will be zero if resistor R2 is sized correctly.

[0062] exist Figure 8BAlso illustrated in FIG. 8 is an exemplary DC bias voltage and peak AC applied RF voltage during the positive half cycle 802 and the negative half cycle 804. The DC bias voltage and peak AC applied RF voltage are examples only, and other voltages may be used in different applications. If other transistors (not shown) other than transistors M1 and M2 in the RF switch stack are analyzed, different voltages will also appear.

[0063] During the positive half cycle 802, the peak AC voltage (V d2 ) is 6 volts, the peak AC voltage (V b2 ) is 4.5 volts, the peak AC voltage (V d1 ) is 3 volts, the peak AC voltage (V b1 ) is 1.5 volts. Figure 8B The source of transistor M1 in is coupled to ground. During the positive half cycle 802, the DC bias voltage (V d2 ), the DC bias voltage (V d1 ) and the DC bias voltage (V s1 ) are set to zero volts. The DC bias voltage (V b2 ) and the DC bias voltage (V b1 ) are both set to negative 2 volts. Therefore, the sum of the AC and DC voltages at the drain of transistor M2 (V d2 ) is 6 volts, the sum of the AC and DC voltages at the bulk node of transistor M2 (V b2 ) is 2.5 volts, the sum of the AC and DC voltages at the drain node of transistor M1 (V d1 ) is 3 volts, the sum of the AC and DC voltages at the bulk node of transistor M1 (V b1 ) is -0.5 volts, the sum of the AC and DC voltages at the source node of transistor M1 is zero volts. Therefore, the voltage 806 across the first leakage current compensation circuit including diode D1 and resistor R1 is 2.5 volts. Therefore, resistor R1 can be appropriately sized to generate less than or equal to the parasitic leakage current i gidl and i gisl The corresponding compensation current of the sum of φI and φI causes only a small or error-free current to flow into or out of the body node of transistor M2.

[0064] During the negative half cycle 804, the peak AC voltage (V d2) is negative 6 volts, and the peak AC voltage (V b2 ) is -4.5 volts, the peak AC voltage (V d1 ) is negative 3 volts, and the peak AC voltage (V b1 ) is -1.5 volts. Figure 8B The source of transistor M1 is coupled to ground. During the negative half cycle 804, the DC bias voltage (V d2 ), the DC bias voltage at the drain node of transistor M1 (V d1 ) and the DC bias voltage (V s1 ) are set to zero volts. The DC bias voltage (V b2 ) and the DC bias voltage (V b1 ) are both set to negative 2 volts. Therefore, the sum of the AC and DC voltages at the drain of transistor M2 (V d2 ) is negative 6 volts, the sum of the AC and DC voltages at the body node of transistor M2 (V b2 ) is -6.5 volts, the sum of the AC and DC voltages at the drain node of transistor M1 (V d1 ) is negative 3 volts, the sum of the AC and DC voltages at the body node of transistor M1 (V b1 ) is -3.5 volts, the sum of the AC and DC voltages at the source node of transistor M1 is zero volts. Therefore, the voltage 808 across the second leakage compensation circuit including diode D2 and resistor R2 is -2.5 volts. Therefore, resistor R2 can be appropriately sized to generate less than or equal to the parasitic leakage current i gidl and i gisl The corresponding compensation current of and , causes only a small or no error current to flow into or out of the body node of transistor M1.

[0065] Fig.9A and Fig. 9B is a circuit diagram of another RF switch device embodiment including a plurality of transistors and including a corresponding plurality of leakage current compensation circuits. Fig.9A and Fig. 9B In the drawings, bias circuits are not shown for clarity, but would typically be included in the normal operating configuration.

[0066] Fig.9A1. An RF switch device 900A is illustrated, which includes a plurality of transistors M1, M2, M3, M4 and M5 coupled in series between source and drain terminals, and a corresponding plurality of compensation networks C coupled between body terminals of respective transistors and drain terminals of adjacent transistors in an RF stack. 11 , C 12 , C 13 and C 14 .exist Fig.9A In , any number of transistors may be used. The drain node of transistor M5 may be coupled to an RF voltage source, or to an additional series transistor that is in turn connected to the RF voltage source. Similarly, the source node of transistor M1 may be coupled to another RF voltage source or to ground, or to an additional series transistor that is in turn connected to another RF voltage source or to ground. Fig.9A In the embodiment of FIG. 1 , the leakage current flowing out of the body node of the transistor (e.g., the negative half cycle of the RF voltage source) flows through the corresponding compensation network and returns to the RF stack, so that the leakage current cannot flow into the bias circuit as described above (in FIG. 1 ). Fig.9A not shown).

[0067] Fig. 9B 9( a) but further comprising a plurality of anti-parallel compensation networks C coupled between the body nodes of respective transistors in the RF stack and the drain nodes of adjacent transistors in the RF stack. 21 , C 22 , C 23 and C 24 .exist Fig. 9B In the embodiment of FIG. 1 , the leakage current flowing out of the body node of the transistor (e.g., the positive half cycle of the RF voltage source) flows through the corresponding compensation network and flows back to the RF stack, so that the leakage current cannot flow into the bias circuit as described above (in the embodiment of FIG. 1 ). Fig. 9B ). Therefore, in Fig. 9B The RF switch device 900B shown in FIG. 1 is configured to compensate for leakage current in both half cycles of the sinusoidal or other periodic waveform of the applied RF voltage. Fig. 9B In the RF switch device 900B, two leakage current circuits (one for each half cycle) correspond to each transistor in the RF stack. Fig. 9B The configuration shown in provides the maximum compensation effect for the generated leakage current.

[0068] Fig. 10A , Fig. 10B and Fig.11is a circuit diagram of another RF switch device embodiment, which includes multiple transistors and includes at least one leakage current compensation circuit. As previously described, although in embodiments, one leakage current compensation circuit per transistor or two leakage current compensation circuits per transistor can provide maximum leakage current cancellation effects, any number of leakage current compensation circuits less than one or two leakage current compensation circuits per transistor can be used. When compared to an uncompensated RF switch, even one leakage current compensation circuit per RF switch will provide the benefits of leakage current cancellation and a corresponding improvement in maintaining bias voltage. Again, although for clarity Fig. 10A , Fig. 10B and Fig.11 Bias circuitry is not included but would normally be included in a normal application.

[0069] Fig. 10A and Fig. 10B Shown with Fig.9A and Fig. 9B , but wherein fewer compensation networks are coupled to a subset of transistors from the same plurality of transistors in the RF switch device. For example, in Fig. 10A In the embodiment, the switch device 1000A corresponds to Fig.9A The switching device is 900A, but only one compensation network C is used. 12 , the compensation network C 12 is coupled between the body node of transistor M2 and the drain node of transistor M3. Fig. 10B In the embodiment, the switch device 1000B corresponds to Fig. 9B The switching device 900B, but only two compensation networks C are used 12 and C 22 . Compensation Network C 12 is coupled between the body node of transistor M2 and the drain node of transistor M3, and the compensation network C 22 is coupled between the body node of transistor M3 and the source node of transistor M2. Fig.9A and Fig. 9B Other subsets of the compensation networks of the group of all compensation networks shown in FIG. 1 may be used. For example, although only compensation network C is depicted 12 , but it is possible to use only the compensation network C 11 or C 13 Alternatively, only the compensation network C can be used. 11 and C 14 , or compensation network C 12 and C 13 Regularly repeating compensation network patterns or randomly scattered compensation networks can be used to improve the leakage current characteristics of the RF switch.

[0070] exist Fig.11 Another RF switch device 1100 is shown in FIG. 1 , wherein at least one first compensation network (C 12 ) is coupled to a subset of transistors (transistors M2 and M3) from a plurality of transistors in the RF switch device, and at least one second compensation network (C 24 ) is coupled to another subset of transistors (transistors M4 and M5) from the plurality of transistors in the RF switch device. The switch device 1100 also generally corresponds to Fig. 9B Switching device 900B (using only compensation network C 12 and C 24 Other patterns of compensation networks and corresponding subsets of transistors may be used if desired. For example, certain patterns of compensation networks may be used to accommodate constraints on the layout of the integrated circuit. Fig.11 The compensation network C 12 and C 24 , but other compensation networks can be used (for example, compensation network C 11 and C 22 , or compensation network C 13 and C 22 ).exist Fig.11 Many other subsets of compensation networks can be used in Fig. 9B The maximum number of compensation networks shown is selected.

[0071] Fig.12 is a circuit diagram of a PMOS-based RF switch device 1200 according to an embodiment, and the PMOS-based RF switch device 1200 includes a leakage current compensation circuit C1. All of the embodiments described above relate to an RF switch device implemented using an NMOS switch transistor, which is an ideal way to implement an RF switch. However, if necessary to adapt to a specific application, the RF switch device can also be implemented using a PMOS transistor. Therefore, the switch device 1200 includes a first PMOS transistor P1 and a second PMOS transistor P2. The drain node of transistor P1 is coupled to the source node of transistor P2. The compensation network C1 is coupled between the drain node of transistor P2 and the body node of transistor P1. Fig.12 The biasing network and additional transistors (if any) in the switching device 1200 are not shown. The previous description of the operation of the compensation network C1 also applies to the Fig.12 The PMOS RF switch embodiment shown in FIG. 1 is different in that the compensation network polarity is reversed and the current direction is opposite. Therefore, Fig.12 Demonstrated implementation of a compensated RF switch using PMOS transistors.

[0072] Although it has been about Figure 2A and Figure 2BA bias network for an RF switch is shown and depicted, but various other possible arrangements of bias networks may be used, including but not limited to:

[0073] As in Figure 2A and Figure 2B As shown in FIG. 1 , a high ohmic resistor and a bias DC voltage V are coupled between the gate node, the source-drain node and the body node of the corresponding transistor in the stack. g 、V b 、V s ; as in Fig.13 As shown in , high ohmic resistors coupled between the gate nodes, source-drain nodes, and body nodes of each transistor in the stack form a series of bias resistor chains that are tapped to bias the voltage at one or more points along the chain; Figure 2A , Figure 2B and Fig.13 Any combination of bias circuit arrangements for a single high voltage RF switch as shown in Figure 2A , Figure 2B and Fig.13 Any combination of bias circuit arrangements for a single high voltage RF switch, where V b and / or V s is a feedback regulated bias voltage as described in co-pending patent application Ser. No. 15 / 644,435, entitled “SYSTEM AND METHOD FOR RF SWITCH BIASING,” the entire contents of which are incorporated herein by reference and fully set forth herein.

[0074] Fig.13 An exemplary circuit portion 1300 of a high voltage RF switch is shown, which includes a first NMOS transistor M1 connected in series with a second NMOS transistor M2, and includes an alternative bias circuit. In the series connection, the source node of transistor M1 is coupled to the drain node of transistor M2. The drain node of transistor M2 is directly coupled to the RF high voltage source, or indirectly coupled to the RF high voltage source through one or more transistors (also connected in series). The source node of transistor M1 is directly coupled to ground or another RF high voltage source, or indirectly coupled to another RF high voltage source through one or more transistors (also connected in series). The gate node of transistor M1 is coupled to the ground through a bias resistor R gc Coupled to the gate bias voltage V g , and the gate node of transistor M2 is biased by resistor R gg1 and R gc Coupled to the gate bias voltage V g The body node of transistor M1 is connected to the bias resistor R bc Coupled to the body bias voltage V b, and the body node of transistor M2 is biased by resistor R bb1 and R bc Coupled to the body bias voltage V b The source node of transistor M1 is connected to the sdc Coupled to V s Bias voltage. The source-drain node between transistors M1 and M2 is connected via resistors Rsd1 and R sdc Coupled to V s Bias voltage. The drain node of transistor M2 is connected to the sd2 , R sd1 and R sdc Coupled to V s The above bias circuit can be repeated and used in Fig.13 Any additional series transistors not shown in the figure. Any leakage current compensation circuit described herein can be used with Fig.13 used with the bias circuit shown in .

[0075] Circuits using RF switches with the leakage current compensation circuits described herein have advantages over circuits using uncompensated RF switches including, but not limited to, introducing less signal distortion, achieving good performance at higher operating voltages, improving reliability by avoiding "hot spots" within the RF switch due to excessive local voltages across individual switching transistors, and overall better achieving designed operating conditions despite the presence of leakage currents.

[0076] As described herein, while matching leakage currents in RF switch transistors with equivalent compensation currents produced by leakage current compensation circuits is desirable, over- or under-compensating these leakage currents with leakage current compensation circuits will still provide benefits when compared to an uncompensated RF switch.

[0077] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations with reference to the illustrative embodiments of the present invention and other embodiments of the present invention will be apparent to those skilled in the art. Therefore, the appended claims include any such modifications or embodiments.

Claims

1. A radio frequency (RF) switching device, comprising: a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled in series at a first source / drain terminal of the second transistor to establish a switchable RF path; as well as a first compensation network coupled directly between a body terminal of the first transistor and a second source / drain terminal of the second transistor, wherein the first compensation network is configured to establish a path for current flow in a first direction between the body terminal of the first transistor and the second source / drain terminal of the second transistor, and the first compensation network is configured to block current flow in a second direction opposite to the first direction between the body terminal of the first transistor and the source / drain terminal of the second transistor.

2. The RF switching device of claim 1, wherein the current flow in the first direction is configured to be less than or equal to a leakage current associated with the body terminal of the first transistor. 3 . The RF switching device of claim 1 , wherein the leakage current associated with the body terminal of the first transistor comprises a gate-induced source leakage current or a gate-induced drain leakage current. The RF switching device of claim 1 , wherein the first compensation network comprises a diode circuit.

5. The RF switching device of claim 4, wherein the diode circuit comprises A diode or multiple diodes coupled in series.

6. The RF switching device of claim 1, wherein the first compensation network comprises a diode-connected transistor circuit.

7. The RF switching device of claim 6, wherein the diode-connected transistor circuit comprises: diode connected transistor; a diode connected transistor coupled in series with a resistor; a diode-connected transistor having a resistor coupled between a drain terminal and a gate terminal of the diode-connected transistor; Alternatively, a diode-connected transistor having a first resistor coupled between a drain terminal and a gate terminal of the diode-connected transistor and a second resistor coupled in series with a source terminal of the diode-connected transistor. 8 . The RF switching device of claim 1 , further comprising a third transistor inserted between the first transistor and the second transistor.

9. The RF switching device of claim 1, further comprising a second compensation network coupled between the body terminal of the second transistor and a source / drain terminal of the first transistor.

10. The RF switching device of claim 9, wherein the second compensation network comprises a rectifying element.

11. The RF switching device of claim 9, wherein a current flowing through the second compensation network is configured to be less than or equal to a leakage current associated with the body terminal of the second transistor.

12. A radio frequency (RF) switching device, comprising: Multiple transistors connected in series to form a switchable current path; as well as a plurality of first compensation networks coupled directly between a body terminal of an Nth transistor of the plurality of transistors and a drain terminal of an N+1th transistor of the plurality of transistors, Wherein each of the first compensation networks comprises a rectifying element, wherein the series connection is formed between a source terminal of an N+1th transistor and a drain terminal of an Nth transistor, and wherein N is a positive integer.

13. The RF switching device of claim 12, wherein the plurality of first compensation networks is less than the plurality of transistors.

14. The RF switch device of claim 12, further comprising a plurality of second compensation networks coupled between a body terminal of an M+1th transistor of the plurality of transistors and a source terminal of an Mth transistor of the plurality of transistors, Wherein each of the second compensation networks comprises a rectifying element, and wherein M is a positive integer.

15. The RF switching device of claim 14, wherein the plurality of second compensation networks is less than the plurality of transistors.

16. A method of compensating a radio frequency (RF) switching device, the radio frequency (RF) switching device comprising a first transistor and a second transistor, the first transistor and the second transistor forming a switchable current path, the method comprising: A first compensation current is caused to flow directly between the body terminal of the first transistor and the drain terminal of the second transistor in a first direction, and current flow between the body terminal of the first transistor and the drain terminal of the second transistor in a second direction opposite to the first direction is blocked.

17. The method according to claim 16 also includes generating a second compensation current in a first direction between the body terminal of the second transistor and the source terminal of the first transistor, and blocking the flow of current in a second direction opposite to the first direction between the body terminal of the second transistor and the source terminal of the first transistor.

18. The method of claim 17, further comprising applying an alternating voltage signal to the RF switch. 19 . The method of claim 18 , wherein the first compensation current is generated during a first half cycle of the applied AC voltage signal, and the second compensation current is generated during a second half cycle of the applied AC voltage signal.

20. The method of claim 19, wherein the first compensation current is less than or equal to a leakage current at the body terminal of the first transistor, and wherein the second compensation current is less than or equal to a leakage current at the body terminal of the second transistor.

21. A radio frequency (RF) switching device, comprising: a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled in series at a common node to establish a switchable RF path between a load terminal of the second transistor and a load terminal of the first transistor; as well as a compensation network coupled directly between a body terminal of the first transistor and a load terminal of the second transistor, wherein the compensation network is configured to establish a path for current flow in a first direction between the body terminal of the first transistor and the load terminal of the second transistor, and the compensation network is configured to block current flow in a second direction opposite to the first direction between the body terminal of the first transistor and the load terminal of the second transistor.

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