Scanning drive unit and display device

Abstract

A scanning drive unit and a display device are provided. The display device includes a timing control unit. The timing control unit generates a clock signal, a start signal, and image data. The scanning drive unit includes: a plurality of driving stages, which sequentially output the clock signal as a scanning signal in response to the start signal. The data drive unit generates a data signal based on the image data. The display unit has pixels that emit light at a brightness corresponding to the data signal in response to the scanning signal. The timing control unit shields the clock signal in a portion of a first frame interval in which the scanning drive unit sequentially outputs the scanning signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a scan driving unit and a display device. Background Art

[0002] The display device includes a display panel and a driving unit. The display panel includes scan lines, data lines and pixels. The driving unit includes a scan driving unit that sequentially provides scan signals to the scan lines and a data driving unit that provides data signals to the data lines. The pixels respond to the scan signals provided by the corresponding scan lines and can emit light at a brightness corresponding to the data signals provided by the corresponding data lines.

[0003] In order to reduce power consumption, the display device may display only a portion of the frame's image or drive only a portion of the display panel.

[0004] In order to drive only a part of the area of ​​the display panel, the scan driving unit may select only the scan line corresponding to the part of the area and provide the scan signal to the scan line.

[0005] However, this requires adding a circuit structure for selecting only a part of the scan lines, so that the circuit structure of the scan driving unit becomes complicated. Summary of the invention

[0006] An object of the present invention is to provide a scan driving unit and a display device which can prevent the circuit structure of the scan driving unit from becoming complicated and drive only a part of the display panel to reduce power consumption.

[0007] In order to achieve an object of the present invention, an embodiment of the present invention relates to a display device comprising: a timing control unit generating a clock signal, a start signal and image data; a scan drive unit having a plurality of drive stages that sequentially output the clock signal as a scan signal in response to the start signal; a data drive unit generating a data signal based on the image data; and a display unit having pixels that emit light at a brightness corresponding to the data signal in response to the scan signal. The timing control unit shields the clock signal in a portion of a first frame interval in which the scan drive unit sequentially outputs the scan signal.

[0008] According to one embodiment, it may be that: the multiple driving stages respectively respond to the carry signal and output the clock signal as the scan signal, the first driving stage among the multiple driving stages receives the start signal as the carry signal, and the remaining driving stages among the multiple driving stages except the first driving stage receive the scan signal of the upper driving stage as the carry signal.

[0009] According to an embodiment, the clock signal may include a first clock signal and a second clock signal, the first clock signal has a pulse waveform, and the second clock signal is a signal in which the first clock signal is shifted by half a period.

[0010] According to an embodiment, the first driver stage among the plurality of driver stages may output the second clock signal as the scanning signal, and the second driver stage adjacent to the first driver stage among the plurality of driver stages may output the first clock signal as the scanning signal.

[0011] According to an embodiment, the timing control unit may shield at least one of the first clock signal and the second clock signal in the partial interval of the frame interval.

[0012] According to an embodiment, the timing control unit may shield the second clock signal and not shield the first clock signal in the partial interval of the frame interval.

[0013] According to one embodiment, it may be that: the second clock signal has a pulse of a first voltage level between a first moment and a second moment, maintains a second voltage level different from the first voltage level at a third moment and a fourth moment, the first moment, the second moment, the third moment and the fourth moment are respectively separated by half a cycle of the second clock signal, and the third moment and the fourth moment are included in the part of the interval.

[0014] According to one embodiment, the first clock signal may have a pulse of the first voltage level between the second moment and the third moment, and a pulse of the first voltage level between the fourth moment and the fifth moment, and the fifth moment is shifted from the fourth moment by half a cycle of the first clock signal.

[0015] According to an embodiment, the part of the intervals may correspond to at least one driving stage among the plurality of driving stages.

[0016] According to an embodiment, the portion of the interval may be smaller than the period of the first clock signal.

[0017] According to an embodiment, at least one of the plurality of driving stages may output the scanning signal at a cut-off voltage level, wherein the cut-off voltage level is a voltage level that turns off transistors of the pixels that receive the scanning signal.

[0018] According to one embodiment, the first driving stage may include: a first node control unit, which transmits the carry signal to the first node based on the first clock signal and the second clock signal; and a buffer unit, which outputs the second clock signal as the scan signal based on the first node voltage of the first node.

[0019] According to one embodiment, the first driving stage may also include a second node control unit that transmits the first clock signal to a second node based on a first node voltage of the first node, and the buffer unit migrates the voltage level of the scan signal to a cutoff voltage level based on a second node voltage of the second node.

[0020] According to one embodiment, it may be that: the timing control unit masks the clock signal in the first interval in the first frame interval, and masks the clock signal in the second interval in the second frame interval, and the first position of the second interval in the second frame interval is different from the second position of the first interval in the first frame interval.

[0021] According to an embodiment, the timing control unit may shift the image data based on a difference between the first position and the second position and then output the image data.

[0022] According to an embodiment, the data driving unit may block the output of the data signal in a remaining section after the part of the section in the frame section.

[0023] In order to achieve one purpose of the present invention, an embodiment of the present invention involves a scanning drive unit including: a first clock signal line; a second clock signal line; a shielding unit, which transmits a first clock signal and a second clock signal to the first clock signal line and the second clock signal line respectively, and shields a part of at least one of the first clock signal and the second clock signal; and a plurality of driving stages, which are connected to the first clock signal line and the second clock signal line, and output scanning signals in sequence based on the first clock signal and the second clock signal, the plurality of driving stages respectively respond to a carry signal to output the clock signal as the scanning signal, and the plurality of driving stages respectively receive the scanning signal of the upper driving stage as the carry signal.

[0024] According to an embodiment, the shielding unit may include: a switch element having a first electrode receiving the second clock signal, a second electrode connected to the second clock signal line, and a gate electrode receiving a shielding control signal.

[0025] The display device and the scan driver according to the embodiment of the present invention can shield one of the clock signals in a part of a frame period, thereby shielding the output of the drive stage corresponding to the shielded clock signal, that is, the scan signal (or carry signal). Thus, the display device can operate only a part of the display panel without adding a separate circuit structure, thereby reducing power consumption.

[0026] In addition, the display device can further reduce power consumption by increasing the impedance of the output end of the data driving unit or blocking the output during the partial period. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a block diagram showing a display device according to an embodiment of the present invention.

[0028] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0029] Figure 3 It is shown in Figure 2 A waveform diagram of an example of a signal measured in a pixel.

[0030] Figure 4 It is shown Figure 1 A block diagram of an example of a scan driving unit included in a display device.

[0031] Figure 5 It is shown Figure 4 A circuit diagram of an example of a first driving stage included in a scan driving unit.

[0032] Figure 6 It is shown in Figure 5 FIG. 1 is a waveform diagram of an example of a signal measured at the first driver stage.

[0033] Figure 7 It is shown in Figure 5 FIG. 1 is a waveform diagram of a comparative example of a signal measured at the first driver stage.

[0034] Figure 8 It is shown in Figure 5 FIG. 2 is a waveform diagram of another example of a signal measured at the first driver stage.

[0035] Fig. 9 It is based on Figure 8 A waveform diagram is shown to illustrate the operation of the display device.

[0036] Fig.10 It is shown in Figure 1 A waveform diagram of an example of a signal measured in a display device.

[0037] Fig.11 It is shown Figure 1 A block diagram of another example of a scan driving unit included in a display device.

[0038] Explanation of symbols: 100 - display device; 101 - first input terminal; 102 - second input terminal; 103 - third input terminal; 104 - output terminal; 110 - display unit; 120 - scan drive unit; 130 - data drive unit; 140 - timing control unit; 150 - light emitting drive unit; SST1 - first node control unit; SST2 - second node control unit; SST3 - buffer unit; ST_MASK - shielding unit; ST1, ST2, ST3, ST4 - first to fourth drive stages. DETAILED DESCRIPTION

[0039] The present invention can be modified in many ways and can have many embodiments. Specific embodiments are shown in the drawings and described in detail in the specification. However, the present invention is not limited to the embodiments disclosed below and can be implemented in many ways.

[0040] On the other hand, in order to clearly illustrate the present invention, some components that are not directly related to the features of the present invention may be omitted in the drawings. In addition, the size or proportion of some components in the drawings may be exaggerated. In the entire drawings, for the same or similar components, even if they appear in different drawings, the same reference numbers and symbols will be given as much as possible, and repeated descriptions will be omitted.

[0041] Figure 1 This is a block diagram showing a display device according to an embodiment of the present invention.

[0042] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0043] Reference Figure 1 The display device 100 may include a display unit 110, a scan driver 120 (scan driver or gate driver), a data driver 130 (data driver or source driver), a timing controller 140 (timing controller) and an emission driver 150 (emission driver).

[0044] The display portion 110 may include scan lines SL1 to SLn (where n is a positive integer) (or gate lines), data lines DL1 to DLm (where m is a positive integer), light emission control lines EL1 to ELn, and pixels PXL. The pixels PXL may be arranged in a region (e.g., a pixel region) divided by the scan lines SL1 to SLn, the data lines DL1 to DLm, and the light emission control lines EL1 to ELn.

[0045] The pixel PXL may be connected to at least one of the scan lines SL1 to SLn, one of the data lines DL1 to DLm, and at least one of the light emission control lines EL1 to ELn. For example, the pixel PXL may be connected to the scan line SLi, the upper scan line SLi-1 adjacent to the scan line SLi, the data line DLj, and the light emission control line ELi (where i and j are positive integers, respectively).

[0046] The pixel PXL can be initialized in response to the scan signal provided by the upper scan line SLi-1 (or the scan signal provided at the previous moment, the previous gate signal), and store or record the data signal provided by the data line DLj in response to the scan signal provided by the scan line SLi (or the scan signal provided at the current moment, the gate signal), and emit light with a brightness corresponding to the stored data signal in response to the light-emitting control signal provided by the light-emitting control line ELi.

[0047] A first power supply voltage VDD and a second power supply voltage VSS may be provided to the display unit 110. The power supply voltages VDD and VSS are voltages required for the operation of the pixel PXL, and the first power supply voltage VDD may have a voltage level higher than that of the second power supply voltage VSS.

[0048] The scan driving unit 120 may generate a scan signal based on the scan control signal SCS, and sequentially provide the scan signal to the scan lines SL1 to SLn. Here, the scan control signal SCS may include a start signal, a clock signal, etc., which may be provided by the timing control unit 140. For example, the scan driving unit 120 may include a shift register (or a driving stage), which sequentially generates and outputs a pulse-form scan signal corresponding to the pulse-form start signal using a clock signal.

[0049] For the specific structure of the scanning driving unit 120, please refer to Figure 4 And then described.

[0050] The light-emitting driving unit 150 may generate a light-emitting control signal based on the light-emitting driving control signal ECS, and provide the light-emitting control signal to the light-emitting control lines EL1 to ELn sequentially or simultaneously. Here, the light-emitting driving control signal ECS may include a light-emitting start signal, a light-emitting clock signal, etc., which are provided by the timing control unit 140. For example, the light-emitting driving unit 150 may include a shift register, which sequentially generates and outputs a pulse-form light-emitting control signal corresponding to the pulse-form light-emitting start signal using the light-emitting clock signal.

[0051] The data driving unit 130 may generate a data signal based on the image data DATA2 and the data control signal DCS provided from the timing control unit 140, and provide the data signal to the display unit 110 (or the pixel PXL). Here, the data control signal DCS is a signal for controlling the operation of the data driving unit 130, and may include a load signal (or a data enable signal) for instructing the output of a valid data signal, etc.

[0052] In an embodiment, the data driving unit 130 may block the output of the data signal in at least a portion of a frame interval. Here, a frame interval may be an interval for displaying a frame of an image. Regarding the timing at which the data driving unit 130 blocks the output of the data signal, reference will be made to Fig.10 And then described.

[0053] The timing control unit 140 may receive input image data DATA1 and a control signal CS from the outside (e.g., an image processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and transform the input image data DATA1 to generate image data DATA2. For example, the timing control unit 140 may transform the input image data DATA1 in RGB format into image data DATA2 in RGBG format that conforms to the pixel arrangement in the display unit 110.

[0054] In one embodiment, the timing control section 140 may shield at least one signal in the clock signal in a portion of a frame interval. For example, the first clock signal in the clock signal has a first voltage level (e.g., a cut-off voltage level that turns off a switch element or a transistor), and has a pulse waveform that periodically transitions to a second voltage level (e.g., a turn-on voltage level that turns on a switch element or a transistor), and the timing control section 140 may skip the transition of the first clock signal to the second voltage level in a portion of the interval. That is, the first clock signal includes pulses that periodically have a turn-on voltage level, and the timing control section 140 may shield or eliminate at least one pulse of the first clock signal in a portion of the interval. Thus, the first clock signal may have a first voltage level in a portion of the interval to replace the second voltage level.

[0055] In this case, the scanning driving unit 120 may sequentially output the scanning signal in the form of pulses having the second voltage level until a portion of the interval in one frame interval, and output the scanning signal having only the first voltage level in a portion of the interval in one frame interval (after a portion of the interval). Therefore, only the pixels in a portion of the display unit 110 (i.e., the region corresponding to the interval until a portion of the interval in one frame interval) may be selected to emit light.

[0056] The scanning signal (i.e., the scanning signal in the pulse form having the second voltage level) can be applied to only a part of the scanning lines SL1 to SLn by only shielding at least one of the clock signals of the timing control unit 140. Thus, the display device 100 can provide the scanning signal to only a part of the scanning lines SL1 to SLn without adding a circuit structure or modifying the scanning driving unit 120, thereby driving a part of the display unit 110 to reduce power consumption.

[0057] On the other hand, at least one of the scan driver 120, the data driver 130, the timing control unit 140, and the light driver 150 may be formed in the display unit 110, or may be implemented as an IC and connected to the display unit 110 in a tape carrier package. In addition, at least two of the scan driver 120, the data driver 130, the timing control unit 140, and the light driver 150 may be implemented by one IC.

[0058] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0059] Reference Figure 2 The pixel PXL may include a first transistor T1 to a seventh transistor T7, a storage capacitor Cst and a light emitting element LD.

[0060] The first transistor T1 to the seventh transistor T7 may be implemented by P-type transistors, but are not limited thereto. For example, at least a portion of the first transistor T1 to the seventh transistor T7 may also be implemented by N-type transistors.

[0061] The first electrode of the first transistor T1 (driving transistor) may be connected to the node N2, or connected to the first power line via the fifth transistor T5. The second electrode of the first transistor T1 may be connected to the node N1, or connected to the anode of the light emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may control the amount of current flowing from the first power line (i.e., the power line that transmits the first power voltage VDD) to the second power line (i.e., the power line that transmits the second power voltage VSS) via the light emitting element LD corresponding to the voltage of the third node N3.

[0062] The second transistor T2 may be connected between the data line DLj and the node N2. The gate electrode of the second transistor T2 may be connected to the scan line SLi. When a scan signal is supplied to the scan line SLi, the second transistor T2 may be turned on to electrically connect the data line DLj and the first electrode of the first transistor T1.

[0063] The third transistor T3 may be connected between the node N1 and the third node N3. The gate electrode of the third transistor T3 may be connected to the scan line SLi. When the scan signal is supplied to the scan line SLi, the third transistor T3 may be turned on to electrically connect the node N1 and the third node N3. Thus, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0064] The storage capacitor Cst may be connected between the first power line and the third node N3. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0065] The fourth transistor T4 may be connected between the third node N3 and an initialization power line (i.e., a power line that transmits an initialization power voltage Vint). The gate electrode of the fourth transistor T4 may be connected to the upper scan line SLi-1. The fourth transistor T4 may be turned on when a scan signal is supplied to the upper scan line SLi-1, thereby supplying the initialization power voltage Vint to the node N1. Here, the initialization power voltage Vint may be set to have a voltage level lower than that of the data signal.

[0066] The fifth transistor T5 may be connected between the first power line and the node N2. A gate electrode of the fifth transistor T5 may be connected to the light emission control line ELi. The fifth transistor T5 may be turned off when a light emission control signal is supplied to the light emission control line ELi, and may be turned on otherwise.

[0067] The sixth transistor T6 may be connected between the node N1 and the light emitting element LD. A gate electrode of the sixth transistor T6 may be connected to the light emitting control line ELi. The sixth transistor T6 may be turned off when a light emitting control signal is supplied to the light emitting control line ELi, and may be turned on otherwise.

[0068] The seventh transistor T7 may be connected between the initialization power line and the anode of the light emitting element LD. The gate electrode of the seventh transistor T7 may be connected to the scan line SLi. The seventh transistor T7 may be turned on when a scan signal is supplied to the scan line SLi, thereby supplying the initialization power voltage Vint to the anode of the light emitting element LD.

[0069] The anode of the light emitting element LD may be connected to the first transistor T1 via the sixth transistor T6, and the cathode of the light emitting element LD may be connected to the second power supply line. The light emitting element LD may generate light of a predetermined brightness corresponding to the current supplied from the first transistor T1. In order to allow the current to flow to the light emitting element LD, the first power supply voltage VDD may be set to have a voltage level higher than the second power supply voltage VSS.

[0070] Figure 3 It is shown in Figure 2 A waveform diagram of an example of a signal measured in a pixel. Figure 3 1 shows the upper scan signal SCAN[i-1] provided to the upper scan line SLi-1, the scan signal SCAN[i] provided to the scan line SLi, the light emitting control signal EM[i] provided to the light emitting control line EL[i], and the data signal DATA within one frame interval.

[0071] Reference Figure 2 as well as Figure 3 , between the first time t1 and the second time t2, the upper scan signal SCAN[i-1] can migrate from the cut-off voltage level (indicated as OFF in the figure, the same below) to the conduction voltage level (indicated as ON in the figure, the same below), and then migrate to the cut-off voltage level again. The first pulse width PW1 when the upper scan signal SCAN[i-1] has the conduction voltage level can be less than 1 horizontal time 1H.

[0072] In response to the upper scan signal SCAN[i-1] of the on voltage level, the fourth transistor T4 is turned on, and the third node N3 or the energy storage capacitor Cst can be initialized by the initialization power supply voltage Vint. Therefore, the interval between the first time t1 and the second time t2 can be called an initialization interval or defined as an initialization interval.

[0073] Between the second time t2 and the third time t3 , the scan signal SCAN[i] may transition from the cut-off voltage level to the on voltage level, and then transition to the cut-off voltage level again.

[0074] In response to the scan signal SCAN[i] of the on voltage level, the second transistor T2 and the third transistor T3 can be turned on, and the data signal (i.e., the data signal DATA[i] corresponding to the scan signal SCAN[i]) is stored in the energy storage capacitor Cst. Thus, the interval between the second time t2 and the third time t3 can be called a recording interval or defined as a recording interval.

[0075] In addition, between the second time t2 and the third time t3, in response to the scan signal SCAN[i] of the on voltage level, the seventh transistor T7 is turned on, and the anode of the light emitting element LD may be initialized by the initialization power supply voltage Vint.

[0076] After the third time t3, the light emission control signal EM[i] may transition from the off voltage level to the on voltage level.

[0077] In response to the light emitting control signal EM[i] of the on voltage level, the fifth transistor T5 and the sixth transistor T6 are turned on, and a current corresponding to the voltage level of the third node N3 (i.e., the data signal DATA[i] corresponding to the scan signal SCAN[i]) is provided from the first power line to the light emitting element LD, and the light emitting element LD can emit light at a brightness corresponding to the current. Therefore, the interval after the third time t3 in one frame interval can be called a light emitting interval or defined as a light emitting interval.

[0078] Figure 4 It is shown Figure 1 A block diagram of an example of a scan driving unit included in a display device.

[0079] Reference Figure 4 The scan driving unit 120 may include driving stages ST1 to ST4 (or, scanning driving stages, scanning driving stage circuits). The driving stages ST1 to ST4 may be connected to corresponding scanning lines SL1 to SL4, respectively, and are commonly connected to clock signal lines (i.e., signal lines transmitting clock signals CLK1 and CLK2). The driving stages ST1 to ST4 may have substantially the same circuit structure.

[0080] The driving stages ST1 to ST4 may include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 , respectively.

[0081] The first input terminal 101 may receive a carry signal. Here, the carry signal may include a start signal FLM (or a start pulse), or an output signal (i.e., a scan signal) of an upper drive stage (or a previous drive stage). For example, the first input terminal 101 of the first drive stage ST1 may receive the start signal FLM, and the first input terminals 101 of the remaining drive stages ST2 to ST4 may receive a scan signal of an upper drive stage. That is, the scan signal of the upper drive stage of the corresponding drive stage may be provided to the corresponding drive stage as a carry signal.

[0082] The second input terminal 102 of the first driver stage ST1 can be connected to the first clock signal line to receive the first clock signal CLK1, and the third input terminal 103 can be connected to the second clock signal line to receive the second clock signal CLK2. The second input terminal 102 of the second driver stage ST2 can be connected to the second clock signal line to receive the second clock signal CLK2, and the third input terminal 103 can be connected to the first clock signal line to receive the first clock signal CLK1. Similar to the first driver stage ST1, the second input terminal 102 of the third driver stage ST3 can be connected to the first clock signal line to receive the first clock signal CLK1, and the third input terminal 103 can be connected to the second clock signal line to receive the second clock signal CLK2. Similar to the second driver stage ST2, the second input terminal 102 of the fourth driver stage ST4 can be connected to the second clock signal line to receive the second clock signal CLK2, and the third input terminal 103 can be connected to the first clock signal line to receive the first clock signal CLK1. That is, the first clock signal line and the second clock signal line may be alternately connected to the second input terminal 102 and the third input terminal 103 of each driver stage, or the first clock signal CLK1 and the second clock signal CLK2 may be alternately provided to the second input terminal 102 and the third input terminal 103 of each driver stage.

[0083] The pulses of the first clock signal CLK1 provided through the first clock signal line and the pulses of the second clock signal CLK2 provided through the second clock signal line may not overlap each other in time, which will be described below. At this time, the pulses may each have a conduction voltage level.

[0084] The driving stages ST1 to ST4 may receive a first voltage VGH (or a high voltage level) and a second voltage VGL (or a low voltage level). The first voltage VGH may be set to a cut-off voltage level and the second voltage VGL may be set to a turn-on voltage level.

[0085] Figure 5 It is shown Figure 4 A circuit diagram of an example of a first driving stage included in a scanning driving unit. Figure 4The driving stages ST1 to ST4 shown are substantially the same as each other except for the structures of receiving the clock signals CLK1 and CLK2 , so the driving stages ST1 to ST4 are included in the following description, and the first driving stage ST1 is described.

[0086] Reference Figure 4 as well as Figure 5 , the first driving stage ST1 may include a first node control part SST1 , a second node control part SST2 , and a buffer part SST3 .

[0087] The first node control unit SST1 may transfer a start signal FLM (or a carry signal) or a first voltage VGH to the first node Q based on the first clock signal CLK1 and the second clock signal CLK2. The first node control unit SST1 may include a first switching element M1, a second switching element M2, and a third switching element M3.

[0088] The first switch element M1 may include: a first electrode connected to the first input terminal 101 or receiving the start signal FLM (or carry signal); a second electrode connected to the first node Q; and a gate electrode connected to the second input terminal 102 or receiving the first clock signal CLK1.

[0089] The second switching element M2 may include: a first electrode receiving the first voltage VGH; a second electrode providing the first voltage VGH to the first node Q; and a gate electrode receiving a signal of the second node QB.

[0090] The third switch element M3 may include: a first electrode connected to the second electrode of the second switch element M2; a second electrode connected to the first node Q; and a gate electrode connected to the third input terminal 103 or receiving the second clock signal CLK2. Here, the second switch element M2 and the third switch element M3 may be connected in series.

[0091] The second node control unit SST2 may transmit the second voltage VGL or the first clock signal CLK1 lower than the first DC voltage to the second node QB based on the first clock signal CLK1 and the signal (or voltage level) of the first node Q. The second node control unit SST2 may include a fourth switching element M4 and a fifth switching element M5.

[0092] The fourth switching element M4 may include: a first electrode receiving the first clock signal CLK1; a second electrode connected to the second node QB; and a gate electrode receiving a signal of the first node Q.

[0093] The fifth switching element M5 may include: a first electrode receiving the second voltage VGL; a second electrode connected to the second node QB; and a gate electrode receiving the first clock signal CLK1 .

[0094] The buffer unit SST3 can output the first scan signal SCAN[1] (or scan signal) including the second clock signal CLK2 as a pulse based on the signal of the first node Q and the signal of the second node QB. That is, the buffer unit SST3 can output the second clock signal CLK2 as the first scan signal SCAN[1] (or scan signal) based on the signal of the first node Q and the signal of the second node QB. The first scan signal SCAN[1] can be provided to the second driver stage ST2 as a carry signal (refer to Figure 4 )(or the next driver stage, the subsequent driver stage).

[0095] The buffer part SST3 may include a sixth switching element M6 (or pull-up switching element) and a seventh switching element M7 (or pull-down switching element). The sixth switching element M6 may include a first electrode receiving the first voltage VGH, a second electrode connected to the output terminal 104, and a gate electrode connected to the second node QB.

[0096] The seventh switching element M7 may include: a first electrode connected to the output terminal 104 ; a second electrode receiving the second clock signal CLK2 ; and a gate electrode connected to the first node Q.

[0097] The buffer part SST3 may further include a first capacitor C1 and a second capacitor C2.

[0098] The first capacitor C1 may be connected between the first electrode of the seventh switching element M7 and the gate electrode of the seventh switching element M7 .

[0099] The second capacitor C2 may be connected between the first electrode of the sixth switching element M6 and the gate electrode of the sixth switching element M6 .

[0100] exist Figure 5 In the embodiment, the first to seventh switching elements M1 to M7 are formed of P-type transistors, but this is an example and the present invention is not limited thereto. For example, the first to seventh switching elements M1 to M7 may also be formed of N-type transistors.

[0101] Figure 6 It is shown in Figure 5 The waveform diagram of an example of the signal measured at the first driver stage. Figure 6 In the example, the interval from the first time point TP1 to the sixth time point TP6 is set to be one horizontal time 1H.

[0102] Reference Figure 5 as well as Figure 6, between the first moment TP1 and the second moment TP2, the first clock signal CLK1 may migrate from the cut-off voltage level to the on-voltage level and then migrate back to the cut-off voltage level. That is, between the first moment TP1 and the second moment TP2, the first clock signal CLK1 may have a pulse of the on-voltage level. The width of the pulse of the on-voltage level of the first clock signal CLK1 may be the same as the reference Figure 3 The first pulse widths PW1 described above are substantially equal.

[0103] Then, between the second time TP2 and the third time TP3, the second clock signal CLK2 may transition from the cut-off voltage level to the on voltage level and then transition back to the cut-off voltage level. That is, between the second time TP2 and the third time TP3, the second clock signal CLK2 may have a pulse of the on voltage level.

[0104] The first clock signal CLK1 and the second clock signal CLK2 may have the same period (for example, 2 horizontal periods), and the pulse of the second clock signal CLK2 may appear 1 horizontal period 1H later than the pulse of the first clock signal CLK1. That is, the second clock signal CLK2 may be a signal obtained by shifting the first clock signal CLK1 by 1 horizontal period 1H (or half a period of the first clock signal CLK1).

[0105] In the first interval P1 between the first time TP1 and the third time TP3, the start signal FLM can maintain the off voltage level. That is, the first interval P1 is an interval before the start signal FLM of the on voltage level is applied, which can be defined as an initialization interval.

[0106] In the second interval P2 between the third time TP3 and the fourth time TP4, the start signal FLM may have a pulse of the on voltage level. For example, at the first sub-time TPS1, the start signal FLM may migrate from the off voltage level to the on voltage level, and at the second sub-time TPS2, the start signal FLM may migrate from the on voltage level to the off voltage level.

[0107] In addition, the first clock signal CLK1 may have a pulse of a turn-on voltage level.

[0108] In this case, the first switch element M1 may be turned on in response to the first clock signal CLK1 to transfer the start signal FLM to the first node Q. Thus, the first node Q may have a turn-on voltage level (or the second voltage VGL) corresponding to the start signal FLM.

[0109] The seventh switch element M7 may be turned on in response to the signal V_Q at the first node Q, pull down the first scan signal SCAN[1] (or the scan signal SCAN[i]), and output the second clock signal CLK2 as the first scan signal SCAN[1].

[0110] Here, since the second clock signal CLK2 has a cut-off voltage level, the first scan signal SCAN[1] may have a cut-off voltage level.

[0111] The first capacitor C1 may store a voltage difference between a turn-off voltage level and a turn-on voltage level according to a signal V_Q of the first node Q (or a voltage level of the first node Q) and a first scan signal SCAN[1].

[0112] The fifth switching element M5 may be turned on in response to the first clock signal CLK1 to transfer the second voltage VGL to the second node QB. Thus, the second node QB may have the second voltage VGL (or a turn-on voltage level).

[0113] That is, in the second interval P2, the first driver stage ST1 can prepare the output of the first scan signal SCAN[1] in response to the start signal FLM (or the previous gate signal). The second interval P2 can be defined as a preparation interval (or a detection period of the start signal FLM) in which the first driver stage ST1 prepares the output of the scan signal.

[0114] In the third interval P3 between the fourth time TP4 and the fifth time TP5, the second clock signal CLK2 may have a pulse of the on voltage level. For example, at the third sub-time TPS3, the second clock signal CLK2 may migrate from the off voltage level to the on voltage level, and at the fourth sub-time TPS4, the second clock signal CLK2 may migrate from the on voltage level to the off voltage level.

[0115] In this case, the first node Q has a turn-on voltage level due to the first capacitor C1, and therefore, the seventh switch element M7 can maintain a turn-on state in response to the signal V_Q of the first node Q. Thus, the first scan signal SCAN[1] can have a turn-on voltage level according to the second clock signal CLK2. On the other hand, the first node Q can have a voltage level (e.g., a second turn-on voltage level) lower than the turn-on voltage level due to the bootstrap of the first capacitor C1.

[0116] The fourth switch element M4 may be turned on in response to the signal of the first node Q to transmit the first clock signal CLK1 to the second node QB. Thus, the second node QB may have a cutoff voltage level (or the first voltage VGH) according to the first clock signal CLK1 having a cutoff voltage level.

[0117] That is, in the third interval P3 , the first driving stage ST1 outputs the first scan signal SCAN[ 1 ] having the on voltage level, and the third interval P3 may be defined as an output interval.

[0118] On the other hand, the second driver stage ST2 (refer to Figure 4 ) can prepare the output of the second scan signal SCAN[2] (or the scan signal SCAN[i+1]) in response to the first scan signal SCAN[1] at the turn-on voltage level.

[0119] Then, between the fifth time TP5 and the sixth time TP6 , the first clock signal CLK1 may have a pulse of the on voltage level.

[0120] At the fifth sub-time TPS5, the first switch element M1 is turned on in response to the first clock signal CLK1, and the first node Q can be connected to the first input terminal 101. Between the fifth time TP5 and the sixth time TP6, since the start signal FLM of the cut-off voltage level is applied to the first input terminal 101, the first node Q can migrate to the cut-off voltage level (or the first voltage VGH).

[0121] In addition, the fifth switch element M5 can be turned on in response to the first clock signal CLK1 to transfer the second voltage VGL to the second node QB. The sixth switch element M6 can be turned on in response to the signal V_QB at the second node QB to pull up the first scan signal SCAN[1] (or scan signal SCAN[i]) and output the first voltage VGH as the first scan signal SCAN[1].

[0122] The second driver stage ST2 (refer to Figure 4 ) may operate identically or similarly to the first driving stage ST1 in the third interval P3 and output a second scan signal SCAN[2] having a turn-on voltage level.

[0123] Then, at intervals of 1 horizontal time 1H, the subsequent driving stages (for example, refer to Figure 4 The third driving stage ST3 and the fourth driving stage ST4 described above can output scanning signals in sequence.

[0124] Figure 7 It is shown in Figure 5 The waveform diagram of the comparative example of the signal measured at the first driving stage. Figure 7 It is shown in Figure 6 The waveform diagram corresponding to the waveform diagram of Figure 6 Waveform diagram of .

[0125] Reference Figures 5 to 7 In the interval between the third time TP3 and the fourth time TP4, the start signal FLM may not have a pulse of the on voltage level but maintain the off voltage level. Figure 1 The timing control unit 140 described above can skip the start signal FLM and provide the start signal FLM at the cut-off voltage level.

[0126] In this case, the first driving stage ST1 can operate in the same manner as the interval between the first time TP1 and the second time TP2. Thus, the signal V_Q of the first node Q can maintain the cut-off voltage level (or the first voltage VGH), and the signal V_QB of the second node QB can maintain the turn-on voltage level (or the second voltage VGL).

[0127] In addition, according to the operation of the first driver stage ST1 between the third moment TP3 and the fourth moment TP4, between the fourth moment TP4 and the fifth moment TP5, the first driver stage ST1 can operate in the same manner as the interval between the second moment TP2 and the third moment TP3. Thus, the signal V_Q of the first node Q can maintain the cut-off voltage level (or the first voltage VGH), and the signal V_QB of the second node QB can maintain the on-voltage level (or the second voltage VGL). Thus, the first scan signal SCAN[1] (or the scan signal SCAN[i]) can have a cut-off voltage level.

[0128] Between the fourth time TP4 and the fifth time TP5, the first scan signal SCAN[1], that is, to the second driving stage ST2 (refer to Figure 4 ) The first scan signal SCAN[1] provided as the carry signal has a cut-off voltage level, so between the fifth time T5 and the sixth time T6, the second scan signal SCAN[2] (or the scan signal SCAN[i+1]) may have a cut-off voltage level.

[0129] Thus, during one frame period, the scanning driving unit 120 (see Figure 1 ) may not output a scanning signal of the on voltage level, but only output a scanning signal of the off voltage level. During one frame interval, the driving stages ST1 to ST4 in the scanning driving unit 120 do not perform a toggle operation of the scanning signal, thereby reducing power consumption.

[0130] Here, as the start signal FLM is masked, the reference Figure 1 Part of the scanning lines SL1 to SLn described above and the pixels corresponding thereto.

[0131] Therefore, the display device 100 (see Figure 1) can replace the start signal FLM and shield at least one of the clock signals CLK1 and CLK2, thereby selectively driving a portion of the scan lines SL1 to SLn and the pixels corresponding thereto.

[0132] Figure 8 It is shown in Figure 5 FIG. 2 is a waveform diagram of another example of the signal measured at the first driver stage. Figure 8 Shown with Figure 6 The waveform diagram corresponding to the waveform diagram of Figure 6 Waveform diagram of .

[0133] Reference Figure 5 , Figure 6 as well as Figure 8 In the interval between the third time TP3 and the fourth time TP4, the start signal FLM may have a pulse of the on voltage level. Figure 1 The timing control unit 140 described above can normally output the start signal FLM. In addition, the first clock signal CLK1 can have a pulse of a turn-on voltage level.

[0134] In this case, the first switch element M1 may be turned on in response to the first clock signal CLK1 to transfer the start signal FLM to the first node Q. Thus, the first node Q may have a turn-on voltage level (or the second voltage VGL) corresponding to the start signal FLM.

[0135] The seventh switch element M7 may be turned on in response to the signal V_Q at the first node Q, pull down the first scan signal SCAN[1] (or the scan signal SCAN[i]), and output the second clock signal CLK2 as the first scan signal SCAN[1].

[0136] Here, the second clock signal CLK2 has a cut-off voltage level, and thus the first scan signal SCAN[1] may have a cut-off voltage level.

[0137] The first capacitor C1 may store a voltage difference between a turn-off voltage level and a turn-on voltage level according to a signal V_Q of the first node Q (or a voltage level of the first node Q) and a first scan signal SCAN[1].

[0138] The fifth switching element M5 may be turned on in response to the first clock signal CLK1 to transfer the second voltage VGL to the second node QB. Thus, the second node QB may have the second voltage VGL (or a turn-on voltage level).

[0139] That is, in the second interval P2 , the first driving stage ST1 may prepare for output of the first scan signal SCAN[ 1 ] in response to the start signal FLM (or the previous gate signal).

[0140] In a third interval P3 between the fourth time TP4 and the fifth time TP5 , the second clock signal CLK2 may maintain the off voltage level instead of a pulse having the on voltage level.

[0141] For example, the timing control unit 140 (see Figure 1 ) can shield the second clock signal CLK2 to output the second clock signal CLK2 of the cut-off voltage level, or block the output of the second clock signal CLK2 in the third interval P3 corresponding to the first driver stage ST1 (ie, the output interval of the first driver stage ST1).

[0142] In this case, the first node Q has a turn-on voltage level due to the first capacitor C1, and thus the seventh switch element M7 can maintain a turn-on state in response to the signal V_Q of the first node Q. Thus, the first scan signal SCAN[1] can maintain a turn-off voltage level according to the second clock signal CLK2.

[0143] Then, between the fifth time TP5 and the sixth time TP6 , the first clock signal CLK1 may have a pulse of the on voltage level.

[0144] In this case, the first switch element M1 may be turned on in response to the first clock signal CLK1, and the first node Q may be connected to the first input terminal 101. Between the fifth time TP5 and the sixth time TP6, the start signal FLM of the cut-off voltage level is applied to the first input terminal 101, so the first node Q may migrate to the cut-off voltage level (or the first voltage VGH).

[0145] For reference, between the fifth time TP5 and the sixth time TP6, when the first clock signal CLK1 has a cut-off voltage level, the signal V_Q of the first node Q can maintain a turn-on voltage level (or the second voltage VGL). In this case, in the subsequent interval (for example, after the sixth time TP6), the second clock signal CLK2 of the turn-on voltage level can be output as the first scan signal SCAN[1]. Thus, in the third interval P3, when the second clock signal CLK2 is shielded, in the interval immediately following the third interval P3 (that is, from the fifth time TP5 to the sixth time TP6), the first clock signal CLK1 should have a pulse of the turn-on voltage level.

[0146] On the other hand, between the fourth time TP4 and the fifth time TP5, the first scan signal SCAN[1], that is, the carry signal, is provided to the second driving stage ST2 (refer to Figure 4) has a cut-off voltage level, and therefore, between the fifth time TP5 and the sixth time TP6, the second scan signal SCAN[2] (or, the scan signal SCAN[i+1]) may have a cut-off voltage level.

[0147] That is, the display device 100 (see Figure 1 ) (or the timing control unit 140) can shield the output (or scan signal, carry signal) of the driving stage (eg, the first driving stage ST1) corresponding to the shielded clock signal by shielding one of the clock signals CLK1 and CLK2.

[0148] Thus, the scan drive unit 120 may not only not output a scan signal during a frame interval, but may also selectively provide a scan signal only in a specific interval within a frame interval, that is, only to a portion of the scan lines SL1 to SLn, thereby achieving selective driving of a portion of pixels. For example, instead of shielding the second clock signal CLK2 in the third interval P3, when shielding the first clock signal CLK1 in the interval between the fifth moment TP5 and the sixth moment TP6, the first scan signal SCAN[1] may have a turn-on voltage level, and the second scan signal SCAN[2] may have a turn-off voltage level. That is, only the first scan line SL1 (refer to FIG. 1 ) to which the first scan signal SCAN[1] is applied may be selected. Figure 1 ).

[0149] Fig. 9 It is based on Figure 8 The waveform diagram is a diagram for explaining the operation of the display device. Fig. 9 The operation of the display device 100 in the first mode MODE1 (or the first frame period) and the operation of the display device 100 in the second mode MODE2 (or the second frame period) are shown. Fig.10 It is shown in Figure 1 This is a waveform diagram of an example of a signal measured in a display device. Fig.10 The scanning signals and the data signal DATA related to different operations of the display device 100 in the first mode MODE1 are shown.

[0150] Reference Figure 1 , Figure 8 as well as Fig. 9 In the first mode MODE1, the timing control unit 140 may shield at least one of the clock signals CLK1 and CLK2 corresponding to the X-th row (where X is a positive integer) of the display unit 110. That is, in a portion of the interval corresponding to the X-th row in one frame interval, at least one of the clock signals CLK1 and CLK2 may maintain an off-voltage level instead of a pulse having an on-voltage level.

[0151] In this case, if Fig.10 As shown, the scan signals of the on-voltage level (i.e., the first scan signal SCAN[1] to the X-1th scan signal SCAN[X-1]) can be provided sequentially from the scan driver 120 to the rows before the X-th row (or the pixels PXL) of the display unit 110, and no scan signals can be provided or scan signals of the off-voltage level (e.g., the X-th scan signal SCAN[X], the X+1th scan signal SCAN[X+1]) can be provided from the scan driver 120 to the rows from the X-th row to the n-th row (i.e., the last row) of the display unit 110.

[0152] When the frame image corresponding to a frame interval includes a valid first object image OBJ1 and the remaining parts of the frame image except the first object image OBJ1 are meaningless, that is, when a valid image is displayed before the X-th row X-th ROW of the display unit 110, the operation of the display device 100 under the first mode MODE1 may be effective.

[0153] In one embodiment, when at least one of the clock signals CLK1 and CLK2 is shielded corresponding to the X-th row of the display unit 110 , the data driving unit 130 may block the output of the data signal in the interval corresponding to the row after the X-th row.

[0154] like Fig.10 As shown, for the first to X-1th rows, the data signal DATA provided from the data driving unit 130 to the display unit 110 may have a valid value, and for rows after the Xth row, the data signal DATA may not have a valid value.

[0155] For example, the data driving unit 130 may significantly increase the impedance of the output end (ie, the output end connected to the data lines DL1 to DLm) of the data driving unit 130 or block the connection to the data lines DL1 to DLm in the interval corresponding to the Xth row in one frame interval.

[0156] Thus, the power consumption of the display device 100 can be further reduced.

[0157] On the other hand, in the second mode MODE2, the timing control unit 140 may shield at least one of the clock signals CLK1 and CLK2 corresponding to the Y-th row (where Y is a positive integer) of the display unit 110. That is, in a portion of the interval corresponding to the Y-th row in one frame interval, at least one of the clock signals CLK1 and CLK2 may maintain an off-voltage level instead of a pulse having an on-voltage level.

[0158] In this case, for the rows (or pixels PXL) from the 1st row 1st ROW to before the Y-th row Y-th ROW of the display unit 110, the scan signals of the on-voltage level are sequentially provided from the scan driving unit 120, and for the rows from the Y-th row Y-th ROW to the n-th row n-th ROW (i.e., the last row) of the display unit 110, the scan driving unit 120 may not provide a scan signal or may provide a scan signal of the off-voltage level.

[0159] When a frame image corresponding to one frame period includes a valid first object image OBJ1 , the first object image OBJ1 may be displayed in a region before the Y-th row Y-th ROW of the display unit 110 .

[0160] The second position (or time) MASK2 of the section where the clock signals CLK1 and CLK2 are masked in the second mode MODE2 may be different from the first position MASK1 of the section where the clock signals CLK1 and CLK2 are masked in the first mode MODE1.

[0161] In each embodiment, the input data image DATA1 (refer to Figure 1 ) is the same or similar to the input data image DATA1 in the second mode MODE2 (or the second frame interval), for example, when the input data image DATA1 in the second mode MODE2 includes the object image OBJ1, the data driving unit 130 can shift the input data image DATA1 in the second mode MODE2 and output it based on the difference between the first position (or moment) MASK1 where the clock signals CLK1 and CLK2 are masked in the first mode MODE1 and the second position MASK2 where the clock signals CLK1 and CLK2 are masked in the second mode MODE2. Here, the object image OBJ1 is configured at the same position as the position of the first object image OBJ1 included in the input data image DATA1 in the first mode MODE1.

[0162] For example, Fig. 9As shown, as in the first mode MODE1, the first object image OBJ1 to be displayed adjacent to the X-th row X-th ROW can be shifted by an amount corresponding to the difference between the X-th row X-th row and the Y-th row Y-th row so as to be displayed adjacent to the Y-th row Y-th ROW.

[0163] For reference, when the first object image OBJ1 (e.g., a clock image) is continuously displayed only in a specific area of ​​the display unit 110, the specific area deteriorates faster than other areas. Therefore, by displacing the first object image OBJ1 to various positions and then displaying them, as in the first mode MODE1 and the second mode MODE2, it is possible to prevent or alleviate the situation where only the specific area of ​​the display unit 110 is deteriorated.

[0164] As reference Fig. 9 as well as Fig.10 As described above, the display device 100 can selectively drive only a portion of the scan lines SL1 to SLn and a portion of the pixels corresponding thereto by adjusting only the timing of at least one of the shielding clock signals CLK1 and CLK2. In addition, the display device 100 (or the data driving unit 130) can block the output of the data signal corresponding to the remaining portion except for the selected portion of the scan lines SL1 to SLn. Therefore, the power consumption of the display device 100 can be further reduced.

[0165] Fig.11 It is shown Figure 1 A block diagram of another example of a scan driving unit included in a display device.

[0166] Reference Figure 1 , Figure 4 as well as Fig.11 , Fig.11 The scanning driving unit 120 further includes a shielding unit ST_MASK, which is similar to Figure 4 The scanning driving unit 120 is different. In addition to the shielding part ST_MASK, Fig.11 The scanning driving unit 120 is substantially the same as Figure 4 The scanning driving unit 120 is the same or similar to that of FIG. 1 , and thus will not be described repeatedly.

[0167] The shielding part ST_MASK transmits the first clock signal CLK1 and the second clock signal CLK2 to the first clock signal line and the second clock signal line respectively, and can shield a part of at least one of the first clock signal CLK1 and the second clock signal CLK2.

[0168] In one embodiment, the shielding part ST_MASK may include a switch element SW. The switch element SW may include: a first electrode receiving the second clock signal CLK2; a second electrode connected to the second clock signal line; and a gate electrode receiving the shielding control signal SC_MASK. Here, the shielding control signal SC_MASK is provided from the outside (for example, the timing control part 140 or the data driving part 130), and has a pulse, for example, which can be Figure 8 The third interval P3 described above has a conduction voltage level. Fig. 9 as well as Fig.10 The timing for blocking the output of the data driving part 130 described above is provided from the data driving part 130 , or may be the same as a control signal for blocking the output of the data driving part 130 .

[0169] In this case, with reference Figure 8 The second clock signal CLK2 described above is similarly sent to the driver stages ST1 to ST4 (see Figure 4 ) can be shielded by the switching element SW.

[0170] On the other hand, Fig.11 1 shows the case where the switch element SW receives the second clock signal CLK2 and then transmits or blocks the second clock signal line, however, the switch element SW is not limited thereto. For example, instead of the case where the first electrode of the switch element SW receives the second clock signal CLK2, the first electrode of the switch element SW can be connected to the first voltage VGH (refer to Figure 4 When the switch element SW is turned on by the masking control signal SC_MASK, the first voltage VGH (or a voltage of a cut-off voltage level) is applied to the second clock signal line, so the second clock signal CLK2 can maintain a cut-off voltage level.

[0171] In addition, Fig.11 The shielding part ST_MASK is shown to include a switch element SW, but the shielding part ST_MASK is not limited thereto. For example, similar to the switch element SW, the shielding part ST_MASK may also include an additional switch element that receives the first clock signal CLK1 and transmits it to the first clock signal line, and the additional switch element may also work in response to the shielding control signal SC_MASK or another control signal.

[0172] The technical concept of the present invention is specifically described according to the above embodiments, but it should be noted that the embodiments are used to illustrate the present invention rather than to limit the present invention. In addition, those skilled in the art can understand that there may be multiple variations within the scope of the technical concept of the present invention.

[0173] The scope of the present invention is not limited by the contents described in the detailed description of the specification, but is determined by the claims. In addition, it should be interpreted that the meaning and scope of the claims and all changes or modifications derived from their equivalent concepts are included in the scope of the present invention.

Claims

1. A display device, comprising: A timing control unit, generating a clock signal, a start signal and image data; a scanning driving unit including a plurality of driving stages which sequentially output the clock signal as a scanning signal in response to the start signal; A data driving unit, generating a data signal based on the image data; as well as The display unit includes pixels that emit light at a brightness corresponding to the data signal in response to the scanning signal. The timing control unit shields the clock signal in a portion of a first frame period in which the scan driving unit sequentially outputs the scan signal, The timing control unit shields the clock signal in a first interval in the first frame interval, and shields the clock signal in a second interval in the second frame interval, A first position of the second interval within the second frame interval is different from a second position of the first interval within the first frame interval.

2. The display device according to claim 1, wherein: The plurality of driving stages respectively respond to the carry signal and output the clock signal as the scanning signal. A first driver stage among the plurality of driver stages receives the start signal as the carry signal, The remaining driving stages of the plurality of driving stages except the first driving stage receive the scanning signal of the upper driving stage as the carry signal, The clock signal includes a first clock signal and a second clock signal, The first clock signal has a pulse waveform, The second clock signal is a signal obtained by shifting the first clock signal by half a period.

3. The display device according to claim 2, wherein: The first driving stage among the plurality of driving stages outputs the second clock signal as the scanning signal, A second driving stage adjacent to the first driving stage among the plurality of driving stages outputs the first clock signal as the scanning signal.

4. The display device according to claim 2, wherein: The timing control unit masks at least one of the first clock signal and the second clock signal in the partial period of the frame period.

5. The display device according to claim 4, wherein: The timing control unit masks the second clock signal and does not mask the first clock signal in the partial period of the frame period.

6. The display device according to claim 5, wherein: The second clock signal has a pulse of a first voltage level between a first time point and a second time point, and maintains a second voltage level different from the first voltage level at a third time point and a fourth time point. The first moment, the second moment, the third moment and the fourth moment are sequentially separated by half a cycle of the second clock signal. The third moment and the fourth moment are included in the part of the interval, The first clock signal has a pulse of the first voltage level between the second time and the third time, and has a pulse of the first voltage level between the fourth time and the fifth time, The fifth time point is shifted from the fourth time point by half a cycle of the first clock signal.

7. The display device according to claim 4, wherein: The part of the intervals corresponds to at least one driving stage among the plurality of driving stages, The portion of the interval is smaller than the period of the first clock signal, At least one of the plurality of driving stages outputs the scanning signal at a cut-off voltage level, The off-voltage level is a voltage level that turns off transistors that are included in each of the pixels and receive the scan signal.

8. The display device according to claim 2, wherein: The first driver stage comprises: A first node control unit, transmitting the carry signal to the first node based on the first clock signal and the second clock signal; a buffer section that outputs the second clock signal as the scanning signal based on a first node voltage of the first node; and a second node control unit, transmitting the first clock signal to a second node based on a first node voltage of the first node, The buffer unit shifts the voltage level of the scanning signal to an off-voltage level based on a second node voltage of the second node.

9. The display device according to claim 1, wherein: The timing control unit shifts the image data based on a difference between the first position and the second position and then outputs the image data.

10. The display device according to claim 1, wherein: The data driving unit blocks output of the data signal in a remaining section after the portion of the section in the frame section.

Images