Capacitor and method for forming same, DRAM cell and memory

Abstract

The present invention relates to a capacitor and a method for forming the same, a DRAM unit and a memory, wherein the method for forming the capacitor comprises: providing a substrate, wherein an electrical contact is formed in the substrate; forming a dielectric layer on the surface of the substrate, wherein the dielectric layer comprises: a supporting layer and a sacrificial layer stacked alternately; forming at least two capacitor holes penetrating the sacrificial layer and the supporting layer and exposing the same electrical contact; forming a lower electrode layer covering the inner wall of the capacitor hole, wherein the lower electrode layer is connected to the electrical contact; removing the sacrificial layer; and sequentially forming a capacitor dielectric layer and an upper electrode layer on the inner and outer surfaces of the lower electrode layer and the surface of the supporting layer. The above method can increase the unit area capacitance value of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a capacitor and a method for forming the same, a DRAM unit and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of many repeated storage units, each of which usually includes a capacitor and a transistor.

[0003] With the continuous development of semiconductor technology, the performance requirements for capacitors in semiconductor integrated circuits are getting higher and higher. For example, it is hoped that more capacitors can be formed in a limited area to improve the integration of capacitors. The improvement of the integration of capacitors can improve the integration of dynamic memory.

[0004] In the prior art, in order to improve the integration of capacitors, the capacitors are usually designed into a vertical shape, and the capacitance per unit area is increased by increasing the height of the capacitors. However, as the height of the capacitors increases, the risk of collapse is more likely to occur.

[0005] Therefore, how to effectively improve the integration of capacitors is a problem that needs to be solved urgently. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a capacitor and a method for forming the same, and a memory, so as to improve the integration of the capacitor.

[0007] In order to solve the above problems, the technical solution of the present invention provides a method for forming a capacitor, including: providing a substrate, in which an electrical contact portion is formed; forming alternatingly stacked support layers and sacrificial layers on the surface of the substrate; forming at least two capacitor holes that penetrate the sacrificial layer and the support layer and expose the electrical contact portion; forming a lower electrode layer covering the inner surface of the capacitor hole, the lower electrode layer being connected to the electrical contact portion; removing the sacrificial layer; and sequentially forming a capacitor dielectric layer and an upper electrode layer on the inner and outer surfaces of the lower electrode layer and the surface of the support layer.

[0008] Optionally, the method for forming at least two of the capacitor holes includes: forming a mask layer on the surface of the alternately stacked supporting layer and sacrificial layer, patterning the mask layer to form at least two openings in the mask layer above the electrical contact portion, and etching the alternately stacked supporting layer and sacrificial layer along the openings to the surface of the electrical contact portion to form the capacitor holes.

[0009] Optionally, the method of patterning the mask layer includes: performing doping treatment on the mask layer to form a first part and a second part arranged at intervals in the mask layer, the first part and the second part having different doping concentrations, wherein the mask layer corresponding to the electrical contact portion includes at least two first parts or two second parts; selectively removing the first part or the second part in the mask layer above the electrical contact portion to pattern the mask layer.

[0010] Optionally, the method of patterning the mask layer includes: etching the mask layer to form a recessed portion in the mask layer, wherein the recessed portion is located above the electrical contact portion; performing doping treatment on the recessed portion to form a first part and a second part arranged at intervals in the recessed portion, wherein the first part and the second part have different doping concentrations, and the recessed portion includes at least two first parts or two second parts; selectively removing the first part or the second part in the recessed portion to pattern the mask layer.

[0011] Optionally, the method for forming at least two of the capacitor holes includes: forming a first mask layer on the surface of the alternately stacked support layer and sacrificial layer, etching the first mask layer, forming a recessed portion in the first mask layer, and the recessed portion is located above the electrical contact portion; forming a second mask layer covering the inner surface of the recessed portion and the surface of the first mask layer, patterning the second mask layer, forming at least two openings in the second mask layer located at the bottom of the recessed portion, and etching the alternately stacked support layer and sacrificial layer along the openings to the surface of the electrical contact portion to form the capacitor hole.

[0012] Optionally, the method of patterning the second mask layer includes: performing doping treatment on the second mask layer to form a first part and a second part arranged at intervals in the second mask layer, the first part and the second part having different doping concentrations, wherein the second mask layer corresponding to the electrical contact portion includes at least two first parts or two second parts; selectively removing the first part or the second part in the second mask layer to pattern the second mask layer.

[0013] Optionally, the doping treatment includes two ion implantation processes that are tilted and in opposite directions.

[0014] Optionally, the tilt angle of the ion implantation process ranges from 5° to 45°.

[0015] Optionally, the size of the recessed portion is smaller than or equal to the size of the electrical contact portion.

[0016] The technical solution of the present invention also provides a capacitor, comprising: a substrate, an electrical contact portion formed in the substrate; a lower electrode layer connected to the electrical contact portion, the lower electrode layer comprising at least two sub-electrode layers arranged at intervals, the bottom of the sub-electrode layer being connected to the electrical contact portion; a capacitor dielectric layer located on the inner and outer surfaces of the lower electrode layer, and an upper electrode layer located on the surface of the capacitor dielectric layer.

[0017] Optionally, the cross-section of the sub-electrode layer is U-shaped.

[0018] Optionally, the capacitor dielectric layer and the upper electrode layer are both continuous material layers.

[0019] Optionally, it further includes a support structure located between the spaced-apart sub-electrode layers, the support structure connecting the sub-electrode layers, and the capacitor dielectric layer and the upper electrode layer are sequentially formed on the inner and outer surfaces of the support structure.

[0020] Optionally, the supporting structure includes at least: a first supporting layer and a second supporting layer, wherein the first supporting layer is formed on the surface of the substrate and is located at the bottom periphery of the lower electrode layer and between two sub-electrode layers, and the second supporting layer is located at the middle periphery of the lower electrode layer and between two sub-electrode layers.

[0021] To solve the above problems, the technical solution of the present invention also provides a DRAM unit, comprising: a transistor having a source region and a drain region; a capacitor as described in any one of the above items; wherein the transistor is arranged in the substrate, and the capacitor is in contact with the source region or the drain region through the electrical contact portion.

[0022] The technical solution of the present invention further provides a memory, including a storage array formed by a plurality of DRAM units as described above.

[0023] The method for forming a capacitor of the present invention forms two capacitor holes on the electrical contact portion of the substrate, thereby forming two double-sided capacitor structures on a single electrical contact portion, thereby increasing the capacitance per unit area of ​​the capacitor. In addition, since at least two capacitor holes are formed on the same electrical contact portion, the integration of the capacitor has been greatly improved. Therefore, under the premise of meeting the requirements for the integration of the capacitor, the height of the capacitor hole can be appropriately reduced to avoid the collapse of the capacitor.

[0024] Furthermore, through doping treatment, at least two first parts or two second parts with different doping concentrations are formed in the mask layer. By selectively removing the two first parts or the two second parts, the position and size of the capacitor hole are defined, which can greatly reduce the size of the capacitor hole, not be limited by the size of the photolithography process, and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 11 A structural schematic diagram of a capacitor forming process according to a specific embodiment of the present invention;

[0026] Fig.12 FIG. 4 is a schematic diagram of the structure of a DRAM unit according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background art, the integration level of capacitors in the prior art needs to be further improved.

[0028] In order to solve the above problems, the applicant has proposed a new capacitor and a method for forming the same. In order to further improve the integration of the capacitor, more than two U-shaped lower electrode layers can be formed in a capacitor and connected to the same electrical contact. To form more than two U-shaped lower electrode layers, it is necessary to form more than two capacitor holes on an electrical contact, and the critical dimensions of the capacitor holes are greatly reduced. However, under current process conditions, it is difficult to achieve this through existing photolithography and etching processes. Even if a smaller capacitor hole can be formed through a double patterning process, multiple photolithography and etching are required, which greatly increases the process cost. The applicant has overcome the above problems through a new capacitor and a method for forming the same.

[0029] The specific embodiments of the capacitor and its forming method, DRAM unit and memory provided by the present invention are described in detail below with reference to the accompanying drawings.

[0030] Please refer to Figures 1 to 11 , which is a structural schematic diagram of the formation process of a capacitor according to a specific embodiment of the present invention.

[0031] Please refer to Figure 1 A substrate 100 is provided, wherein an electrical contact portion 101 is formed in the substrate 100; a dielectric layer 110 is formed on the surface of the substrate 100, wherein the dielectric layer 110 includes: a supporting layer and a sacrificial layer that are alternately stacked.

[0032] Word lines, bit lines, transistors, isolation structures and other structures may also be formed inside the substrate 100, which are not shown in the figure.

[0033] The dielectric layer 110 may be formed on the surface of the substrate 100 by using a deposition process such as an atomic layer deposition process or a chemical vapor deposition process. It should be noted that the dielectric layer 110 includes support layers and sacrificial layers alternately stacked in sequence, the number of the support layers is greater than the number of the sacrificial layers, and the bottom material layer and the top material layer in the stacked structure composed of the sacrificial layers and the support layers are both the support layers, and the number of the support layers and the sacrificial layers may be set as required, and is not limited to this specific embodiment.

[0034] In this specific embodiment, the dielectric layer 110 includes a first supporting layer 102 formed on the surface of the substrate 100, a first sacrificial layer 103 located on the surface of the first supporting layer 102, a second supporting layer 104 located on the surface of the first sacrificial layer 103, a second sacrificial layer 105 located on the surface of the second supporting layer 104, and a third supporting layer 106 located on the surface of the second sacrificial layer 105. The materials of the first supporting layer 102, the second supporting layer 104, and the third supporting layer 106 include silicon nitride, and the materials of the first sacrificial layer 104 and the second sacrificial layer 105 include silicon oxide. In other specific embodiments, the number of supporting layers and sacrificial layers can also be increased, thereby increasing the height of the capacitor and further increasing the capacitance value of the capacitor. The number of supporting layers can also be appropriately reduced, for example, only including the first supporting layer 102 and the second supporting layer 104.

[0035] Subsequently, at least two capacitor holes are formed which penetrate the sacrificial layer and the supporting layer and expose the same electrical contact portion.

[0036] Please refer to Figures 2 to 6B , is a schematic diagram of the process structure of forming two capacitor holes in a specific embodiment.

[0037] Please refer to Figure 2 , forming a first mask layer 200 on the surface of the dielectric layer 110 ; etching the first mask layer 200 to form a recessed portion 201 in the first mask layer 200 . The recessed portion 201 is located directly above the electrical contact portion 101 .

[0038] The material of the first mask layer 200 may be silicon oxide or other mask materials, and preferably, is different from the material of the third supporting layer 106 , so as to facilitate the subsequent removal of the first mask layer 200 .

[0039] The shape and size of the recessed portion 201 are consistent with the shape and size of the electrical contact portion 101. The first mask layer 200 may be etched using the photomask used to form the electrical contact portion 101 to form the recessed portion 201. In other specific embodiments, the size of the recessed portion 201 may be smaller than the size of the electrical contact portion 101. Subsequently, a capacitor structure is formed below the recessed portion 201, so that the capacitor structure is located on the surface of the electrical contact portion 101.

[0040] In this specific embodiment, the depth of the recessed portion 201 is less than the thickness of the first mask layer 200 ; in other specific embodiments, the depth of the recessed portion 201 may also be equal to the thickness of the first mask layer 200 , so that the bottom of the recessed portion 201 is located on the surface or inside of the third supporting layer 106 .

[0041] Please refer to Figure 3, forming a second mask layer 300 covering the inner wall of the recessed portion 201 and the surface of the first mask layer 200 .

[0042] The material of the second mask layer 300 can change the etching selectivity by doping.

[0043] In this specific embodiment, the material of the second mask layer 300 is polysilicon, and the second mask layer 300 can be formed by atomic layer deposition or chemical vapor deposition. In other specific embodiments, the second mask layer 300 can also be made of other materials, which are not limited here.

[0044] The thickness of the second mask layer 300 may be 5 nm to 30 nm, and may be adjusted according to the tilt angle of the subsequent tilt implantation to be performed.

[0045] Please refer to Figure 4 , using two ion implantation processes that are tilted and in opposite directions, a doped region 401 is formed in the middle of the second mask layer 300 located at the bottom of the recessed portion 201 .

[0046] The inclination angle of the first ion implantation process is α, and the inclination angle of the second ion implantation process is β. Due to the sidewall shielding of the recess 201, only part of the second mask layer 300 at the middle position of the bottom of the recess 201 can receive two ion implantations to form a doping region 401. The second mask layer 300 at other positions at the bottom of the recess 201 receives at most one ion implantation, and the doping concentration is less than the doping concentration of the doping region 401. Therefore, by selecting a suitable etching process, different etching selectivities can be achieved between the doping region 401 and the regions on both sides of it. The implanted ions used in the ion implantation can be P, B, Ga or As, etc., and the implantation conditions are: the implanted ion energy is 10 to 900 keV, and the doping is 1E11 to 1E13 / cm 2 .

[0047] The doping concentration of the second mask layer 300 on the surface of the dielectric layer 110 is consistent with the doping concentration of the doping region 401 .

[0048] The width of the doped region 401 can be adjusted by adjusting the depth of the recessed portion 201 and the angles of the inclination angles α and β. In this specific embodiment, α=β; in other specific embodiments, the inclination angle can range from 5° to 45°, and the depth of the recessed portion 201 can range from 100 nm to 200 nm.

[0049] Please refer to Figure 5 , the second mask layer 300 on both sides of the doped region 401 at the bottom of the recessed portion 201 is etched by a selective etching process (please refer to Figure 4), forming a second patterned mask layer 3001; using the second patterned mask layer 3001 as a mask, etching the first mask layer 200 (please refer to Figure 4 ) to form a first patterned mask layer 2001.

[0050] The selective etching process may be a wet etching process, and a suitable etching solution is selected for different second mask layer materials. In this specific embodiment, the material of the second patterned mask layer 3001 is polysilicon, and the etching solution used includes: at least one of APM solution, ammonia water and potassium hydroxide solution. The wet etching process has a high etching selectivity for the area with low doping concentration in the second mask layer 300, thereby removing part of the areas on both sides of the doping area 401 to expose the first mask layer 200; continue to etch the first mask layer 200 to form a first patterned mask layer 2001.

[0051] In other specific embodiments, the selective etching process may also be a dry etching process, and the etching gas used includes CF 4 , SF 6 and at least one of HBr, for example, CF 4 and HBr as etching gases.

[0052] The first mask layer 200 is etched by dry etching process, and the etching gas used includes C X F Y \CH X F Y and Ar, wherein X and Y are both integers greater than or equal to 1.

[0053] Please refer to Fig. 6A and 6B , with the second patterned mask layer 3001 (please refer to Figure 5 ) and the first patterned mask layer 2001 (please refer to Figure 5 ) is used as a mask to etch the dielectric layer 110 to the surface of the electrical contact portion 101 to form two capacitor holes 601. Figure 6B It is a top schematic diagram of the area where the capacitor hole 601 is located.

[0054] The dielectric layer 110 is etched by dry etching process, and different etching gases are used for different material layers in the dielectric layer 110. The materials of the first support layer 102, the second support layer 104 and the third support layer 106 are silicon nitride, and the etching gas used includes CF 4 , SF 6 and at least one of HBr; the material of the first sacrificial layer 103 and the second sacrificial layer 105 is silicon oxide, and the etching gas used includes SF 6 and O2 .

[0055] In this specific embodiment, the cross section of the electrical contact portion 101 is circular; the recessed portion 201 (see Figure 4 ) is also circular in cross section, and therefore, the capacitor hole 601 is formed with an arc-shaped side wall on the outside.

[0056] Through two ion implantation processes, the doping region 401 can be adjusted (see Figure 5 ) to adjust the size of the capacitor hole 601. Since there is no need to use a photolithography process to limit the size of the capacitor hole 601, the key size of the capacitor hole 601 is not limited by the photolithography process, and the process cost can be reduced. The maximum width of the capacitor hole 601 can range from 16-21nm, the height of the capacitor hole 601 can range from 800nm ​​to 1600nm, and the spacing between adjacent capacitor holes 601 ranges from 30nm to 50nm. Since at least two capacitor holes are formed on the same electrical contact portion in this embodiment, the integration of the capacitor has been greatly improved. Therefore, on the premise of meeting the requirements for the integration of the capacitor, the size of the capacitor hole in this embodiment can be relatively large to reduce the process difficulty.

[0057] The first patterned mask layer 2001 and the second patterned mask layer 3001 may be removed by stripping, grinding, etc., and may also be consumed in the process of forming the capacitor hole 601 .

[0058] In some specific embodiments, the method for forming the at least two capacitor holes may include: forming a mask layer on the surface of the dielectric layer, patterning the mask layer so that at least two openings are formed in the mask layer directly above the electrical contact portion, and etching the dielectric layer along the openings to the surface of the electrical contact portion to form the capacitor holes. The method for patterning the mask layer includes: performing a doping treatment on the mask layer so that a first portion and a second portion arranged at intervals are formed in the mask layer, and the first portion and the second portion have different doping concentrations, wherein the mask layer corresponding to the portion directly above the electrical contact portion includes at least two first portions or two second portions; selectively removing the first portion or the second portion of the mask layer directly above the electrical contact portion, and patterning the mask layer. Alternatively, the method for patterning the mask layer includes: etching the mask layer to form a recessed portion in the mask layer, wherein the recessed portion is located directly above the electrical contact portion; performing doping treatment on the recessed portion to form a first part and a second part arranged at intervals in the recessed portion, wherein the first part and the second part have different doping concentrations, and the recessed portion includes at least two first parts or two second parts; selectively removing the first part or the second part in the recessed portion to pattern the mask layer.

[0059] In some specific embodiments, the method for forming the at least two capacitor holes includes: forming a first mask layer on the surface of the dielectric layer, etching the first mask layer, forming a recessed portion in the first mask layer, and the recessed portion is located directly above the electrical contact portion; forming a second mask layer covering the inner wall of the recessed portion and the surface of the first mask layer, patterning the second mask layer, forming at least two openings in the second mask layer located at the bottom of the recessed portion, and etching the dielectric layer along the openings to the surface of the electrical contact portion to form the capacitor hole. Wherein, the method for patterning the second mask layer may include: performing a doping treatment on the second mask layer so that a first portion and a second portion arranged at intervals are formed in the second mask layer, and the first portion and the second portion have different doping concentrations, wherein the second mask layer corresponding to the portion directly above the electrical contact portion includes at least two first portions or two second portions; selectively removing the first portion or the second portion of the second mask layer directly above the electrical contact portion, and patterning the second mask layer.

[0060] Please refer to Fig. 7A and 7B , forming a lower electrode layer 701 covering the inner walls of the two capacitor holes 601 and the surface of the dielectric layer 110.

[0061] The lower electrode layer 701 may be formed by a deposition process such as an atomic layer deposition process, a physical vapor deposition process or a plasma vapor deposition process. In this specific embodiment, the lower electrode layer 701 covers the sidewalls and the bottom of the capacitor hole 601 and the top surface of the dielectric layer 110. The material of the lower electrode layer 701 includes metal materials such as titanium nitride, tantalum nitride, copper or tungsten.

[0062] Please refer to Figure 8 , a third mask layer is formed on the surface of the dielectric layer 110, and a patterned photoresist layer 805 is formed on the surface of the third mask layer.

[0063] The third mask layer closes the capacitor hole 601. In this specific embodiment, the third grinding layer includes a silicon nitride layer 801, a silicon oxide layer 803, a pad layer 803 and an anti-reflection layer 805. The pattern of the patterned photoresist layer 805 defines the position and shape of the opening to be formed subsequently. In this specific embodiment, the shape of the pattern in the patterned photoresist layer 805 is circular. In other specific embodiments, it can also be other shapes.

[0064] Please refer to Fig.9A and 9B , with the photoresist layer 805 (please refer to Figure 8) as a mask, etching the third mask layer to form a third patterned mask layer; using the third patterned mask layer as a mask, etching the dielectric layer 110 to form an opening 901 that at least exposes a portion of the sacrificial layer.

[0065] The patterned photoresist layer 805 (see Figure 8 ), anti-reflection layer 806 (please refer to Figure 8 ) and cushion layer 803 (please refer to Figure 8 ) is consumed in the process of etching the dielectric layer 110.

[0066] The opening 901 is partially located on the electrical contact portion 101 , overlaps with the two capacitor holes 601 , and at least laterally exposes the two capacitor holes 601 . Fig. 9B Only the portion of the opening 901 located above the electrical contact portion 101 is shown.

[0067] Since only a portion of the capacitor hole 601 overlaps with the opening 901 , a portion of the support layer is retained around each capacitor hole 601 to ensure the structural stability of the lower electrode layer 701 during the subsequent removal of the sacrificial layer.

[0068] Please refer to Fig. 10A and 10B , remove the first sacrificial layer 103 along the opening 901 (please refer to Fig.9A ) and the second sacrificial layer 105 (please refer to Fig.9A ), exposing a portion of the side wall of the lower electrode layer 701 covering the side wall of the capacitor hole 601.

[0069] The first sacrificial layer 103 and the second sacrificial layer 105 are removed by wet etching. The etching solution used in the wet etching process includes a hydrofluoric acid solution. The corrosion rate of the sacrificial layer is much greater than the corrosion rate of the supporting layer. When the sacrificial layer is completely removed, the supporting layer is almost completely retained.

[0070] The silicon nitride layer 801 and the silicon oxide layer 802 may be removed first, and then the sacrificial layers may be removed along the opening 901. The silicon nitride layer 801 and the silicon oxide layer 802 may be removed by chemical mechanical polishing, and in this specific embodiment, the lower electrode layer on the surface of the dielectric layer 110 is removed at the same time.

[0071] Please refer to Fig.11 A capacitor dielectric layer 1101 and an upper electrode layer 1102 are sequentially formed on the inner and outer surfaces of the lower electrode layer 701 .

[0072] The material of the capacitor dielectric layer 1101 can be a high-K dielectric material to increase the capacitance value of the capacitor per unit area, including ZrO x, HfO x 、ZrTiO x 、RuO x , SbO x 、AlO x A laminate formed by one of the above materials or two or more of the above materials.

[0073] An upper electrode layer 1102 covering the outer surface of the capacitor dielectric layer 1101 is formed by an atomic layer deposition process, a plasma vapor deposition process, a sputtering process, etc. The upper electrode layer 1102 includes a compound formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride (TiSixNy), or other conductive materials.

[0074] Subsequently, a conductive filling layer, such as a boron-doped germanium silicon layer, may be formed on the surface of the upper electrode layer 1102 . The conductive filling layer fills the gaps between the upper electrode layers 1102 .

[0075] The method for forming the capacitor forms at least two capacitor holes on one electrical contact portion, thereby forming at least two double-sided capacitor structures on one electrical contact portion, thereby increasing the capacitance value per unit area.

[0076] A specific embodiment of the present invention further provides a capacitor.

[0077] Please refer to Fig.11 FIG. 1 is a schematic structural diagram of a capacitor according to a specific embodiment of the present invention.

[0078] The capacitor includes: a substrate 100, in which an electrical contact portion 101 is formed; a lower electrode layer 701, which includes at least two sub-electrode layers arranged at intervals, and the bottom of the sub-electrode layer is connected to the electrical contact portion 101; a capacitor dielectric layer 1101 located on the inner and outer surfaces of the lower electrode layer, and an upper electrode layer 1102 located on the surface of the capacitor dielectric layer 1101.

[0079] In some specific embodiments, the capacitor dielectric layer 1101 and the upper electrode layer 1102 are both continuous material layers.

[0080] In some specific embodiments, the cross section of the sub-electrode layer is U-shaped, and the bottom of the U-shaped cross section is located on the surface of the electrical contact portion 101 .

[0081] In some specific embodiments, the distance between the U-shaped cross sections of the two sub-electrode layers is in the range of 30 nm to 50 nm.

[0082] In some specific embodiments, the capacitor further includes a support structure located between the spaced-apart sub-electrode layers, and the capacitor dielectric layer 1101 and the upper electrode layer 1102 are sequentially formed on the inner and outer surfaces of the support structure.

[0083] In this specific embodiment, the support structure includes: a first support layer 102, a second support layer 104 and a third support layer 106, all of which are located on the substrate 100 and connected to the lower electrode layer 701, wherein the third support layer 106 is located at the periphery of the opening of the lower electrode layer 701, the second support layer 104 is located at the periphery of the middle of the lower electrode layer 701 and between the two sub-electrode layers, and the first support layer 102 is formed on the surface of the substrate 100 and is located at the periphery of the bottom of the lower electrode layer 701 and between the two sub-electrode layers. The capacitor dielectric layer 1101 also covers the surfaces of the first support layer, the second support layer and the third support layer.

[0084] Since at least two capacitor holes are formed on the same electrical contact portion in this embodiment, the integration of the capacitor has been greatly improved. Therefore, under the premise of meeting the requirements of the integration of the capacitor, the height of the capacitor hole can be reduced, so that the capacitor is not easy to collapse. Therefore, the number of supporting layers in the supporting structure can be appropriately reduced. For example, the supporting structure can only include the first supporting layer 102 and the second supporting layer 104.

[0085] In a specific embodiment of the present invention, a DRAM unit is also provided, comprising a plurality of capacitors as described in the above specific embodiments, and a transistor having a source region and a drain region, wherein the transistor is arranged in the substrate, and the capacitor is in contact with the source region or the drain region through the electrical contact portion.

[0086] Please refer to Fig.12 , the substrate 1200 includes a semiconductor substrate and a dielectric layer located on the surface of the semiconductor substrate, the semiconductor substrate includes an active area 1201 and an isolation structure 1202, the isolation structure 1202 may be a shallow trench isolation structure, and is arranged around the active area 1201. A transistor is formed in the active area, the transistor has a buried gate structure, including a gate 1204 buried in the active area 1201, a gate dielectric layer 1204 located between the gate and the active area 1201, and the transistor also includes a source region 1205 and a drain region 1206 located on both sides of the gate 1204. In this specific implementation, two gates 1204 are formed in the active area 1201, the drain region 1206 is located between the two gates 1204, and the source region 1205 is located outside the two gates 1204. An insulating layer 1207 is formed on the top of the gate 1204, flush with the surface of the active area 1201.

[0087] An interconnect structure is formed in the dielectric layer 1207 on the surface of the semiconductor substrate, which is used to form an electrical connection with the transistors in the semiconductor substrate. Specifically, a first electrical contact 1208 connected to the source region 1205 is formed in the dielectric layer 1207, and a second electrical contact 1210 connected to the drain region 1206 is also formed in the dielectric layer 1207, which is used to connect to a bit line (not shown in the figure).

[0088] In this specific embodiment, the DRAM cell further includes a capacitor whose lower electrode is connected to the first electrical contact 1208. In this specific embodiment, two capacitors are formed on the active area, namely, capacitor 1211 and capacitor 1212, and the capacitors 1211 and 1212 are respectively connected to the source region 1205 of the transistor through the first electrical contact 1208.

[0089] The structures of the capacitors 1211 and 1212 are described in the above specific embodiments, which will not be described here in detail. Since a single capacitor includes two double-sided capacitor structures, the capacitance value of the single capacitor is increased, thereby improving the storage density of the DRAM unit.

[0090] In other specific embodiments, the capacitor may also be connected to the drain of the transistor.

[0091] In this specific embodiment, the transistor is a buried gate structure transistor. In other specific embodiments, the transistor may also be a planar gate structure or a ring gate structure transistor, which is not limited here.

[0092] This specific embodiment also provides a memory, which includes a memory array formed by the above DRAM units. The capacitor in each DRAM unit of the memory includes two double-sided capacitor structures, which increases the capacitance value of a single capacitor and improves the storage density of the memory.

[0093] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a capacitor, characterized in that: include: providing a substrate having a plurality of electrical contacts formed therein; Forming alternately stacked support layers and sacrificial layers on the surface of the substrate; At least two capacitor holes are formed that penetrate the sacrificial layer and the supporting layer and expose each of the electrical contacts. The method for forming the at least two capacitor holes comprises: forming a mask layer on the surfaces of the alternately stacked supporting layer and the sacrificial layer, patterning the mask layer so that at least two openings are formed in the mask layer above each of the electrical contacts, and etching the alternately stacked supporting layer and the sacrificial layer along the openings to the surfaces of each of the electrical contacts to form the capacitor holes; The method for patterning the mask layer includes: performing doping treatment on the mask layer so that a first portion and a second portion arranged at intervals are formed in the mask layer, and the first portion and the second portion have different doping concentrations, wherein the mask layer corresponding to each electrical contact portion includes at least two first portions or two second portions; selectively removing the first portion or the second portion of the mask layer above each electrical contact portion to pattern the mask layer; forming a lower electrode layer covering the inner surface of the capacitor hole, wherein the lower electrode layer is connected to each of the electrical contact portions; removing the sacrificial layer; A capacitor dielectric layer and an upper electrode layer are sequentially formed on the inner and outer surfaces of the lower electrode layer and the surface of the support layer.

2. The method for forming a capacitor according to claim 1, wherein: The method for patterning the mask layer includes: etching the mask layer to form a recessed portion in the mask layer, wherein the recessed portion is located above the electrical contact portion; performing doping treatment on the recessed portion to form a first part and a second part arranged at intervals in the recessed portion, wherein the first part and the second part have different doping concentrations, and the recessed portion includes at least two first parts or two second parts; selectively removing the first part or the second part in the recessed portion to pattern the mask layer.

3. The method for forming a capacitor according to claim 1, wherein: The method for forming at least two of the capacitor holes includes: forming a first mask layer on the surface of the alternately stacked support layer and sacrificial layer, etching the first mask layer, forming a recessed portion in the first mask layer, and the recessed portion is located above the electrical contact portion; forming a second mask layer covering the inner surface of the recessed portion and the surface of the first mask layer, patterning the second mask layer, forming at least two openings in the second mask layer located at the bottom of the recessed portion, and etching the support layer and the sacrificial layer along the openings to the surface of the electrical contact portion to form the capacitor holes.

4. The method for forming a capacitor according to claim 3, wherein: The method for patterning the second mask layer includes: performing doping treatment on the second mask layer to form a first part and a second part arranged at intervals in the second mask layer, the first part and the second part have different doping concentrations, wherein the second mask layer corresponding to the electrical contact part includes at least two first parts or two second parts; selectively removing the first part or the second part in the second mask layer to pattern the second mask layer.

5. The method for forming a capacitor according to claim 1, 2 or 4, characterized in that: The doping process includes two ion implantation processes that are tilted and in opposite directions.

6. The method for forming a capacitor according to claim 5, wherein: The tilt angle of the ion implantation process ranges from 5° to 45°.

7. The method for forming a capacitor according to claim 2 or 3, characterized in that: The size of the recessed portion is smaller than or equal to the size of the electrical contact portion.

8. A capacitor formed according to the forming method according to any one of claims 1 to 7.

9. A DRAM cell, characterized in that: include: a transistor having a source region and a drain region; A capacitor formed according to any one of the forming methods of claims 1 to 7; wherein the capacitor is in contact with the source region or the drain region through the electrical contact portion.

10. A memory, characterized in that: include: A memory array formed by a plurality of DRAM cells as claimed in claim 9.

Images