Incremental analog-to-digital converter

Abstract

The present invention discloses an incremental analog-to-digital converter, comprising a digital-to-analog converter and a loop filter; a quantizer outputs a quantized signal; the digital-to-analog converter is coupled to the output end of the quantizer and generates an estimated value of the quantized signal; the loop filter operates according to the difference between the analog input signal and the estimated value, and the output end of the loop filter is coupled to the input end of the quantizer; and the loop filter has a preset circuit, and in the reset stage of the incremental analog-to-digital converter, the preset circuit presets the output terminal of the loop filter.

Description

Technical Field

[0001] The present invention relates to the field of electrical technology, and in particular to an incremental analog-to-digital converter. Background Art

[0002] Delta-sigma analog-to-digital converters (ADCs) are used in many applications due to the reduction in cost and circuit complexity. Wireless communication systems (e.g., telecommunication systems, television, radio, and other media systems, data communication networks, and other systems that use wireless transmitters and wireless receivers to pass information between remote points) often use delta-sigma ADCs.

[0003] The Δ-Σ ADC includes a Δ-Σ (Δ-Σ) modulator and a digital filter. The analog input signal (Ain) is processed by the Δ-Σ modulator, and the output of the Δ-Σ modulator is a quantized signal, which is digitally integrated by the digital filter to generate a digital representation (Dout) of the analog input signal (Ain). In the Δ-Σ modulator, a rough estimate of the analog input signal (Ain) is fed back and subtracted from the analog input signal (Ain), and the resulting difference is integrated to compensate for the resulting difference. The Δ-Σ ADC can be referred to as an n-order Δ-Σ ADC, where n is equal to the number of cascaded analog integrators in the Δ-Σ modulator. The number of digital integrals provided by the digital filter is preferably the same as the number of cascaded analog integrators in the Δ-Σ modulator.

[0004] One specific type of delta-sigma ADC is called an incremental ADC, in which the analog and digital integrators in the ADC are reset or reset after each analog-to-digital conversion cycle in preparation for the next analog-to-digital conversion cycle.

[0005] However, the reset or resetting process on the analog integrator may cause nonlinear problems, which greatly affects the accuracy of the incremental ADC. Summary of the invention

[0006] In view of this, the present invention provides an incremental analog-to-digital converter to improve the accuracy of the incremental ADC.

[0007] According to a first aspect of the present invention, an incremental analog-to-digital converter is disclosed, comprising:

[0008] a delta-sigma modulator that performs delta-sigma modulation on an analog input signal to output a quantized signal; and

[0009] a digital filter receiving the quantized signal to generate a digital representation of the analog input signal, wherein:

[0010] The delta-sigma modulator includes a quantizer, a digital-to-analog converter and a loop filter;

[0011] The quantizer outputs the quantized signal;

[0012] The digital-to-analog converter is coupled to the output of the quantizer and generates an estimate of the quantized signal;

[0013] The loop filter operates on the difference between the analog input signal and the estimate, and an output of the loop filter is coupled to an input of a quantizer; and

[0014] The loop filter has a preset circuit, which presets an output terminal of the loop filter in advance during a reset phase of the incremental analog-to-digital converter.

[0015] The incremental analog-to-digital converter of the present invention adopts a preset circuit, and in the reset phase of the incremental analog-to-digital converter, the preset circuit presets the output terminal of the loop filter to be non-zero, and the non-zero preset value is fed back to the loop filter, so that the difference after the input signal is subtracted from the non-zero preset value is reduced, which effectively limits the difference. Therefore, all analog integrators in the loop filter operate in the linear region of the analog integrator, reducing the nonlinear error caused by the drastic change of the difference at the beginning of each analog-to-digital conversion cycle, thereby improving the accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram illustrating an incremental analog-to-digital converter (ADC) 100 according to an exemplary embodiment of the present invention;

[0017] Figure 2 2 shows the waveform of the reset signal RST;

[0018] Figure 3 Depicted is an incremental ADC 300, which is a continuous time ADC, according to an exemplary embodiment of the present invention;

[0019] Figure 4 The transient waveforms of the integral outputs INT1 and INT2 and the quantized signal Do are shown;

[0020] Figure 5 An incremental ADC 500 , which is a discrete time ADC, is depicted according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0021] Certain terms are used throughout the following description and claims to refer to specific components. As will be appreciated by those skilled in the art, electronic device manufacturers may refer to components by different names. This document is not intended to distinguish between components that have different names but the same function. In the following description and claims, the terms "include" and "comprise" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". Similarly, the term "coupled" is intended to mean an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connectors.

[0022] Figure 1 1 is a block diagram showing an incremental analog-to-digital converter (ADC) 100 according to an exemplary embodiment of the present invention. The incremental ADC 100 includes a delta-sigma modulator 102, a digital filter 104, and a reset signal generator 106. The delta-sigma modulator 102 processes an analog input signal Ain, and the output of the delta-sigma modulator 102 is a quantized signal Do, which is digitally integrated by the digital filter 104 to form a digital representation Dout of the analog input signal Ain. The analog input signal Ain can be a voltage or a current.

[0023] The delta-sigma modulator 102 includes a loop filter 112 (having L (>=1) analog integrators), a quantizer 114, a digital-to-analog converter (DAC) 116, and an adder 118. The DAC 116 outputs a signal 120 (a rough estimate of the input signal Ain), and the adder 118 subtracts the signal 120 from the input signal Ain to obtain a difference 122. The difference 122 is processed by the loop filter 112 and then quantized by the quantizer 114 into a quantized signal Do. The quantized signal Do is not only fed into the digital filter 104, but also fed back as an input to the DAC 116. During the analog-to-digital conversion cycle, the difference 122 is compensated and the integral of the difference 122 (calculated by the loop filter 112) reaches a stable value. The gradually stable quantized signal Do is digitally integrated by the digital filter 104 to generate a digital representation Dout of the analog input signal Ain.

[0024] As shown, during the reset phase after each analog-to-digital conversion cycle, the reset signal generator 106 generates a reset signal RST to reset the incremental ADC 100. According to the reset signal RST, the digital integrator in the digital filter 104 is reset. Specifically, the quantizer 114 is also reset according to the reset signal RST to output a reset value (e.g., Do=0) to the digital filter 104 to completely clean the capacitor of the digital integrator in the digital filter 104. The reset phase enables a one-to-one mapping between the analog input signal Ain and the digital representation Dout. In order to prevent the reset value (e.g., Do=0) from the quantizer 114 from being fed to the next analog-to-digital conversion cycle, an embodiment of the present invention introduces a preset circuit for the output terminal of the loop filter 112. During the reset phase of the incremental ADC 100, the preset circuit presets the output terminal 124 of the loop filter 112 (which can be preset to a positive or negative number, but not zero). At the beginning of each analog-to-digital conversion cycle, the signal transmitted from the output terminal of the loop filter 112 to the quantizer 114 is a preset value (preset in the reset phase) instead of zero. The non-zero preset value is fed back to the loop filter 112 through the quantizer 114, the DAC 116 and the adder 118, which effectively limits the difference 122. Therefore, the analog integrators in the loop filter 112 all operate in the linear region of the analog integrator. The nonlinear error caused by the drastic change of the difference 122 at the beginning of each analog-to-digital conversion cycle is reduced. Specifically, in the prior art, the value at the output terminal (e.g., output terminal 124) of the loop filter is zero (of course, the subsequent quantization signal Do is also zero), so that the output signal (e.g., output signal 120) fed back to the adder (e.g., adder 118) via the DAC (e.g., DAC 116) is also zero. In this way, when the adder uses the input signal Ain to subtract the output signal (e.g., output signal 120), the difference 122 obtained is almost the same as the input signal Ain, which causes the difference 122 to be too large, resulting in a large nonlinear error, affecting the accuracy of the analog-to-digital converter. In the embodiment of the present invention, since a loop filter 112 having a preset circuit is provided, the value at the output terminal 124 of the loop filter 112 after passing through the loop filter 112 is not zero, but is preset by the preset circuit in the loop filter 112 to a preset value, so that the value of the output signal 120 after passing through the DAC 116 is equal to the value of the preset value, and then the adder 118 can be operated to use the input signal Ain to subtract the output signal 120, and the obtained difference 122 will be smaller, thereby limiting the size of the difference 122, reducing the nonlinear error, and thus improving the accuracy.

[0025] Figure 21 shows a waveform of a reset signal RST. The reset signal generator 106 can generate the reset signal RST according to the clock signal CLK. As shown in the figure, a reset phase is required between analog-to-digital conversion cycles. During the reset phase of the incremental ADC 100, the output terminal of the loop filter 112 is preset.

[0026] Figure 3 An incremental ADC 300 , which is a continuous-time ADC, is depicted according to an exemplary embodiment of the present invention.

[0027] like Figure 3 As shown, Figure 1 The loop filter 112 may include Figure 3 The first stage circuit 302 and the second stage circuit 304 shown, wherein each stage circuit (the first stage circuit 302 and the second stage circuit 304) involves integral calculation, the first stage circuit 302 and the second stage circuit 304 can be respectively referred to as analog integrators, the first stage circuit 302 can also be referred to as a first analog integrator, and the second stage circuit 304 can also be referred to as a second analog integrator. Alternatively, in this embodiment, the analog integrator may include a first analog integrator (the first stage circuit 302), and may also include a second analog integrator (the second stage circuit 304). During the reset phase of the incremental ADC 300, the integral output INT1 of the first stage circuit 302 and the integral output INT2 of the second stage circuit 304 are preset (instead of zero). Specifically, in the prior art, the integral output INT1 and the integral output INT2 are both zero. In the embodiment of the present invention, the integral output INT1 of the first stage circuit 302 and the integral output INT2 of the second stage circuit 304 can be respectively preset, and the preset value can be a positive number or a negative number (the adder can correspondingly reduce the input signal Ain according to the positive number or the negative number).

[0028] In the first stage circuit 302, there are an operational amplifier op1, a feedback capacitor C1, a preset element PE1 and a switch SW1. The difference 122 is coupled to the input terminal "-" of the operational amplifier op1. The integrated output INT1 is generated at the output terminal of the operational amplifier op1. The feedback capacitor C1 is coupled between the input terminal "-" and the output terminal of the operational amplifier op1. The preset element PE1 and the switch SW1 are connected in series between the input terminal "-" and the output terminal of the operational amplifier op1. During the reset phase of the incremental ADC 300, the switch SW1 is closed by the reset signal RST, so that the preset element PE1 is connected in parallel with the feedback capacitor C1. The feedback capacitor C1 is not completely cleaned up, so the integrated output INT1 is preset in the reset phase of the incremental ADC 300 instead of being cleaned to zero.

[0029] In the second stage circuit 304, there are an operational amplifier op2, a feedback capacitor C2, an input resistor Rin, a preset element PE2, and a switch SW2. The integrated output INT1 from the first stage circuit 302 is coupled to the input terminal "-" of the operational amplifier op2 through the input resistor Rin. The integrated output INT2 is generated at the output terminal of the operational amplifier op2. The feedback capacitor C2 is coupled between the input terminal "-" and the output terminal of the operational amplifier op2. The preset element PE2 and the switch SW2 are connected in series between the input terminal "-" and the output terminal of the operational amplifier op2. During the reset phase of the incremental ADC 300, the switch SW2 is closed by the reset signal RST, so that the preset element PE2 is connected in parallel with the feedback capacitor C2. The feedback capacitor C2 is not completely cleaned, so during the reset phase of the incremental ADC 300, the integrated output INT2 is preset instead of being reset to zero.

[0030] exist Figure 3 In the embodiment, the second stage circuit 304 further has a preset element PE3 and a switch SW3. The preset element PE3 and the switch SW3 are connected in series between the output terminal of the operational amplifier op1 and the input terminal "-" of the operational amplifier op2. During the reset phase of the incremental ADC 300, the switch SW3 is closed by the reset signal RST, so that the preset element PE3 is connected in parallel with the input resistor Rin. The preset integral output INT1 is coupled to the second stage circuit 304 via the preset element PE3 and the input resistor Rin connected in parallel. The preset element PE3 and the switch SW3 are optional. Among them, the input resistor Rin and the feedback capacitor C2 can form an RC filter circuit to remove noise, etc. In addition, the circuit composed of the preset element PE3 and the switch SW3 can be set according to the type of the received signal. For example, when the input signal Ain is a voltage signal, a circuit similar to the preset element PE3 and the switch SW3 can also be set before the first stage circuit 302. If the input signal Ain is a current signal, a circuit similar to the preset element PE3 and the switch SW3 may not be set. Of course, generally speaking, after passing through the analog integrator (such as the first-stage circuit 302 or the second-stage circuit 304), a voltage is obtained (such as the integrated outputs INT1 and INT2 are voltages). Therefore, when other analog integrators are set behind the analog integrator, a circuit similar to that including the preset element PE3 and the switch SW3 can be set.

[0031] exist Figure 3In the embodiment, the preset elements PE1, PE2 and PE3 are resistors, but are not limited thereto. The preset elements PE1, PE2 and PE3 may be buffers, or any active or passive components. In addition, in the present embodiment, there may be only the first stage circuit 302, but no second stage circuit 304. That is, there may be only one stage circuit (with one preset element) in the embodiment of the present invention. Of course, there may also be circuits with more stages, such as two stages, three stages, etc. (also referred to as first order, second order, third order).

[0032] The switches SW1, SW2 and SW3 and the preset elements PE1, PE2 and PE3 form a preset circuit, which presets the output terminal 124 of the loop filter 112 in the reset phase of the incremental ADC. It can be seen from the above embodiments that the corresponding preset value can be determined by the preset element, for example, the integral output INT1 can be determined by the preset element PE1 (for example, determined by the resistance value of the preset element PE1).

[0033] Figure 4 The instantaneous waveforms of the integral outputs INT1 and INT2 and the quantized signal Do are shown. The solid lines 402, 404 and 406 are the instantaneous waveforms of the integral outputs INT1, INT2 and the quantized signal Do of the incremental ADC 100, respectively. The dotted lines 408, 410 and 412 are the instantaneous waveforms of the signals of the conventional incremental ADC, wherein the output terminal of the loop filter is also reset during the reset phase of the ADC. Referring to the solid lines 402 and 404 in the present invention, the integral outputs INT1 and INT2 are preset (during the time interval 400, corresponding to the reset phase of the ADC), instead of being reset (for example, reset to zero), that is, the analog integrator can be reset during the reset phase, but at this time the integral outputs INT1 and INT2 are also not zero (preset values), that is, the integral outputs INT1 and INT2 are not reset. And it is shown that the settling time is shorter (compared with the dotted lines 408 and 410), that is, compared with the dotted line 412, due to the preset integral outputs INT1 and INT2, the quantized signal Do shown in the solid line 406 is quickly increased to the expected value. In the present invention, the transient response of the incremental ADC is significantly improved, thereby being able to meet higher load conversion requirements and adapt to more application scenarios.

[0034] Figure 5 An incremental ADC 500 , which is a discrete-time ADC, is depicted according to an exemplary embodiment of the present invention.

[0035] like Figure 5 As shown, Figure 1The loop filter 112 may include two cascaded (ie, serially connected) switched-capacitor integrators 502 and 504, a switch SWa, a preset element PEa, a switch SWb, and a preset element PEb. The switch SWa and the preset element PEa are connected in series. The switch SWb and the preset element PEb are connected in series. The switched-capacitor integrator 502 outputs an integrated output INT1. The switched-capacitor integrator 504 outputs an integrated output INT2. When the switches SWa and SWb are closed according to the reset signal RST of the incremental ADC 500, the analog input signal Ain is coupled to the integrated output INT1 through the preset element PEa, and the integrated output INT1 is coupled to the integrated output INT2 through the preset element PEb. Therefore, when entering the subsequent analog-to-digital conversion cycle, the quantization signal Do is not zero (because the integrated outputs INT1 and INT2 are not zero but preset values), which effectively limits the difference 122. Therefore, the switched-capacitor integrators 502 and 504 all operate (run or work) in their linear regions. Non-linear errors caused by the dramatic change in difference value 122 at the beginning of each analog-to-digital conversion cycle are reduced.

[0036] exist Figure 5 In the example shown, the switched capacitor integrators 502 and 504 are resettable (meaning that the interior of the switched capacitor integrators 502 and 504 can be cleared to zero, but the integral outputs INT1 and INT2 are not zero). According to the reset signal RST, the capacitors in the switched capacitor integrators 502 and 504 are cleaned. The preset state of the integral outputs INT1 and INT2 is achieved by closed switches SWa and SWb and preset elements PEa and PEb (that is, the integral outputs INT1 and INT2 can be preset and not zero). The preset elements PEa and PEb can be resistors, buffers or any active or passive components. The preset values ​​of the integral outputs INT1 and INT2 can be determined by the preset elements PEa and PEb, respectively (for example, by the size of the resistance value of the preset elements PEa and PEb or other parameters).

[0037] The switches SWa and SWb and the preset elements PEa and PEb form a preset circuit that presets the output terminal 124 of the loop filter 112 in a reset phase of the incremental ADC.

[0038] In another exemplary embodiment, RC (Resistor-Capacitance) integrators may be used to replace the switched capacitor integrators 502 and 504. In this embodiment, the switched capacitor integrators 502 and 504 may belong to the first analog integrator and the second analog integrator respectively (the analog integrator may include the first analog integrator and the second analog integrator), wherein the first analog integrator may include the switched capacitor integrator 502 and a switch SWa and a preset element PEa connected in parallel with the switched capacitor integrator 502 (the switch SWa and the preset element PEa are connected in series), one end of the switch SWa is also connected to the input end of the adder 118 (the input end receives the input signal Ain), and one end of the preset element PEa is also connected to the output end of the switched capacitor integrator 502 (that is, the integration output INT1). The second analog integrator may include a switched capacitor integrator 504 and a switch SWb and a preset element PEb connected in parallel with the switched capacitor integrator 504 (the switch SWb and the preset element PEb are connected in series), one end of the switch SWb is also connected to the output end of the preset element PEa (i.e., the integration output INT1), and one end of the preset element PEb is also connected to the output end of the switched capacitor integrator 504 (i.e., the integration output INT2). In this embodiment, there may be only one analog integrator, such as the first analog integrator, or two analog integrators or more analog integrators.

[0039] exist Figure 3 and Figure 5 In the embodiment, only two cascade (series) integrators are shown. However, the number of cascade (series) integrators in the loop filter 112 is not limited to two, and may be one, or three, or more. In the present embodiment, two-stage analog integrators are provided to more accurately set the preset value, thereby improving the accuracy of the converter. Any circuit design that pre-sets the output terminal 124 of the loop filter 112 during the reset phase of the entire ADC should be considered within the scope of the present invention.

[0040] based on Figure 3 The loop filter 112 may include a plurality of analog integrators (e.g., a first stage circuit and a second stage circuit) cascaded in a series or one analog integrator, and the preset circuit of the loop filter 112 includes analog integrators of a plurality of preset elements (PE#) corresponding to the plurality of modules in a one-to-one correspondence. In the reset phase of the incremental analog-to-digital converter, each preset element is connected in parallel with the feedback capacitor of the corresponding analog integrator.

[0041] based on Figure 5According to the concept of FIG. 1 , the loop filter 112 may include a plurality of analog integrators connected in series or one analog integrator, and during the reset phase of the incremental analog-to-digital converter, the preset circuit of the loop filter 112 couples the analog input signal to the output terminal of the analog integrator.

[0042] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. An incremental analog-to-digital converter, characterized in that: include: A delta-sigma modulator performs delta-sigma modulation on an analog input signal to output a quantized signal; as well as a digital filter receiving the quantized signal to generate a digital representation of the analog input signal, in: The delta-sigma modulator includes a quantizer, a digital-to-analog converter and a loop filter; The quantizer outputs the quantized signal; The digital-to-analog converter is coupled to the output of the quantizer and generates an estimate of the quantized signal; The loop filter operates on the difference between the analog input signal and the estimate, and an output of the loop filter is coupled to an input of a quantizer; and The loop filter has a preset circuit, and in the reset phase of the incremental analog-to-digital converter, the preset circuit presets the output terminal of the loop filter; The loop filter includes a first analog integrator; The first analog integrator has a first operational amplifier and a first feedback capacitor coupled between an input terminal and an output terminal of the first operational amplifier; The preset circuit includes a first switch and a first preset element, wherein the first switch and the first preset element are connected in series between an input terminal and an output terminal of the first operational amplifier, and the first preset element is a resistor; as well as During a reset phase of the incremental analog-to-digital converter, the first switch is closed and the output terminal of the loop filter is preset to a non-zero preset value.

2. The incremental analog-to-digital converter according to claim 1, wherein: The loop filter includes a plurality of analog integrators, the plurality of analog integrators including the first analog integrator; The preset circuit includes a plurality of preset elements, and the plurality of preset elements include the first preset element; as well as During the reset phase of the incremental analog-to-digital converter, each of the preset elements is connected in parallel with a feedback capacitor of the corresponding analog integrator.

3. The incremental analog-to-digital converter according to claim 1, wherein: The loop filter further includes a second analog integrator coupled between the first analog integrator and the quantizer; The second analog integrator has a second operational amplifier and a second feedback capacitor coupled between an input terminal and an output terminal of the second operational amplifier; The preset circuit further includes a second switch and a second preset element, wherein the second switch and the second preset element are connected in series between an input terminal and an output terminal of the second operational amplifier; as well as During a reset phase of the incremental analog-to-digital converter, the second switch is closed.

4. The incremental analog-to-digital converter according to claim 3, wherein: the second analog integrator comprising an input resistor coupled between an output terminal of the first operational amplifier and an input terminal of the second operational amplifier; The preset circuit further includes: a third switch and a third preset element, wherein the third switch and the third preset element are connected in series between the output terminal of the first operational amplifier and the input terminal of the second operational amplifier; as well as During a reset phase of the incremental analog-to-digital converter, the third switch is closed.

5. The incremental analog-to-digital converter according to claim 4, characterized in that: The second preset element and the third preset element are resistors.

6. The incremental analog-to-digital converter according to claim 1, wherein: The digital filter comprises a digital integrator, and the digital integrator is reset during the reset phase of the incremental analog-to-digital converter.

7. The incremental analog-to-digital converter according to claim 1, wherein: During a reset phase of the incremental analog-to-digital converter, the first analog integrator is reset.

8. An incremental analog-to-digital converter, characterized in that: include: A delta-sigma modulator performs delta-sigma modulation on an analog input signal to output a quantized signal; as well as a digital filter receiving the quantized signal to generate a digital representation of the analog input signal, in: The delta-sigma modulator includes a quantizer, a digital-to-analog converter and a loop filter; The quantizer outputs the quantized signal; The digital-to-analog converter is coupled to the output of the quantizer and generates an estimate of the quantized signal; The loop filter operates on the difference between the analog input signal and the estimate, and an output of the loop filter is coupled to an input of a quantizer; and The loop filter has a preset circuit, and in the reset phase of the incremental analog-to-digital converter, the preset circuit presets the output terminal of the loop filter; The loop filter comprises a first analog integrator, the first analog integrator comprises a first switched capacitor integrator, a first switch and a first preset element connected in parallel with the first switched capacitor integrator, the first switch and the first preset element being connected in series; During a reset phase of the incremental analog-to-digital converter, the first switch is closed, the preset circuit couples the analog input signal to the output terminal of the first analog integrator, and the output terminal of the loop filter is preset to a non-zero preset value.

9. The incremental analog-to-digital converter according to claim 8, characterized in that: During a reset phase of the incremental analog-to-digital converter, the first analog integrator is reset.

10. The incremental analog-to-digital converter according to claim 8, wherein: The digital filter comprises a digital integrator, and the digital integrator is reset during the reset phase of the incremental analog-to-digital converter.

11. The incremental analog-to-digital converter according to claim 10, wherein: During a reset phase of the incremental analog-to-digital converter, the quantizer is reset.

Images