A wake-up and sleep circuit for AC charging CP signal

Abstract

The invention discloses an AC charging CP signal wake-up and sleep circuit, which is characterized by comprising a 5V normal power module, a CP signal conversion module, a D trigger module, a D latch module, a BMS main control chip, a selection switch module and a power supply module, wherein: the 5V normal power module is respectively connected to the CP signal conversion module, the D trigger module and the D latch module; the CP signal conversion module is sequentially connected to the D trigger module, the D latch module, the selection switch module and the power supply module; the BMS main control chip is respectively connected to the D trigger module, the D latch module, the selection switch module and the power supply module. The invention realizes the function of automatically waking up the BMS by the AC charging CP signal and automatically putting the BMS to sleep by controlling the logic combination of the high and low level changes of the input and output signals of the D trigger and the D latch, and has great production practice significance.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management, and in particular to a wake-up and sleep circuit of an alternating current charging CP signal. Background Art

[0002] The Battery Management System (BMS) is a battery protection device and a bridge between the battery and the load terminal. It provides overcharge, over-discharge, over-temperature and other protection functions for the battery according to the actual use status of the battery monitored online to ensure the safe use of the battery. The battery management system BMS is widely used in many fields such as electric vehicles, communication base stations, robots, etc.

[0003] Taking electric vehicles as an example, when the on-board power battery system (hereinafter referred to as the battery system) is charged by AC charging, if the charging gun on the car charging pile is not unplugged for a long time after charging is completed, the battery system will consume power, which will affect the car's cruising range; it will also cause the on-board battery to be fed, affecting the normal use of the on-board electronic and electrical components (including BMS).

[0004] The reason for the above problems is that the charging gun is not unplugged after charging is completed, and the charging gun always maintains a 12V voltage for the charging wake-up CP (CP stands for charging wake-up) signal to the battery management system BMS, so that the battery management system BMS cannot enter a low-power sleep state, but continues to maintain a high-power normal working state. At this time, if the battery management system BMS is powered by an on-board DC / DC power supply (powered by the battery system), the DC / DC power supply will consume the power of the battery system due to continuous power supply to the battery management system BMS; if the battery management system BMS is powered by an on-board battery, the battery management system BMS will continue to consume the power of the on-board battery.

[0005] Currently, there are two types of charging wake-up CP signals for AC charging: 12V or PWM signal.

[0006] In view of the above problems, some existing technical solutions use the PWM signal output from the CP end (i.e., the charging wake-up end) of the AC charging interface to wake up the BMS and control the BMS to sleep. However, the PWM signal detection and processing circuit and the PWM signal driving circuit of these technical solutions are relatively complex and have high design costs.

[0007] Therefore, there is an urgent need to develop a wake-up and sleep solution for the AC charging CP signal that does not use the PWM signal as a trigger signal and has a low cost. Summary of the invention

[0008] The purpose of the present invention is to provide a wake-up and sleep circuit for an AC charging CP signal in view of the technical defects in the prior art.

[0009] To this end, the present invention provides an AC charging CP signal wake-up and sleep circuit, including a 5V normal power module, a CP signal conversion module, a D trigger module, a D latch module, a BMS main control chip, a selection switch module and a power module, wherein:

[0010] The 5V constant power module is connected to the CP signal conversion module, the D flip-flop module and the D latch module respectively, and is used to provide a continuous 5V DC output for the CP signal conversion module, the D flip-flop module and the D latch module;

[0011] A CP signal conversion module, which has two input ends respectively connected to the output end CP of the charging interface of the charging gun and the output end of the 5V normal power module, and is used to convert the CP signal output by the output end CP of the charging interface of the charging gun into a 5V signal, and then input it into the clock signal input end CLK of the D flip-flop module;

[0012] A D flip-flop module, wherein the signal input terminal D1 and the preset input terminal PRE are respectively connected to the output terminal of the 5V constant power module;

[0013] A D flip-flop module, having a clear input terminal CLR connected to an output terminal of the BMS main control chip;

[0014] A D flip-flop module, having a clock signal input terminal CLK connected to the output terminal of the CP signal conversion module, and used for receiving a 5V signal input by the CP signal conversion module;

[0015] A D flip-flop module, having an output terminal connected to an input terminal D2 of the D latch module, for providing an input signal to the D latch module;

[0016] A D latch module, having a latch enable input terminal LEN connected to an output terminal of a 5V normal power module;

[0017] A D latch module, which has an output enable input terminal OEN connected to the output terminal of the BMS main control chip, and is used to receive an output state control signal output by the BMS main control chip;

[0018] A D latch module, having an input terminal D2 connected to the output terminal of the D flip-flop module, for receiving an output signal of the D flip-flop module;

[0019] A D latch module, having an output end connected to the input end of the selection switch module, for inputting a charging wake-up signal WKUP to the selection switch module;

[0020] The BMS main control chip includes three signal output terminals, wherein the first signal output terminal is connected to the clear input terminal CLR of the D flip-flop module, and is used to provide a clear control signal for the D flip-flop module, and control the high and low level states of the input signal of the clear input terminal CLR of the D flip-flop module;

[0021] Among them, the second signal output terminal of the BMS main control chip is connected to the output enable input terminal OEN of the D latch module, and is used to provide an output state control signal for the D latch module, thereby controlling the high and low level states of the input signal of the output enable input terminal OEN of the D latch module;

[0022] The third signal output terminal of the BMS main control chip is connected to the input terminal of the selection switch module, and is used to provide a charging wake-up self-locking signal PWR for the selection switch module;

[0023] In addition, the power input terminal DVDD of the BMS main control chip is connected to the output terminal of the power module, and is used to receive the DC power output by the power module;

[0024] The PWM input terminal of the BMS main control chip is connected to the output terminal CP of the charging interface of the charging gun, and is used to detect the PWM signal provided by the output terminal CP of the charging interface of the charging gun to determine whether charging is completed;

[0025] A selection switch module, which includes two signal input terminals for realizing an OR logic function;

[0026] A first signal input end of the selection switch module is connected to the output end of the D latch module and is used to receive a charging wake-up signal WKUP input by the D latch module;

[0027] The second signal input end of the selection switch module is connected to the output of the BMS main control chip and is used to receive the charging wake-up self-locking signal PWR output by the BMS main control chip;

[0028] The output end of the selection switch module is connected to the power enable input end EN of the power module, and is used to provide a power enable signal EN to the power module, thereby controlling the on and off of the power output of the power module;

[0029] A power supply module having a power output enable input terminal EN connected to the output terminal of the selection switch module and used to receive a power enable signal EN output by the selection switch module, wherein the high and low level states of the power enable signal EN control whether the power supply module outputs a DC power supply;

[0030] The output end of the power module is connected to the power input end DVDD of the BMS main control chip. When the power module outputs DC power, the power module supplies power to the BMS main control chip, thereby waking up the battery management system BMS. When the power module does not output DC power, it stops supplying power to the BMS main control chip, thereby putting the BMS into sleep mode.

[0031] The input end of the 5V normal power module is connected to an external normal power source of 12V or 24V.

[0032] The CP signal conversion module 200 includes a switch K1, a switch K2, a resistor R15, a resistor R16 and a resistor R17, wherein:

[0033] The controlled end of the switch K1 is connected to the output end CP of the charging port of the charging gun;

[0034] One end of the switch K1 is connected to the second pin of the resistor R15;

[0035] The other end of the switch K1 is connected to the ground terminal GND;

[0036] The controlled end of the switch K2 is connected to the first pin of the resistor R15;

[0037] One end of the switch K2 is connected to the output end of the 5V normal power module;

[0038] The other end of the switch K2 is connected to the first pin of the resistor R16;

[0039] The first pin of the resistor R17 is connected to the second pin of the resistor R16 and the clock signal input terminal CLK of the D flip-flop module;

[0040] The second pin of the resistor R17 is connected to the ground terminal GND.

[0041] Wherein, the D trigger module includes a D trigger and a reset control circuit, and the D trigger and the reset control circuit are connected;

[0042] Among them, the D flip-flop is edge triggered and has preset and clear functions. The clear control circuit is connected to the first signal output terminal of the BMS main control chip, and is used to receive the clear control signal output by the BMS main control chip, so as to control whether the clear function of the D flip-flop is effective.

[0043] The D trigger module includes a D trigger, a resistor R1, a resistor R2, a resistor R3, a resistor R8 and a reset control circuit, wherein:

[0044] The zeroing control circuit includes resistors R4, R5, R6, R7 and an enhanced N-channel field effect transistor Q1;

[0045] The power input terminal VCC of the D flip-flop is connected to the second pin of the resistor R1;

[0046] The preset input of the D flip-flop The end is connected to the second pin of the resistor R2;

[0047] The input terminal D of the D flip-flop is connected to the second pin of the resistor R3;

[0048] The clear input of the D flip-flop Connect the first pin of the resistor R5;

[0049] The output terminal Q of the D flip-flop is connected to the first pin of the resistor R8;

[0050] The clock signal input terminal CLK of the D flip-flop is connected to the output terminal of the CP signal conversion module;

[0051] The first pin of the resistor R1, the first pin of the resistor R2 and the first pin of the resistor R3 are respectively connected to the output end of the 5V normal power module;

[0052] The second pin of the resistor R8 is connected to the first pin of the resistor R9;

[0053] The second pin of the resistor R9 is connected to the ground terminal GND;

[0054] The second pin of the resistor R5 is connected to the second pin of the resistor R4 and the drain D of the NMOS transistor Q1 respectively;

[0055] The first pin of the resistor R4 is connected to the output end of the 5V normal power module;

[0056] The gate G of the NMOS transistor Q1 is connected to the first pin of the resistor R6 and the second pin of the resistor R7 respectively;

[0057] The source S of the NMOS tube Q1 and the first pin of the resistor R7 are connected to the ground terminal GND respectively;

[0058] The second pin of the resistor R6 is connected to the third signal output terminal of the BMS main control chip.

[0059] Wherein, the D latch module includes a D latch and an output control circuit, and the D latch and the output control circuit are connected;

[0060] Wherein, the D latch has a tri-state gate output function;

[0061] The output control circuit is connected to the second signal output terminal of the BMS main control chip, and is used to receive the output enable signal OEN output by the BMS main control chip.

[0062] Wherein, the D latch module includes a D latch, a resistor R10, a resistor R11, a resistor R14 and an output control circuit;

[0063] Wherein, the output control circuit includes a resistor R12 and a resistor R13;

[0064] The power input terminal VCC of the D latch is connected to the second pin of the resistor R11;

[0065] The latch input terminal LE of the D latch is connected to the second pin of the resistor R10;

[0066] The input terminal D of the D latch is connected to the second pin of the resistor R8 and the first pin of the resistor R9 respectively;

[0067] The output enable input of the D latch Respectively connect the second pin of the resistor R12 and the first pin of the resistor R13;

[0068] The output terminal Q of the D latch is connected to the first pin of the resistor R14 and the input terminal of the selection switch module;

[0069] The first pin of the resistor R10 and the first pin of the resistor R11 are respectively connected to the output end of the 5V normal power module;

[0070] The first pin of the resistor R12 is connected to the ground terminal GND;

[0071] The second pin of the resistor R13 is respectively connected to the second pin of the resistor R6 and the third signal output terminal of the BMS main control chip;

[0072] The second pin of the resistor R14 is connected to the ground terminal GND.

[0073] Among them, the control logic strategy of the circuit to wake up the battery management system BMS through the CP signal is as follows:

[0074] Step S0: Before the charging gun is inserted, the CP signal outputted by the output terminal CP of the charging interface of the charging gun is 0V and the BMS is in a dormant state. The BMS main control chip has no reset control signal inputted into the D trigger module, so that the reset function of the D trigger module is invalid, that is, the output terminal of the D trigger module will change in the same direction as its input signal after the clock signal CLK has a rising edge valid signal. When the clock signal CLK is invalid, the output of the D trigger module is a low-level signal; the BMS main control chip has no output state control signal inputted into the D latch module, so that the high-impedance output of the D latch module is invalid, that is, the output of the D trigger module changes in the same direction as its input signal, and the output charging wake-up signal WKUP is a low-level signal;

[0075] Step S1: After the charging gun is inserted and before charging starts, the CP signal outputted by the output terminal CP of the charging interface of the charging gun jumps from 0V to 12V. The rising edge valid signal is input into the clock signal input terminal CLK of the D flip-flop module via the CP signal conversion module, triggering the output of the D flip-flop module to change from low level to high level, so that the charging wake-up signal WKUP outputted by the D latch module changes from low level to high level valid signal, so that the power enable signal EN outputted by the selection switch module is high level, triggering the power module to output power to activate the BMS main control chip, at which time the BMS is initially awakened but charging is not allowed;

[0076] Step S2: After the BMS is initially awakened, the BMS main control chip outputs a high-level charging awakening self-locking signal PWR to the selection switch module, and the power enable signal EN output by the selection switch module continues to maintain a high level, controls the power module to output power, and continuously supplies power to the BMS main control chip; the BMS main control chip inputs a high-level reset control signal to the D flip-flop module, so that the reset function of the D flip-flop module changes from invalid to valid, that is, the output signal of the D flip-flop module is locked from a high level to a low level until the reset control signal is revoked; the BMS main control chip inputs a high-level output state control signal to the D latch module, so that the high-impedance output of the D latch changes from invalid to valid, that is, the charging wake-up signal WKUP output by the D latch module is locked from a high level to a low level until the output state control signal is revoked; at this point, the BMS is fully awakened and charging is allowed.

[0077] Wherein, after step S2, the following control steps are also included:

[0078] Step S3: When the charging of the charging gun starts, the CP signal output by the output terminal CP of the charging interface of the charging gun changes from 12V to a PWM signal until the charging is completed. The rising edge of the PWM signal does not affect the low-level output signals of the D flip-flop module and the D latch module. The PWM signal is the basis for the BMS main control chip to determine the end of charging; wherein, when the output terminal CP of the charging interface of the charging gun no longer provides a PWM signal, it indicates that the charging is completed; otherwise, if it continues to provide it, it indicates that the charging is not yet completed.

[0079] After step S3, the following control steps are also included:

[0080] Step S4: When charging is completed and the charging gun is not unplugged, the CP signal output by the output terminal CP of the charging interface of the charging gun changes from a PWM signal to 12V. At this time, the control logic strategy of automatically putting the BMS into sleep mode by executing the CP signal specifically includes the following sub-steps:

[0081] Step S40, before the BMS goes into sleep, under the combined effect of the D flip-flop module clearing function being effective and the D latch module high impedance output being effective, the charging wake-up signal WKUP output by the D latch module 400 is kept at a low level, that is, the WKUP signal is invalid; the charging wake-up self-locking signal PWR output by the BMS main control chip 500 is kept at a high level, that is, the PWR signal is effective;

[0082] Step S41, when the CP signal outputted by the output terminal CP of the charging port of the charging gun changes from a PWM signal to a 12V continuous high level signal, the third signal output terminal of the BMS main control chip stops outputting the charging wake-up self-locking signal PWR, that is, the PWR signal changes from a high level to a low level;

[0083] Step S42, the power enable signal EN output by the switch selection module changes from a high level to a low level, so that the power module stops outputting power and no longer supplies power to the BMS main control chip;

[0084] Step S43, after the BMS main control chip is powered off, there is no output signal input to the D flip-flop module and the D latch module, so that the clearing function of the D flip-flop module changes from valid to invalid, and the high-impedance output of the D latch module changes from valid to invalid, so that the outputs of the D flip-flop module and the D latch can change in the same direction as their input signals;

[0085] Step S44: In view of the fact that the CP signal outputted by the output terminal CP of the charging interface of the charging gun maintains a high level of 12V, and there is no rising edge signal that jumps from 0V to 12V input to the clock signal input terminal CLK of the D flip-flop module, the output of the D flip-flop module still maintains a low level, so that the charging wake-up signal WKUP also maintains a low level, thereby locking the BMS main control chip into a power-off state. At this point, the BMS is in sleep mode.

[0086] It can be seen from the technical solution provided by the present invention that, compared with the prior art, the present invention provides a wake-up and sleep circuit for an AC charging CP signal, which does not use a PWM signal as a trigger signal, but realizes the function of automatically waking up the BMS and automatically sleeping the BMS by the AC charging CP signal through the logical combination control of the high and low level changes of the input and output signals of the D flip-flop and the D latch, which has great production practical significance.

[0087] In addition, the hardware circuit design of the present invention is scientific, the electronic components are commonly used models, easy to select, no additional system resources of the BMS main control chip are required, and the circuit board occupies a small space, and the design cost is very low;

[0088] In addition, the hardware circuit of the present invention has very low power consumption and hardly increases the BMS system overhead. Even if the charging gun is not unplugged for a long time, the battery system or the on-board battery will not consume power, thereby ensuring the required working time of the vehicle. Therefore, the technical solution of the present invention has strong practical value and market promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Figure 1 A structural block diagram of a wake-up and sleep circuit of an AC charging CP signal provided by the present invention;

[0090] Figure 2 A schematic diagram of a specific connection structure of an AC charging CP signal wake-up and sleep circuit provided by the present invention. DETAILED DESCRIPTION

[0091] In order to make the technical means implemented by the present invention easier to understand, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It is also necessary to explain that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings.

[0092] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0093] See also Figure 1 , Figure 2 The present invention provides an AC charging CP signal wake-up and sleep circuit, including a 5V constant power module 100, a CP signal conversion module 200, a D trigger module 300, a D latch module 400, a BMS main control chip 500, a selection switch module 600 and a power module 700, wherein:

[0094] The 5V constant power module 100 is connected to the CP signal conversion module 200, the D flip-flop module 300 and the D latch module 400, respectively, and is used to provide a continuous 5V DC output for the CP signal conversion module 200, the D flip-flop module 300 and the D latch module 400;

[0095] In the present invention, in a specific implementation, the input end of the 5V normal power module 100 is connected to an external normal power source of 12V or 24V.

[0096] The CP signal conversion module 200 has two input terminals respectively connected to the output terminal CP of the charging interface of the charging gun and the output terminal of the 5V normal power module 100, and is used to convert the CP signal outputted by the output terminal CP of the charging interface of the charging gun into a 5V signal, and then input it into the clock signal input terminal CLK of the D flip-flop module 300;

[0097] The D flip-flop module 300 has a signal input terminal D1 and a preset input terminal PRE which are respectively connected to the output terminal of the 5V constant power module 100, and the signals of the two input terminals are always kept as high level signals;

[0098] The D flip-flop module 300 has a clear input terminal CLR connected to the output terminal of the BMS main control chip 500, and the high and low level states of the input signal of the clear input terminal CLR are controlled by the output terminal of the BMS main control chip 500;

[0099] A D flip-flop module 300, having a clock signal input terminal CLK connected to the output terminal of the CP signal conversion module 200, for receiving a 5V signal input by the CP signal conversion module 200, wherein the 5V signal is valid on a rising edge;

[0100] A D flip-flop module 300, having an output terminal connected to an input terminal D2 of the D latch module 400, for providing an input signal to the D latch module 400;

[0101] It should be noted that, for the D flip-flop module 300, according to the level state of all the above-mentioned input signals (i.e., the 5V signal output by the 5V normal power module 100, the 5V signal output by the CP signal conversion module 200, and the reset control signal output by the BMS main control chip 500), the corresponding signal is output, specifically: when the reset input terminal CLR of the D flip-flop module 300 is at a low level, the output terminal of the D flip-flop module 300 is at a low level, which is independent of the signal level states of D1 and CLK; when the reset input terminal CLR of the D flip-flop module 300 is at a high level, when the clock CLK signal output by the CP signal conversion module 200 changes from a low level to a high level, the output of the D flip-flop module is consistent with the level state of the DC output D1 signal output by the 5V normal power module 100, and when the D1 signal is at a high level, the output terminal of the D flip-flop module is at a high level, otherwise, the output terminal is at a low level.

[0102] The D latch module 400 has a latch enable input terminal LEN connected to the output terminal of the 5V constant power module 100, and always keeps the input signal at a high level;

[0103] A D latch module 400, which has an output enable input terminal OEN connected to the output terminal of the BMS main control chip 500, and the high and low level states of the output enable input terminal OEN are controlled by the output of the BMS main control chip 500, and is used to receive the output state control signal output by the BMS main control chip 500;

[0104] The D latch module 400 has an input terminal D2 connected to the output terminal of the D flip-flop module 400 and is used to receive the output signal of the D flip-flop module 300;

[0105] A D latch module 400, having an output end connected to the input end of the selection switch module 600, for inputting a charging wake-up signal WKUP to the selection switch module 600;

[0106] It should be noted that the D latch module 400 determines whether to output the charging wake-up signal WKUP according to the level state of all the above input signals (i.e., the 5V signal output by the 5V constant power module 100, the output signal of the D flip-flop module 400, and the output state control signal output by the BMS main control chip 500). Specifically, when the output enable input terminal OEN of the D latch module 400 is at a low level, the output terminal of the D latch module 400 is at a low level, and no charging wake-up signal WKUP is output, which is consistent with the input terminal D of the D latch module 400. 2 has nothing to do with the signal level state input by the D latch module 400; when the output enable input terminal OEN of the D latch module 400 is at a high level, the output terminal of the D latch module 400 is consistent with the level state of the D2 signal input by the input terminal D2 of the D latch module 400, and when the D2 signal input by the input terminal D2 of the D latch module 400 is at a high level, a high-level valid charging wake-up signal WKUP is output, and when the D2 signal input by the input terminal D2 of the D latch module 400 is at a low level, no charging wake-up signal WKUP is output.

[0107] The BMS main control chip 500 includes three signal output terminals, wherein the first signal output terminal is connected to the clear input terminal CLR of the D flip-flop module 300, and is used to provide a clear control signal for the D flip-flop module 300, and control the high and low level states of the input signal of the clear input terminal CLR of the D flip-flop module 300;

[0108] Among them, the second signal output terminal of the BMS main control chip 500 is connected to the output enable input terminal OEN of the D latch module 400, and is used to provide an output state control signal for the D latch module 400, thereby controlling the high and low level states of the input signal of the output enable input terminal OEN of the D latch module 400;

[0109] The third signal output terminal of the BMS main control chip 500 is connected to the input terminal of the selection switch module 600, and is used to provide the charging wake-up self-locking signal PWR for the selection switch module 600;

[0110] In addition, the power input terminal DVDD of the BMS main control chip 500 is connected to the output terminal of the power module 700, and is used to receive the DC power output by the power module 700;

[0111] The BMS main control chip 500 has a PWM input terminal, which is connected to the output terminal CP of the charging interface of the charging gun, and is used to detect the PWM signal provided by the output terminal CP of the charging interface of the charging gun, and determine whether charging is completed. When the output terminal CP of the charging interface of the charging gun no longer provides a PWM signal, it means that charging is completed; otherwise, if it continues to provide it, it means that charging has not yet ended.

[0112] A selection switch module 600 includes two signal input terminals for implementing an OR logic function;

[0113] A first signal input terminal of the selection switch module 600 is connected to the output terminal of the D latch module 400 and is used to receive the charging wake-up signal WKUP input by the D latch module 400;

[0114] The second signal input end of the selection switch module 600 is connected to the output of the BMS main control chip 500 and is used to receive the charging wake-up self-locking signal PWR output by the BMS main control chip 500;

[0115] The output end of the selection switch module 600 is connected to the power enable input end EN of the power module 700, so as to provide a power enable signal EN to the power module 700, thereby controlling the on and off of the power output of the power module 700;

[0116] It should be noted that the selection switch module 600 determines whether to output the power enable signal EN according to the high and low level states of the charging wake-up signal WKUP and the charging wake-up self-locking signal PWR. Specifically, when the charging wake-up self-locking signal PWR output by the BMS main control chip 500 is at a high level, the power enable signal EN output by the selection switch module 600 is also at a high level, which is independent of the level state of the charging signal wake-up signal WKUP; when the charging wake-up self-locking signal PWR output by the BMS main control chip 500 is at a low level, if the charging signal wake-up signal WKUP input by the D latch module 400 is at a high level, the power enable signal EN output by the selection switch module 600 is also at a high level; if the charging signal wake-up signal WKUP input by the D latch module 400 is at a low level, the power enable signal EN output by the selection switch module 600 is also at a low level.

[0117] The power module 700 has a power output enable input terminal EN connected to the output terminal of the selection switch module 600 and used to receive a power enable signal EN output by the selection switch module 600. The high and low level states of the power enable signal EN control whether the power module 700 outputs a DC power supply;

[0118] It should be noted that when the power enable signal EN output by the selection switch module 600 is at a high level, the power module 700 outputs a DC power supply, and when it is at a low level, the power module 700 stops outputting the DC power supply.

[0119] The output end of the power module 700 is connected to the power input end DVDD of the BMS main control chip 500. When the power module 700 outputs DC power, the power module 700 supplies power to the BMS main control chip 500, thereby waking up the BMS. When the power module 700 does not output DC power, it stops supplying power to the BMS main control chip 500, thereby putting the BMS into sleep mode.

[0120] In the present invention, it should be noted that the charging gun is the charging gun on the existing car charging pile. As described in the background technology part, the charging gun is not unplugged after charging is completed, and the charging wake-up CP (CP stands for charging wake-up) signal from the charging gun to the battery management system BMS always maintains a 12V voltage, so that the battery management system BMS cannot enter a low-power sleep state, but continues to maintain a high-power normal working state. At this time, if the battery management system BMS is powered by an on-board DC / DC power supply (powered by the battery system), the DC / DC power supply will consume the power of the battery system due to continuous power supply to the battery management system BMS; if the battery management system BMS is powered by an on-board battery, the battery management system BMS will continue to consume the power of the on-board battery.

[0121] In specific implementation, the charging gun is a charging pile on any electric vehicle conductive charging system (i.e., charging pile) that complies with the National Standard of the People's Republic of China GBT18487.1-2015 "General Requirements for Electric Vehicle Conductive Charging System Part 1".

[0122] In the present invention, the specific implementation is as follows: Figure 2 As shown, the CP signal conversion module 200 includes a switch K1, a switch K2, a resistor R15, a resistor R16 and a resistor R17, wherein:

[0123] The controlled end of the switch K1 is connected to the output end CP of the charging port of the charging gun;

[0124] One end of the switch K1 is connected to the second pin of the resistor R15;

[0125] The other end of the switch K1 is connected to the ground terminal GND;

[0126] The controlled end of the switch K2 is connected to the first pin of the resistor R15;

[0127] One end of the switch K2 is connected to the output end of the 5V normal power module 100;

[0128] The other end of the switch K2 is connected to the first pin of the resistor R16;

[0129] The first pin of the resistor R17 is connected to the second pin of the resistor R16 and the clock signal input terminal CLK of the D flip-flop module;

[0130] The second pin of the resistor R17 is connected to the ground terminal GND.

[0131] It should be noted that the switches K1 and K2 may be MOSFET, triode or photocoupler, so as to convert the input CP signal into an edge trigger signal acceptable to the D flip-flop module 300 .

[0132] It should be noted that, for the CP signal conversion module 200, when its input end is not connected to the output end CP of the charging port of the charging gun, the CP signal is 0V, so that the switch K1 and the switch K2 are both disconnected, and the signal of the first pin of the resistor R17 is low, that is, the output of the CP signal conversion module 200 is low. When the output end CP of the charging port of the charging gun is connected, the input signal CP of the CP signal conversion module 200 jumps from a low level to a high level (12V), so that the switches K1 and K2 are turned on, and the 5V output of the 5V normal power module is turned on, and the signal of the first pin of the resistor R17 jumps from a low level to a high level, that is, the output of the CP signal conversion module 200 is high.

[0133] In the present invention, the specific implementation is as follows: Figure 2 As shown, the D flip-flop module 300 includes a D flip-flop and a reset control circuit, and the D flip-flop and the reset control circuit are connected;

[0134] Among them, the D flip-flop is edge-triggered (rising edge valid) and has preset and clearing functions. The clearing control circuit is connected to the first signal output terminal of the BMS main control chip 500, and is used to receive the clearing control signal output by the BMS main control chip 500, so as to control whether the clearing function of the D flip-flop is valid.

[0135] In specific implementation, the D trigger module 300 includes a D trigger, a resistor R1, a resistor R2, a resistor R3, a resistor R8 and a reset control circuit, wherein:

[0136] The zeroing control circuit includes resistors R4, R5, R6, R7 and an enhanced N-channel field effect transistor (hereinafter referred to as NMOS transistor) Q1;

[0137] The power input terminal VCC of the D flip-flop is connected to the second pin of the resistor R1;

[0138] The preset input of the D flip-flop The end is connected to the second pin of the resistor R2;

[0139] The input terminal D of the D flip-flop is connected to the second pin of the resistor R3;

[0140] The clear input of the D flip-flop Connect the first pin of the resistor R5;

[0141] The output terminal Q of the D flip-flop is connected to the first pin of the resistor R8;

[0142] The clock signal input terminal CLK of the D flip-flop is connected to the output terminal of the CP signal conversion module 200;

[0143] The first pin of the resistor R1, the first pin of the resistor R2 and the first pin of the resistor R3 are respectively connected to the output end of the 5V normal power module;

[0144] The second pin of the resistor R8 is connected to the first pin of the resistor R9;

[0145] The second pin of the resistor R9 is connected to the ground terminal GND;

[0146] The second pin of the resistor R5 is connected to the second pin of the resistor R4 and the drain D of the NMOS transistor Q1 respectively;

[0147] The first pin of the resistor R4 is connected to the output end of the 5V normal power module;

[0148] The gate G of the NMOS transistor Q1 is connected to the first pin of the resistor R6 and the second pin of the resistor R7 respectively;

[0149] The source S of the NMOS tube Q1 and the first pin of the resistor R7 are connected to the ground terminal GND respectively;

[0150] The second pin of the resistor R6 is connected to the third signal output terminal (ie, the charging wake-up self-locking signal PWR output terminal) of the BMS main control chip 500 .

[0151] It should be noted that see Figure 2 As shown, for the D flip-flop module 300, the input terminal D of the D flip-flop, the preset enable input terminal The power input terminal VCC is connected to the output of the 5V normal power module 100 through resistors R3, R2 and R1 respectively, and always maintains a 5V high level; the latch input enable terminal LE and the power input terminal VCC of the D latch are connected to the output of the 5V normal power module 100 through resistors R10 and R11 respectively, and always maintains a 5V high level.

[0152] It should be noted that, for the D flip-flop module 300, in the reset control circuit, if there is no PWR signal input to the second pin of the resistor R6, the resistor R7 connects the gate of the NMOS transistor Q1 to the power ground, pulls the gate voltage of the NMOS transistor Q1 down to a low level, and turns it off; the resistors R4 and R5 connect the reset input terminal of the D flip-flop to the reset input terminal of the D flip-flop. Connected to the output terminal of the 5V constant power module 100, maintaining the reset input terminal of the D flip-flop When the PWR signal (high level) is input to the second pin of the resistor R6, the NMOS tube Q1 is turned on, and the second pin of the resistor R5 and the second pin of the resistor R4 are connected to the ground terminal GND. The resistor R5 turns the reset input terminal of the D flip-flop It is connected to the ground terminal GND and maintains a low level, so that the clearing function of the D flip-flop is effective, and the output of the D flip-flop is locked to a low level without being affected by the clock input signal CLK.

[0153] It should be noted that, for the D flip-flop module 300, when the D flip-flop clear function is invalid, when there is no rising edge signal at the clock signal input terminal CLK of the D flip-flop, the output terminal Q of the D flip-flop is connected to the ground terminal GND through the resistor R8 and the resistor R9, maintaining the output signal at a low level; when there is a rising edge signal at the clock signal input terminal CLK of the D flip-flop, the output terminal Q outputs a high level.

[0154] In the present invention, the specific implementation is as follows: Figure 2 As shown, the D latch module 400 includes a D latch and an output control circuit, and the D latch and the output control circuit are connected;

[0155] Wherein, the D latch has a tri-state gate output function;

[0156] The output control circuit is connected to the second signal output terminal of the BMS main control chip 500 and is used to receive the output enable signal OEN output by the BMS main control chip 500, thereby controlling the D latch to output a corresponding level signal according to the tri-state gate control logic.

[0157] In specific implementation, the D latch module 400 includes a D latch, a resistor R10, a resistor R11, a resistor R14 and an output control circuit;

[0158] Wherein, the output control circuit includes a resistor R12 and a resistor R13;

[0159] The power input terminal VCC of the D latch is connected to the second pin of the resistor R11;

[0160] The latch input terminal LE of the D latch is connected to the second pin of the resistor R10;

[0161] The input terminal D of the D latch is connected to the second pin of the resistor R8 and the first pin of the resistor R9 respectively;

[0162] The output enable input of the D latch Respectively connect the second pin of the resistor R12 and the first pin of the resistor R13;

[0163] The output terminal Q of the D latch is connected to the first pin of the resistor R14 and the input terminal of the selection switch module 600;

[0164] The first pin of the resistor R10 and the first pin of the resistor R11 are respectively connected to the output end of the 5V normal power module 100;

[0165] The first pin of the resistor R12 is connected to the ground terminal GND;

[0166] The second pin of the resistor R13 is respectively connected to the second pin of the resistor R6 and the third signal output terminal (i.e., the charging wake-up self-locking signal PWR output terminal) of the BMS main control chip 500;

[0167] The second pin of the resistor R14 is connected to the ground terminal GND.

[0168] It should be noted that see Figure 2 As shown, for the D latch module 400, in the output control circuit, when there is no PWR signal input to the second pin of the resistor R13, the resistor R12 turns the output enable input terminal of the D latch Connected to the power ground GND, the output enable input terminal is maintained When the input signal of the resistor R13 is low, the high-impedance output of the D latch is invalid, that is, the output of the D latch changes in the same direction as the input signal. When the input terminal D is high, the charging wake-up signal WKUP output by the output terminal Q is also high and valid, which can wake up the BMS main control chip 500. When the second pin of the resistor R13 has a PWR signal (high level) input, the output enable input terminal of the D latch is The pull-up is high level, so that the high-impedance output of the D latch is valid, that is, the output terminal Q of the D latch is in a high-impedance state, and the output terminal Q of the D latch is connected to the ground terminal GND through the resistor R14, then the charging wake-up signal WKUP output by the output terminal Q is pulled down to a low level, so that the charging wake-up signal WKUP is in an invalid state; when the high-impedance output of the D latch is valid, the charging wake-up signal WKUP is locked in an invalid state and is not affected by the change of the input signal of the input terminal D of the D latch.

[0169] In the present invention, in terms of specific implementation, it should be noted that the CP signal conversion module 200 can be a coupling circuit composed of a MOSFET or a transistor, can be composed of a photocoupler, or can be other circuit structures with similar functions, for converting the input CP signal into an edge trigger signal acceptable to the D trigger module 300.

[0170] In the present invention, in specific implementation, it should be noted that the selection switch module 600 can choose to use the currently commonly used OR logic circuit, such as composed of discrete resistors / diodes, or composed of switch integrated chips, or composed of existing OR logic integrated chips, etc.

[0171] In the present invention, in terms of specific implementation, it should be noted that the power supply module 700 and the 5V normal power module 100 can use the currently commonly used low-power, step-down DC power supply circuit or integrated power supply module 700, such as linear LDO, switching power supply, etc. The DC power supply circuit or integrated power supply module 700 should have a power output enable function to control the on and off of the power output.

[0172] In the present invention, in terms of specific implementation, it should be noted that the BMS main control chip 500 can apply currently commonly used brands, series and models, such as NXP's MC9S12 series, Infineon's TC2 series TC265, etc. The model of the BMS main control chip 500 is not within the protection scope of the present invention.

[0173] In the present invention, in specific implementation, based on the wake-up and sleep circuit of the AC charging CP signal provided by the present invention, the CP signal output by the output terminal CP of the charging interface of the charging gun can be changed from 0V to a rising edge valid signal of 12V, thereby serving as a BMS wake-up trigger signal (i.e., CP signal). The control logic strategy of the circuit to wake up the battery management system BMS through the CP signal is as follows:

[0174] Step S0: Before the charging gun is inserted, the CP signal outputted by the output terminal CP of the charging interface of the charging gun is 0V and the BMS is in a dormant state. The BMS main control chip 500 has no reset control signal inputted into the D trigger module, so that the reset function of the D trigger module 300 is invalid, that is, the output terminal of the D trigger module 300 will change in the same direction as its input signal after the clock signal CLK has a rising edge valid signal, and when the clock signal CLK is invalid, the output of the D trigger module 300 is a low level signal; the BMS main control chip 500 has no output state control signal inputted into the D latch module 400, so that the high impedance output of the D latch module 400 is invalid, that is, the output of the D trigger module 300 changes in the same direction as its input signal, and the output charging wake-up signal WKUP is a low level signal;

[0175] Step S1: After the charging gun is inserted and charging starts, the CP signal outputted by the output terminal CP of the charging interface of the charging gun jumps from 0V to 12V. The rising edge valid signal is input into the clock signal input terminal CLK of the D flip-flop module 300 through the CP signal conversion module, triggering the output of the D flip-flop module 300 to change from a low level (obtained by the above-mentioned wake-up control logic step S0) to a high level, so that the charging wake-up signal WKUP outputted by the D latch module 400 changes from a low level (obtained by the wake-up control logic step S0) to a high level valid signal, so that the power enable signal EN outputted by the selection switch module 600 is a high level, triggering the power module 700 to output power to activate the BMS main control chip 500. At this time, the BMS is initially awakened but charging is not allowed;

[0176] Step S2: After the BMS is initially awakened, the BMS main control chip 500 outputs a high-level charging awakening self-locking signal PWR to the selection switch module 600, and the power enable signal EN output by the selection switch module 600 continues to maintain a high level, controls the power module 700 to output power, and continuously supplies power to the BMS main control chip 500; the BMS main control chip 500 inputs a high-level reset control signal to the D flip-flop module 300, so that the reset function of the D flip-flop module 300 changes from invalid to valid, that is, the output signal of the D flip-flop module 300 is locked from a high level to a low level until the reset control signal is revoked; the BMS main control chip 500 inputs a high-level output state control signal to the D latch module 400, so that the high-impedance output of the D latch changes from invalid to valid, that is, the charging wake-up signal WKUP output by the D latch module 400 is locked from a high level to a low level until the output state control signal is revoked; at this point, the BMS is fully awakened and charging is allowed.

[0177] In specific implementation, in the control logic step S2, the charging wake-up signal WKUP output by the D latch module 400 is invalidated, and only the charging wake-up self-locking signal PWR is kept valid, so that the BMS can automatically sleep after charging is completed.

[0178] For the present invention, after step S2, the following control steps are also included:

[0179] Step S3: When the charging of the charging gun starts, the CP signal output by the output terminal CP of the charging interface of the charging gun changes from 12V to a PWM signal until the charging is completed. The rising edge of the PWM signal does not affect the low-level output signals of the D trigger module 300 and the D latch module 400. The PWM signal is the basis for the BMS main control chip 500 to determine the end of charging; wherein, when the output terminal CP of the charging interface of the charging gun no longer provides a PWM signal, it indicates that the charging is completed; otherwise, if it continues to be provided, it indicates that the charging has not yet ended.

[0180] For the present invention, after step S3, the following control steps are also included:

[0181] Step S4: When charging is completed and the charging gun is not unplugged, the CP signal output by the output terminal CP of the charging interface of the charging gun changes from a PWM signal to 12V. At this time, the control logic strategy of automatically putting the BMS into sleep mode by executing the CP signal specifically includes the following sub-steps:

[0182] Step S40, before the BMS goes into sleep, under the combined effect of the clearing function of the D flip-flop module 300 being effective and the high-impedance output of the D latch module 400 being effective, the charging wake-up signal WKUP output by the D latch module 400 is kept at a low level, that is, the WKUP signal is invalid; the charging wake-up self-locking signal PWR output by the BMS main control chip 500 is kept at a high level, that is, the PWR signal is effective;

[0183] Step S41, when the CP signal outputted by the output terminal CP of the charging port of the charging gun changes from a PWM signal to a 12V continuous high level signal, the third signal output terminal of the BMS main control chip 500 stops outputting the charging wake-up self-locking signal PWR, that is, the PWR signal changes from a high level to a low level;

[0184] Step S42, the power enable signal EN output by the switch selection module 600 changes from a high level to a low level, so that the power module 700 stops outputting power and no longer supplies power to the BMS main control chip 500;

[0185] Step S43: After the BMS main control chip 500 is powered off, no output signal is input to the D flip-flop module 300 and the D latch module 400, so that the clearing function of the D flip-flop module 300 changes from valid to invalid, and the high-impedance output of the D latch module 400 changes from valid to invalid, so that the outputs of the D flip-flop module 300 and the D latch can change in the same direction as their input signals;

[0186] Step S44, considering that the CP signal outputted by the output terminal CP of the charging interface of the charging gun maintains a high level of 12V, and no rising edge signal jumping from 0V to 12V is inputted into the clock signal input terminal CLK of the D flip-flop module 300, the output of the D flip-flop module 300 still maintains a low level, so that the charging wake-up signal WKUP also maintains a low level, thereby locking the BMS main control chip 500 into a power-off state. At this point, the BMS is in sleep mode.

[0187] It should be noted that the wake-up and sleep circuit of the AC charging CP signal provided by the present invention can be directly applied to the battery management system BMS, and can also be applied to other electronic control systems for controlling the wake-up and sleep of the BMS, or electronic devices with wake-up and sleep requirements.

[0188] In summary, compared with the prior art, the present invention provides an AC charging CP signal wake-up and sleep circuit, which does not use a PWM signal as a trigger signal. It realizes the function of automatically waking up the BMS and automatically putting the BMS to sleep by the AC charging CP signal through the logical combination control of the high and low level changes of the input and output signals of the D flip-flop and the D latch, which has great production practical significance.

[0189] In addition, the hardware circuit design of the present invention is scientific, the electronic components are generally used, and are easy to select, and do not need to occupy additional system resources of the BMS main control chip 500, and the circuit board occupies a small space, and the design cost is very low;

[0190] In addition, the hardware circuit of the present invention has very low power consumption and hardly increases the BMS system overhead. Even if the charging gun is not unplugged for a long time, the battery system or the on-board battery will not consume power, thereby ensuring the required working time of the vehicle. Therefore, the technical solution of the present invention has strong practical value and market promotion value.

[0191] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A wake-up and sleep circuit for an AC charging CP signal, characterized in that: It comprises a 5V normal power module (100), a CP signal conversion module (200), a D trigger module (300), a D latch module (400), a BMS main control chip (500), a selection switch module (600) and a power module (700), wherein: A 5V constant power module (100) is respectively connected to the CP signal conversion module (200), the D flip-flop module (300) and the D latch module (400), and is used to provide a continuous 5V DC output for the CP signal conversion module (200), the D flip-flop module (300) and the D latch module (400); A CP signal conversion module (200), having two input ends respectively connected to the output end CP of the charging interface of the charging gun and the output end of the 5V normal power module (100), for converting the CP signal outputted by the output end CP of the charging interface of the charging gun into a 5V signal, which is then inputted into the clock signal input end CLK of the D flip-flop module (300); A D flip-flop module (300), having a signal input terminal D1 and a preset input terminal PRE, which are respectively connected to the output terminal of the 5V constant power module (100); A D flip-flop module (300), having a clear input terminal CLR connected to an output terminal of a BMS main control chip (500); A D flip-flop module (300), having a clock signal input terminal CLK connected to the output terminal of the CP signal conversion module (200), and used for receiving a 5V signal input by the CP signal conversion module (200); A D flip-flop module (300), having an output end connected to an input end D2 of a D latch module (400) and used to provide an input signal to the D latch module (400); A D latch module (400), having a latch enable input terminal LEN connected to an output terminal of a 5V normal power module (100); A D latch module (400), having an output enable input terminal OEN connected to an output terminal of a BMS main control chip (500), and used for receiving an output state control signal output by the BMS main control chip (500); A D latch module (400), having an input terminal D2 connected to the output terminal of the D flip-flop module (400) and used for receiving an output signal of the D flip-flop module (300); A D latch module (400), having an output end connected to the input end of the selection switch module (600) and used for inputting a charging wake-up signal WKUP to the selection switch module (600); The BMS main control chip (500) comprises three signal output terminals, wherein the first signal output terminal is connected to the clear input terminal CLR of the D flip-flop module (300) and is used to provide a clear control signal for the D flip-flop module (300) and control the high and low level states of the input signal of the clear input terminal CLR of the D flip-flop module (300); The second signal output terminal of the BMS main control chip (500) is connected to the output enable input terminal OEN of the D latch module (400) and is used to provide an output state control signal for the D latch module (400), thereby controlling the high and low level states of the input signal of the output enable input terminal OEN of the D latch module (400); The third signal output terminal of the BMS main control chip (500) is connected to the input terminal of the selection switch module (600) and is used to provide a charging wake-up self-locking signal PWR for the selection switch module (600); In addition, the power input terminal DVDD of the BMS main control chip (500) is connected to the output terminal of the power module (700) and is used to receive the direct current power output by the power module (700); The BMS main control chip (500) has a PWM input terminal connected to the output terminal CP of the charging interface of the charging gun, and is used to detect the PWM signal provided by the output terminal CP of the charging interface of the charging gun, and determine whether charging is completed; A selection switch module (600), comprising two signal input terminals for realizing an OR logic function; A first signal input end of the selection switch module (600) is connected to the output end of the D latch module (400) and is used to receive a charging wake-up signal WKUP input by the D latch module (400); A second signal input terminal of the selection switch module (600) is connected to the output of the BMS main control chip (500) and is used to receive a charging wake-up self-locking signal PWR output by the BMS main control chip (500); The output end of the selection switch module (600) is connected to the power enable input end EN of the power module (700) to provide a power enable signal EN to the power module (700), thereby controlling the on and off of the power output of the power module (700); A power supply module (700) having a power output enable input terminal EN connected to the output terminal of the selection switch module (600) and used for receiving a power enable signal EN output by the selection switch module (600), wherein the high or low level state of the power enable signal EN controls whether the power supply module (700) outputs a DC power supply; The output end of the power module (700) is connected to the power input end DVDD of the BMS main control chip (500); when the power module (700) outputs direct current power, the power module (700) supplies power to the BMS main control chip (500), thereby waking up the battery management system BMS; and when the power module (700) does not output direct current power, the power module stops supplying power to the BMS main control chip (500), thereby putting the BMS into hibernation; The control logic strategy of the AC charging CP signal wake-up and sleep circuit to wake up the battery management system BMS through the CP signal is as follows: Step S0: before the charging gun is inserted, the CP signal outputted by the output terminal CP of the charging interface of the charging gun is 0V and the BMS is in a dormant state; the BMS main control chip (500) has no reset control signal inputted into the D flip-flop module, so that the reset function of the D flip-flop module (300) is invalid, that is, the output terminal of the D flip-flop module (300) will change in the same direction as its input signal after a rising edge valid signal appears in the clock signal CLK, and when the clock signal CLK is invalid, the output of the D flip-flop module (300) is a low-level signal; the BMS main control chip (500) has no output state control signal inputted into the D latch module (400), so that the high-impedance output of the D latch module (400) is invalid, that is, the output of the D flip-flop module (300) changes in the same direction as its input signal, and the output charging wake-up signal WKUP is a low-level signal; Step S1: After the charging gun is inserted and before charging begins, the CP signal outputted by the output terminal CP of the charging interface of the charging gun jumps from 0V to 12V, and the rising edge valid signal is input into the clock signal input terminal CLK of the D flip-flop module (300) via the CP signal conversion module (200), triggering the output of the D flip-flop module (300) to change from a low level to a high level, causing the charging wake-up signal WKUP outputted by the D latch module (400) to change from a low level to a high level valid signal, causing the power enable signal EN outputted by the selection switch module (600) to be a high level, triggering the power module (700) to output power to activate the BMS main control chip (500), at which point the BMS is initially awakened but charging is not allowed; Step S2: After the BMS is initially awakened, the BMS main control chip (500) outputs a high-level charging awakening self-locking signal PWR to the selection switch module (600), and the power enable signal EN output by the selection switch module (600) continues to maintain a high level, controlling the power module (700) to output power, and continuously supplying power to the BMS main control chip (500); the BMS main control chip (500) inputs a high-level clearing control signal to the D flip-flop module (300), so that the clearing signal of the D flip-flop module (300) is The zero function changes from invalid to valid, i.e. the output signal of the D flip-flop module (300) is locked from a high level to a low level until the zero clearing control signal is cancelled; the BMS main control chip (500) inputs a high level output state control signal to the D latch module (400), so that the high impedance state output of the D latch changes from invalid to valid, i.e. the charging wake-up signal WKUP output by the D latch module (400) is locked from a high level to a low level until the output state control signal is cancelled; at this point, the BMS is fully awakened and charging is allowed.

2. The wake-up and sleep circuit of the AC charging CP signal according to claim 1, characterized in that: The input end of the 5V normal power module (100) is connected to an external normal power source of 12V or 24V.

3. The wake-up and sleep circuit of the AC charging CP signal as claimed in claim 1, characterized in that: The CP signal conversion module 200 includes a switch K1, a switch K2, a resistor R15, a resistor R16 and a resistor R17, wherein: The controlled end of the switch K1 is connected to the output end CP of the charging port of the charging gun; One end of the switch K1 is connected to the second pin of the resistor R15; The other end of the switch K1 is connected to the ground terminal GND; The controlled end of the switch K2 is connected to the first pin of the resistor R15; One end of the switch K2 is connected to the output end of the 5V normal power module (100); The other end of the switch K2 is connected to the first pin of the resistor R16; The first pin of the resistor R17 is connected to the second pin of the resistor R16 and the clock signal input terminal CLK of the D flip-flop module; The second pin of the resistor R17 is connected to the ground terminal GND.

4. The wake-up and sleep circuit of the AC charging CP signal as claimed in claim 1, characterized in that: The D flip-flop module (300) comprises a D flip-flop and a reset control circuit, wherein the D flip-flop and the reset control circuit are connected; The D flip-flop is edge triggered and has preset and clear functions, and the clear control circuit is connected to the first signal output terminal of the BMS main control chip (500) and is used to receive a clear control signal output by the BMS main control chip (500), thereby controlling whether the clear function of the D flip-flop is effective.

5. The wake-up and sleep circuit of the AC charging CP signal as claimed in claim 4, characterized in that: The D trigger module (300) comprises a D trigger, a resistor R1, a resistor R2, a resistor R3, a resistor R8 and a reset control circuit, wherein: The zeroing control circuit includes resistors R4, R5, R6, R7 and an enhanced N-channel field effect transistor Q1; The power input terminal VCC of the D flip-flop is connected to the second pin of the resistor R1; The preset input terminal PRE of the D flip-flop is connected to the second pin of the resistor R2; The input terminal D of the D flip-flop is connected to the second pin of the resistor R3; The clear input terminal CLR of the D flip-flop is connected to the first pin of the resistor R5; The output terminal Q of the D flip-flop is connected to the first pin of the resistor R8; The clock signal input terminal CLK of the D flip-flop is connected to the output terminal of the CP signal conversion module (200); The first pin of the resistor R1, the first pin of the resistor R2 and the first pin of the resistor R3 are respectively connected to the output end of the 5V normal power module; The second pin of the resistor R8 is connected to the first pin of the resistor R9; The second pin of the resistor R9 is connected to the ground terminal GND; The second pin of the resistor R5 is connected to the second pin of the resistor R4 and the drain D of the NMOS tube Q1 respectively; The first pin of the resistor R4 is connected to the output end of the 5V normal power module; The gate G of the NMOS transistor Q1 is connected to the first pin of the resistor R6 and the second pin of the resistor R7 respectively; The source S of the NMOS tube Q1 and the first pin of the resistor R7 are connected to the ground terminal GND respectively; The second pin of the resistor R6 is connected to the third signal output terminal of the BMS main control chip (500).

6. The wake-up and sleep circuit of the AC charging CP signal as claimed in claim 5, characterized in that: The D latch module (400) comprises a D latch and an output control circuit, wherein the D latch and the output control circuit are connected; Wherein, the D latch has a tri-state gate output function; The output control circuit is connected to the second signal output terminal of the BMS main control chip (500) and is used to receive an output enable signal OEN output by the BMS main control chip (500).

7. The wake-up and sleep circuit of the AC charging CP signal as claimed in claim 6, characterized in that: The D latch module (400) comprises a D latch, a resistor R10, a resistor R11, a resistor R14 and an output control circuit; Wherein, the output control circuit includes a resistor R12 and a resistor R13; The power input terminal VCC of the D latch is connected to the second pin of the resistor R11; The latch input terminal LE of the D latch is connected to the second pin of the resistor R10; The input terminal D of the D latch is connected to the second pin of the resistor R8 and the first pin of the resistor R9 respectively; The output enable input terminal OE of the D latch is connected to the second pin of the resistor R12 and the first pin of the resistor R13 respectively; The output terminal Q of the D latch is connected to the first pin of the resistor R14 and the input terminal of the selection switch module (600); The first pin of the resistor R10 and the first pin of the resistor R11 are respectively connected to the output end of the 5V normal power module (100); The first pin of the resistor R12 is connected to the ground terminal GND; The second pin of the resistor R13 is respectively connected to the second pin of the resistor R6 and the third signal output terminal of the BMS main control chip (500); The second pin of the resistor R14 is connected to the ground terminal GND.

8. The wake-up and sleep circuit of the AC charging CP signal as claimed in claim 1, characterized in that: After step S2, the following control steps are also included: Step S3: When charging of the charging gun starts, the CP signal outputted by the output terminal CP of the charging interface of the charging gun changes from 12V to a PWM signal until charging is completed, and the rising edge of the PWM signal does not affect the low-level output signals of the D flip-flop module (300) and the D latch module (400), and the PWM signal is the basis for the BMS main control chip (500) to judge whether charging is completed; wherein, when the output terminal CP of the charging interface of the charging gun no longer provides the PWM signal, it indicates that charging is completed; otherwise, if it continues to provide the PWM signal, it indicates that charging is not yet completed.

9. The wake-up and sleep circuit of the AC charging CP signal as claimed in claim 8, characterized in that: After step S3, the following control steps are also included: Step S4: When charging is completed and the charging gun is not unplugged, the CP signal output by the output terminal CP of the charging interface of the charging gun changes from a PWM signal to 12V. At this time, the control logic strategy of automatically putting the BMS into sleep mode by executing the CP signal specifically includes the following sub-steps: Step S40, before the BMS goes into sleep, under the combined effect of the clearing function of the D flip-flop module (300) being effective and the high-impedance output of the D latch module (400) being effective, the charging wake-up signal WKUP output by the D latch module 400 is kept at a low level, that is, the WKUP signal is invalid; the charging wake-up self-locking signal PWR output by the BMS main control chip 500 is kept at a high level, that is, the PWR signal is effective; Step S41, when the CP signal outputted by the output terminal CP of the charging port of the charging gun changes from a PWM signal to a 12V continuous high level signal, the third signal output terminal of the BMS main control chip (500) stops outputting the charging wake-up self-locking signal PWR, that is, the PWR signal changes from a high level to a low level; Step S42, the power enable signal EN output by the switch selection module (600) changes from a high level to a low level, so that the power module (700) stops outputting power and no longer supplies power to the BMS main control chip (500); Step S43: after the BMS main control chip (500) is powered off, no output signal is input into the D flip-flop module (300) and the D latch module (400), so that the clearing function of the D flip-flop module (300) changes from valid to invalid, and the high-impedance output of the D latch module (400) changes from valid to invalid, so that the outputs of the D flip-flop module (300) and the D latch can change in the same direction as their input signals; Step S44: Since the CP signal outputted by the output terminal CP of the charging interface of the charging gun maintains a high level of 12V, and no rising edge signal jumping from 0V to 12V is inputted into the clock signal input terminal CLK of the D flip-flop module (300), the output of the D flip-flop module (300) still maintains a low level, so that the charging wake-up signal WKUP also maintains a low level, thereby locking the BMS main control chip (500) into a power-off state, and the BMS is now in sleep mode.

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