Level shifter and level shifting method

Abstract

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at first and second voltage levels; a cross-latch circuit coupled to the input circuit, the cross-latch circuit having first and second output terminals configured to provide complementary output signals at third and fourth voltage levels, wherein the input circuit includes first and second control nodes configured to output first and second control signals at first and fourth voltage levels based on the input signal; and a tracking circuit coupled to the input circuit and the cross-latch circuit, configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the larger of the first and third voltage levels, and the second tracking signal is the larger of the second and third voltage levels. Embodiments of the present invention also relate to a level shifting method.

Description

Technical Field

[0001] Embodiments of the present invention relate to a level shifter and a level shifting method. Background Art

[0002] Many electronic devices such as desktop computers, laptops, tablets, smartphones, etc. employ multiple integrated circuits, often in combination with multiple discrete semiconductor devices, to process and store information. Some electronic devices use multiple voltage levels to power their multiple integrated circuits and discrete semiconductor devices accordingly. Voltage level shifters may be employed to shift and adapt the voltage level of digital signals between integrated circuits using different voltages. Summary of the invention

[0003] An embodiment of the present invention provides a level shifter, comprising: an input circuit having a first input terminal and a second input terminal configured to receive complementary input signals at a first voltage level and a second voltage level; a cross-latch circuit coupled to the input circuit, the cross-latch circuit having a first output terminal and a second output terminal configured to provide complementary output signals at a third voltage level and a fourth voltage level, wherein the input circuit comprises a first control node and a second control node configured to output a first control signal and a second control signal at the first voltage level and the fourth voltage level based on the input signal; and a tracking circuit coupled to the input circuit and the cross-latch circuit, configured to input a first tracking signal and a second tracking signal to the cross-latch circuit based on the first control signal and the second control signal, wherein the first tracking signal is the larger of the first control signal and the third voltage level, and the second tracking signal is the larger of the second control signal and the third voltage level.

[0004] Another embodiment of the present invention provides a level shifter, comprising: a first input terminal and a second input terminal, configured to receive complementary first input signals and second input signals in a low voltage domain; a first output terminal and a second output terminal, configured to provide complementary first output signals and second output signals in a high voltage domain corresponding to the first input signal and the second input signal; an input circuit, connected between the first input terminal and the second input terminal and the first output terminal and the second output terminal, the input circuit having a first control node and a second control node, the first control node and the second control node being configured to output a first control signal and a second control signal in a high voltage domain and in a low voltage domain based on the first input signal and the second input signal; a cross latch circuit, coupled to the input circuit and the first output terminal and the second output terminal, the cross latch circuit having a first input terminal and a second input terminal; a tracking circuit, coupled to the first control node and the second control node and the first input terminal and the second input terminal of the cross latch circuit, the tracking circuit being configured to provide the first tracking signal and the second tracking signal in the high voltage domain to the first input terminal and the second input terminal of the cross latch circuit based on the first control signal and the second control signal.

[0005] Another embodiment of the present invention provides a level shifting method, comprising: receiving a first input signal and a second input signal having respective first voltage levels and second voltage levels, wherein the second voltage level is higher than the first voltage level; generating a first control signal having a first voltage level based on the first input signal; generating a second control signal having a fourth voltage level higher than the second voltage level based on the second input signal; providing a first tracking signal having a third voltage level higher than the first voltage level to a cross-latch circuit based on the first control signal; providing a second tracking signal having a fourth voltage level to the cross-latch circuit based on the second control signal; outputting a first output signal having a third voltage level based on the second tracking signal through the cross-latch circuit; and outputting a second output signal having a fourth voltage level based on the first tracking signal through the cross-latch circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a circuit diagram of an example of a level shifter according to some embodiments.

[0008] Figure 2 is a circuit diagram of a level shifter including an alternative example of an input circuit and a tracking circuit according to some embodiments.

[0009] Figure 3 is a circuit diagram of a level shifter including an alternative example of a cross-latch circuit according to some embodiments.

[0010] Figure 4 is a circuit diagram of a level shifter including an alternative example of an input circuit and a tracking circuit according to some embodiments.

[0011] Figure 5 is a circuit diagram of a level shifter including an alternative example of an input circuit according to some embodiments.

[0012] Figure 6 is a circuit diagram of a level shifter including an alternative example of a cross-latch circuit according to some embodiments.

[0013] Figure 7 is a circuit diagram of a level shifter including another alternative example of a cross latch circuit according to some embodiments.

[0014] Figure 8 is a device having various NMOS and PMOS components identified according to some embodiments. Figure 2 Circuit diagram of a level shifter.

[0015] Fig. 9 According to some embodiments, Figure 8 A block diagram of various aspects of the symmetrical layout of the level shifter.

[0016] Fig.10 According to some embodiments, Figure 8 A block diagram of various aspects of another symmetrical layout of a level shifter.

[0017] Fig.11 According to some embodiments, Figure 8 A block diagram of various aspects of an asymmetric layout of a level shifter.

[0018] Fig.12 is a flow chart of a level shifting method according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0021] Figure 1 1 is a block diagram of various aspects of an overdriven level shifter 100 according to a disclosed embodiment. The level shifter 100 includes a cross latch circuit 110, an input circuit 120, and a tracking circuit 130. The input circuit receives complementary input signals I and IN in a first voltage domain A and is therefore connected to VDDA and VSSA voltage signals. The cross latch circuit 110 operates in a second voltage domain B and is therefore connected to VDDB and VSSB voltage signals. In some embodiments, the second voltage level VDDA and the first voltage level VSSA may be equal to 1.8V and 0V (ground), respectively, while the fourth voltage level VDDB and the third voltage level VSSB may be equal to 3.3V and 1.8V, respectively. In other examples, the second and first voltage levels VDDA and VSSA may be equal to 1.2V and 0V (ground), respectively, while the fourth and third voltage levels VDDB and VSSB may be equal to 1.8V and 0.6V, respectively. In other words, the second and third voltage levels VDDA and VSSB are at the same voltage level, and the level shifter 100 is actually connected to receive three voltage levels: VSSA, VDDA / VSSB, and VDDB. Other voltage levels are also within the scope of the disclosure.

[0022] The cross latch circuit 110 provides complementary output signals Z and ZN. The cross latch circuit typically operates in a single voltage domain (VDD, VSS). Therefore, the output signals Z, ZN swing between a low state and a high state in the single voltage domain. The disclosed embodiment employs the cross latch circuit 110 in an overdrive level shifter circuit. Therefore, the input signals I and IN are in a lower first voltage domain and therefore swing between VDDA and VSSA voltage levels, while the outputs Z and ZN are shifted to a higher second voltage domain and therefore swing between VDDB and VSSB.

[0023] To provide enhanced performance and reliability, the tracking circuit 130 outputs an overdrive or tracking signal to the cross latch circuit 110 based on the input signals I and IN, rather than applying the complementary input signals I and IN in the first voltage domain directly to the cross latch circuit 110. More specifically, the tracking circuit 130 is configured to provide the cross latch circuit 110 with a tracking signal that is the greater of the control signal A and the VSSB voltage level, or the greater of the control signal B and the VSSB voltage level. In other words, the tracking signal is provided in the second voltage domain, even though the control signals A and B may be in the first voltage domain or the second voltage domain.

[0024] In the example shown, input terminals 202 and 204 receive complementary input signals I and IN, respectively, in a first voltage domain, while output terminals 102 and 104 provide complementary output signals Z and ZN in a second voltage domain. Figure 1 As shown, input circuit 120 is connected between input terminals 202 and 204 for receiving signals in a first (lower) voltage domain A and output terminals 102 and 104 for outputting signals in a second (higher) voltage domain B. Control signals A and B output at nodes 206 and 208, respectively, can thus swing between a low VSSA signal in the first voltage domain and a high VDDB signal in the second voltage domain.

[0025] The cross latch circuit 110 includes a first pair of transistors including a first transistor 210 and a second transistor 212 connected in series and a second pair of transistors including a third transistor 214 and a fourth transistor 216 connected in series. In the example shown, the first and third transistors 210, 214 are PMOS transistors, and the second and fourth transistors 212, 216 are NMOS transistors. The two pairs of transistors are connected between the VDDB and VSSB voltage rails. In the example shown, the gate terminal of the transistor 216 is connected to the output terminal 102, which is located at the junction of the source / drain terminals of the first pair of transistors 210, 212, and the gate terminal of the transistor 212 is connected to the output terminal 104, which is located at the junction of the source / drain terminals of the second pair of transistors 214, 216.

[0026] The level shifter 100 also includes an input circuit 120 including series-connected transistors 218 and 220 connected between the output terminal 102 and the input terminal 202, and series-connected transistors 222 and 224 connected between the output terminal 104 and the input terminal 204. In the example shown, the transistors 218 and 222 are PMOS transistors, and the transistors 220 and 224 are NMOS transistors. The control signals A and B are received at respective nodes 206 and 208 by the tracking circuit 130 connected to the gate terminals of the PMOS transistors 214 and 210 of the latch circuit 110. More specifically, the tracking circuit is configured such that the gate of the PMOS transistor 210 receives the tracking signal, which is the higher of the control signal B or VSSB, while the gate of the PMOS transistor 214 receives the higher of the control signal A or VSSB.

[0027] The gate terminals of the NMOS transistors 220, 224 are coupled to receive the VDDA voltage signal, and the gate terminals of the PMOS transistors 218, 222 are coupled to receive the VSSB voltage signal. As described above, in some embodiments, VDDA and VSSB are the same voltage level. For example, when the input signal I transitions from a logic high to a logic low in the first voltage domain, the input signal I at the input terminal 202 is at the VSSA voltage level. The NMOS transistor 220 is turned on with the VDDA signal at its gate, pulling the control signal A at the node 206 to a low (VSSA).

[0028] Tracking circuit 130 is configured such that PMOS transistor 214 of cross-latch circuit 110 receives the higher of control signal A or VSSB. Therefore, the gate of the PMOS transistor receives a low VSSB signal (logic low in the second voltage domain), turning on PMOS transistor 214. This pulls the ZN signal at output terminal 104 to a logic high (VDDB) in the second voltage domain. The high ZN signal further turns on NMOS transistor 212, pulling the Z signal at output terminal 102 to a low (VSSB) in the second voltage domain. The low Z signal further turns off NMOS transistor 216 to latch the ZN output signal in its high state.

[0029] As described above, the PMOS transistors 210 , 214 of the cross latch circuit 110 are controlled by the tracking circuit 130 , with the gate of the PMOS transistor 210 receiving the higher of the control signal B or VSSB and the gate of the PMOS transistor 214 receiving the higher of the control signal A or VSSB. Figure 2An exemplary level shifter 200 is depicted showing further aspects of an embodiment of a tracking circuit 130a configured to compare the A and B signals to VSSB and output appropriate tracking signals C and D to PMOS transistors 214 and 210, respectively.

[0030] Figure 2 The cross latch circuit 110 shown in FIG. Figure 1 , and thus includes a first transistor 210 and a second transistor 212 connected in series and a third transistor 214 and a fourth transistor 216 connected in series. The first and third transistors 210, 214 are PMOS transistors, and the second and fourth transistors 212, 216 are NMOS transistors. The two transistor pairs are connected between the VDDB and VSSB voltage rails. The gate terminal of transistor 216 is connected to the output terminal 102, and the gate terminal of transistor 212 is connected to the output terminal 104. The PMOS transistors 210 and 214 receive D and C tracking signals, respectively, from the tracking circuit 130a as further discussed below.

[0031] and Figure 1 The input circuit 120 shown is similar, Figure 2 The input circuit 120a includes a PMOS transistor 218 and an NMOS transistor 220 connected between the output terminal 102 and the input terminal 202, and a PMOS transistor 222 and an NMOS transistor 224 connected between the output terminal 104 and the input terminal 204. The gates of the PMOS transistors 218 and 222 are connected to the VSSB signal, and the gates of the NMOS transistors 220 and 224 are connected to the VDDA signal. In addition, a PMOS transistor 318 is connected between the control node 206 and the PMOS transistor 218, and an NMOS transistor 320 is connected between the control node 206 and the NMOS transistor 220. Similarly, a PMOS transistor 322 is connected between the control node 208 and the PMOS transistor 222, and an NMOS transistor 324 is connected between the control node 208 and the NMOS transistor 224.

[0032] As above combined Figure 1 As stated, Figure 2The tracking circuit 130a shown in FIG. 1 is configured such that the gate of the PMOS transistor 210 receives the higher of the control signal B or VSSB, and the gate of the PMOS transistor 214 receives the higher of the control signal A or VSSB. The tracking circuit 130a includes a cross-coupled PMOS transistor pair 332 including PMOS transistors 332a and 332b configured to output a tracking signal C that is the larger of the control signal A or VSSB, and a cross-coupled PMOS transistor pair 334 including PMOS transistors 334a and 334b ​​configured to output a tracking signal D that is the larger of the control signal B or VSSB. Therefore, the source terminals of the PMOS transistors 332a and 334a are coupled to receive the VSSB signal, and the source terminals of the PMOS transistors 332b and 334b ​​are coupled to receive control nodes 206 and 208 to receive the A and B control signals, respectively. Tracking signal C is received at the gate of PMOS transistor 214 , and tracking signal D is received at the gate of PMOS transistor 210 .

[0033] Figure 2 The embodiment shown in includes additional cross-coupled transistor pairs for generating A and B control signals. More specifically, cross-coupled NMOS transistor pairs 336 and 340 provide respective control signals to the gates of PMOS transistors 318 and 322. Cross-coupled NMOS transistor pair 336 includes NMOS transistors 336a and 336b, whose drains are connected to control signals A and VSSB, respectively. Cross-coupled NMOS transistor pair 340 includes NMOS transistors 340a and 340b, whose drains are connected to control signals B and VSSB, respectively. The sources of cross-coupled transistor pairs 336 and 340 are connected to the gates of PMOS transistors 318 and 322, respectively.

[0034] The cross-coupled PMOS transistor pairs 338 and 342 provide respective control signals to the gates of the NMOS transistors 320 and 324. The cross-coupled PMOS transistor pair 338 includes PMOS transistors 338a and 338b, whose drains are connected to the control signal A and VDDA, respectively. The cross-coupled PMOS transistor pair 342 includes PMOS transistors 342a and 342b, whose drains are connected to the control signal B and VDDA, respectively. The sources of the cross-coupled transistor pairs 338 and 342 are connected to the gates of the NMOS transistors 320 and 324, respectively.

[0035] Thus, when the input signal I transitions from a logic high to a logic low in the first voltage domain, the input signal I at the input terminal 202 is at a VSSA voltage level (e.g., 0V). The series-connected NMOS transistors 220, 320 are turned on, pulling the control signal A at the node 206 to a low (VSSA). The low control signal A is input to the cross-coupled PMOS transistor pair 332 along with VSSB to output the tracking signal C at the VSSB voltage level to the gate of the PMOS transistor 214. This pulls the ZN signal at the output terminal 104 to a logic high (VDDB) in the second voltage domain. The high ZN signal further turns on the NMOS transistor 212, pulling the Z signal at the output terminal 102 to a low (VSSB) in the second voltage domain. The low Z signal further turns off the NMOS transistor 216 to latch the ZN output signal in its high state.

[0036] Figure 3 Another exemplary level shifter 300 illustrating other aspects of an embodiment of the cross-latch circuit 110a is shown. Figure 3 In the example, the C and D control signals are received at the gate of each of the latch transistors 210, 212, 214 and 216. Figure 2 The example shown in has output terminals 102 and 104 cross-coupled to the gates of NMOS transistors 216 and 212, respectively. Figure 3 In the example shown, the tracking signal C or D directly controls each of the latch transistors 210 , 212 , 214 , and 216 to increase the operating speed of the level shifter 300 .

[0037] like Figure 2 In the example shown, input signals I, IN are received at input terminals 202, 204 of input circuit 120a. Cross-latch circuit 110a includes a PMOS transistor 210 and an NMOS transistor 212 connected in series, and a PMOS transistor 214 and an NMOS transistor 216 connected in series. The two transistor pairs are connected between the VDDB and VSSB voltage rails. As described above, the gate terminals of transistors 210 and 212 are connected to receive tracking signal D, and the gate terminals of transistors 214 and 216 are connected to receive tracking signal C.

[0038] PMOS transistors 218 and 318 are connected between output terminal 102 and control node 206, and PMOS transistors 222 and 322 are connected between output terminal 104 and control node 208. NMOS transistors 220 and 320 are connected between control node 206 and input terminal 202, and NMOS transistors 224 and 324 are connected between control node 208 and input terminal 204. The gates of PMOS transistors 218, 222 are connected to the VSSB signal, and the gates of NMOS transistors 220 and 224 are connected to the VDDA signal. The gates of PMOS transistors 318 and 322 are connected to the outputs of cross-coupled NMOS pairs 336 and 340, respectively. The gates of NMOS transistors 320 and 324 are connected to the outputs of cross-coupled PMOS pairs 338 and 342, respectively.

[0039] The cross-coupled PMOS transistor pair 332 and 334 are connected to the control nodes 206 and 208, respectively, and are configured to output tracking signals C and D, respectively. When the input signal I transitions from a logic high to a low in the first voltage domain, the input signal I at the input terminal 202 is at a VSSA voltage level (e.g., 0V). The series-connected NMOS transistors 220, 320 are turned on, pulling the control signal A at the node 206 to a low (VSSA). The low control signal A is input to the cross-coupled PMOS transistor pair 332 along with VSSB to output the tracking signal C at the VSSB voltage level to the gates of the PMOS transistor 214 and the NMOS transistor 216. This turns on the PMOS transistor 214 and turns off the NMOS transistor 216, pulling the ZN signal at the output terminal 104 to a logic high (VDDB) in the second voltage domain. The tracking signal D turns on the NMOS transistor 212 and turns off the PMOS transistor 210, pulling the Z signal at the output terminal 102 to a low (VSSB) in the second voltage domain.

[0040] Figure 4 Shown include Figure 1 The example of the level shifter 400 of the cross-latch circuit 110 shown in FIG. 1 has an input circuit 120 b and a tracking circuit 130 b according to other embodiments. Figure 1 As in the example shown, Figure 4 The cross latch circuit 110 includes a PMOS transistor 210 and an NMOS transistor 212 connected in series, and a PMOS transistor 214 and an NMOS transistor 216 connected in series. The two transistor pairs are connected between the VDDB and VSSB voltage rails. The gate terminal of transistor 216 is connected to the output terminal 102, while the gate terminal of transistor 212 is connected to the output terminal 104. PMOS transistors 210 and 214 receive D and C control signals, respectively, from the tracking circuit 130b.

[0041] Figure 4 The input circuit 120b includes PMOS transistors 218 and 318 connected between the output terminal 102 and the control node 206, and PMOS transistors 222 and 322 connected between the output terminal 104 and the control node 208. NMOS transistors 220 and 320 are connected between the control node 206 and the input terminal 202, and NMOS transistors 224 and 324 are connected between the control node 208 and the input terminal 204. The gates of the PMOS transistors 218, 222 are connected to the VSSB signal, and the gates of the NMOS transistors 220 and 224 are connected to the VDDA signal.

[0042] exist Figure 4 In the tracking circuit 130b of the embodiment, the cross-coupled transistor pair connected to the gates of the PMOS transistors 318 and 322 and the cross-coupled transistor pair connected to the gates of the NMOS transistors 320 and 324 are omitted. Instead, the gates of the PMOS transistors 318 and 322 of the input circuit 120b are also connected to receive the VSSB signal, and the gates of the NMOS transistors 320 and 324 are also connected to receive the VDDA signal. Some alternative embodiments may eliminate transistors 318, 320, 322, and 324.

[0043] and Figure 3 Like the tracking circuit 130a of FIG. 1 , the tracking circuit 130b includes a cross-coupled PMOS transistor pair 332 and 334 connected to the control nodes 206 and 208, respectively, configured to output tracking signals C and D, respectively. When the input signal I transitions from a logic high to a low in the first voltage domain, the input signal I at the input terminal 202 is at a VSSA voltage level (e.g., 0V). The series-connected NMOS transistors 220, 320 are turned on, pulling the control signal A at the node 206 to a low (VSSA). The low control signal A is input to the cross-coupled PMOS transistor pair 332 along with VSSB to output the tracking signal C at the VSSB voltage level to the gate of the PMOS transistor 214. This turns on the PMOS transistor 214, pulling the ZN signal at the output terminal 104 to a logic high (VDDB) in the second voltage domain. The tracking signal D turns off the PMOS transistor 210, pulling the Z signal at the output terminal 102 to a low (VSSB) in the second voltage domain. Output terminals 102 and 104 are cross-coupled to the gates of NMOS transistors 216 and 212, respectively, to latch the Z and ZN signals.

[0044] Figure 5Another embodiment of the level shifter 500 is shown in which the cross latch circuit 110a and the tracking circuit 130b are combined with the input circuit 120c. The input circuit 120c includes PMOS transistors 218 and 318 connected between the output terminal 102 and the control node 206, and PMOS transistors 222 and 322 connected between the output terminal 104 and the control node 208. NMOS transistors 220 and 320 are connected between the control node 206 and the input terminal 202, and NMOS transistors 224 and 324 are connected between the control node 208 and the input terminal 204. The gates of the PMOS transistors 218, 318, 222, and 322 are connected to the VSSB signal, and the gates of the NMOS transistors 220, 320, 224, and 324 are connected to the VDDA signal.

[0045] In addition, input circuit 120c includes diodes connected between control nodes A and B and respective transistors 320 and 324. Figure 5 In the example shown, the diodes are diode-connected NMOS transistors 354 , 356 , but other diode structures are within the scope of the present disclosure.

[0046] As described above, with the cross-latch circuit 110a, the C and D control signals are received at the gate of each latch transistor 210, 212, 214, and 216. Therefore, the tracking signal C or D directly controls each of the latch transistors 210, 212, 214, and 216 to increase the operating speed of the level shifter 100. The cross-coupled PMOS transistor pairs 332 and 334 of the tracking circuit 130b configured to output the tracking signals C and D, respectively, are connected to the control nodes 206 and 208, respectively.

[0047] Figure 6 Another example is shown in which input circuit 120c and tracking circuit 130b are used with another exemplary cross-latch circuit 110b. Figure 6Input circuit 120c in includes PMOS transistors 218 and 318 connected between output terminal 102 and control node 206, and PMOS transistors 222 and 322 connected between output terminal 104 and control node 208. NMOS transistors 220 and 320 are connected between control node 206 and input terminal 202, and NMOS transistors 224 and 324 are connected between control node 208 and input terminal 204. The gates of PMOS transistors 218, 318, 222, and 322 are connected to the VSSB signal, and the gates of NMOS transistors 220, 320, 224, and 324 are connected to the VDDA signal. Cross-coupled PMOS transistor pairs 332 and 334 of tracking circuit 130b configured to output tracking signals C and D, respectively, are connected to control nodes 206 and 208, respectively. Tracking signals C and D are received at the gates of each cross-latch transistor 210, 212, 214, and 216. Diodes are connected between control nodes A and B and respective transistors 320 and 324. Figure 6 In the example shown, the diodes are diode-connected NMOS transistors 354 , 356 , but other diode structures are within the scope of the present disclosure.

[0048] The cross latch circuit 110b also includes NMOS transistors 350 and 352. Transistor 350 is connected in series between NMOS transistor 212 and the VSSB rail, and transistor 352 is connected in series between NMOS transistor 216 and the VSSB rail. The gates of NMOS transistors 350 and 352 are cross-coupled to output terminals 104 and 102, respectively, to latch signals Z and ZN in their complementary states.

[0049] Figure 7 Another example is shown in which the input circuit 120c and the tracking circuit 130b are used with another exemplary cross latch circuit 110c. The input circuit 120c includes PMOS transistors 218 and 318 connected between the output terminal 102 and the control node 206, and PMOS transistors 222 and 322 connected between the output terminal 104 and the control node 208. NMOS transistors 220 and 320 are connected between the control node 206 and the input terminal 202, and NMOS transistors 224 and 324 are connected between the control node 208 and the input terminal 204. The gates of the PMOS transistors 218, 318, 222, and 322 are connected to the VSSB signal, and the gates of the NMOS transistors 220, 320, 224, and 324 are connected to the VDDA signal.

[0050] Cross-coupled PMOS transistor pairs 332 and 334 of tracking circuit 130b, configured to output tracking signals C and D, respectively, are connected to control nodes 206 and 208, respectively. Tracking signals C and D are received at the gate of each cross-latch transistor 210, 212, 214, and 216. Diode-connected NMOS transistors 354, 356 are connected between control nodes A and B and respective transistors 320 and 324, although other diode configurations are within the scope of the present disclosure.

[0051] The cross latch circuit 110c also includes NMOS transistors 360 and 362. Transistor 360 is connected in parallel between NMOS transistor 212 and the VSSB rail, and transistor 362 is connected in series between NMOS transistor 216 and the VSSB rail. The gates of NMOS transistors 360 and 362 are cross-coupled to output terminals 104 and 102, respectively, to latch signals Z and ZN in their complementary states.

[0052] Figures 8 to 11 Depicted is an exemplary level shifter layout in accordance with some embodiments. Figure 8 Shows Figure 2 In the level shifter 200, the cross-coupled PMOS transistor pair 338 and 342 of the tracking circuit 130a is labeled "TP1", and the cross-coupled PMOS transistor pair 332 and 334 of the tracking circuit 130a is labeled "TP2". Figure 8 , the NMOS transistor pair 336 and 340 of the tracking circuit 130a is labeled "TN1". The PMOS transistors 218, 318, 222, and 322 of the input circuit 120a are labeled P1, and the NMOS transistors 220, 320, 224, and 324 of the input circuit 120a are labeled N1. The PMOS transistors 210 and 214 of the cross latch circuit 110 are labeled Mp1, and the NMOS transistors 212 and 216 of the cross latch circuit 110 are labeled Mn1.

[0053] Fig. 9 An exemplary symmetrical layout 900 for the level shifter 200 is shown, where the NT1 , TP1 , P1 , N1 , Mp1 , Mn1 , and TP2 transistors are arranged horizontally symmetrically on either side of a center line 910 . Fig.10Another symmetrical layout 1000 is shown, in which NT1, TP1, P1, N1, Mp1, Mn1 and TP2 transistors are arranged vertically and symmetrically on both sides of the center line 910. In addition, in some examples, the NMOS and PMOS components on each side of the center line 910 can be combined together on their respective sides of the center line 910 to simplify the manufacturing process. This is shown in the exemplary layout 1000, in which the PMOS transistors TP2, TP1, P1 and Mp1 are all located at the upper part 1010 of the layout 1000, and the NMOS transistors Mn1, N1 and TN1 are all located at the lower part 1012 of the layout 1000. In addition, as long as the symmetry is maintained, the transistors NT1, TP1, P1, N1, Mp1, Mn1 and TP2 can be rearranged in other layout positions. Such a symmetrical layout is balanced and allows the output to switch at the same speed and thus improve performance. Fig.11 An example of an asymmetric layout is shown, where the NMOS and PMOS components are not necessarily grouped symmetrically around a center line. For example, such an asymmetric layout may be suitable for low-speed implementations. Other symmetric and asymmetric layouts are also within the scope of the present disclosure.

[0054] Fig.12 1 is a flow chart showing an example of a level shifting method 1200 according to some embodiments. The method 1200 can be implemented in conjunction with any of the exemplary level shifter circuits disclosed herein. Figures 1 to 7 Reference Fig.12 , at step 1210, a first input signal I and a second input signal IN having respective first and second voltage levels VSSA and VDDA are received at input terminals 202 and 204 of the level shifter 100. In the example shown, the second voltage level VDDA is higher than the first voltage level VSSA. At step 1220, a first control signal A having the first voltage level VSSA is generated based on the first input signal I. At step 1230, a second control signal B is generated based on the second input signal IN. The second control signal B is at a fourth voltage level VDDB, which is higher than the second voltage level VDDA.

[0055] In step 1240, a first tracking signal C based on the first control signal A is provided to the cross latch circuit 110. The first tracking signal C has a third voltage level VSSB higher than the first voltage VSSA level. In step 1250, a second tracking signal D based on the second control signal B is provided to the cross latch circuit 110. The second tracking signal D has a fourth voltage level VDDB. In step 1260, a first output signal Z is outputted by the cross latch circuit 110 based on the second tracking signal D having the third voltage level VSSB, and in step 1270, a second output signal ZN is outputted by the cross latch circuit 110 based on the first tracking signal C having the fourth voltage level VDDB.

[0056] The high speed overdrive level shifter device described in the above embodiments utilizes cross latching to perform level shifting. This allows the structure to be used for 2xVDD and 3xVDD applications. For example, the embodiments disclosed herein can provide higher speed switching rates while maintaining or improving system reliability. Some examples provide an operating speed of 250MHz.

[0057] According to some disclosed examples, a level shifter includes an input circuit having a first input terminal and a second input terminal, the first input terminal and the second input terminal being configured to receive complementary input signals at a first voltage level and a second voltage level. A cross latch circuit is coupled to the input circuit. The cross latch circuit has a first output terminal and a second output terminal configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes a first control node and a second control node, the first control node and the second control node being configured to output a first control signal and a second control signal at a first voltage level and a fourth voltage level based on the input signal. A tracking circuit is coupled to the input circuit and the cross latch circuit, and is configured to input a first tracking signal and a second tracking signal to the cross latch circuit based on the first control signal and the second control signal. The first tracking signal is the larger of the first control signal and the third voltage level, and the second tracking signal is the larger of the second control signal and the third voltage level.

[0058] In the above-mentioned level shifter, the cross latch circuit includes: a first PMOS transistor and a first NMOS transistor, which are connected in series between a first voltage rail configured to receive a fourth voltage level and a second voltage rail configured to receive a third voltage level, wherein a junction of the first PMOS transistor and the first NMOS transistor forms a first output terminal; a second PMOS transistor and a second NMOS transistor, which are connected in series between the first voltage rail and the second voltage rail, wherein a junction of the second PMOS transistor and the second NMOS transistor forms a second output terminal; and wherein a gate terminal of the first PMOS transistor is connected to receive a second tracking signal, and a gate terminal of the second PMOS transistor is connected to receive the first tracking signal.

[0059] In the above-mentioned level shifter, the first output terminal is connected to the gate terminal of the second nNMOS transistor; and the second output terminal is connected to the gate terminal of the first NMOS transistor.

[0060] In the above-mentioned level shifter, a gate terminal of the first NMOS transistor is connected to receive the second tracking signal, and a gate terminal of the second NMOS transistor is connected to receive the first tracking signal.

[0061] In the above-mentioned level shifter, the cross latch circuit includes: a third NMOS transistor, which is connected in series with the first NMOS transistor between the first NMOS transistor and the second voltage rail; and a fourth NMOS transistor, which is connected in series with the second NMOS transistor between the second NMOS transistor and the second voltage rail; wherein the gate terminal of the third NMOS transistor is connected to the second output terminal, and the gate terminal of the fourth NMOS transistor is connected to the first output terminal.

[0062] In the above-mentioned level shifter, the cross latch circuit includes: a third NMOS transistor, which is connected in parallel with the first NMOS transistor between the first NMOS transistor and the second voltage rail; and a fourth NMOS transistor, which is connected in parallel with the second NMOS transistor between the second NMOS transistor and the second voltage rail; wherein the gate terminal of the third NMOS transistor is connected to the second output terminal, and the gate terminal of the fourth NMOS transistor is connected to the first output terminal.

[0063] In the above-mentioned level shifter, the input circuit includes: a first PMOS transistor and a first NMOS transistor, which are connected in series between a first output terminal and a first input terminal, wherein a junction of the first PMOS transistor and the first NMOS transistor forms a first control node, wherein a gate terminal of the first PMOS transistor is connected to a third voltage level, and wherein a gate terminal of the first NMOS transistor is connected to a second voltage level; a second PMOS transistor and a second NMOS transistor, which are connected in series between a second output terminal and a second input terminal, wherein a junction of the second PMOS transistor and the second NMOS transistor forms a second control node, wherein a gate terminal of the second PMOS transistor is connected to a third voltage level, and wherein a gate terminal of the second NMOS transistor is connected to the second voltage level.

[0064] In the above-mentioned level shifter, the input circuit includes: a third PMOS transistor, which is connected in series between the first PMOS transistor and the first control node; a fourth PMOS transistor, which is connected in series between the second PMOS transistor and the second control node; a third NMOS transistor, which is connected in series between the first NMOS transistor and the first control node; and a fourth NMOS transistor, which is connected in series between the second NMOS transistor and the second control node.

[0065] In the above-mentioned level shifter, a gate terminal of each of the third PMOS transistor and the fourth PMOS transistor is connected to a third voltage level, and wherein gate terminals of the third NMOS transistor and the fourth NMOS transistor are connected to a second voltage level.

[0066] In the above-mentioned level shifter, the tracking circuit includes: a first cross-coupled PMOS transistor pair having a first input terminal connected to a third voltage level, a second input terminal connected to a first control node, and an output terminal configured to output a first tracking signal; a second cross-coupled PMOS transistor pair having a first input terminal connected to a third voltage level, a second input terminal connected to a second control node, and an output terminal configured to output a second tracking signal.

[0067] In the above-mentioned level shifter, the tracking circuit includes: a first cross-coupled NMOS transistor pair, having a first input terminal connected to a third voltage level, a second input terminal connected to a first control node, and an output terminal; a second cross-coupled NMOS transistor pair, having a first input terminal connected to a third voltage level, a second input terminal connected to a second control node, and an output terminal; and wherein the input circuit includes: a third PMOS transistor, connected in series between the first PMOS transistor and the first control node, the third PMOS transistor having a gate terminal connected to the output terminal of the first cross-coupled NMOS transistor pair; a fourth PMOS transistor, connected in series between the second PMOS transistor and the second control node, the fourth PMOS transistor having a gate terminal connected to the output terminal of the first cross-coupled NMOS transistor pair.

[0068] In the above-mentioned level shifter, the tracking circuit includes: a third cross-coupled PMOS transistor pair, having a first input terminal connected to a second voltage level, a second input terminal connected to a first control node, and an output terminal; a fourth cross-coupled PMOS transistor pair, having a first input terminal connected to the second voltage level, a second input terminal connected to a second control node, and an output terminal; and wherein the input circuit includes: a third NMOS transistor, connected in series between the first NMOS transistor and the first control node, the third NMOS transistor having a gate terminal connected to the output terminal of the third cross-coupled PMOS transistor pair; a fourth NMOS transistor, connected in series between the second NMOS transistor and the second control node, the fourth NMOS transistor having a gate terminal connected to the output terminal of the fourth cross-coupled PMOS transistor pair.

[0069] In other disclosed examples, the level shifter includes a first input terminal and a second input terminal configured to receive complementary first and second input signals in a low voltage domain, and a first output terminal and a second output terminal configured to provide complementary first and second output signals in a high voltage domain corresponding to the first and second input signals. An input circuit is connected between the first and second input terminals and the first and second output terminals. The input circuit has a first control node and a second control node, and the first and second control nodes are configured to output a first control signal and a second control signal in a high voltage domain and in a low voltage domain based on the first and second input signals. A cross latch circuit is coupled to the input circuit and the first and second output terminals, and the cross latch circuit has a first input terminal and a second input terminal. A tracking circuit is coupled to the first and second control nodes and the first and second input terminals of the cross latch circuit. The tracking circuit is configured to provide a first tracking signal and a second tracking signal in a high voltage domain to the first input signal and the second input signal of the cross latch circuit based on the first control signal and the second control signal.

[0070] In the above level shifter, the low voltage domain includes a first voltage level and a second voltage level higher than the first voltage level, and wherein the high voltage domain includes a third voltage level and a fourth voltage level higher than the second voltage level.

[0071] In the above-mentioned level shifter, the second voltage level and the third voltage level are the same voltage level.

[0072] In the above-mentioned level shifter, the cross latch circuit includes: a first PMOS transistor and a first NMOS transistor, which are connected in series between a first voltage rail configured to receive a fourth voltage level and a second voltage rail configured to receive a third voltage level, wherein a junction of the first PMOS transistor and the first NMOS transistor forms a first output terminal, wherein a gate terminal of the first PMOS transistor is connected to receive a second tracking signal; a second PMOS transistor and a second NMOS transistor, which are connected in series between the first voltage rail and the second voltage rail, wherein a junction of the second PMOS transistor and the second NMOS transistor forms a second output terminal, wherein a gate terminal of the second PMOS transistor is connected to receive the first tracking signal.

[0073] In the above-mentioned level shifter, the input circuit includes: a first PMOS transistor and a first NMOS transistor connected in series between a first output terminal and a first input terminal, wherein a junction of the first PMOS transistor and the first NMOS transistor forms a first control node, wherein a gate terminal of the first PMOS transistor is connected to a third voltage level, and wherein a gate terminal of the first NMOS transistor is connected to a second voltage level; a second PMOS transistor and a second NMOS transistor connected in series between a second output terminal and a second input terminal, wherein a junction of the second PMOS transistor and the second NMOS transistor forms a second control node, wherein a gate terminal of the second PMOS transistor is connected to the third voltage level, and wherein a gate terminal of the second NMOS transistor is connected to the second voltage level; and wherein the tracking circuit includes: a first cross-coupled PMOS transistor pair having a first input terminal connected to the third voltage level, a second input terminal connected to the first control node, and an output terminal configured to output a first tracking signal; and a second cross-coupled PMOS transistor pair having a first input terminal connected to the third voltage level, a second input terminal connected to the second control node, and an output terminal configured to output a second tracking signal.

[0074] In the above-mentioned level shifter, the input circuit, the cross latch circuit and the tracking circuit include a plurality of PMOS devices and a plurality of NMOS devices, and wherein the PMOS devices and the NMOS devices are symmetrically arranged in or on a substrate.

[0075] According to another example, a method includes receiving a first input signal and a second input signal having respective first voltage levels and second voltage levels, wherein the second voltage level is higher than the first voltage level. A first control signal having a first voltage level is generated based on the first input signal, and a second control signal having a fourth voltage level higher than the second voltage level is generated based on the second input signal. A first tracking signal having a third voltage level higher than the first voltage level is provided to a cross latch circuit based on the first control signal. A second tracking signal having a fourth voltage level is provided to the cross latch circuit based on the second control signal. A first output signal having a third voltage level is output based on the second tracking signal by the cross latch circuit, and a second output signal having a fourth voltage level is output based on the first tracking signal by the cross latch circuit.

[0076] In the above method, the second voltage level is the same as the third voltage level.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A level shifter, comprising: an input circuit having a first input terminal and a second input terminal configured to receive a pair of complementary input signals, wherein the pair of complementary input signals are at a first voltage level and a second voltage level, respectively; a cross-latch circuit coupled to the input circuit, the cross-latch circuit having a first output terminal and a second output terminal configured to provide a pair of complementary output signals, the pair of complementary output signals being at a third voltage level and a fourth voltage level, respectively, wherein the input circuit includes a first control node and a second control node configured to output a first control signal and a second control signal at the first voltage level and the fourth voltage level based on the input signal; and A tracking circuit, coupled to the input circuit and the cross-latch circuit, is configured to input a first tracking signal and a second tracking signal to the cross-latch circuit based on the first control signal and the second control signal, wherein the first tracking signal is the larger of the first control signal and the third voltage level, and the second tracking signal is the larger of the second control signal and the third voltage level.

2. The level shifter according to claim 1, wherein: The cross latch circuit comprises: a first PMOS transistor and a first NMOS transistor connected in series between a first voltage rail configured to receive the fourth voltage level and a second voltage rail configured to receive the third voltage level, wherein a junction of the first PMOS transistor and the first NMOS transistor forms the first output terminal; a second PMOS transistor and a second NMOS transistor connected in series between the first voltage rail and the second voltage rail, wherein a junction of the second PMOS transistor and the second NMOS transistor forms the second output terminal; and A gate terminal of the first PMOS transistor is connected to receive the second tracking signal, and a gate terminal of the second PMOS transistor is connected to receive the first tracking signal.

3. The level shifter according to claim 2, wherein: The first output terminal is connected to the gate terminal of the second NMOS transistor; and The second output terminal is connected to the gate terminal of the first NMOS transistor.

4. The level shifter according to claim 2, wherein: A gate terminal of the first NMOS transistor is connected to receive the second tracking signal, and a gate terminal of the second NMOS transistor is connected to receive the first tracking signal.

5. The level shifter according to claim 4, wherein: The cross latch circuit comprises: a third NMOS transistor connected in series with the first NMOS transistor between the first NMOS transistor and the second voltage rail; a fourth NMOS transistor connected in series with the second NMOS transistor between the second NMOS transistor and the second voltage rail; Wherein, a gate terminal of the third NMOS transistor is connected to the second output terminal, and a gate terminal of the fourth NMOS transistor is connected to the first output terminal.

6. The level shifter according to claim 4, wherein: The cross latch circuit comprises: a third NMOS transistor connected in parallel with the first NMOS transistor between the first NMOS transistor and the second voltage rail; a fourth NMOS transistor connected in parallel with the second NMOS transistor between the second NMOS transistor and the second voltage rail; Wherein, a gate terminal of the third NMOS transistor is connected to the second output terminal, and a gate terminal of the fourth NMOS transistor is connected to the first output terminal.

7. The level shifter according to claim 1, wherein: The input circuit comprises: a first PMOS transistor and a first NMOS transistor connected in series between the first output terminal and the first input terminal, wherein a junction of the first PMOS transistor and the first NMOS transistor forms the first control node, wherein a gate terminal of the first PMOS transistor is connected to the third voltage level, and wherein a gate terminal of the first NMOS transistor is connected to the second voltage level; A second PMOS transistor and a second NMOS transistor are connected in series between the second output terminal and the second input terminal, wherein a junction of the second PMOS transistor and the second NMOS transistor forms the second control node, wherein a gate terminal of the second PMOS transistor is connected to the third voltage level, and wherein a gate terminal of the second NMOS transistor is connected to the second voltage level.

8. The level shifter according to claim 7, wherein: The input circuit comprises: a third PMOS transistor connected in series between the first PMOS transistor and the first control node; a fourth PMOS transistor connected in series between the second PMOS transistor and the second control node; a third NMOS transistor connected in series between the first NMOS transistor and the first control node; and A fourth NMOS transistor is connected in series between the second NMOS transistor and the second control node.

9. The level shifter according to claim 8, wherein: A gate terminal of each of the third PMOS transistor and the fourth PMOS transistor is connected to the third voltage level, and wherein gate terminals of the third NMOS transistor and the fourth NMOS transistor are connected to the second voltage level.

10. The level shifter according to claim 2, wherein: The tracking circuit comprises: a first cross-coupled PMOS transistor pair having a first input terminal connected to the third voltage level, a second input terminal connected to the first control node, and an output terminal configured to output the first tracking signal; A second cross-coupled PMOS transistor pair has a first input terminal connected to the third voltage level, a second input terminal connected to the second control node, and an output terminal configured to output the second tracking signal.

11. The level shifter according to claim 10, wherein: The tracking circuit comprises: a first cross-coupled NMOS transistor pair having a first input terminal connected to the third voltage level, a second input terminal connected to the first control node, and an output terminal; a second cross-coupled NMOS transistor pair having a first input terminal connected to the third voltage level, a second input terminal connected to the second control node, and an output terminal; and Wherein, the input circuit comprises: a third PMOS transistor connected in series between the first PMOS transistor and the first control node, the third PMOS transistor having a gate terminal connected to the output terminal of the first cross-coupled NMOS transistor pair; A fourth PMOS transistor is connected in series between the second PMOS transistor and the second control node, the fourth PMOS transistor having a gate terminal connected to the output terminal of the first cross-coupled NMOS transistor pair.

12. The level shifter according to claim 10, wherein: The tracking circuit comprises: a third cross-coupled PMOS transistor pair having a first input terminal connected to the second voltage level, a second input terminal connected to the first control node, and an output terminal; a fourth cross-coupled PMOS transistor pair having a first input terminal connected to the second voltage level, a second input terminal connected to the second control node, and an output terminal; and The input circuit includes: a third NMOS transistor connected in series between the first NMOS transistor and the first control node, the third NMOS transistor having a gate terminal connected to the output terminal of the third cross-coupled PMOS transistor pair; A fourth NMOS transistor is connected in series between the second NMOS transistor and the second control node, the fourth NMOS transistor having a gate terminal connected to the output terminal of the fourth cross-coupled PMOS transistor pair.

13. A level shifter, comprising: first and second input terminals configured to receive complementary first and second input signals in a low voltage domain; a first output terminal and a second output terminal configured to provide complementary first and second output signals in a high voltage domain corresponding to the first and second input signals, wherein the low voltage domain is between a first voltage level and a second voltage level higher than the first voltage level, and the high voltage domain is between a third voltage level and a fourth voltage level higher than the second voltage level and higher than the third voltage level; an input circuit connected between the first input terminal and the second input terminal and the first output terminal and the second output terminal, the input circuit having a first control node and a second control node, the first control node and the second control node being configured to output a first control signal in the high voltage domain and a second control signal in the low voltage domain based on the first input signal and the second input signal; a cross latch circuit coupled to the input circuit and the first output terminal and the second output terminal, the cross latch circuit having a first input terminal and a second input terminal; A tracking circuit is coupled to the first control node and the second control node and the first input terminal and the second input terminal of the cross latch circuit, and the tracking circuit is configured to provide a first tracking signal and a second tracking signal in the high voltage domain to the first input terminal and the second input terminal of the cross latch circuit based on the first control signal and the second control signal.

14. The level shifter according to claim 13, wherein: The second voltage level and the third voltage level are both 1.8V.

15. The level shifter according to claim 13, wherein: The second voltage level and the third voltage level are the same voltage level.

16. The level shifter according to claim 14, wherein: The cross latch circuit comprises: a first PMOS transistor and a first NMOS transistor connected in series between a first voltage rail configured to receive the fourth voltage level and a second voltage rail configured to receive the third voltage level, wherein a junction of the first PMOS transistor and the first NMOS transistor forms the first output terminal, wherein a gate terminal of the first PMOS transistor is connected to receive the second tracking signal; A second PMOS transistor and a second NMOS transistor are connected in series between the first voltage rail and the second voltage rail, wherein a junction of the second PMOS transistor and the second NMOS transistor forms the second output terminal, and wherein a gate terminal of the second PMOS transistor is connected to receive the first tracking signal.

17. The level shifter according to claim 16, wherein: The input circuit comprises: a first PMOS transistor and a first NMOS transistor connected in series between the first output terminal and the first input terminal, wherein a junction of the first PMOS transistor and the first NMOS transistor forms the first control node, wherein a gate terminal of the first PMOS transistor is connected to the third voltage level, and wherein a gate terminal of the first NMOS transistor is connected to the second voltage level; a second PMOS transistor and a second NMOS transistor connected in series between the second output terminal and the second input terminal, wherein a junction of the second PMOS transistor and the second NMOS transistor forms the second control node, wherein a gate terminal of the second PMOS transistor is connected to the third voltage level, and wherein a gate terminal of the second NMOS transistor is connected to the second voltage level; and Wherein, the tracking circuit comprises: a first cross-coupled PMOS transistor pair having a first input terminal connected to the third voltage level, a second input terminal connected to the first control node, and an output terminal configured to output the first tracking signal; and A second cross-coupled PMOS transistor pair has a first input terminal connected to the third voltage level, a second input terminal connected to the second control node, and an output terminal configured to output the second tracking signal.

18. The level shifter according to claim 17, wherein: The input circuit, the cross latch circuit and the tracking circuit include a plurality of PMOS devices and a plurality of NMOS devices, and wherein the PMOS devices and the NMOS devices are symmetrically arranged in or on a substrate.

19. A level shifting method, comprising: receiving a first input signal and a second input signal having respective first and second voltage levels, wherein the second voltage level is higher than the first voltage level; generating a first control signal having the first voltage level based on the first input signal; generating a second control signal having a fourth voltage level higher than the second voltage level based on the second input signal; providing a first tracking signal having a third voltage level higher than the first voltage level to a cross latch circuit based on the first control signal; providing a second tracking signal having the fourth voltage level to the cross latch circuit based on the second control signal; outputting, by the cross latch circuit, a first output signal having the third voltage level based on the second tracking signal; and A second output signal having the fourth voltage level is outputted based on the first tracking signal by the cross latch circuit.

20. The method according to claim 19, wherein: The second voltage level is the same as the third voltage level.

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