3D chip packaging structure and preparation method thereof

Abstract

The present invention provides a 3D chip packaging structure and a preparation method thereof, wherein the 3D chip packaging structure comprises: a rewiring layer; a chip, flip-chip bonded to the upper surface of the rewiring layer; a first electrical connection structure, located on the upper surface of the rewiring layer; a first plastic sealing layer, located on the upper surface of the rewiring layer, and plastic sealing the chip and the first electrical connection structure; a second electrical connection structure, located on the upper surface of the first plastic sealing layer; a second plastic sealing layer, located on the upper surface of the first plastic sealing layer; a third electrical connection structure, located on the upper surface of the second plastic sealing layer; a third plastic sealing layer, located on the upper surface of the second plastic sealing layer, and plastic sealing the third electrical connection structure; a top metal wire layer, located on the upper surface of the third plastic sealing layer; and a solder ball bump, located on the lower surface of the rewiring layer. In the 3D chip packaging structure of the present invention, the chip realizes 3D packaging, has low cost and high packaging integration, and can meet the needs of the development trend of miniaturization.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a 3D chip packaging structure and a preparation method thereof. Background Art

[0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size. At present, advanced packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip (FlipChip), Package on Package (POP), etc.

[0003] However, the existing packaging methods and packaging structures obtained by the packaging methods have the problems of high cost, low integration, and failure to meet the needs of the development trend of miniaturization. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a 3D chip packaging structure and a preparation method thereof, so as to solve the problems that the packaging methods and packaging structures in the prior art have high costs, low integration, and cannot meet the needs of the miniaturization development trend.

[0005] To achieve the above objectives and other related objectives, the present invention provides a 3D chip packaging structure, the 3D chip packaging structure comprising:

[0006] Rewiring layers;

[0007] A chip is flip-chip bonded to the upper surface of the rewiring layer and electrically connected to the rewiring layer;

[0008] A first electrical connection structure is located on the upper surface of the rewiring layer and is electrically connected to the rewiring layer;

[0009] A first plastic sealing layer is located on the upper surface of the rewiring layer and plastic seals the chip and the first electrical connection structure;

[0010] a second electrical connection structure, located on the upper surface of the first plastic packaging layer and electrically connected to the first electrical connection structure;

[0011] A second plastic sealing layer is located on the upper surface of the first plastic sealing layer and seals the second electrical connection structure;

[0012] a third electrical connection structure, located on the upper surface of the second plastic packaging layer and electrically connected to the second electrical connection structure;

[0013] A third plastic sealing layer is located on the upper surface of the second plastic sealing layer and plastic seals the third electrical connection structure;

[0014] A top metal wire layer, located on an upper surface of the third plastic encapsulation layer and electrically connected to the third electrical connection structure;

[0015] The solder ball bump is located on the lower surface of the rewiring layer and is electrically connected to the rewiring layer.

[0016] Optionally, the rewiring layer comprises:

[0017] Wiring dielectric layer;

[0018] The metal stacked structure is located in the wiring dielectric layer. The metal stacked structure includes multiple layers of metal wire layers and metal plugs arranged at intervals. The metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

[0019] Optionally, the rewiring layer further comprises:

[0020] A seed layer, located on the lower surface of the wiring dielectric layer and electrically connected to the metal stack structure;

[0021] A plastic packaging material layer is located on the lower surface of the seed layer; the wiring dielectric layer covers the plastic packaging material layer and the seed layer;

[0022] The bottom dielectric layer is located on the lower surface of the wiring dielectric layer.

[0023] Optionally, the first electrical connection structure, the second electrical connection structure and the third electrical connection structure all include welding wires or conductive columns.

[0024] Optionally, the 3D chip packaging structure further includes:

[0025] A first interlayer dielectric layer, located between the first plastic encapsulation layer and the second plastic encapsulation layer;

[0026] a first redistribution metal layer, located in the first interlayer dielectric layer and electrically connected to the first electrical connection structure and the second electrical connection structure;

[0027] A second interlayer dielectric layer, located between the second plastic encapsulation layer and the third plastic encapsulation layer;

[0028] The second redistribution metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure and the third electrical connection structure.

[0029] Optionally, the orthographic projection of the second plastic sealing layer on the upper surface of the first plastic sealing layer is located within the upper surface of the first plastic sealing layer; and the orthographic projection of the third plastic sealing layer on the upper surface of the second plastic sealing layer is located within the upper surface of the second plastic sealing layer.

[0030] Optionally, the thickness of the second plastic encapsulation layer is smaller than the thickness of the first plastic encapsulation layer and larger than the thickness of the third plastic encapsulation layer.

[0031] To achieve the above-mentioned object and other related objects, the present invention further provides a method for preparing a 3D chip packaging structure, the method for preparing the 3D chip packaging structure comprising the following steps:

[0032] Providing a substrate, and forming a sacrificial layer on an upper surface of the substrate;

[0033] forming a rewiring layer on the upper surface of the sacrificial layer;

[0034] Providing a chip, and flip-chip bonding the chip to the upper surface of the rewiring layer, so that the chip and the rewiring layer are electrically connected;

[0035] A first electrical connection structure and a first plastic sealing layer are formed on the upper surface of the rewiring layer; the first electrical connection structure is located in the first plastic sealing layer, and the first electrical connection structure is electrically connected to the rewiring layer; the first plastic sealing layer plastic seals the chip and the first electrical connection structure;

[0036] A second electrical connection structure and a second plastic sealing layer are formed on the upper surface of the first plastic sealing layer; the second electrical connection structure is located in the second plastic sealing layer and is electrically connected to the first electrical connection structure;

[0037] A third electrical connection structure and a third plastic sealing layer are formed on the upper surface of the second plastic sealing layer; the third electrical connection structure is located in the third plastic sealing layer and is electrically connected to the second electrical connection structure;

[0038] forming a top metal wire layer on the upper surface of the third plastic encapsulation layer, wherein the top metal wire layer is electrically connected to the third electrical connection structure;

[0039] removing the substrate and the sacrificial layer;

[0040] A solder bump is formed below the rewiring layer, and the solder bump is electrically connected to the rewiring layer.

[0041] Optionally, forming the rewiring layer on the upper surface of the sacrificial layer comprises the following steps:

[0042] forming a bottom dielectric layer on the upper surface of the sacrificial layer;

[0043] forming a plastic packaging material layer on the upper surface of the bottom dielectric layer;

[0044] forming a seed layer on the upper surface of the plastic packaging material layer;

[0045] Performing a patterning process on the seed layer and the plastic encapsulation material layer;

[0046] A wiring dielectric layer and a metal stack structure are formed on the upper surface of the bottom dielectric layer. The metal stack structure is located in the wiring dielectric layer and is electrically connected to the seed layer. The metal stack structure includes multiple layers of spaced metal wire layers and metal plugs. The metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

[0047] Optionally, before forming the second electrical connection structure and the second plastic encapsulation layer on the upper surface of the first plastic encapsulation layer, the method further includes forming a first interlayer dielectric layer and a first rewiring metal layer on the upper surface of the first plastic encapsulation layer, wherein the first rewiring metal layer is located in the first interlayer dielectric layer and is electrically connected to the first electrical connection structure; the second plastic encapsulation layer is formed on the upper surface of the first interlayer dielectric layer, and the second electrical connection structure is formed on the upper surface of the first rewiring metal layer;

[0048] Before forming the third electrical connection structure and the third plastic encapsulation layer on the upper surface of the second plastic encapsulation layer, the step also includes forming a second interlayer dielectric layer and a second re-wiring metal layer on the upper surface of the second plastic encapsulation layer, the second re-wiring metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure; the third plastic encapsulation layer is formed on the upper surface of the second interlayer dielectric layer, and the third electrical connection structure is formed on the upper surface of the second re-wiring metal layer.

[0049] Optionally, the orthographic projection of the second plastic sealing layer on the upper surface of the first plastic sealing layer is located within the upper surface of the first plastic sealing layer; and the orthographic projection of the third plastic sealing layer on the upper surface of the second plastic sealing layer is located within the upper surface of the second plastic sealing layer.

[0050] Optionally, the thickness of the second plastic encapsulation layer is smaller than the thickness of the first plastic encapsulation layer and larger than the thickness of the third plastic encapsulation layer.

[0051] As described above, the 3D chip packaging structure and preparation method thereof of the present invention have the following beneficial effects: In the 3D chip packaging structure of the present invention, the chip realizes 3D packaging, has low cost and high packaging integration, and can meet the needs of the miniaturization development trend. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1Shown is a flow chart of a method for preparing a 3D chip packaging structure provided in Embodiment 1 of the present invention.

[0053] Figures 2 to 18 It is a schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing the 3D chip packaging structure provided in the first embodiment of the present invention; wherein: Fig.18 Shown is a schematic cross-sectional structure diagram of a 3D chip packaging structure provided in the second embodiment of the present invention.

[0054] Component number description

[0055] 10 Base

[0056] 11 Sacrificial Layer

[0057] 12 Rewiring Layers

[0058] 121 bottom dielectric layer

[0059] 122 plastic material layer

[0060] 123 seed layer

[0061] 124 Wiring Dielectric Layer

[0062] 125 Metal laminate structure

[0063] 13 Chip

[0064] 14. First electrical connection structure

[0065] 15 First plastic layer

[0066] 16. First interlayer dielectric layer

[0067] 17 First redistribution metal layer

[0068] 18. Second electrical connection structure

[0069] 19 Second plastic sealing layer

[0070] 20 Second interlayer dielectric layer

[0071] 21 Second redistribution metal layer

[0072] 22. Third electrical connection structure

[0073] 23 The third plastic sealing layer

[0074] 24 Top metal wire layer

[0075] 25 solder ball bumps

[0076] 26 Opening DETAILED DESCRIPTION

[0077] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] See also Figures 1 to 18 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0079] Embodiment 1

[0080] See also Figure 1 The present invention provides a method for preparing a 3D chip packaging structure, and the method for preparing the 3D chip packaging structure comprises the following steps:

[0081] 1) providing a substrate, and forming a sacrificial layer on the upper surface of the substrate;

[0082] 2) forming a rewiring layer on the upper surface of the sacrificial layer;

[0083] 3) providing a chip, and flip-chip bonding the chip to the upper surface of the rewiring layer, so that the chip and the rewiring layer are electrically connected;

[0084] 4) forming a first electrical connection structure and a first plastic packaging layer on the upper surface of the rewiring layer; the first electrical connection structure is located in the first plastic packaging layer, and the first electrical connection structure is electrically connected to the rewiring layer; the first plastic packaging layer plastic-packages the chip and the first electrical connection structure;

[0085] 5) forming a second electrical connection structure and a second plastic sealing layer on the upper surface of the first plastic sealing layer; the second electrical connection structure is located in the second plastic sealing layer and is electrically connected to the first electrical connection structure;

[0086] 6) forming a third electrical connection structure and a third plastic sealing layer on the upper surface of the second plastic sealing layer; the third electrical connection structure is located in the third plastic sealing layer and is electrically connected to the second electrical connection structure;

[0087] 7) forming a top metal wire layer on the upper surface of the third plastic encapsulation layer, wherein the top metal wire layer is electrically connected to the third electrical connection structure;

[0088] 8) removing the substrate and the sacrificial layer;

[0089] 9) forming a solder bump below the rewiring layer, wherein the solder bump is electrically connected to the rewiring layer.

[0090] In step 1), refer to Figure 1 The S1 step in Figure 2 , providing a substrate 10 , and forming a sacrificial layer 11 on the upper surface of the substrate 10 .

[0091] As an example, the material of the substrate 10 can be one material selected from silicon, glass, silicon oxide, ceramic, polymer and metal, or a composite material of two or more thereof, and its shape can be circular, square or any other desired shape. Preferably, in this embodiment, the material of the substrate 10 is silicon.

[0092] As an example, the sacrificial layer 11 serves as a separation layer between the rewiring layer and the substrate 10 in the subsequent process. It is best to be made of an adhesive material with a smooth surface. It must have a certain bonding force with the rewiring layer. In addition, it also has a strong bonding force with the substrate 10. Generally speaking, the bonding force between the sacrificial layer 11 and the substrate 10 needs to be greater than the bonding force with the rewiring layer.

[0093] As an example, the sacrificial layer 11 may include a polymer layer or a tape-shaped adhesion layer; specifically, the material of the sacrificial layer 11 may be selected from a tape with sticky surfaces on both sides (for example, a chip attachment film or a non-conductive film, etc.) or an adhesive made by a spin coating process, etc.; preferably, in this embodiment, the sacrificial layer 11 is preferably a UV tape, which can be easily torn off after being irradiated with UV light (ultraviolet light); of course, in other examples, the sacrificial layer 11 may also be made of other material layers formed by physical vapor deposition or chemical vapor deposition, such as epoxy resin (Epoxy), silicone rubber (Silicone rubber), polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), etc. When the substrate 10 is subsequently separated, the sacrificial layer 11 may be removed by wet etching, chemical mechanical grinding, etc.

[0094] As an example, the sacrificial layer 11 may also be formed by an automatic bonding process.

[0095] In step 2), refer to Figure 1 The S2 step in Figures 3 to 5 , a rewiring layer 12 is formed on the upper surface of the sacrificial layer 11 .

[0096] As an example, in step 2), forming the rewiring layer 12 on the upper surface of the sacrificial layer 11 may include the following steps:

[0097] 2-1) forming a bottom dielectric layer 121 on the upper surface of the sacrificial layer 11, such as Figure 3 As shown;

[0098] 2-2) Forming a plastic encapsulation material layer 122 on the upper surface of the bottom dielectric layer 121, such as Figure 3 As shown;

[0099] 2-3) forming a seed layer 123 on the upper surface of the molding material layer 122, such as Figure 3 As shown;

[0100] 2-4) The seed layer 123 and the plastic encapsulation material layer 122 are subjected to a graphic treatment, such as Figure 4 As shown; specifically, the seed layer 123 and the plastic encapsulation material layer 122 may be patterned by using a photolithography and etching process;

[0101] 2-5) forming a wiring dielectric layer 124 and a metal stack structure 125 on the upper surface of the bottom dielectric layer 121, wherein the metal stack structure 125 is located in the wiring dielectric layer 124 and is electrically connected to the seed layer 123, as shown in FIG. Figure 5 As shown; the metal stack structure 125 includes multiple layers of spaced metal wire layers (not shown) and metal plugs (not shown), wherein the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

[0102] As an example, the material of the bottom dielectric layer 121 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass; the bottom dielectric layer 121 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0103] As an example, the material of the molding material layer 122 may include but is not limited to polyimide, silicone or epoxy resin, etc.

[0104] As an example, the seed layer 123 may be formed by, but is not limited to, a sputtering process; the material of the seed layer 123 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 123 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.

[0105] As an example, the material of the wiring dielectric layer 124 may include a low-k dielectric material. As an example, the wiring dielectric layer 124 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0106] As an example, the metal line layer may include a single metal layer, or may include two or more metal layers. As an example, the material of the metal line layer and the material of the metal plug may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0107] In step 3), refer to Figure 1 The S3 steps in Figure 6 , providing a chip 13, and flip-chip bonding the chip 13 to the upper surface of the rewiring layer 12, so that the chip 13 is electrically connected to the rewiring layer 12.

[0108] As an example, the chip 13 may be any functional chip, a device structure (not shown) may be formed inside the chip 13, a connection pad (not shown) may be formed on the front side of the chip 13, and the connection pad is electrically connected to the device structure.

[0109] As an example, the chip 13 may be flip-chip bonded to the upper surface of the rewiring layer 12 using any existing bonding process; the connection pads of the chip 13 are electrically connected to the metal stack structure 125 in the rewiring layer 12 .

[0110] In step 4), refer to Figure 1 Step S4 in Figures 6 to 8 A first electrical connection structure 14 and a first plastic packaging layer 15 are formed on the upper surface of the rewiring layer 12; the first electrical connection structure 14 is located in the first plastic packaging layer 15, and the first electrical connection structure 14 is electrically connected to the rewiring layer 12; the first plastic packaging layer 15 plastic packages the chip 13 and the first electrical connection structure 14.

[0111] As an example, the first electrical connection structure 14 may be formed on the upper surface of the rewiring layer 12 by using a wire bonding process or a pillar bonding process; the first electrical connection structure 14 may include a bonding wire or a conductive pillar.

[0112] As an example, the number of the first electrical connection structures 14 can be set according to actual needs. Figures 6 to 8 Only four first electrical connection structures 14 are shown as an example. In actual examples, the number of the first electrical connection structures 14 is not limited thereto.

[0113] As an example, the first plastic encapsulation layer 15 may be formed on the upper surface of the rewiring layer 12 by, but not limited to, a molding bottom filling process, an imprint molding process, a transfer molding process, a liquid sealing plastic encapsulation process, a vacuum lamination process or a spin coating process; preferably, in this embodiment, a molding bottom filling process is used to form the first plastic encapsulation layer 15 on the upper surface of the rewiring layer 12. The first plastic encapsulation layer 15 is formed by the molding bottom filling process, and the first plastic encapsulation layer 15 can smoothly and quickly fill the gap between the chip 13 and the first electrical connection structure 14, and can effectively avoid interface stratification; and the molding bottom filling process is not limited like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.

[0114] As an example, the material of the first plastic packaging layer 15 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0115] As an example, the upper surface of the initially formed first plastic encapsulation layer 15 may be higher than the top of the first electrical connection structure 14. Figure 7 As shown, at this time, after the first plastic encapsulation layer 15 is formed, a process of thinning the first plastic encapsulation layer 15 needs to be performed. Specifically, the first plastic encapsulation layer 15 can be thinned by, but not limited to, a chemical mechanical polishing process, so that the upper surface of the retained first plastic encapsulation layer 15 is flush with the top of the first electrical connection structure 14, as shown in FIG. Figure 8 Of course, in other examples, the upper surface of the initially formed first plastic encapsulation layer 15 is flush with the top of the first electrical connection structure 14, such as Figure 8 As shown, at this time, the process of thinning the first plastic sealing layer 15 can be saved.

[0116] As an example, Fig. 9 As shown, after step 4), the following steps are also included: forming a first interlayer dielectric layer 16 and a first rewiring metal layer 17 on the upper surface of the first plastic encapsulation layer 15, the first rewiring metal layer 17 is located in the first interlayer dielectric layer 16, and the first rewiring metal layer 17 is electrically connected to the first electrical connection structure 14. The first interlayer dielectric layer 16 can enhance the bonding force between the first plastic encapsulation layer 15 and the second plastic encapsulation layer 19 formed subsequently, and at the same time, the first rewiring metal layer 17 in the first interlayer dielectric layer 16 can realize rewiring, and the position and number of the second electrical connection structure 18 formed subsequently can be adjusted as needed.

[0117] As an example, the material of the first interlayer dielectric layer 16 may include a low-k dielectric material. As an example, the first interlayer dielectric layer 16 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0118] As an example, the material of the first rewiring metal layer 17 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0119] In step 5), refer to Figure 1 Step S5 in Figure 10 to Figure 11 , a second electrical connection structure 18 and a second plastic sealing layer 19 are formed on the upper surface of the first plastic sealing layer 15 ; the second electrical connection structure 18 is located in the second plastic sealing layer 19 , and the second electrical connection structure 18 is electrically connected to the first electrical connection structure 14 .

[0120] It should be noted that when the first interlayer dielectric layer 16 and the first re-wiring metal layer 17 are formed on the upper surface of the first plastic encapsulation layer 15, the second plastic encapsulation layer 19 is formed on the upper surface of the first interlayer dielectric layer 16, and the second electrical connection structure 18 is formed on the upper surface of the first re-wiring metal layer 17, and the second electrical connection structure 18 is electrically connected to the first electrical connection structure 14 via the first re-wiring metal layer 17.

[0121] As an example, the second electrical connection structure 18 may be formed by a wire bonding process or a pillar bonding process; the second electrical connection structure 18 may include a bonding wire or a conductive pillar.

[0122] As an example, the number of the second electrical connection structures 18 can be set according to actual needs. Figure 10 to Figure 11 Only four second electrical connection structures 18 are shown as an example. In actual examples, the number of the second electrical connection structures 18 is not limited thereto.

[0123] As an example, the second plastic encapsulation layer 19 may be formed by, but not limited to, a molding bottom filling process, an imprint molding process, a transfer molding process, a liquid sealing plastic encapsulation process, a vacuum lamination process or a spin coating process; preferably, in this embodiment, a molding bottom filling process is used to form the second plastic encapsulation layer 19. The molding bottom filling process is used to form the second plastic encapsulation layer 19, and the second plastic encapsulation layer 19 can smoothly and quickly fill the gap between the second electrical connection structures 18, and can effectively avoid interface stratification; and the molding bottom filling process is not limited like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.

[0124] As an example, the material of the second plastic packaging layer 19 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0125] As an example, the orthographic projection of the second plastic sealing layer 19 on the upper surface of the first plastic sealing layer 15 is located within the upper surface of the first plastic sealing layer 15; that is, the edges of the orthographic projection of the second plastic sealing layer 19 on the upper surface of the first plastic sealing layer 15 are all located within the upper surface of the first plastic sealing layer 15, and are spaced apart from the edges of the upper surface of the first plastic sealing layer 15; that is, the dimensions of the cross-section of the second plastic sealing layer 19 (that is, the cross-section parallel to the upper surface of the substrate 10) in all directions are smaller than the dimensions of the upper surface of the first plastic sealing layer 15 in the corresponding directions; that is, the area of ​​the orthographic projection of the second plastic sealing layer 19 on the upper surface of the first plastic sealing layer 15 is smaller than the area of ​​the upper surface of the first plastic sealing layer 15.

[0126] As an example, Fig.12 As shown, after step 5), the following steps are also included: forming a second interlayer dielectric layer 20 and a second rewiring metal layer 21 on the upper surface of the second plastic encapsulation layer 19, the second rewiring metal layer 21 is located in the second interlayer dielectric layer 20, and the second rewiring metal layer 21 is electrically connected to the second electrical connection structure 18. The second interlayer dielectric layer 20 can enhance the bonding force between the second plastic encapsulation layer 19 and the subsequently formed third plastic encapsulation layer 23. At the same time, the second rewiring metal layer 21 in the second interlayer dielectric layer 20 can realize rewiring, and the position and number of the subsequently formed third electrical connection structure 22 can be adjusted as needed.

[0127] As an example, the material of the second interlayer dielectric layer 20 may include a low-k dielectric material. As an example, the second interlayer dielectric layer 20 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass, and the second interlayer dielectric layer 20 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0128] As an example, the material of the second rewiring metal layer 21 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0129] In step 6), refer to Figure 1 Step S6 in Figure 13 to Figure 14 , a third electrical connection structure 22 and a third plastic sealing layer 23 are formed on the upper surface of the second plastic sealing layer 19 ; the third electrical connection structure 22 is located in the third plastic sealing layer 23 , and the third electrical connection structure 22 is electrically connected to the second electrical connection structure 18 .

[0130] It should be noted that when the second interlayer dielectric layer 20 and the second re-wiring metal layer 21 are formed on the upper surface of the second plastic encapsulation layer 19, the third plastic encapsulation layer 23 is formed on the upper surface of the second interlayer dielectric layer 20, and the third electrical connection structure 22 is formed on the upper surface of the second re-wiring metal layer 21, and the third electrical connection structure 22 is electrically connected to the second electrical connection structure 18 via the second re-wiring metal layer 21.

[0131] As an example, the third electrical connection structure 22 may be formed by a wire bonding process or a pillar bonding process; the third electrical connection structure 22 may include a bonding wire or a conductive pillar.

[0132] As an example, the number of the third electrical connection structures 22 can be set according to actual needs. Figure 13 to Figure 14 Only four third electrical connection structures 22 are shown as an example. In actual examples, the number of the third electrical connection structures 22 is not limited thereto.

[0133] As an example, the third plastic sealing layer 23 may be formed by, but not limited to, a molding bottom filling process, an imprint molding process, a transfer molding process, a liquid sealing plastic sealing process, a vacuum lamination process or a spin coating process; preferably, in this embodiment, the third plastic sealing layer 23 is formed by a molding bottom filling process. The third plastic sealing layer 23 is formed by a molding bottom filling process, and the third plastic sealing layer 23 can smoothly and quickly fill the gap between the third electrical connection structures 22, and can effectively avoid interface stratification; and the molding bottom filling process is not limited like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.

[0134] As an example, the material of the third plastic packaging layer 23 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0135] As an example, the orthographic projection of the third plastic sealing layer 23 on the upper surface of the second plastic sealing layer 19 is located within the upper surface of the second plastic sealing layer 19; that is, the edges of the orthographic projection of the third plastic sealing layer 23 on the upper surface of the second plastic sealing layer 19 are all located within the upper surface of the second plastic sealing layer 19, and are spaced apart from the edges of the upper surface of the second plastic sealing layer 19; that is, the dimensions of the cross-section of the third plastic sealing layer 23 (that is, the cross-section parallel to the upper surface of the substrate 10) in all directions are smaller than the dimensions of the upper surface of the second plastic sealing layer 19 in the corresponding directions; that is, the area of ​​the orthographic projection of the third plastic sealing layer 23 on the upper surface of the second plastic sealing layer 19 is smaller than the area of ​​the upper surface of the second plastic sealing layer 19.

[0136] As an example, the thickness of the second plastic encapsulation layer 19 is less than the thickness of the first plastic encapsulation layer 15 and greater than the thickness of the third plastic encapsulation layer 23. Of course, in other examples, the thickness of the first plastic encapsulation layer 15, the thickness of the second plastic encapsulation layer 19 and the thickness of the third plastic encapsulation layer 23 may be the same.

[0137] In step 7), refer to Figure 1 S7 steps in Fig.15 A top metal wire layer 24 is formed on the upper surface of the third plastic encapsulation layer 23 , and the top metal wire layer 24 is electrically connected to the third electrical connection structure 22 .

[0138] As an example, the material of the top metal wire layer 24 may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more of the above.

[0139] In step 8), refer to Figure 1 S8 steps in Fig.16 , remove the substrate 10 and the sacrificial layer 11.

[0140] As an example, the sacrificial layer 11 and the substrate 10 may be removed by a grinding process, a thinning process or a tearing process; preferably, in this embodiment, the substrate 10 is removed by tearing off the sacrificial layer 11 .

[0141] In step 9), refer to Figure 1 S9 steps in Figure 17 to Figure 18 A solder bump 25 is formed below the rewiring layer 12 , and the solder bump 25 is electrically connected to the rewiring layer 12 .

[0142] As an example, in step 9), forming the solder bump 25 below the rewiring layer 12 may include the following steps:

[0143] 9-1) forming an opening 26 in the bottom dielectric layer 121 and the molding material layer 122, wherein the opening 26 exposes the seed layer 123. Fig.17 As shown;

[0144] 9-2) forming a solder bump 25 in the opening 26, wherein the solder bump 25 contacts the seed layer 123, as shown in FIG. Fig.18 shown.

[0145] As an example, the material of the solder bump 25 may include at least one of copper and tin.

[0146] Embodiment 2

[0147] Please combine Figures 2 to 17 Continue reading Fig.18 The present invention also provides a 3D chip packaging structure, the 3D chip packaging structure comprising: a rewiring layer 12; a chip 13, the chip 13 is flip-chip bonded to the upper surface of the rewiring layer 12, and the chip 13 is electrically connected to the rewiring layer 12; a first electrical connection structure 14, the first electrical connection structure 14 is located on the upper surface of the rewiring layer 12, and the first electrical connection structure 14 is electrically connected to the rewiring layer 12; a first plastic sealing layer 15, the first plastic sealing layer 15 is located on the upper surface of the rewiring layer 12, and the first plastic sealing layer 15 plastic seals the chip 13 and the first electrical connection structure 14; a second electrical connection structure 18, the second electrical connection structure 18 is located on the upper surface of the first plastic sealing layer 15, and the second point connection structure 18 is electrically connected to the first electrical connection structure 14; a second plastic sealing layer 19, The second plastic sealing layer 19 is located on the upper surface of the first plastic sealing layer 15, and the second plastic sealing layer 19 plastic seals the second electrical connection structure 18; the third electrical connection structure 22, the third electrical connection structure 22 is located on the upper surface of the second plastic sealing layer 19, and the third electrical connection structure 22 is electrically connected to the second electrical connection structure 18; the third plastic sealing layer 23, the third plastic sealing layer 23 is located on the upper surface of the second plastic sealing layer 19, and the third plastic sealing layer 23 plastic seals the third electrical connection structure 22; the top metal wire layer 24, the top metal wire layer 24 is located on the upper surface of the third plastic sealing layer 23, and the top metal wire layer 24 is electrically connected to the third electrical connection structure 22; the solder ball bump 25, the solder ball bump 25 is located on the lower surface of the rewiring layer 12, and the solder ball bump 25 is electrically connected to the rewiring layer 12.

[0148] As an example, the rewiring layer 12 may include: a wiring dielectric layer 124; a metal stack structure 125, wherein the metal stack structure 125 is located within the wiring dielectric layer 124, and the metal stack structure 125 includes multiple layers of spaced-apart metal wire layers (not shown) and metal plugs (not shown), wherein the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

[0149] As an example, the rewiring layer 12 may also include: a seed layer 123, the seed layer 123 is located on the lower surface of the wiring dielectric layer 124, and the seed layer 123 is electrically connected to the metal stack structure 125; a molding material layer 122, the molding material layer 122 is located on the lower surface of the seed layer 123; the wiring dielectric layer 124 covers the molding material layer 122 and the seed layer 123 bottom dielectric layer 121, and the bottom dielectric layer 121 is located on the lower surface of the wiring dielectric layer 124.

[0150] As an example, the material of the bottom dielectric layer 121 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass; the bottom dielectric layer 121 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0151] As an example, the material of the molding material layer 122 may include but is not limited to polyimide, silicone or epoxy resin, etc.

[0152] As an example, the seed layer 123 may be formed by, but is not limited to, a sputtering process; the material of the seed layer 123 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 123 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.

[0153] As an example, the material of the wiring dielectric layer 124 may include a low-k dielectric material. As an example, the wiring dielectric layer 124 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0154] As an example, the metal line layer may include a single metal layer, or may include two or more metal layers. As an example, the material of the metal line layer and the material of the metal plug may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0155] As an example, the chip 13 may be any functional chip, a device structure (not shown) may be formed inside the chip 13, a connection pad (not shown) may be formed on the front side of the chip 13, and the connection pad is electrically connected to the device structure.

[0156] As an example, the first electrical connection structure 14 may include a bonding wire or a conductive column.

[0157] As an example, the number of the electrical connection structures 14 can be set according to actual needs. Fig.18 Only four first electrical connection structures 14 are shown as an example. In actual examples, the number of the first electrical connection structures 14 is not limited thereto.

[0158] As an example, the material of the first plastic packaging layer 15 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0159] As an example, the upper surface of the first plastic packaging layer 15 is flush with the top of the first electrical connection structure 14 .

[0160] As an example, the second electrical connection structure 18 may include a bonding wire or a conductive pillar.

[0161] As an example, the number of the second electrical connection structures 18 can be set according to actual needs. Fig.18 Only four second electrical connection structures 18 are shown as an example. In actual examples, the number of the second electrical connection structures 18 is not limited thereto.

[0162] As an example, the material of the second plastic packaging layer 19 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0163] As an example, the upper surface of the second plastic packaging layer 19 is flush with the upper surface of the second electrical connection structure 18 .

[0164] As an example, the orthographic projection of the second plastic sealing layer 19 on the upper surface of the first plastic sealing layer 15 is located within the upper surface of the first plastic sealing layer 15; that is, the edges of the orthographic projection of the second plastic sealing layer 19 on the upper surface of the first plastic sealing layer 15 are all located within the upper surface of the first plastic sealing layer 15, and are spaced apart from the edges of the upper surface of the first plastic sealing layer 15; that is, the dimensions of the cross-section of the second plastic sealing layer 19 (that is, the cross-section parallel to the upper surface of the substrate 10) in all directions are smaller than the dimensions of the upper surface of the first plastic sealing layer 15 in the corresponding directions; that is, the area of ​​the orthographic projection of the second plastic sealing layer 19 on the upper surface of the first plastic sealing layer 15 is smaller than the area of ​​the upper surface of the first plastic sealing layer 15.

[0165] As an example, the third electrical connection structure 22 may include a bonding wire or a conductive column.

[0166] As an example, the number of the third electrical connection structures 22 can be set according to actual needs. Fig.18 Only four third electrical connection structures 22 are shown as an example. In actual examples, the number of the third electrical connection structures 22 is not limited thereto.

[0167] As an example, as an example, the material of the third plastic packaging layer 23 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0168] As an example, the upper surface of the third plastic packaging layer 23 is flush with the top of the third electrical connection structure 22 .

[0169] As an example, the orthographic projection of the third plastic sealing layer 23 on the upper surface of the second plastic sealing layer 19 is located within the upper surface of the second plastic sealing layer 19; that is, the edges of the orthographic projection of the third plastic sealing layer 23 on the upper surface of the second plastic sealing layer 19 are all located within the upper surface of the second plastic sealing layer 19, and are spaced apart from the edges of the upper surface of the second plastic sealing layer 19; that is, the dimensions of the cross-section of the third plastic sealing layer 23 (that is, the cross-section parallel to the upper surface of the substrate 10) in all directions are smaller than the dimensions of the upper surface of the second plastic sealing layer 19 in the corresponding directions; that is, the area of ​​the orthographic projection of the third plastic sealing layer 23 on the upper surface of the second plastic sealing layer 19 is smaller than the area of ​​the upper surface of the second plastic sealing layer 19.

[0170] As an example, the thickness of the second plastic encapsulation layer 19 is less than the thickness of the first plastic encapsulation layer 15 and greater than the thickness of the third plastic encapsulation layer 23. Of course, in other examples, the thickness of the first plastic encapsulation layer 15, the thickness of the second plastic encapsulation layer 19 and the thickness of the third plastic encapsulation layer 23 may be the same.

[0171] As an example, the material of the top metal wire layer 24 may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more of the above.

[0172] As an example, the solder bump 25 is in contact with the seed layer 123 .

[0173] As an example, the material of the solder bump 25 may include at least one of copper and tin.

[0174] As an example, the 3D chip packaging structure also includes: a first interlayer dielectric layer 16, the first interlayer dielectric layer 16 is located between the first plastic encapsulation layer 15 and the second plastic encapsulation layer 19; a first rewiring metal layer 17, the first rewiring metal layer 17 is located in the first interlayer dielectric layer 16, and the first rewiring metal layer 17 is electrically connected to the first electrical connection structure 14 and the second electrical connection structure 18; a second interlayer dielectric layer 20, the second interlayer dielectric layer 20 is located between the second plastic encapsulation layer 19 and the third plastic encapsulation layer 23; a second rewiring metal layer 21, the second rewiring metal layer 21 is located in the second interlayer dielectric layer 20, and the second rewiring metal layer 21 is electrically connected to the second electrical connection structure 18 and the third electrical connection structure 22.

[0175] As an example, the material of the first interlayer dielectric layer 16 may include a low-k dielectric material. As an example, the first interlayer dielectric layer 16 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0176] As an example, the material of the first rewiring metal layer 17 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0177] As an example, the material of the second interlayer dielectric layer 20 may include a low-k dielectric material.

[0178] As an example, the second interlayer dielectric layer 20 can be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and can be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0179] As an example, the material of the second rewiring metal layer 21 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0180] In summary, the present invention provides a 3D chip packaging structure and a preparation method thereof, wherein the 3D chip packaging structure comprises: a rewiring layer; a chip flip-chip bonded to the upper surface of the rewiring layer and electrically connected to the rewiring layer; a first electrical connection structure located on the upper surface of the rewiring layer and electrically connected to the rewiring layer; a first plastic sealing layer located on the upper surface of the rewiring layer and plastic sealing the chip and the first electrical connection structure; a second electrical connection structure located on the upper surface of the first plastic sealing layer and electrically connected to the first electrical connection structure; a second plastic sealing layer located on the upper surface of the first plastic sealing layer and plastic sealing the second electrical connection structure; a third electrical connection structure located on the upper surface of the second plastic sealing layer and electrically connected to the second electrical connection structure; a third plastic sealing layer located on the upper surface of the second plastic sealing layer and plastic sealing the third electrical connection structure; a top metal wire layer located on the upper surface of the third plastic sealing layer and electrically connected to the third electrical connection structure; a solder ball bump located on the lower surface of the rewiring layer and electrically connected to the rewiring layer. In the 3D chip packaging structure of the present invention, the chip realizes 3D packaging, has low cost and high packaging integration, and can meet the needs of the miniaturization development trend.

[0181] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A 3D chip packaging structure, characterized in that: The 3D chip packaging structure comprises: Rewiring layers; A chip is flip-chip bonded to the upper surface of the rewiring layer and electrically connected to the rewiring layer; A first electrical connection structure is located on the upper surface of the rewiring layer and is electrically connected to the rewiring layer; A first plastic sealing layer is located on the upper surface of the rewiring layer and plastic seals the chip and the first electrical connection structure; a second electrical connection structure, located on the upper surface of the first plastic packaging layer and electrically connected to the first electrical connection structure; a second plastic sealing layer, located on the upper surface of the first plastic sealing layer, and sealing the second electrical connection structure; the edges of the orthographic projection of the second plastic sealing layer on the upper surface of the first plastic sealing layer are all located within the upper surface of the first plastic sealing layer, and are spaced apart from the edges of the upper surface of the first plastic sealing layer; a third electrical connection structure, located on the upper surface of the second plastic packaging layer and electrically connected to the second electrical connection structure; a third plastic sealing layer, located on the upper surface of the second plastic sealing layer, and sealing the third electrical connection structure; the edges of the orthographic projection of the third plastic sealing layer on the upper surface of the second plastic sealing layer are all located within the upper surface of the second plastic sealing layer, and are spaced apart from the edges of the upper surface of the second plastic sealing layer; A top metal wire layer, located on an upper surface of the third plastic encapsulation layer and electrically connected to the third electrical connection structure; The solder ball bump is located on the lower surface of the rewiring layer and is electrically connected to the rewiring layer.

2. The 3D chip packaging structure according to claim 1, characterized in that: The rewiring layer comprises: Wiring dielectric layer; The metal stacked structure is located in the wiring dielectric layer. The metal stacked structure includes multiple layers of metal wire layers and metal plugs arranged at intervals. The metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

3. The 3D chip packaging structure according to claim 2, characterized in that: The rewiring layer further comprises: A seed layer, located on the lower surface of the wiring dielectric layer and electrically connected to the metal stack structure; A plastic packaging material layer is located on the lower surface of the seed layer; the wiring dielectric layer covers the seed layer and the plastic packaging material layer; The bottom dielectric layer is located on the lower surface of the wiring dielectric layer.

4. The 3D chip packaging structure according to claim 1, characterized in that: The first electrical connection structure, the second electrical connection structure and the third electrical connection structure all include welding wires or conductive pillars.

5. The 3D chip packaging structure according to claim 1, characterized in that: The 3D chip packaging structure further includes: A first interlayer dielectric layer, located between the first plastic encapsulation layer and the second plastic encapsulation layer; a first redistribution metal layer, located in the first interlayer dielectric layer and electrically connected to the first electrical connection structure and the second electrical connection structure; A second interlayer dielectric layer, located between the second plastic encapsulation layer and the third plastic encapsulation layer; The second redistribution metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure and the third electrical connection structure.

6. The 3D chip packaging structure according to claim 1, characterized in that: The thickness of the second plastic encapsulation layer is smaller than the thickness of the first plastic encapsulation layer and larger than the thickness of the third plastic encapsulation layer.

7. A method for preparing a 3D chip packaging structure, characterized in that: The preparation method of the 3D chip packaging structure comprises the following steps: Providing a substrate, and forming a sacrificial layer on an upper surface of the substrate; forming a rewiring layer on the upper surface of the sacrificial layer; Providing a chip, and flip-chip bonding the chip to the upper surface of the rewiring layer, so that the chip and the rewiring layer are electrically connected; A first electrical connection structure and a first plastic packaging layer are formed on the upper surface of the rewiring layer; the first electrical connection structure is located in the first plastic packaging layer, and the first electrical connection structure is electrically connected to the rewiring layer; The first plastic sealing layer plastic seals the chip and the first electrical connection structure; A second electrical connection structure and a second plastic sealing layer are formed on the upper surface of the first plastic sealing layer; the second electrical connection structure is located in the second plastic sealing layer and is electrically connected to the first electrical connection structure; the edges of the orthographic projection of the second plastic sealing layer on the upper surface of the first plastic sealing layer are all located in the upper surface of the first plastic sealing layer and are spaced apart from the edges of the upper surface of the first plastic sealing layer; A third electrical connection structure and a third plastic sealing layer are formed on the upper surface of the second plastic sealing layer; the third electrical connection structure is located in the third plastic sealing layer and is electrically connected to the second electrical connection structure; the edges of the orthographic projection of the third plastic sealing layer on the upper surface of the second plastic sealing layer are all located in the upper surface of the second plastic sealing layer and are spaced apart from the edges of the upper surface of the second plastic sealing layer; forming a top metal wire layer on the upper surface of the third plastic encapsulation layer, wherein the top metal wire layer is electrically connected to the third electrical connection structure; removing the substrate and the sacrificial layer; A solder ball bump is formed below the rewiring layer, and the solder ball bump is electrically connected to the rewiring layer.

8. The method for preparing the 3D chip packaging structure according to claim 7, characterized in that: Forming the rewiring layer on the upper surface of the sacrificial layer comprises the following steps: forming a bottom dielectric layer on the upper surface of the sacrificial layer; forming a plastic packaging material layer on the upper surface of the bottom dielectric layer; forming a seed layer on the upper surface of the plastic packaging material layer; Performing a patterning process on the seed layer and the plastic encapsulation material layer; A wiring dielectric layer and a metal stack structure are formed on the upper surface of the bottom dielectric layer. The metal stack structure is located in the wiring dielectric layer and is electrically connected to the seed layer. The metal stack structure includes multiple layers of spaced metal wire layers and metal plugs. The metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

9. The method for preparing a 3D chip packaging structure according to claim 7, characterized in that: Before forming the second electrical connection structure and the second plastic encapsulation layer on the upper surface of the first plastic encapsulation layer, the method further includes forming a first interlayer dielectric layer and a first rewiring metal layer on the upper surface of the first plastic encapsulation layer, wherein the first rewiring metal layer is located in the first interlayer dielectric layer and is electrically connected to the first electrical connection structure; The second plastic encapsulation layer is formed on the upper surface of the first interlayer dielectric layer, and the second electrical connection structure is formed on the upper surface of the first rewiring metal layer; Before forming the third electrical connection structure and the third plastic encapsulation layer on the upper surface of the second plastic encapsulation layer, the step also includes forming a second interlayer dielectric layer and a second re-wiring metal layer on the upper surface of the second plastic encapsulation layer, the second re-wiring metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure; the third plastic encapsulation layer is formed on the upper surface of the second interlayer dielectric layer, and the third electrical connection structure is formed on the upper surface of the second re-wiring metal layer.

10. The method for preparing a 3D chip packaging structure according to claim 9, characterized in that: The thickness of the second plastic encapsulation layer is smaller than the thickness of the first plastic encapsulation layer and larger than the thickness of the third plastic encapsulation layer.

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