3D chip packaging structure and preparation method thereof

Abstract

The present invention provides a 3D chip packaging structure and a preparation method thereof, wherein the 3D chip packaging structure comprises: a rewiring layer; a first electrical connection structure, located on a first surface of the rewiring layer; a first plastic encapsulation layer, located on a first surface of the rewiring layer; a second electrical connection structure, located on a surface of the first plastic encapsulation layer away from the rewiring layer; a second plastic encapsulation layer, located on a surface of the first plastic encapsulation layer away from the rewiring layer; a chip, flip-chip bonded to a second surface of the rewiring layer; a third electrical connection structure, located on a second surface of the rewiring layer; a third plastic encapsulation layer, located on a second surface of the rewiring layer; an orthographic projection of the third plastic encapsulation layer on a surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer; a metal lead layer, located on a surface of the third plastic encapsulation layer away from the rewiring layer; and a solder ball bump, located on a surface of the metal lead layer away from the third plastic encapsulation layer. The 3D chip packaging structure of the present invention can effectively increase the effective area of ​​a chip in the 3D chip packaging structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a 3D chip packaging structure and a preparation method thereof. Background Art

[0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size. At present, advanced packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip (FlipChip), Package on Package (POP), etc.

[0003] However, the existing packaging methods and packaging structures obtained by the above packaging methods have the problems of high cost, low integration, and failure to meet the needs of the development trend of miniaturization. In addition, in the existing packaging methods and packaging structures obtained by the above packaging methods, the effective area of ​​the chip in the packaging structure is small due to the large size of the plastic sealing layer of the plastic-sealed chip. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a 3D chip packaging structure and a preparation method thereof, so as to solve the problems of high cost, insufficient integration, and inability to meet the needs of the development trend of miniaturization in the packaging methods and packaging structures in the prior art, as well as the problem of small effective area of ​​the chip in the packaging structure due to the large size of the plastic layer of the plastic-encapsulated chip.

[0005] To achieve the above objectives and other related objectives, the present invention provides a 3D chip packaging structure, the 3D chip packaging structure comprising:

[0006] A rewiring layer including a first surface and a second surface opposite to each other;

[0007] A first electrical connection structure is located on a first surface of the rewiring layer and is electrically connected to the rewiring layer;

[0008] A first plastic sealing layer is located on a first surface of the rewiring layer and plastic seals the first electrical connection structure;

[0009] A second electrical connection structure is located on a surface of the first plastic packaging layer away from the rewiring layer and is electrically connected to the first electrical connection structure;

[0010] A second plastic encapsulation layer is located on a surface of the first plastic encapsulation layer away from the rewiring layer and plastic encapsulates the second electrical connection structure;

[0011] A chip is flip-chip bonded to the second surface of the rewiring layer and electrically connected to the rewiring layer;

[0012] a third electrical connection structure, located on the second surface of the rewiring layer and electrically connected to the rewiring layer;

[0013] A third plastic encapsulation layer is located on the second surface of the rewiring layer and encapsulates the third electrical connection structure and the chip; the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer;

[0014] A metal lead layer, located on a surface of the third plastic packaging layer away from the rewiring layer and electrically connected to the third electrical connection structure;

[0015] The solder ball bump is located on the surface of the metal lead layer away from the third plastic packaging layer.

[0016] Optionally, the rewiring layer comprises:

[0017] Wiring dielectric layer;

[0018] The metal stacked structure is located in the wiring dielectric layer. The metal stacked structure includes multiple layers of metal wire layers and metal plugs arranged at intervals. The metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

[0019] Optionally, the first electrical connection structure, the second electrical connection structure and the third electrical connection structure all include welding wires or conductive columns.

[0020] Optionally, the 3D chip packaging structure further includes:

[0021] A first interlayer dielectric layer, located between the first plastic encapsulation layer and the second plastic encapsulation layer;

[0022] a first redistribution metal layer, located in the first interlayer dielectric layer and electrically connected to the first electrical connection structure and the second electrical connection structure;

[0023] A second interlayer dielectric layer is located on a surface of the second plastic encapsulation layer away from the first plastic encapsulation layer;

[0024] The second redistribution metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure.

[0025] Optionally, an orthographic projection of the second plastic sealing layer on the surface of the first plastic sealing layer is located within the surface of the first plastic sealing layer.

[0026] Optionally, the orthographic projections of the third plastic sealing layer and the second plastic sealing layer on the same surface of the first plastic sealing layer overlap.

[0027] Optionally, the thickness of the third plastic sealing layer is the same as the thickness of the second plastic sealing layer, and the thickness of the third plastic sealing layer and the thickness of the second plastic sealing layer are both smaller than the thickness of the first plastic sealing layer.

[0028] To achieve the above-mentioned object and other related objects, the present invention further provides a method for preparing a 3D chip packaging structure, the method for preparing the 3D chip packaging structure comprising the following steps:

[0029] Providing a substrate, and forming a sacrificial layer on a surface of the substrate;

[0030] forming a rewiring layer on a surface of the sacrificial layer away from the substrate;

[0031] A first electrical connection structure and a first plastic packaging layer are formed on a surface of the rewiring layer away from the sacrificial layer; the first electrical connection structure is located in the first plastic packaging layer, and the first electrical connection structure is electrically connected to the rewiring layer;

[0032] A second electrical connection structure and a second plastic encapsulation layer are formed on a surface of the first plastic encapsulation layer away from the rewiring layer; the second electrical connection structure is located in the second plastic encapsulation layer and is electrically connected to the first electrical connection structure;

[0033] removing the substrate and the sacrificial layer;

[0034] Providing a chip, bonding the chip to a surface of the rewiring layer away from the first plastic packaging layer, wherein the chip is electrically connected to the rewiring layer;

[0035] A third electrical connection structure and a third plastic encapsulation layer are formed on a surface of the rewiring layer away from the first plastic encapsulation layer; the third electrical connection structure is located in the third plastic encapsulation layer and is electrically connected to the rewiring layer; the third plastic encapsulation layer encapsulates the chip and the third electrical connection structure; the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer;

[0036] forming a metal lead layer on a surface of the third plastic encapsulation layer away from the rewiring layer, wherein the metal lead layer is electrically connected to the third electrical connection structure;

[0037] A solder ball bump is formed on a surface of the metal lead layer away from the third plastic packaging layer, and the solder bump is electrically connected to the metal lead layer.

[0038] Optionally, forming the rewiring layer on the upper surface of the sacrificial layer comprises the following steps:

[0039] forming a bottom dielectric layer on a surface of the sacrificial layer away from the substrate;

[0040] forming a plastic packaging material layer on a surface of the bottom dielectric layer away from the sacrificial layer;

[0041] forming a seed layer on a surface of the plastic encapsulation material layer away from the bottom dielectric layer;

[0042] Performing a patterning process on the seed layer and the plastic encapsulation material layer;

[0043] A wiring dielectric layer and a metal stack structure are formed on the surface of the bottom dielectric layer away from the substrate, wherein the metal stack structure is located in the wiring dielectric layer and is electrically connected to the seed layer; the metal stack structure includes multiple layers of metal wire layers and metal plugs arranged at intervals, wherein the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers;

[0044] After removing the substrate and the sacrificial layer and before bonding the chip to the surface of the rewiring layer away from the first molding layer, the method further includes removing the bottom dielectric layer and the molding material layer.

[0045] Optionally, before forming the second electrical connection structure and the second plastic encapsulation layer on the surface of the first plastic encapsulation layer away from the rewiring layer, the method further includes forming a first interlayer dielectric layer and a first rewiring metal layer on the surface of the first plastic encapsulation layer away from the rewiring layer, wherein the first rewiring metal layer is located in the first interlayer dielectric layer and is electrically connected to the first electrical connection structure; the second plastic encapsulation layer is formed on the surface of the first interlayer dielectric layer away from the first plastic encapsulation layer, and the second electrical connection structure is formed on the upper surface of the first rewiring metal layer;

[0046] Before removing the substrate and the sacrificial layer, the method also includes forming a second interlayer dielectric layer and a second rewiring metal layer on the surface of the second plastic encapsulation layer away from the first plastic encapsulation layer. The second rewiring metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure.

[0047] Optionally, an orthographic projection of the second plastic sealing layer on the surface of the first plastic sealing layer is located within the surface of the first plastic sealing layer.

[0048] Optionally, the orthographic projections of the third plastic sealing layer and the second plastic sealing layer on the same surface of the first plastic sealing layer overlap.

[0049] Optionally, the thickness of the third plastic sealing layer is the same as the thickness of the second plastic sealing layer, and the thickness of the third plastic sealing layer and the thickness of the second plastic sealing layer are both smaller than the thickness of the first plastic sealing layer.

[0050] As described above, the 3D chip packaging structure and the preparation method thereof of the present invention have the following beneficial effects:

[0051] In the 3D chip packaging structure of the present invention, the chip realizes 3D packaging, which has low cost and high packaging integration, and can meet the needs of the development trend of miniaturization;

[0052] In the 3D chip packaging structure of the present invention, the orthographic projection of the third plastic packaging layer used for plastic-sealing the chip on the surface of the first plastic packaging layer is located within the surface of the first plastic packaging layer. The size of the third plastic packaging layer used for plastic-sealing the chip is relatively small, which can effectively increase the effective area of ​​the chip in the 3D chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 Shown is a flow chart of a method for preparing a 3D chip packaging structure provided in Embodiment 1 of the present invention.

[0054] Figures 2 to 16 It is a schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing the 3D chip packaging structure provided in the first embodiment of the present invention; wherein: Fig.16 Shown is a schematic cross-sectional structure diagram of a 3D chip packaging structure provided in the second embodiment of the present invention.

[0055] Component number description

[0056] 10 Base

[0057] 11 Sacrificial Layer

[0058] 12 Rewiring Layers

[0059] 121 bottom dielectric layer

[0060] 122 plastic material layer

[0061] 123 seed layer

[0062] 124 Wiring Dielectric Layer

[0063] 125 Metal laminate structure

[0064] 13. First electrical connection structure

[0065] 14 First plastic layer

[0066] 15. First interlayer dielectric layer

[0067] 16 First redistribution metal layer

[0068] 17. Second electrical connection structure

[0069] 18 Second plastic layer

[0070] 19 Second interlayer dielectric layer

[0071] 20 Second redistribution metal layer

[0072] 21 Chip

[0073] 22. Third electrical connection structure

[0074] 23 The third plastic sealing layer

[0075] 24 Metal lead layer

[0076] 25 solder ball bumps DETAILED DESCRIPTION

[0077] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] See also Figures 1 to 16 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0079] Embodiment 1

[0080] See also Figure 1 The present invention provides a method for preparing a 3D chip packaging structure, and the method for preparing the 3D chip packaging structure comprises the following steps:

[0081] 1) providing a substrate, and forming a sacrificial layer on a surface of the substrate;

[0082] 2) forming a rewiring layer on a surface of the sacrificial layer away from the substrate;

[0083] 3) forming a first electrical connection structure and a first plastic packaging layer on a surface of the rewiring layer away from the sacrificial layer; the first electrical connection structure is located in the first plastic packaging layer, and the first electrical connection structure is electrically connected to the rewiring layer;

[0084] 4) forming a second electrical connection structure and a second plastic encapsulation layer on a surface of the first plastic encapsulation layer away from the rewiring layer; the second electrical connection structure is located in the second plastic encapsulation layer and is electrically connected to the first electrical connection structure;

[0085] 5) removing the substrate and the sacrificial layer;

[0086] 6) providing a chip, bonding the chip to a surface of the rewiring layer away from the first plastic packaging layer, wherein the chip is electrically connected to the rewiring layer;

[0087] 7) forming a third electrical connection structure and a third plastic encapsulation layer on a surface of the rewiring layer away from the first plastic encapsulation layer; the third electrical connection structure is located in the third plastic encapsulation layer and is electrically connected to the rewiring layer; the third plastic encapsulation layer encapsulates the chip and the third electrical connection structure; the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer;

[0088] 8) forming a metal lead layer on a surface of the third plastic encapsulation layer away from the rewiring layer, wherein the metal lead layer is electrically connected to the third electrical connection structure;

[0089] 9) forming solder bumps on a surface of the metal lead layer away from the third plastic packaging layer, wherein the solder bumps are electrically connected to the metal lead layer.

[0090] In step 1), refer to Figure 1 The S1 step in Figure 2 , providing a substrate 10 , and forming a sacrificial layer 11 on a surface of the substrate 10 .

[0091] As an example, the material of the substrate 10 can be one material selected from silicon, glass, silicon oxide, ceramic, polymer and metal, or a composite material of two or more thereof, and its shape can be circular, square or any other desired shape. Preferably, in this embodiment, the material of the substrate 10 is silicon.

[0092] As an example, the sacrificial layer 11 serves as a separation layer between the rewiring layer and the substrate 10 in the subsequent process. It is best to be made of an adhesive material with a smooth surface. It must have a certain bonding force with the rewiring layer. In addition, it also has a strong bonding force with the substrate 10. Generally speaking, the bonding force between the sacrificial layer 11 and the substrate 10 needs to be greater than the bonding force with the rewiring layer.

[0093] As an example, the sacrificial layer 11 may include a polymer layer or a tape-shaped adhesion layer; specifically, the material of the sacrificial layer 11 may be selected from a tape with sticky surfaces on both sides (for example, a chip attachment film or a non-conductive film, etc.) or an adhesive made by a spin coating process, etc.; preferably, in this embodiment, the sacrificial layer 11 is preferably a UV tape, which can be easily torn off after being irradiated with UV light (ultraviolet light); of course, in other examples, the sacrificial layer 11 may also be made of other material layers formed by physical vapor deposition or chemical vapor deposition, such as epoxy resin (Epoxy), silicone rubber (Silicone rubber), polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), etc. When the substrate 10 is subsequently separated, the sacrificial layer 11 may be removed by wet etching, chemical mechanical grinding, etc.

[0094] As an example, the sacrificial layer 11 may also be formed by an automatic bonding process.

[0095] In step 2), refer to Figure 1 The S2 step in Figures 3 to 5 A rewiring layer 12 is formed on a surface of the sacrificial layer 11 away from the substrate 10 .

[0096] As an example, in step 2), forming the rewiring layer 12 on the surface of the sacrificial layer 11 away from the substrate 10 may include the following steps:

[0097] 2-1) forming a bottom dielectric layer 121 on the surface of the sacrificial layer 11 away from the substrate 10, such as Figure 3 As shown;

[0098] 2-2) forming a plastic encapsulation material layer 122 on a surface of the bottom dielectric layer 121 away from the sacrificial layer 121, such as Figure 3 As shown;

[0099] 2-3) forming a seed layer 123 on the surface of the molding material layer 122 away from the bottom dielectric layer 121, such as Figure 3 As shown;

[0100] 2-4) The seed layer 123 and the plastic encapsulation material layer 122 are subjected to a graphic treatment, such as Figure 4 As shown;

[0101] 2-5) forming a wiring dielectric layer 124 and a metal stack structure 125 on the surface of the bottom dielectric layer 121 away from the substrate 10, wherein the metal stack structure 125 is located in the wiring dielectric layer 124 and is electrically connected to the seed layer 123, as shown in FIG. Figure 5As shown; the metal stack structure 125 includes multiple layers of spaced metal wire layers (not shown) and metal plugs (not shown), wherein the metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

[0102] As an example, the material of the bottom dielectric layer 121 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass; the bottom dielectric layer 121 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0103] As an example, the material of the molding material layer 122 may include but is not limited to polyimide, silicone or epoxy resin, etc.

[0104] As an example, the seed layer 123 may be formed by, but is not limited to, a sputtering process; the material of the seed layer 123 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 123 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.

[0105] As an example, the material of the wiring dielectric layer 124 may include a low-k dielectric material. As an example, the wiring dielectric layer 124 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0106] As an example, the metal line layer may include a single metal layer, or may include two or more metal layers. As an example, the material of the metal line layer and the material of the metal plug may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0107] In step 3), refer to Figure 1 The S3 steps in Figures 6 to 8 A first electrical connection structure 13 and a first plastic encapsulation layer 14 are formed on the surface of the rewiring layer 12 away from the sacrificial layer 11 ; the first electrical connection structure 13 is located in the first plastic encapsulation layer 14 , and the first electrical connection structure 13 is electrically connected to the rewiring layer 12 .

[0108] As an example, a wire bonding process or a pillar bonding process may be used to form the first electrical connection structure 13 on the surface of the rewiring layer 12 away from the sacrificial layer 11; the first electrical connection structure 13 may include a welding wire or a conductive pillar.

[0109] As an example, the number of the first electrical connection structures 13 can be set according to actual needs. Figures 6 to 8 Only four first electrical connection structures 13 are shown as an example. In actual examples, the number of the first electrical connection structures 13 is not limited thereto.

[0110] As an example, a molding bottom filling process, an imprint molding process, a transfer molding process, a liquid sealing plastic sealing process, a vacuum lamination process or a spin coating process may be used, but is not limited to, to form the first plastic sealing layer 14 on the surface of the rewiring layer 12 away from the sacrificial layer 11; preferably, in this embodiment, a molding bottom filling process is used to form the first plastic sealing layer 14 on the surface of the rewiring layer 12 away from the sacrificial layer 11. The molding bottom filling process is used to form the first plastic sealing layer 14, and the first plastic sealing layer 14 can smoothly and quickly fill the gap between the first electrical connection structures 13, which can effectively avoid interface stratification; and the molding bottom filling process is not limited like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.

[0111] As an example, the material of the first plastic packaging layer 14 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0112] As an example, the surface of the initially formed first plastic encapsulation layer 14 away from the sacrificial layer 11 may be higher than the surface of the first electrical connection structure 13 away from the sacrificial layer 11. Figure 7 As shown, at this time, after the first plastic encapsulation layer 15 is formed, a process of thinning the first plastic encapsulation layer 15 is required. Specifically, the first plastic encapsulation layer 15 can be thinned by, but not limited to, a chemical mechanical polishing process, so that the surface of the retained first plastic encapsulation layer 15 away from the sacrificial layer 11 is flush with the surface of the first electrical connection structure 13 away from the sacrificial layer 11, as shown in FIG. Figure 8 Of course, in other examples, the surface of the initially formed first plastic encapsulation layer 15 away from the sacrificial layer 11 is flush with the surface of the first electrical connection structure 13 away from the sacrificial layer 11, such as Figure 8 As shown, at this time, the process of thinning the first plastic sealing layer 15 can be saved.

[0113] As an example, Fig. 9As shown, after step 3), the following steps are also included: forming a first interlayer dielectric layer 15 and a first rewiring metal layer 16 on the surface of the first plastic encapsulation layer 15 away from the rewiring layer 12, the first rewiring metal layer 16 is located in the first interlayer dielectric layer 15, and the first rewiring metal layer 16 is electrically connected to the first electrical connection structure 13. The first interlayer dielectric layer 15 can enhance the bonding force between the first plastic encapsulation layer 14 and the second plastic encapsulation layer 18 formed subsequently, and at the same time, the first rewiring metal layer 16 in the first interlayer dielectric layer 15 can realize rewiring, and the position and number of the second electrical connection structure 17 formed subsequently can be adjusted as needed.

[0114] As an example, the material of the first interlayer dielectric layer 15 may include a low-k dielectric material. As an example, the first interlayer dielectric layer 15 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0115] As an example, the material of the first rewiring metal layer 16 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0116] In step 4), refer to Figure 1 Step S4 in Figure 10 to Figure 11 A second electrical connection structure 17 and a second plastic layer 18 are formed on the surface of the first plastic layer 14 away from the rewiring layer 12; the second electrical connection structure 17 is located in the second plastic layer 18, and the second electrical connection structure 17 is electrically connected to the first electrical connection structure 13.

[0117] It should be noted that when the first interlayer dielectric layer 15 and the first rewiring metal layer 16 are formed on the surface of the first plastic encapsulation layer 14 away from the rewiring layer 12, the second plastic encapsulation layer 18 is formed on the surface of the first interlayer dielectric layer 15 away from the first plastic encapsulation layer 14, and the second electrical connection structure 17 is formed on the surface of the first rewiring metal layer 16 away from the first plastic encapsulation layer 14, and the second electrical connection structure 17 is electrically connected to the first electrical connection structure 13 via the first rewiring metal layer 16.

[0118] As an example, the second electrical connection structure 17 may be formed by a wire bonding process or a pillar bonding process; the second electrical connection structure 17 may include a bonding wire or a conductive pillar.

[0119] As an example, the number of the second electrical connection structures 17 can be set according to actual needs. Figure 10 to Figure 11Only four second electrical connection structures 17 are shown as an example. In actual examples, the number of the second electrical connection structures 17 is not limited thereto.

[0120] As an example, the second plastic sealing layer 18 may be formed by, but not limited to, a molding bottom filling process, an imprint molding process, a transfer molding process, a liquid sealing plastic sealing process, a vacuum lamination process or a spin coating process; preferably, in this embodiment, a molding bottom filling process is used to form the second plastic sealing layer 18. The molding bottom filling process is used to form the second plastic sealing layer 18, and the second plastic sealing layer 18 can smoothly and quickly fill the gap between the second electrical connection structures 17, which can effectively avoid interface stratification; and the molding bottom filling process is not limited like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.

[0121] As an example, the material of the second molding layer 18 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0122] As an example, Fig.12 As shown, after step 4), the following steps are also included: forming a second interlayer dielectric layer 19 and a second rewiring metal layer 20 on the surface of the second plastic encapsulation layer 18 away from the first plastic encapsulation layer 14, the second rewiring metal layer 20 is located in the second interlayer dielectric layer 19, and the second rewiring metal layer 20 is electrically connected to the second electrical connection structure 17.

[0123] As an example, the material of the second interlayer dielectric layer 19 may include a low-k dielectric material. As an example, the second interlayer dielectric layer 19 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and the second interlayer dielectric layer 19 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0124] As an example, the material of the second rewiring metal layer 20 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0125] In step 5), refer to Figure 1 Step S5 in Fig.13 , remove the substrate 10 and the sacrificial layer 11.

[0126] As an example, the sacrificial layer 11 and the substrate 10 may be removed by a grinding process, a thinning process or a tearing process; preferably, in this embodiment, the substrate 10 is removed by tearing off the sacrificial layer 11 .

[0127] As an example, after step 5), the method further includes removing the bottom dielectric layer 121 and the molding material layer 122 to expose the seed layer 123 .

[0128] In step 6), refer to Figure 1 Step S6 in Fig.14 , providing a chip 21 , bonding the chip 21 to a surface of the rewiring layer 12 away from the first plastic packaging layer 14 , and the chip 21 is electrically connected to the rewiring layer 12 .

[0129] As an example, the chip 21 may be any functional chip, a device structure (not shown) may be formed inside the chip 21, and a connection pad (not shown) may be formed on the front side of the chip 21, and the connection pad is electrically connected to the device structure.

[0130] As an example, the chip 21 can be flip-chip bonded to the surface of the rewiring layer away from the first plastic layer 14 using any existing bonding process; the connection pads of the chip 21 are electrically connected to the metal stack structure 125 in the rewiring layer 12.

[0131] In step 7), refer to Figure 1 S7 steps in Fig.14 A third electrical connection structure 22 and a third plastic sealing layer 23 are formed on the surface of the rewiring layer 12 away from the first plastic sealing layer 14; the third electrical connection structure 22 is located in the third plastic sealing layer 23, and the third electrical connection structure 22 is electrically connected to the rewiring layer 12; the third plastic sealing layer 23 seals the chip 21 and the third electrical connection structure 22; the orthographic projection of the third plastic sealing layer 23 on the surface of the first plastic sealing layer 14 is located in the surface of the first plastic sealing layer 14.

[0132] As an example, the orthographic projection of the third plastic sealing layer 23 on the surface of the first plastic sealing layer 14 is located within the surface of the first plastic sealing layer 14, that is, the edges of the orthographic projection of the third plastic sealing layer 23 on the surface of the first plastic sealing layer 14 are all located within the upper surface of the first plastic sealing layer 14, and are spaced apart from the edges of the surface of the first plastic sealing layer 14 (for example, the surface in contact with the rewiring layer 12); that is, the dimensions of the cross-section of the third plastic sealing layer 23 (that is, the cross-section parallel to the upper surface of the substrate 10) in all directions are smaller than the dimensions of the surface of the first plastic sealing layer 14 in the corresponding directions; that is, the area of ​​the orthographic projection of the third plastic sealing layer 23 on the upper surface of the first plastic sealing layer 14 is smaller than the area of ​​the surface of the first plastic sealing layer 14. The orthographic projection of the third plastic encapsulation layer 23 for encapsulating the chip 21 on the surface of the first plastic encapsulation layer 14 is located within the surface of the first plastic encapsulation layer 14. The size of the third plastic encapsulation layer 23 for encapsulating the chip 21 is relatively small, which can effectively cover the effective area of ​​the chip 21 in the 3D chip packaging structure; that is, under the premise that the area of ​​the 3D chip packaging structure is constant, the number of the chips 21 in the 3D chip packaging structure can be increased.

[0133] As an example, the orthographic projections of the third plastic encapsulation layer 23 and the second plastic encapsulation layer 18 on the same surface of the first plastic encapsulation layer 14 may overlap, that is, the cross section of the third plastic encapsulation layer 23 and the cross section of the second plastic encapsulation layer 18 have the same size in the same direction.

[0134] As an example, the thickness of the third plastic encapsulation layer 23 is the same as the thickness of the second plastic encapsulation layer 18, and the thickness of the third plastic encapsulation layer 23 and the thickness of the second plastic encapsulation layer 18 are both less than the thickness of the first plastic encapsulation layer 14. Of course, in other examples, the thickness of the third plastic encapsulation layer 23, the thickness of the second plastic encapsulation layer 18, and the thickness of the first plastic encapsulation layer 14 may also be the same.

[0135] As an example, the third electrical connection structure 22 may be formed by a wire bonding process or a pillar bonding process; the third electrical connection structure 22 may include a bonding wire or a conductive pillar.

[0136] As an example, the number of the third electrical connection structures 22 can be set according to actual needs. Figure 13 to Figure 14 Only four third electrical connection structures 22 are shown as an example. In actual examples, the number of the third electrical connection structures 22 is not limited thereto.

[0137] As an example, the third plastic sealing layer 23 may be formed by, but not limited to, a molding bottom filling process, an imprint molding process, a transfer molding process, a liquid sealing plastic sealing process, a vacuum lamination process or a spin coating process; preferably, in this embodiment, the third plastic sealing layer 23 is formed by a molding bottom filling process. The third plastic sealing layer 23 is formed by a molding bottom filling process, and the third plastic sealing layer 23 can smoothly and quickly fill the gap between the third electrical connection structures 22, and can effectively avoid interface stratification; and the molding bottom filling process is not limited like the capillary bottom filling process in the prior art, which greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.

[0138] As an example, the material of the third plastic packaging layer 23 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0139] In step 8), refer to Figure 1 S8 steps in Fig.15 A metal lead layer 24 is formed on a surface of the third plastic encapsulation layer 23 away from the rewiring layer 12 , and the metal lead layer 24 is electrically connected to the third electrical connection structure 22 .

[0140] As an example, the material of the metal lead layer 24 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0141] In step 9), refer to Figure 1 S9 steps in Fig.16 A solder bump 25 is formed on a surface of the metal lead layer 24 away from the third plastic packaging layer 23 , and the solder bump 25 is electrically connected to the metal lead layer 24 .

[0142] As an example, the material of the solder ball bump 25 may include at least one of copper and tin. The process of forming the solder ball bump 25 is known to those skilled in the art and will not be described here.

[0143] Embodiment 2

[0144] Please combine Figures 2 to 15 Continue reading Fig.16The present invention also provides a 3D chip packaging structure, the 3D chip packaging structure comprising: a rewiring layer 12, the rewiring layer 12 comprising a first surface and a second surface relative to each other; a first electrical connection structure 13, the first electrical connection structure 13 is located on the first surface of the rewiring layer 12, and the first electrical connection structure 13 is electrically connected to the rewiring layer 12; a first plastic sealing layer 14, the first plastic sealing layer 14 is located on the first surface of the rewiring layer 12, and the first plastic sealing layer 14 plastic seals the first electrical connection structure 13; a second electrical connection structure 17, the second electrical connection structure 17 is located on the surface of the first plastic sealing layer 14 away from the rewiring layer 12, and the second electrical connection structure 17 is electrically connected to the first electrical connection structure 13; a second plastic sealing layer 18, the second plastic sealing layer 18 is located on the surface of the first plastic sealing layer 14 away from the rewiring layer 12, and the second plastic sealing layer 18 plastic seals the second electrical connection structure 17; chip 21, the chip 21 is flip-chip bonded to the second surface of the rewiring layer 12, and the chip 21 is electrically connected to the rewiring layer 12; a third electrical connection structure 22, the third electrical connection structure 22 is located on the second surface of the rewiring layer 12, and the third electrical connection structure 22 is electrically connected to the rewiring layer 12; a third plastic encapsulation layer 23, the third plastic encapsulation layer 23 is located on the second surface of the rewiring layer 12, and the third plastic encapsulation layer 23 encapsulates the third electrical connection structure 22 and the chip 21; the orthographic projection of the third plastic encapsulation layer 23 on the surface of the first plastic encapsulation layer 14 is located within the surface of the first plastic encapsulation layer 14; a metal lead layer 24, the metal lead layer 24 is located on the surface of the third plastic encapsulation layer 23 away from the rewiring layer 12, and the metal lead 24 is electrically connected to the third electrical connection structure 22; a solder ball bump 25, the solder ball bump 25 is located on the surface of the metal lead layer 24 away from the third plastic encapsulation layer 23.

[0145] As an example, the rewiring layer 12 may include: a wiring dielectric layer 124; a metal stack structure 123, wherein the metal stack structure 123 is located within the wiring dielectric layer 124, and the metal stack structure 123 includes multiple layers of spaced-apart metal wire layers (not shown) and metal plugs (not shown), wherein the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers.

[0146] As an example, the rewiring layer 12 may further include a seed layer 123 , wherein the seed layer 123 is located in the wiring dielectric layer 124 and is located on a surface of the metal stack structure 123 away from the first plastic encapsulation layer 14 .

[0147] As an example, the seed layer 123 may be formed by, but is not limited to, a sputtering process; the material of the seed layer 123 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 123 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.

[0148] As an example, the material of the wiring dielectric layer 124 may include a low-k dielectric material. As an example, the wiring dielectric layer 124 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0149] As an example, the metal line layer may include a single metal layer, or may include two or more metal layers. As an example, the material of the metal line layer and the material of the metal plug may include one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0150] As an example, the first electrical connection structure 13 may include a bonding wire or a conductive column.

[0151] As an example, the number of the first electrical connection structures 13 can be set according to actual needs. Fig.16 Only four first electrical connection structures 13 are shown as an example. In actual examples, the number of the first electrical connection structures 13 is not limited thereto.

[0152] As an example, the material of the first plastic packaging layer 14 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0153] As an example, the second electrical connection structure 17 may include a bonding wire or a conductive column.

[0154] As an example, the number of the second electrical connection structures 17 can be set according to actual needs. Fig.16 Only four second electrical connection structures 17 are shown as an example. In actual examples, the number of the second electrical connection structures 17 is not limited thereto.

[0155] As an example, the material of the second molding layer 18 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0156] As an example, the chip 21 may be any functional chip, a device structure (not shown) may be formed inside the chip 21, and a connection pad (not shown) may be formed on the front side of the chip 21, and the connection pad is electrically connected to the device structure.

[0157] As an example, the chip 21 can be flip-chip bonded to the surface of the rewiring layer away from the first plastic layer 14 using any existing bonding process; the connection pads of the chip 21 are electrically connected to the metal stack structure 125 in the rewiring layer 12.

[0158] As an example, the orthographic projection of the third plastic sealing layer 23 on the surface of the first plastic sealing layer 14 is located within the surface of the first plastic sealing layer 14, that is, the edges of the orthographic projection of the third plastic sealing layer 23 on the surface of the first plastic sealing layer 14 are all located within the upper surface of the first plastic sealing layer 14, and are spaced apart from the edges of the surface of the first plastic sealing layer 14 (for example, the surface in contact with the rewiring layer 12); that is, the dimensions of the cross-section of the third plastic sealing layer 23 (that is, the cross-section parallel to the upper surface of the substrate 10) in all directions are smaller than the dimensions of the surface of the first plastic sealing layer 14 in the corresponding directions; that is, the area of ​​the orthographic projection of the third plastic sealing layer 23 on the upper surface of the first plastic sealing layer 14 is smaller than the area of ​​the surface of the first plastic sealing layer 14. The orthographic projection of the third plastic encapsulation layer 23 for encapsulating the chip 21 on the surface of the first plastic encapsulation layer 14 is located within the surface of the first plastic encapsulation layer 14. The size of the third plastic encapsulation layer 23 for encapsulating the chip 21 is relatively small, which can effectively cover the effective area of ​​the chip 21 in the 3D chip packaging structure; that is, under the premise that the area of ​​the 3D chip packaging structure is constant, the number of the chips 21 in the 3D chip packaging structure can be increased.

[0159] As an example, the orthographic projections of the third plastic encapsulation layer 23 and the second plastic encapsulation layer 18 on the same surface of the first plastic encapsulation layer 14 may overlap, that is, the cross section of the third plastic encapsulation layer 23 and the cross section of the second plastic encapsulation layer 18 have the same size in the same direction.

[0160] As an example, the thickness of the third plastic encapsulation layer 23 is the same as the thickness of the second plastic encapsulation layer 18, and the thickness of the third plastic encapsulation layer 23 and the thickness of the second plastic encapsulation layer 18 are both less than the thickness of the first plastic encapsulation layer 14. Of course, in other examples, the thickness of the third plastic encapsulation layer 23, the thickness of the second plastic encapsulation layer 18, and the thickness of the first plastic encapsulation layer 14 may also be the same.

[0161] As an example, the third electrical connection structure 22 may include a bonding wire or a conductive column.

[0162] As an example, the number of the third electrical connection structures 22 can be set according to actual needs. Fig.16 Only four third electrical connection structures 22 are shown as an example. In actual examples, the number of the third electrical connection structures 22 is not limited thereto.

[0163] As an example, the material of the third plastic packaging layer 23 may include but is not limited to polymer-based materials, resin-based materials, polyimide, silicone or epoxy resin, etc.

[0164] As an example, the material of the metal lead layer 24 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0165] As an example, the material of the solder ball bump 25 may include at least one of copper and tin. The process of forming the solder ball bump 25 is known to those skilled in the art and will not be described here.

[0166] As an example, the 3D chip packaging structure also includes: a first interlayer dielectric layer 15, the first interlayer dielectric layer 15 is located between the first plastic encapsulation layer 14 and the second plastic encapsulation layer 18; a first rewiring metal layer 16, the second rewiring metal layer 16 is located in the first interlayer dielectric layer 15, and the second rewiring metal layer 16 is electrically connected to the first electrical connection structure 13 and the second electrical connection structure 17; a second interlayer dielectric layer 19, the second interlayer dielectric layer 19 is located on the surface of the second plastic encapsulation layer 18 away from the first plastic encapsulation layer 14; a second rewiring metal layer 20, the second rewiring metal layer 20 is located in the second interlayer dielectric layer 19, and the second rewiring metal layer 20 is electrically connected to the second electrical connection structure 17.

[0167] As an example, the material of the first interlayer dielectric layer 15 may include a low-k dielectric material. As an example, the first interlayer dielectric layer 15 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0168] As an example, the material of the first rewiring metal layer 16 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0169] As an example, the material of the second interlayer dielectric layer 19 may include a low-k dielectric material. As an example, the second interlayer dielectric layer 19 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, and the second interlayer dielectric layer 19 may be formed by processes such as spin coating, CVD, plasma enhanced CVD, etc.

[0170] As an example, the material of the second rewiring metal layer 20 may include one material selected from the group consisting of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.

[0171] In summary, the present invention provides a 3D chip packaging structure and a preparation method thereof, wherein the 3D chip packaging structure comprises: a rewiring layer, comprising a first surface and a second surface opposite to each other; a first electrical connection structure, located on the first surface of the rewiring layer and electrically connected to the rewiring layer; a first plastic sealing layer, located on the first surface of the rewiring layer, and plastic sealing the first electrical connection structure; a second electrical connection structure, located on a surface of the first plastic sealing layer away from the rewiring layer, and electrically connected to the first electrical connection structure; a second plastic sealing layer, located on a surface of the first plastic sealing layer away from the rewiring layer, and plastic sealing the second electrical connection structure The chip is flip-chip bonded to the second surface of the rewiring layer and electrically connected to the rewiring layer; the third electrical connection structure is located on the second surface of the rewiring layer and electrically connected to the rewiring layer; the third plastic encapsulation layer is located on the second surface of the rewiring layer and plastic encapsulates the third electrical connection structure and the chip; the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer; the metal lead layer is located on the surface of the third plastic encapsulation layer away from the rewiring layer and electrically connected to the third electrical connection structure; the solder ball bump is located on the surface of the metal lead layer away from the third plastic encapsulation layer. In the 3D chip packaging structure of the present invention, the chip realizes 3D packaging, with low cost and high packaging integration, which can meet the needs of the development trend of miniaturization; in the 3D chip packaging structure of the present invention, the orthographic projection of the third plastic encapsulation layer used for plastic encapsulating the chip on the surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer, and the size of the third plastic encapsulation layer used for plastic encapsulating the chip is small, which can effectively increase the effective area of ​​the chip in the 3D chip packaging structure.

[0172] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A 3D chip packaging structure, characterized in that: The 3D chip packaging structure comprises: A rewiring layer comprises a first surface and a second surface opposite to each other; the rewiring layer comprises a wiring dielectric layer and a metal stack structure located in the wiring dielectric layer; A first electrical connection structure is located on a first surface of the rewiring layer and is electrically connected to the rewiring layer; A first plastic sealing layer is located on a first surface of the rewiring layer and plastic seals the first electrical connection structure; A second electrical connection structure is located on a surface of the first plastic packaging layer away from the rewiring layer and is electrically connected to the first electrical connection structure; A second plastic encapsulation layer is located on a surface of the first plastic encapsulation layer away from the rewiring layer and plastic encapsulates the second electrical connection structure; A chip is flip-chip bonded to the second surface of the rewiring layer and electrically connected to the rewiring layer; A third electrical connection structure is located on the second surface of the rewiring layer and is electrically connected to the rewiring layer; the third electrical connection structure includes a conductive column; A third plastic encapsulation layer is located on the second surface of the rewiring layer and encapsulates the third electrical connection structure and the chip; the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer; the edges of the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer are all located within the upper surface of the first plastic encapsulation layer and are spaced from the edges of the surface of the first plastic encapsulation layer; the orthographic projections of the third plastic encapsulation layer and the second plastic encapsulation layer on the same surface of the first plastic encapsulation layer overlap; A metal lead layer, located on a surface of the third plastic packaging layer away from the rewiring layer and electrically connected to the third electrical connection structure; The solder ball bump is located on the surface of the metal lead layer away from the third plastic packaging layer.

2. The 3D chip packaging structure according to claim 1, characterized in that: The metal stacked structure includes multiple layers of metal wire layers and metal plugs arranged at intervals. The metal plugs are located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.

3. The 3D chip packaging structure according to claim 1, characterized in that: The first electrical connection structure and the second electrical connection structure both include welding wires or conductive columns.

4. The 3D chip packaging structure according to claim 1, characterized in that: The 3D chip packaging structure further includes: A first interlayer dielectric layer, located between the first plastic encapsulation layer and the second plastic encapsulation layer; a first redistribution metal layer, located in the first interlayer dielectric layer and electrically connected to the first electrical connection structure and the second electrical connection structure; A second interlayer dielectric layer is located on a surface of the second plastic encapsulation layer away from the first plastic encapsulation layer; The second redistribution metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure.

5. The 3D chip packaging structure according to claim 1, characterized in that: The thickness of the third plastic sealing layer is the same as the thickness of the second plastic sealing layer, and the thickness of the third plastic sealing layer and the thickness of the second plastic sealing layer are both smaller than the thickness of the first plastic sealing layer.

6. A method for preparing a 3D chip packaging structure, characterized in that: The preparation method of the 3D chip packaging structure comprises the following steps: Providing a substrate, and forming a sacrificial layer on a surface of the substrate; forming a rewiring layer on a surface of the sacrificial layer away from the substrate; A first electrical connection structure and a first plastic packaging layer are formed on a surface of the rewiring layer away from the sacrificial layer; the first electrical connection structure is located in the first plastic packaging layer, and the first electrical connection structure is electrically connected to the rewiring layer; A second electrical connection structure and a second plastic encapsulation layer are formed on a surface of the first plastic encapsulation layer away from the rewiring layer; the second electrical connection structure is located in the second plastic encapsulation layer and is electrically connected to the first electrical connection structure; removing the substrate and the sacrificial layer; Providing a chip, bonding the chip to a surface of the rewiring layer away from the first plastic packaging layer, wherein the chip is electrically connected to the rewiring layer; A third electrical connection structure and a third plastic encapsulation layer are formed on the surface of the rewiring layer away from the first plastic encapsulation layer; the third electrical connection structure is located in the third plastic encapsulation layer and is electrically connected to the rewiring layer; the third electrical connection structure includes a conductive column; the third plastic encapsulation layer encapsulates the chip and the third electrical connection structure; the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer is located within the surface of the first plastic encapsulation layer; the edges of the orthographic projection of the third plastic encapsulation layer on the surface of the first plastic encapsulation layer are all located within the upper surface of the first plastic encapsulation layer, and there is a distance between the edges of the surface of the first plastic encapsulation layer; the orthographic projections of the third plastic encapsulation layer and the second plastic encapsulation layer on the same surface of the first plastic encapsulation layer overlap; forming a metal lead layer on a surface of the third plastic encapsulation layer away from the rewiring layer, wherein the metal lead layer is electrically connected to the third electrical connection structure; A solder ball bump is formed on a surface of the metal lead layer away from the third plastic packaging layer, and the solder ball bump is electrically connected to the metal lead layer.

7. The method for preparing the 3D chip packaging structure according to claim 6, characterized in that: Forming the rewiring layer on the upper surface of the sacrificial layer comprises the following steps: forming a bottom dielectric layer on a surface of the sacrificial layer away from the substrate; forming a plastic encapsulation material layer on a surface of the bottom dielectric layer away from the sacrificial layer; forming a seed layer on a surface of the molding material layer away from the bottom dielectric layer; Performing a patterning process on the seed layer and the plastic encapsulation material layer; A wiring dielectric layer and a metal stack structure are formed on the surface of the bottom dielectric layer away from the substrate, wherein the metal stack structure is located in the wiring dielectric layer and is electrically connected to the seed layer; the metal stack structure includes multiple layers of metal wire layers and metal plugs arranged at intervals, wherein the metal plugs are located between adjacent metal wire layers to electrically connect adjacent metal wire layers; After removing the substrate and the sacrificial layer and before bonding the chip to the surface of the rewiring layer away from the first molding layer, the method further includes removing the bottom dielectric layer and the molding material layer.

8. The method for preparing the 3D chip packaging structure according to claim 6, characterized in that: Before forming the second electrical connection structure and the second plastic encapsulation layer on the surface of the first plastic encapsulation layer away from the rewiring layer, the method further includes forming a first interlayer dielectric layer and a first rewiring metal layer on the surface of the first plastic encapsulation layer away from the rewiring layer, wherein the first rewiring metal layer is located in the first interlayer dielectric layer and is electrically connected to the first electrical connection structure; The second plastic encapsulation layer is formed on a surface of the first interlayer dielectric layer away from the first plastic encapsulation layer, and the second electrical connection structure is formed on an upper surface of the first rewiring metal layer; Before removing the substrate and the sacrificial layer, the method also includes forming a second interlayer dielectric layer and a second rewiring metal layer on the surface of the second plastic encapsulation layer away from the first plastic encapsulation layer. The second rewiring metal layer is located in the second interlayer dielectric layer and is electrically connected to the second electrical connection structure.

9. The method for preparing a 3D chip packaging structure according to claim 6, characterized in that: The thickness of the third plastic sealing layer is the same as the thickness of the second plastic sealing layer, and the thickness of the third plastic sealing layer and the thickness of the second plastic sealing layer are both smaller than the thickness of the first plastic sealing layer.

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