A voltage conversion circuit and a readout circuit

Abstract

A readout circuit is suitable for an image sensor, the image sensor includes a bit line output terminal, and outputs a bit line signal. The readout circuit includes: a ramp signal generating circuit, suitable for providing a first ramp signal and a second ramp signal, the first ramp signal and the second ramp signal have the same amplitude and opposite polarity; a conversion circuit, suitable for performing operations according to the bit line signal and a reference signal to obtain a first differential signal and a second differential signal, the first differential signal and the second differential signal have the same amplitude and opposite polarity, and the differential amplitude of the first differential signal and the second differential signal is proportional to the differential amplitude of the bit line signal and the reference signal; a difference comparator, suitable for comparing the first differential signal and the second differential signal output by the conversion circuit and the first ramp signal and the second ramp signal output by the ramp signal generating circuit, and outputting a differential comparison signal.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a voltage conversion circuit and a readout circuit. Background Art

[0002] The image quality produced by CMOS image sensors depends on the signal-to-noise ratio of the image signal. Signal strength depends on light intensity, exposure time, photoelectric conversion efficiency, etc. There are two main types of noise: solid noise and random noise. For image processing, there is a minimum signal-to-noise ratio required to obtain effective image information. If the signal-to-noise ratio is lower than this, image information cannot be obtained. Therefore, the noise index that the chip can achieve determines the minimum illumination of the sensor.

[0003] The noise level of a CMOS image sensor determines the lowest brightness scene it can detect, and the image sensor also has an upper limit on the highest brightness it can achieve in the same frame. In the same frame, the ratio of the highest brightness signal level to the noise level is defined as the dynamic range. Therefore, the dynamic range requires not only a low noise level for the sensor, but also the ability to accept a larger signal swing.

[0004] In the prior art, a single-slope analog-to-digital converter is generally used as a readout circuit of a CMOS image sensor, which is easily affected by noise signals. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a voltage conversion circuit and a readout circuit of a CMOS image sensor, so as to improve the anti-interference capability of the readout circuit of the CMOS image sensor.

[0006] To solve the above problems, an embodiment of the present invention provides a voltage conversion circuit, which is suitable for converting two input signals into a differential signal. The voltage conversion circuit includes: a first input terminal and a second input terminal, which are respectively suitable for inputting a first input signal and a second input signal; a conversion circuit, which is suitable for performing conversion according to the first input signal and the second input signal to obtain a first output signal and a second output signal, wherein the first output signal and the second output signal have the same amplitude and opposite polarity, and the differential amplitude of the first output signal and the second output signal is proportional to the differential amplitude of the first input signal and the second input signal; and a first output terminal and a second output terminal, which are suitable for outputting the first output signal and the second output signal.

[0007] Optionally, the conversion circuit includes: a first addition and multiplication operation module, suitable for obtaining a first addition and multiplication signal based on the first input signal and the second input signal, the first addition and multiplication signal being -0.5A times the sum of the first input signal and the second input signal, where A is a constant; a second addition and multiplication operation module, suitable for obtaining a first output signal based on the first addition and multiplication signal and the first input signal, the first output signal being 0.5A / (1+A) times the difference between the first input signal and the second input signal; and a third addition and multiplication operation module, suitable for obtaining a second output signal based on the first addition and multiplication signal and the second input signal, the second output signal being 0.5A / (1+A) times the difference between the second input signal and the first input signal.

[0008] Optionally, the first input signal is a DC level.

[0009] Optionally, the first addition and multiplication operation module includes a first operational amplifier, a first capacitor, a second capacitor and a third capacitor, wherein: one end of the first capacitor is coupled to the first input terminal, and the other end is coupled to the negative input terminal of the first operational amplifier; one end of the second capacitor is coupled to the second input terminal, and the other end is coupled to the negative input terminal of the first operational amplifier; one end of the third capacitor is coupled to the negative input terminal of the first operational amplifier, and the other end is coupled to the output terminal of the first operational amplifier; the capacitance values ​​of the first capacitor and the second capacitor are the same, and the capacitance value of the third capacitor is 2 / A times the capacitance value of the first capacitor.

[0010] Optionally, the second addition and multiplication operation module includes a fourth capacitor and a fifth capacitor, and the capacitance value of the fourth capacitor is A times the capacitance value of the fifth capacitor, wherein: one end of the fourth capacitor is coupled to the first input end, one end of the fifth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the fourth capacitor and the fifth capacitor are coupled together as the output end of the second addition and multiplication operation module, and output the first output signal.

[0011] Optionally, the third addition and multiplication operation module includes a sixth capacitor and a seventh capacitor, the capacitance value of the sixth capacitor is A times the capacitance value of the seventh capacitor, wherein: one end of the sixth capacitor is coupled to the second input end, one end of the seventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the sixth capacitor and the seventh capacitor are coupled together as the output end of the third addition and multiplication operation module, and output the second output signal.

[0012] Optionally, the first addition and multiplication operation module includes a first PMOS transistor and a first NMOS transistor, an eighth capacitor, a ninth capacitor and a first switch, wherein: one end of the eighth capacitor is coupled to the first input end, and the other end is coupled to the gate of the first NMOS transistor; one end of the ninth capacitor is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; one end of the first switch is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded, and its drain is coupled to the drain of the first PMOS transistor as the output end of the first addition and multiplication operation module; the source of the first PMOS transistor is coupled to an external power supply, and its gate is externally connected to a bias voltage; the capacitance value of the ninth capacitor is 2 / A times the capacitance value of the eighth capacitor.

[0013] Optionally, the second addition and multiplication operation module includes a tenth capacitor and an eleventh capacitor, and the capacitance value of the tenth capacitor is A times the capacitance value of the eleventh capacitor, wherein: one end of the tenth capacitor is coupled to the first input end, one end of the eleventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the tenth capacitor and the eleventh capacitor are coupled together as the output end of the second addition and multiplication operation module, and output the first output signal.

[0014] Optionally, the third addition and multiplication operation module includes a twelfth capacitor and a thirteenth capacitor, the capacitance value of the twelfth capacitor is A times the capacitance value of the thirteenth capacitor, wherein: one end of the twelfth capacitor is coupled to the second input end, one end of the thirteenth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the twelfth capacitor and the thirteenth capacitor are coupled together as the output end of the third addition and multiplication operation module, and output the second output signal.

[0015] An embodiment of the present invention further provides a readout circuit, which is applicable to an image sensor, wherein the image sensor includes a bit line output terminal, which outputs a bit line signal, and the readout circuit includes: a ramp signal generating circuit, which is applicable to providing a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal have the same amplitude and opposite polarity; a conversion circuit, which is applicable to performing operations based on the bit line signal and a reference signal to obtain a first differential signal and a second differential signal, wherein the first differential signal and the second differential signal have the same amplitude and opposite polarity, and the differential amplitude of the first differential signal and the second differential signal is proportional to the differential amplitude of the bit line signal and the reference signal; and a difference comparator, which is applicable to comparing the first differential signal and the second differential signal output by the conversion circuit and the first ramp signal and the second ramp signal output by the ramp signal generating circuit, and outputting a differential comparison signal.

[0016] Optionally, the readout circuit further includes a counter adapted to count according to the differential comparison signal output by the difference comparator.

[0017] Optionally, the difference comparator includes a first subtraction circuit, a second subtraction circuit and a first single-ended comparator.

[0018] Optionally, the two input ends of the first subtraction circuit are respectively coupled to the two output ends of the conversion circuit, and the first differential signal and the second differential signal are input; the two input ends of the second subtraction circuit are respectively coupled to the two output ends of the ramp signal generating circuit, and the first ramp signal and the second ramp signal are input; the output ends of the first subtraction circuit and the second subtraction circuit are respectively coupled to the two input ends of the first single-ended comparator, and the output end of the first single-ended comparator outputs a differential comparison signal.

[0019] Optionally, the difference comparator includes a first adding circuit, a second adding circuit and a second single-ended comparator.

[0020] Optionally, the two input terminals of the first adding circuit are respectively coupled to one of the output terminals of the conversion circuit and one of the output terminals of the ramp signal generating circuit, and the first differential signal and the second ramp signal are input; the two input terminals of the second adding circuit are respectively coupled to the other output terminal of the conversion circuit and the other output terminal of the ramp signal generating circuit, and the first ramp signal and the second differential signal are respectively input; the output terminals of the first adding circuit and the second adding circuit are respectively coupled to the two input terminals of the second single-ended comparator, and the output terminals of the second single-ended comparator output the differential comparison signal.

[0021] Optionally, the difference comparator comprises a four-input differential operational amplifier.

[0022] Optionally, the first differential signal, the second differential signal, the first ramp signal and the second ramp signal are respectively input into four input terminals of the four-input differential operational amplifier, and the output terminals of the four-input differential operational amplifier output differential comparison signals.

[0023] Optionally, the conversion circuit includes: a first addition and multiplication operation module, suitable for obtaining a first addition and multiplication signal according to the bit line signal and the reference signal, the first addition and multiplication signal being -0.5A times the sum of the bit line signal and the reference signal, where A is a constant; a second addition and multiplication operation module, suitable for obtaining a first differential signal according to the first addition and multiplication signal and the reference signal, the first differential signal being 0.5A / (1+A) times the difference between the reference signal and the bit line signal; and a third addition and multiplication operation module, suitable for obtaining a second differential signal according to the first addition and multiplication signal and the bit line signal, the second differential signal being 0.5A / (1+A) times the difference between the bit line signal and the reference signal.

[0024] Optionally, the reference signal is a bit line signal output by a reference pixel unit of a CMOS image sensor.

[0025] Optionally, the reference signal is a DC level.

[0026] Optionally, the first addition and multiplication operation module includes a first operational amplifier, a first capacitor, a second capacitor and a third capacitor, wherein: one end of the first capacitor is coupled to the output end of the reference signal, and the other end is coupled to the negative input end of the first operational amplifier; one end of the second capacitor is coupled to the output end of the bit line signal, and the other end is coupled to the negative input end of the first operational amplifier; one end of the third capacitor is coupled to the negative input end of the first operational amplifier, and the other end is coupled to the output end of the first operational amplifier; the capacitance values ​​of the first capacitor and the second capacitor are the same, and the capacitance value of the third capacitor is 2 / A times the capacitance value of the first capacitor.

[0027] Optionally, the second addition and multiplication operation module includes a fourth capacitor and a fifth capacitor, and the capacitance value of the fourth capacitor is A times the capacitance value of the fifth capacitor, wherein: one end of the fourth capacitor is coupled to the output end of the reference signal, one end of the fifth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the fourth capacitor and the fifth capacitor are coupled together as the output end of the second addition and multiplication operation module, and output the first differential signal.

[0028] Optionally, the third addition and multiplication operation module includes a sixth capacitor and a seventh capacitor, the capacitance value of the sixth capacitor is A times the capacitance value of the seventh capacitor, wherein: one end of the sixth capacitor is coupled to the output end of the bit line signal, one end of the seventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the sixth capacitor and the seventh capacitor are coupled together as the output end of the third addition and multiplication operation module, and output the second differential signal.

[0029] Optionally, the first addition and multiplication operation module includes a first PMOS transistor and a first NMOS transistor, an eighth capacitor, a ninth capacitor and a first switch, wherein: one end of the eighth capacitor is coupled to the output end of the bit line signal, and the other end is coupled to the gate of the first NMOS transistor; one end of the ninth capacitor is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; one end of the first switch is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded, and its drain is coupled to the drain of the first PMOS transistor as the output end of the first addition and multiplication operation module; the source of the first PMOS transistor is coupled to an external power supply, and its gate is externally connected to a bias voltage; the capacitance value of the ninth capacitor is 2 / A times the capacitance value of the eighth capacitor.

[0030] Optionally, the second addition and multiplication operation module includes a tenth capacitor and an eleventh capacitor, and the capacitance value of the tenth capacitor is A times the capacitance value of the eleventh capacitor, wherein: one end of the tenth capacitor is coupled to the output end of the reference signal, one end of the eleventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the tenth capacitor and the eleventh capacitor are coupled together as the output end of the second addition and multiplication operation module, and output the first differential signal.

[0031] Optionally, the third addition and multiplication operation module includes a twelfth capacitor and a thirteenth capacitor, the capacitance value of the twelfth capacitor is A times the capacitance value of the thirteenth capacitor, wherein: one end of the twelfth capacitor is coupled to the output end of the bit line signal, one end of the thirteenth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the twelfth capacitor and the thirteenth capacitor are coupled together as the output end of the third addition and multiplication operation module, and output the second differential signal.

[0032] The voltage conversion circuit provided in the embodiment of the present invention can convert two input signals into two differential signal outputs with the same amplitude and opposite polarity, and the differential amplitude of the two output signals is proportional to the differential amplitude of the two input signals. Even if the input signals have large differences, they can be converted into signals with proportional differential amplitudes.

[0033] The readout circuit of the CMOS image sensor provided by the embodiment of the present invention has four input terminals, and compares the difference between the first differential signal and the second differential signal output by the voltage conversion circuit with the difference between the first ramp signal and the second ramp signal output by the ramp signal generating circuit. Compared with the traditional single-ended readout circuit, the embodiment of the present invention adopts a differential working mode, and its input terminal is the difference between the potentials of two nodes, and the interference of power supply, ground and other signals will be offset, thereby greatly improving the anti-interference ability of the circuit.

[0034] Furthermore, the readout circuit of the CMOS image sensor provided by the embodiment of the present invention includes the voltage conversion circuit provided by the embodiment of the present invention, which can convert the input signals into signals with the same amplitude and opposite polarity even when the input signals are greatly different. In this way, the output signal of the voltage conversion circuit is used as the input signal of the difference comparator in the readout circuit, which solves the problem of the narrow common-mode input range of the difference comparator and greatly expands the working range of the readout circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structure of using a single slope analog-to-digital converter to perform a readout operation on a pixel array in the prior art;

[0036] Figure 2 yes Figure 1 A schematic diagram of the working timing of the readout operation on the pixel array;

[0037] Figure 3 A schematic diagram of a module of a voltage conversion circuit according to an embodiment of the present invention is shown;

[0038] Figure 4 A schematic diagram of a module of a voltage conversion circuit according to an embodiment of the present invention is shown;

[0039] Figure 5 A schematic diagram of the circuit structure of a voltage conversion circuit provided by an embodiment of the present invention is shown;

[0040] Figure 6 A schematic diagram of the circuit structure of a voltage conversion circuit provided by another embodiment of the present invention is shown;

[0041] Figure 7 A schematic diagram of a module of a readout circuit according to an embodiment of the present invention is shown;

[0042] Figure 8 A schematic diagram of a module of a difference comparator provided by an embodiment of the present invention is shown;

[0043] Fig. 9 A module schematic diagram of a difference comparator provided by another embodiment of the present invention is shown;

[0044] Fig.10A schematic diagram showing the circuit structure of a readout circuit of a CMOS image sensor according to an embodiment of the present invention; and

[0045] Fig.11 Shows Fig.10 A schematic diagram of the working timing of a readout circuit of a CMOS image sensor in an embodiment of the present invention is provided. DETAILED DESCRIPTION

[0046] The existing single slope analog-to-digital converter readout circuit has a structural block diagram as shown below: Figure 1 (not limited to this structure), where BL is the output bit line signal of the pixel, and the Ramp signal is the ramp signal generated by the ramp signal generating circuit. The reference workflow is as follows Figure 2 As shown, the comparator is first auto-zeroed, and then the ramp signal begins to approach the negative node voltage Vn of the comparator, and starts counting at the same time. When the ramp signal exceeds Vn, the comparator flips and the counter stops counting. In order to achieve Correlated Double Sample (CDS), the output signal is sampled twice in one signal output cycle, that is, once the reset level of the pixel is sampled, and the other time the signal level of the pixel is sampled, generating two sampling pulses. If the two sampling values ​​are subtracted, the interference of the reset noise is basically eliminated, and the actual effective amplitude of the signal level is obtained.

[0047] like Figure 1 As shown, the existing single slope analog-to-digital converter readout circuit adopts a single-ended working mode, and its reference potential is a fixed potential (usually ground). The interference of power supply, ground and other signals will directly damage the useful signal actually needed.

[0048] To this end, the present invention proposes a voltage conversion circuit and a readout circuit suitable for an image sensor. The circuit adopts a differential working mode and has a strong anti-interference ability and a relatively large working range.

[0049] Reference Figure 3, a module schematic diagram of a voltage conversion circuit of an embodiment of the present invention is given. The voltage conversion circuit 1 includes: a first input terminal IN1 and a second input terminal IN2, respectively suitable for inputting a first input signal and a second input signal; a conversion circuit 10, suitable for converting according to the first input signal and the second input signal to obtain a first output signal and a second output signal, the first output signal and the second output signal have the same amplitude and opposite polarity, and the differential amplitude of the first output signal and the second output signal is proportional to the differential amplitude of the first input signal and the second input signal; a first output terminal OU1 and a second output terminal OU2, suitable for outputting the first output signal and the second output signal.

[0050] Figure 4 FIG. 1 is a schematic diagram showing a circuit structure of a voltage conversion circuit of an embodiment of the present invention. Figure 4 As shown, the conversion circuit 10 includes: a first addition and multiplication operation module 101, adapted to obtain a first addition and multiplication signal Vcm according to the first input signal Vip and the second input signal Vin, wherein the first addition and multiplication signal Vcm is -0.5A times the sum of the first input signal Vip and the second input signal Vin, that is, Vcm=-0.5A(Vip+Vin), wherein A is a constant; a second addition and multiplication operation module 102, adapted to obtain a first output signal Vop according to the first addition and multiplication signal Vcm and the first input signal Vip, wherein the first output signal Vop is 0.5A / (1+A) times the difference between the first input signal Vip and the second input signal Vin, that is, Vop=0.5A*(Vip-Vin) / (1+A); the third addition and multiplication operation module 103 is suitable for obtaining the second output signal Von according to the first addition and multiplication signal Vcm and the second input signal Vin, and the second output signal Vonp is 0.5A / (1+A) times the difference between the second input signal Vin and the first input signal Vip, that is, Von=0.5A*(Vin-Vip) / (1+A).

[0051] After the above circuit, the first output signal Vop and the second output signal Von have opposite polarities and the same amplitude, and are differential signals; and the differential amplitude of the first output signal Vop and the second output signal Von is proportional to the differential amplitude of the first input signal Vip and the second input signal Vin, specifically: Vop-Von=A*(Vip-Vin) / (1+A), that is: the differential amplitude of the first output signal Vop and the second output signal Von is A / (1+A) times the differential amplitude of the first input signal Vip and the second input signal Vin.

[0052] Figure 5 FIG. 1 is a schematic diagram of a circuit structure of a voltage conversion circuit provided by an embodiment of the present invention. Figure 5 As shown, the first addition and multiplication operation module 101 includes a first operational amplifier Q1, a first capacitor C1, a second capacitor C2 and a third capacitor C3, wherein: one end of the first capacitor C1 is coupled to the first input end, inputting the first input signal Vip, and the other end is coupled to the negative input end of the first operational amplifier Q1; one end of the second capacitor C2 is used as the second input end, inputting the second input signal Vin, and the other end is coupled to the negative input end of the first operational amplifier Q1; one end of the third capacitor C3 is coupled to the negative input end of the first operational amplifier Q1, and the other end is coupled to the output end of the first operational amplifier Q1, outputting the first addition and multiplication signal Vcm; the first capacitor C1 and the second capacitor C2 have the same capacitance value, and the capacitance value of the third capacitor C3 is 2 / A times the capacitance value of the first capacitor C1, that is, C3=2C1 / A, where A is a constant. Then the first addition and multiplication signal Vcm=(-0.5A)*(Vin+Vip).

[0053] like Figure 5 As shown, the second addition and multiplication operation module 102 includes a fourth capacitor C4 and a fifth capacitor C5, and the capacitance value of the fourth capacitor C4 is A times the capacitance value of the fifth capacitor C5, wherein: one end of the fourth capacitor C4 is coupled to the first input end, and the first input signal Vip is input; one end of the fifth capacitor C5 is coupled to the output end of the first addition and multiplication operation module, and the first addition and multiplication signal Vcm is input; the other ends of the fourth capacitor C4 and the fifth capacitor C5 are coupled together as the output end of the second addition and multiplication operation module 102, and the first output signal Vop is output.

[0054] like Figure 5 As shown, the third addition and multiplication operation module 103 includes a sixth capacitor C6 and a seventh capacitor C7, and the capacitance value of the sixth capacitor C6 is A times the capacitance value of the seventh capacitor C7, wherein: one end of the sixth capacitor C6 is coupled to the second input end, and the second input signal Vin is input; one end of the seventh capacitor C7 is coupled to the output end of the first addition and multiplication operation module, and the first addition and multiplication signal Vcm is input; the other ends of the sixth capacitor C6 and the seventh capacitor C7 are coupled together as the output end of the third addition and multiplication operation module 103, and the second output signal Von is output.

[0055] Depend on Figure 5It can be seen that the first output signal Vop=0.5A*(Vip-Vin) / (1+A), the second output signal Von=0.5A*(Vin-Vip) / (1+A), then the first output signal Vop and the second output signal Von have opposite polarities and the same amplitude, and are differential signals; and the differential amplitude of the first output signal Vop and the second output signal Von is proportional to the differential amplitude of the first input signal Vip and the second input signal Vin, specifically: Vop-Von=A*(Vip-Vin) / (1+A), that is: the differential amplitude of the first output signal Vop and the second output signal Von is A / (1+A) times the differential amplitude of the first input signal Vip and the second input signal Vin.

[0056] Figure 6 FIG. 1 is a circuit structure diagram of a voltage conversion circuit provided by another embodiment of the present invention, which is applicable when the first input signal Vip is a DC level. Figure 6 As shown, the first addition and multiplication operation module 101 includes a first PMOS transistor MP1 and a first NMOS transistor MN1, an eighth capacitor C8, a ninth capacitor C9 and a first switch S1, wherein: one end of the eighth capacitor C8 is coupled to the first input end, inputs the first input signal Vip, and the other end is coupled to the gate of the first NMOS transistor MN1; one end of the ninth capacitor C9 is coupled to the gate of the first NMOS transistor MN1, and the other end is coupled to the drain of the first NMOS transistor MN1; one end of the first switch S1 is coupled to the first The gate of the NMOS transistor MN1 is coupled, and the other end is coupled to the drain of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is grounded, and its drain is coupled to the drain of the first PMOS transistor MP1, serving as the output of the first addition and multiplication operation module 101, outputting the first addition and multiplication signal Vcm; the source of the first PMOS transistor MP1 is coupled to an external power supply, and its gate is externally connected to a bias voltage; the capacitance value of the ninth capacitor C9 is 2 / A times the capacitance value of the eighth capacitor C8, that is, C9=2C8 / A, where A is a constant. Figure 6 It can be known that the first multiplied signal Vcm=(-0.5A)*Vin.

[0057] like Figure 6As shown, the second addition and multiplication operation module 102 includes a tenth capacitor C10 and an eleventh capacitor C11, and the capacitance value of the tenth capacitor C10 is A times the capacitance value of the eleventh capacitor C11, wherein: one end of the tenth capacitor C10 is coupled to the first input end, and the first input signal Vip is input; one end of the eleventh capacitor C11 is coupled to the output end of the first addition and multiplication operation module, and the first addition and multiplication signal Vcm is input; the other ends of the tenth capacitor C10 and the eleventh capacitor C11 are coupled together as the output end of the second addition and multiplication operation module 102, and the first output signal Vop is output.

[0058] like Figure 6 As shown, the third addition and multiplication operation module 103 includes a twelfth capacitor C12 and a thirteenth capacitor C13, and the capacitance value of the twelfth capacitor C12 is A times the capacitance value of the thirteenth capacitor C13, wherein: one end of the twelfth capacitor C12 is coupled to the second input end, and the second input signal Vin is input; one end of the thirteenth capacitor C13 is coupled to the output end of the first addition and multiplication operation module, and the first addition and multiplication signal Vcm is input; the other ends of the twelfth capacitor C12 and the thirteenth capacitor C13 are coupled together as the output end of the third addition and multiplication operation module 103, and the second output signal Von is output.

[0059] Depend on Figure 6 It can be seen that the first output signal Vop = -0.5A*Vin / (1+A), the second output signal Von = 0.5A*Vin / (1+A), then the first output signal Vop and the second output signal Von have opposite polarities and the same amplitude, and are differential signals; and the differential amplitude of the first output signal Vop and the second output signal Von is proportional to the differential amplitude of the first input signal Vip and the second input signal Vin, specifically: Vop-Von = -A*Vin / (1+A), that is: the differential amplitude of the first output signal Vop and the second output signal Von is A / (1+A) times the differential amplitude of the first input signal Vip and the second input signal Vin.

[0060] Figure 7The module diagram of a readout circuit provided by an embodiment of the present invention is shown in FIG. The readout circuit is applicable to an image sensor, wherein the image sensor comprises a bit line output terminal, outputs a bit line signal Vbl, and the bit line signal Vbl is used as an input signal of a conversion circuit. The readout circuit includes: a ramp signal generating circuit 30, adapted to provide a first ramp signal Vrp and a second ramp signal Vrn, wherein the first ramp signal Vrp and the second ramp signal Vrn have the same amplitude and opposite polarities; a conversion circuit 20, adapted to perform operations based on a bit line signal Vbl and a reference signal Vref to obtain a first differential signal Vnp and a second differential signal Vnn, wherein the first differential signal Vnp and the second differential signal Vnn have the same amplitude and opposite polarities, and the differential amplitude of the first differential signal Vnp and the second differential signal Vnn is proportional to the differential amplitude of the bit line signal Vbl and the reference signal Vref; a difference comparator 40, adapted to compare the first differential signal Vnp and the second differential signal Vnn output by the conversion circuit 20, and the first ramp signal Vrp and the second ramp signal Vrn output by the ramp signal generating circuit 30, and output a differential comparison signal Vout.

[0061] The conversion circuit 20 includes the voltage conversion circuit 1 provided in the embodiment of the present invention. Figure 3 As shown, its specific implementation and principle refer to the above description, which will not be repeated here. The voltage conversion circuit 20 includes two input terminals, wherein the reference signal Vref is input to the first input terminal, and the bit line signal Vbl is input to the second input terminal. In one embodiment, the reference signal Vref is a bit line signal output by a reference pixel unit of a CMOS image sensor. In another embodiment, the reference signal Vref is a DC level superimposed with a noise signal.

[0062] As can be seen from the foregoing description, the first differential signal Vnp output by the conversion circuit 20 is 0.5A*(Vref-Vbl) / (1+A), and the second differential signal Vnn is 0.5A*(Vbl-Vref) / (1+A). Therefore, the first differential signal Vnp and the second differential signal Vnn have opposite polarities and the same amplitude, and are differential signals; and the differential amplitude of the first differential signal Vnp and the second differential signal Vnn is proportional to the differential amplitude of the bit line signal Vbl and the reference signal Vref. Specifically, Vnp-Vnn is A*(Vref-Vbl) / (1+A). That is to say, the differential amplitude of the first differential signal Vnp and the second differential signal Vnn is A / (1+A) times the differential amplitude of the reference signal Vref and the bit line signal Vbl.

[0063] In one embodiment, the difference comparator 40 is a four-input differential operational amplifier, such as Figure 7As shown, two input terminals are coupled to the two output terminals of the conversion circuit 20, and the first differential signal Vnp and the second differential signal Vnn output after the reference signal Vref and the bit line signal Vbl are converted by the conversion circuit 20 are input respectively, and the other two input terminals are coupled to the two output terminals of the ramp signal generating circuit 30, and the first ramp signal Vrp and the second ramp signal Vrn are input respectively. The comparator in the difference comparator 40 is responsible for comparing the difference between the first differential signal Vnp and the second differential signal Vnn with the difference between the first ramp signal Vrp and the second ramp signal Vrn, that is, comparing the size of Vnp-Vnn with Vrp-Vrn, or judging the size of (Vrp-Vrn)-(Vnp-Vnn) and 0; in other words, judging the size of (Vnn+Vrp)-(Vnp+Vrn) and 0. Specifically, when the circuit is working, when the difference between the first ramp signal Vrp and the second ramp signal Vrn is greater than the difference between the first differential signal Vnp and the second differential signal Vnn, the differential comparison signal Vout output by the difference comparator 40 is a high level; when the difference between the first ramp signal Vrp and the second ramp signal Vrn is less than the difference between the first differential signal Vnp and the second differential signal Vnn, the differential comparison signal Vout output by the difference comparator 40 is a low level.

[0064] like Figure 8As shown, in another embodiment, the difference comparator 40a includes a first subtraction circuit 401, a second subtraction circuit 402 and a first single-ended comparator 403. The two input terminals of the first subtraction circuit 401 are coupled to the two output terminals of the conversion circuit 20, and the first differential signal Vnp and the second differential signal Vnn output after the reference signal Vref and the bit line signal Vbl are converted by the conversion circuit 20 are respectively input. The two input terminals of the second subtraction circuit 402 are coupled to the two output terminals of the ramp signal generating circuit 30, and the first ramp signal Vrp and the second ramp signal Vrn are respectively input. The output terminals of the first subtraction circuit 401 and the second subtraction circuit 402 are respectively coupled to the two input terminals of the first single-ended comparator 403, and the output terminal of the first single-ended comparator 403 outputs the differential comparison signal Vout. The first single-ended comparator 403 is responsible for comparing the difference between the first differential signal Vnp and the second differential signal Vnn with the difference between the first ramp signal Vrp and the second ramp signal Vrn, that is, comparing (Vnp-Vnn) with (Vrp-Vrn), or judging the difference between (Vrp-Vrn)-(Vnp-Vnn) and 0. Specifically, when the circuit is working, when the difference between the first ramp signal Vrp and the second ramp signal Vrn is greater than the difference between the first differential signal Vnp and the second differential signal Vnn, the differential comparison signal Vout output by the first single-ended comparator 403 is a high level; when the difference between the first ramp signal Vrp and the second ramp signal Vrn is less than the difference between the first differential signal Vnp and the second differential signal Vnn, the differential comparison signal Vout output by the first single-ended comparator 403 is a low level.

[0065] like Fig. 9As shown, in another embodiment, the difference comparator 40b includes a first adding circuit 404, a second adding circuit 405 and a second single-ended comparator 406. The two input ends of the first adding circuit 404 are respectively input with the first differential signal Vnp and the second ramp signal Vrn. The two input ends of the second adding circuit 405 are respectively input with the first ramp signal Vrp and the second differential signal Vnn. The output ends of the first adding circuit 404 and the second adding circuit 405 are respectively coupled with the two input ends of the second single-ended comparator 406, and the output end of the second single-ended comparator 406 outputs a differential comparison signal Vout. The second single-ended comparator 406 is responsible for comparing the sum of the first differential signal Vnp and the second ramp signal Vrn with the sum of the first ramp signal Vrp and the second differential signal Vnn, that is, the size of (Vnp+Vrn)-(Vnn+Vrp) and 0. Specifically, when the circuit is working, when the sum of the first differential signal Vnp and the second ramp signal Vrn is greater than the sum of the first ramp signal Vrp and the second differential signal Vnn, the differential comparison signal Vout output by the second single-ended comparator 406 is a high level; when the sum of the first differential signal Vnp and the second ramp signal Vrn is less than the sum of the first ramp signal Vrp and the second differential signal Vnn, the differential comparison signal Vout output by the second single-ended comparator 406 is a low level.

[0066] Alternatively, if Figure 7 As shown, the readout circuit further includes: a counter 50, adapted to count according to the differential comparison signal Vout output by the difference comparator.

[0067] Fig.10 The present invention is a schematic diagram of a circuit structure of a readout circuit of a CMOS image sensor provided by an embodiment of the present invention. Fig.10 The conversion circuit 20 in the embodiment adopts the above Figure 6 In the embodiment, the difference comparator 40 adopts the above Figure 7 The embodiments in .

[0068] Fig.11 yes Fig.10 The working timing diagram of the readout circuit provided in the embodiment is as follows. Fig.10 As shown, in this embodiment, the reference signal Vref is a DC level with only noise disturbance, that is, Vref=0. The conversion circuit 20 adopts Figure 6As shown in the circuit structure and constant A=1, then C9=2C8, C8=C10=C11=C12=C13. From this relationship, it can be known that the reference signal Vref is converted by the conversion circuit 20 and the output first differential signal Vnp=0.5A*(Vref-Vbl) / (1+A)=-0.25Vbl, and the second differential signal Vnn=0.5A*(Vbl-Vref) / (1+A)=0.25Vbl. Then the first differential signal Vnp and the second differential signal Vnn have opposite polarities and the same amplitude, and are differential signals. The first differential signal Vnp, the second differential signal Vnn, the first ramp signal Vrp and the second ramp signal Vrn are sent to the difference comparator 40 with four input terminals. The difference comparator 40 compares the difference between the first differential signal Vnp and the second differential signal Vnn with the difference between the first ramp signal Vrp and the second ramp signal Vrn, and outputs a differential comparison signal Vout according to the comparison structure. The differential comparison signal Vout is used as the input signal of the counter 50, and the counter 50 outputs a sampling pulse signal Vd according to the size of the differential comparison signal Vout.

[0069] like Fig.10 As shown, the readout circuit further includes a second switch S2 and a third switch S3.

[0070] The following is a brief introduction Fig.10 The working principle of the readout circuit. When the operation starts, the second switch S2 and the third switch S3 are closed to provide a suitable bias voltage for the difference comparator 40. The first switch S1 in the conversion circuit 20 is also closed to provide a suitable bias voltage for the conversion circuit 20. After that, the second switch S2 and the third switch S3 are opened, and the reset level of the pixel is sampled. After the reset level sampling of the pixel is completed, the first switch S1 is also opened, and the conversion circuit 20 starts to work. The conversion circuit 20 converts the bit line signal Vbl and the reference signal Vref output by the pixel unit into differential signals with opposite polarities and the same amplitude: the first differential signal Vnp and the second differential signal Vnn. The first differential signal Vnp and the second differential signal Vnn are input to the two input terminals of the difference comparator 40, and the difference comparator 40 compares the difference between the first ramp signal Vrp and the second ramp signal Vrn with the difference between the first differential signal Vnp and the second differential signal Vnn, and outputs the differential comparison signal Vout according to the comparison structure. The differential comparison signal Vout is used as an input signal of the counter 50 . The counter 50 outputs a sampling pulse signal Vd according to the magnitude of the differential comparison signal Vout, thereby completing the sampling of the signal level of the pixel.

[0071] The voltage conversion circuit provided in the embodiment of the present invention can convert two input signals into two differential signal outputs with the same amplitude and opposite polarity, and the differential amplitude of the two output signals is proportional to the differential amplitude of the two input signals. Even if the input signals have large differences, they can be converted into signals with proportional differential amplitudes.

[0072] The readout circuit of the CMOS image sensor provided by the embodiment of the present invention has four input terminals, and compares the difference between the first differential signal and the second differential signal output by the voltage conversion circuit with the difference between the first ramp signal and the second ramp signal output by the ramp signal generating circuit. Compared with the traditional single-ended readout circuit, the embodiment of the present invention adopts a differential working mode, and its input terminal is the difference between the potentials of two nodes, and the interference of power supply, ground and other signals will be offset, thereby greatly improving the anti-interference ability of the circuit.

[0073] Furthermore, the readout circuit of the CMOS image sensor provided by the embodiment of the present invention includes the voltage conversion circuit provided by the embodiment of the present invention, which can convert the input signals into signals with the same amplitude and opposite polarity even when the input signals are greatly different. In this way, the output signal of the voltage conversion circuit is used as the input signal of the difference comparator in the readout circuit, which solves the problem of the narrow common-mode input range of the difference comparator and greatly expands the working range of the readout circuit.

[0074] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A voltage conversion circuit, suitable for converting two input signals into a differential signal, characterized in that: The voltage conversion circuit comprises: The first input terminal and the second input terminal are respectively adapted to input a first input signal and a second input signal; a conversion circuit, adapted to perform conversion according to a first input signal and a second input signal to obtain a first output signal and a second output signal, wherein the first output signal and the second output signal have the same amplitude and opposite polarity, and the differential amplitude between the first output signal and the second output signal is proportional to the differential amplitude between the first input signal and the second input signal; A first output terminal and a second output terminal, adapted to output a first output signal and a second output signal; The conversion circuit comprises: A first addition and multiplication operation module, adapted to obtain a first addition and multiplication signal according to the first input signal and the second input signal, wherein the first addition and multiplication signal is -0.5A times the sum of the first input signal and the second input signal, wherein A is a constant; A second addition and multiplication operation module, adapted to obtain a first output signal according to the first addition and multiplication signal and a first input signal, wherein the first output signal is 0.5A / (1+A) times the difference between the first input signal and the second input signal; The third addition and multiplication operation module is adapted to obtain a second output signal according to the first addition and multiplication signal and the second input signal, wherein the second output signal is 0.5A / (1+A) times the difference between the second input signal and the first input signal.

2. The voltage conversion circuit according to claim 1, characterized in that: The first input signal is a DC level.

3. The voltage conversion circuit according to claim 1, wherein: The first addition and multiplication operation module includes a first operational amplifier, a first capacitor, a second capacitor and a third capacitor, wherein: one end of the first capacitor is coupled to the first input end, and the other end is coupled to the negative input end of the first operational amplifier; one end of the second capacitor is coupled to the second input end, and the other end is coupled to the negative input end of the first operational amplifier; one end of the third capacitor is coupled to the negative input end of the first operational amplifier, and the other end is coupled to the output end of the first operational amplifier; the capacitance values ​​of the first capacitor and the second capacitor are the same, and the capacitance value of the third capacitor is 2 / A times the capacitance value of the first capacitor.

4. The voltage conversion circuit according to claim 1, wherein: The second addition and multiplication operation module includes a fourth capacitor and a fifth capacitor, and the capacitance value of the fourth capacitor is A times the capacitance value of the fifth capacitor, wherein: one end of the fourth capacitor is coupled to the first input end, one end of the fifth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the fourth capacitor and the fifth capacitor are coupled together as the output end of the second addition and multiplication operation module, and output the first output signal.

5. The voltage conversion circuit according to claim 1, wherein: The third addition and multiplication operation module includes a sixth capacitor and a seventh capacitor, and the capacitance value of the sixth capacitor is A times the capacitance value of the seventh capacitor, wherein: one end of the sixth capacitor is coupled to the second input end, one end of the seventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the sixth capacitor and the seventh capacitor are coupled together as the output end of the third addition and multiplication operation module, and output the second output signal.

6. The voltage conversion circuit according to claim 2, characterized in that: The first addition and multiplication operation module includes a first PMOS transistor and a first NMOS transistor, an eighth capacitor, a ninth capacitor and a first switch, wherein: one end of the eighth capacitor is coupled to the first input end, and the other end is coupled to the gate of the first NMOS transistor; one end of the ninth capacitor is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; one end of the first switch is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded, and its drain is coupled to the drain of the first PMOS transistor as the output end of the first addition and multiplication operation module; the source of the first PMOS transistor is coupled to an external power supply, and its gate is externally connected to a bias voltage; the capacitance value of the ninth capacitor is 2 / A times the capacitance value of the eighth capacitor.

7. The voltage conversion circuit according to claim 2, characterized in that: The second addition and multiplication operation module includes a tenth capacitor and an eleventh capacitor, and the capacitance value of the tenth capacitor is A times the capacitance value of the eleventh capacitor, wherein: one end of the tenth capacitor is coupled to the first input end, one end of the eleventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the tenth capacitor and the eleventh capacitor are coupled together as the output end of the second addition and multiplication operation module, and output the first output signal.

8. The voltage conversion circuit according to claim 2, characterized in that: The third addition and multiplication operation module includes a twelfth capacitor and a thirteenth capacitor, the capacitance value of the twelfth capacitor is A times the capacitance value of the thirteenth capacitor, wherein: one end of the twelfth capacitor is coupled to the second input end, one end of the thirteenth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the twelfth capacitor and the thirteenth capacitor are coupled together as the output end of the third addition and multiplication operation module, and output the second output signal.

9. A readout circuit, suitable for an image sensor, the image sensor comprising a bit line output terminal, outputting a bit line signal, characterized in that: The readout circuit comprises: A ramp signal generating circuit, adapted to provide a first ramp signal and a second ramp signal, wherein the first ramp signal and the second ramp signal have the same amplitude and opposite polarity; a conversion circuit, adapted to perform an operation according to the bit line signal and the reference signal to obtain a first differential signal and a second differential signal, wherein the first differential signal and the second differential signal have the same amplitude and opposite polarity, and the differential amplitude of the first differential signal and the second differential signal is proportional to the differential amplitude of the bit line signal and the reference signal; a difference comparator, adapted to compare the first differential signal and the second differential signal output by the conversion circuit, and the first ramp signal and the second ramp signal output by the ramp signal generating circuit, and output a differential comparison signal; The conversion circuit comprises: A first addition and multiplication operation module, adapted to obtain a first addition and multiplication signal according to the bit line signal and the reference signal, wherein the first addition and multiplication signal is -0.5A times the sum of the bit line signal and the reference signal, wherein A is a constant; a second addition and multiplication operation module, adapted to obtain a first differential signal according to the first addition and multiplication signal and a reference signal, wherein the first differential signal is 0.5A / (1+A) times the difference between the reference signal and the bit line signal; The third addition and multiplication operation module is adapted to obtain a second differential signal according to the first addition and multiplication signal and the bit line signal, wherein the second differential signal is 0.5A / (1+A) times the difference between the bit line signal and the reference signal.

10. The readout circuit according to claim 9, wherein: Also includes: The counter is adapted to count according to the differential comparison signal output by the difference comparator.

11. The readout circuit according to claim 9, characterized in that The difference comparator includes a first subtraction circuit, a second subtraction circuit and a first single-ended comparator.

12. The readout circuit according to claim 11, wherein: The two input ends of the first subtraction circuit are respectively coupled to the two output ends of the conversion circuit, and the first differential signal and the second differential signal are input; the two input ends of the second subtraction circuit are respectively coupled to the two output ends of the ramp signal generating circuit, and the first ramp signal and the second ramp signal are input; the output ends of the first subtraction circuit and the second subtraction circuit are respectively coupled to the two input ends of the first single-ended comparator, and the output end of the first single-ended comparator outputs a differential comparison signal.

13. The readout circuit according to claim 9, characterized in that The difference comparator includes a first adding circuit, a second adding circuit and a second single-ended comparator.

14. The readout circuit according to claim 13, wherein: The two input terminals of the first adding circuit are respectively coupled to one of the output terminals of the conversion circuit and one of the output terminals of the ramp signal generating circuit, and the first differential signal and the second ramp signal are input; the two input terminals of the second adding circuit are respectively coupled to the other output terminal of the conversion circuit and the other output terminal of the ramp signal generating circuit, and the first ramp signal and the second differential signal are respectively input; the output terminals of the first adding circuit and the second adding circuit are respectively coupled to the two input terminals of the second single-ended comparator, and the output terminal of the second single-ended comparator outputs a differential comparison signal.

15. The readout circuit according to claim 9, characterized in that The difference comparator includes a differential operational amplifier with four input terminals.

16. The readout circuit according to claim 15, characterized in that The first differential signal, the second differential signal, the first ramp signal and the second ramp signal are respectively input into four input terminals of the four-input differential operational amplifier, and the output terminals of the four-input differential operational amplifier output differential comparison signals.

17. The readout circuit according to claim 9, characterized in that The reference signal is a bit line signal output by a reference pixel unit of the CMOS image sensor.

18. The readout circuit according to claim 17, wherein: The reference signal is a DC level.

19. The readout circuit according to claim 17, wherein: The first addition and multiplication operation module includes a first operational amplifier, a first capacitor, a second capacitor and a third capacitor, wherein: one end of the first capacitor is coupled to the output end of the reference signal, and the other end is coupled to the negative input end of the first operational amplifier; one end of the second capacitor is coupled to the output end of the bit line signal, and the other end is coupled to the negative input end of the first operational amplifier; one end of the third capacitor is coupled to the negative input end of the first operational amplifier, and the other end is coupled to the output end of the first operational amplifier; the capacitance values ​​of the first capacitor and the second capacitor are the same, and the capacitance value of the third capacitor is 2 / A times the capacitance value of the first capacitor.

20. The readout circuit according to claim 17, wherein: The second addition and multiplication operation module includes a fourth capacitor and a fifth capacitor, and the capacitance value of the fourth capacitor is A times the capacitance value of the fifth capacitor, wherein: one end of the fourth capacitor is coupled to the output end of the reference signal, one end of the fifth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the fourth capacitor and the fifth capacitor are coupled together as the output end of the second addition and multiplication operation module, and the first differential signal is output.

21. The readout circuit according to claim 17, wherein: The third addition and multiplication operation module includes a sixth capacitor and a seventh capacitor, and the capacitance value of the sixth capacitor is A times the capacitance value of the seventh capacitor, wherein: one end of the sixth capacitor is coupled to the output end of the bit line signal, one end of the seventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the sixth capacitor and the seventh capacitor are coupled together as the output end of the third addition and multiplication operation module, and the second differential signal is output.

22. The readout circuit according to claim 18, wherein: The first addition and multiplication operation module includes a first PMOS transistor and a first NMOS transistor, an eighth capacitor, a ninth capacitor and a first switch, wherein: one end of the eighth capacitor is coupled to the output end of the bit line signal, and the other end is coupled to the gate of the first NMOS transistor; one end of the ninth capacitor is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; one end of the first switch is coupled to the gate of the first NMOS transistor, and the other end is coupled to the drain of the first NMOS transistor; the source of the first NMOS transistor is grounded, and its drain is coupled to the drain of the first PMOS transistor as the output end of the first addition and multiplication operation module; the source of the first PMOS transistor is coupled to an external power supply, and its gate is externally connected to a bias voltage; the capacitance value of the ninth capacitor is 2 / A times the capacitance value of the eighth capacitor.

23. The readout circuit according to claim 18, wherein: The second addition and multiplication operation module includes a tenth capacitor and an eleventh capacitor, and the capacitance value of the tenth capacitor is A times the capacitance value of the eleventh capacitor, wherein: one end of the tenth capacitor is coupled to the output end of the reference signal, one end of the eleventh capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the tenth capacitor and the eleventh capacitor are coupled together as the output end of the second addition and multiplication operation module, and the first differential signal is output.

24. The readout circuit according to claim 18, wherein: The third addition and multiplication operation module includes a twelfth capacitor and a thirteenth capacitor, the capacitance value of the twelfth capacitor is A times the capacitance value of the thirteenth capacitor, wherein: one end of the twelfth capacitor is coupled to the output end of the bit line signal, one end of the thirteenth capacitor is coupled to the output end of the first addition and multiplication operation module, and the other ends of the twelfth capacitor and the thirteenth capacitor are coupled together as the output end of the third addition and multiplication operation module, and output the second differential signal.

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