A dual-core chip and a method for backing up and restoring its program

Abstract

The present invention discloses a dual-core chip and a method for backing up and restoring a program thereof, wherein the dual-core chip comprises: a first central processing unit CPU1, referred to as CPU1; a second central processing unit CPU2, referred to as CPU2, which is connected to the first central processing unit CPU1 through an internal communication bus; a first flash memory module, which is operated by the first central processing unit CPU1, and comprises a CPU1 boot loader area, a CPU1 application program execution area, a CPU1 application program temporary storage area, and a CPU2 application program backup area; a second flash memory module, which is operated by the second central processing unit CPU2, and comprises a CPU2 boot loader area, a CPU2 application program execution area, a CPU2 application program temporary storage area, and a CPU1 application program backup area; wherein the dual-core chip communicates with the outside through an external communication bus. In summary, the dual-core chip in the present invention realizes program backup and recovery simply and reliably by utilizing the internal Flash space of the chip, thereby improving the MTBF of the entire system and the anti-interference recovery capability of the entire embedded system.

Description

[Technical field]

[0001] The invention relates to the field of embedded systems, and in particular to a dual-core chip and a method for backing up and restoring a program thereof. [Background technology]

[0002] Once an error occurs in the program update of an embedded system, it usually causes the system to crash and cannot be restored through remote upgrades. It can only be restored through on-site maintenance or factory repair, which increases the after-sales maintenance cost and reduces the service life of the entire embedded system.

[0003] Therefore, it is necessary to provide a new technical solution to overcome the above problems. [Summary of the invention]

[0004] The technical problem to be solved by the present invention is to provide a dual-core chip and a method for backing up and restoring its program, which can safely and quickly perform cross-backup and rapid recovery without using an external storage device.

[0005] In order to solve the above problems, according to the first aspect of the present invention, the present invention provides a dual-core chip, which includes: a first central processing unit CPU1, which is referred to as CPU1; a second central processing unit CPU2; a first flash memory module, which is operated by the first central processing unit CPU1, and includes a CPU1 boot loader area, a CPU1 application execution area, a CPU1 application temporary storage area and a CPU2 application backup area; a second flash memory module, which is operated by the second central processing unit CPU2, and includes a CPU2 boot loader area, a CPU2 application execution area, a CPU2 application temporary storage area and a CPU1 application backup area; an internal communication bus, which is used for communication connection between the first central processing unit CPU1 and the second central processing unit CPU2; an external communication bus, which is used for the first central processing unit CPU1, the second central processing unit CPU2 to communicate with the outside.

[0006] According to a second aspect of the present invention, the present invention provides a program recovery method for a dual-core chip, which includes: the CPU1 detects whether the system is normal, and if normal, continues to detect, otherwise, the CPU1 stops working; after the CPU1 stops working, it notifies the CPU2 to stop working; the CPU2 sends the CPU1 program backed up in the CPU1 application backup area of ​​the second flash memory module to the CPU1; the CPU1 writes the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module; the CPU1 performs program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module.

[0007] According to the third aspect of the present invention, the present invention provides a program recovery method for a dual-core chip, which includes: the CPU1 receives a program recovery instruction; the CPU1 stops working; after the CPU1 stops working, the CPU2 is notified to stop working; the CPU2 sends the CPU1 program backed up in the CPU1 application backup area in the second flash memory module to the CPU1 application temporary storage area of ​​the first flash memory module; the CPU1 sends the CPU2 program backed up in the CPU2 application backup area in the first flash memory module to the CPU2; the CPU2 writes the received CPU2 program into the CPU2 application temporary storage area of ​​the second flash memory module; the CPU1 performs program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module, and the CPU2 performs program recovery based on the CPU2 program stored in the CPU2 application temporary storage area of ​​the second flash memory module.

[0008] According to a fourth aspect of the present invention, the present invention provides a program backup method for a dual-core chip, comprising: the CPU1 receives a program backup instruction; the CPU2 sends the CPU2 program in the CPU2 application execution area in the second flash memory module to the CPU1; the CPU1 writes the received CPU2 program into the CPU2 application backup area of ​​the first flash memory module; the CPU1 sends the CPU1 program in the CPU1 application execution area in the first flash memory module to the CPU2; the CPU2 writes the received CPU1 program into the CPU1 application backup area of ​​the second flash memory module.

[0009] Compared with the prior art, the dual-core chip in the present invention can safely and quickly perform cross-backup and rapid recovery without using an external storage device to prevent a single chip program error from causing the system to fail to operate normally under special circumstances, thereby extending the service life of the entire embedded system and the anti-interference ability of the entire system.

[0010] Other objects, features and advantages of the present invention will be described in detail below in conjunction with the accompanying drawings in the specific implementation manner.

Brief Description of the Drawings

[0011] The present invention will be more easily understood with reference to the accompanying drawings and the following detailed description, wherein like reference numerals correspond to like structural components, wherein:

[0012] Figure 1 is a schematic diagram of the structure of a dual-core chip in one embodiment of the present invention;

[0013] Figure 2 for Figure 1 The flowchart of the program recovery method of the dual-core chip in one embodiment is shown;

[0014] Figure 3 for Figure 1 The flowchart of the program recovery method of the dual-core chip in another embodiment is shown;

[0015] Figure 4 for Figure 1 The diagram shown is a flow chart of a program backup method for a dual-core chip in one embodiment. [Specific implementation method]

[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The term "one embodiment" or "embodiment" as used herein means that a particular feature, structure or characteristic associated with the embodiment may be included in at least one implementation of the present invention. The term "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor does it necessarily refer to a separate or selected embodiment that is mutually exclusive with other embodiments. The terms "multiple" and "several" in the present invention mean two or more. The term "and / or" in the present invention means "and" or "or".

[0018] Please refer to Figure 1 As shown, it is a schematic diagram of the structure of a dual-core chip in one embodiment of the present invention. Figure 1 The dual-core chip 110 shown includes a first central processing unit (CPU) CPU1 , a second central processing unit CPU2 , a first flash memory module 112 (or flash memory) and a second flash memory module 114 .

[0019] The first central processing unit CPU1 is communicatively connected to the second central processing unit CPU2 via an internal communication bus; the first flash memory module 112 is operated by the first central processing unit CPU1 (or the first central processing unit CPU1 performs permission management on the first flash memory module 112); the second flash memory module 114 is operated by the second central processing unit CPU2 (or the second central processing unit CPU2 performs permission management on the second flash memory module 114).

[0020] For the convenience of description, CPU1 is referred to as the first central processing unit CPU1, and CPU2 is referred to as the second central processing unit CPU2 hereinafter.

[0021] The first flash memory module 112 is divided into four areas: the first area is the CPU1 boot loader (BootLoader) area, the second area is the CPU1 application execution area, the third area is the CPU1 application temporary storage area, and the fourth area is the CPU2 application backup area. Among them, the CPU1 boot loader (BootLoader) area is a fixed program, which is used to perform upgrades; the CPU1 application execution area is used to store the application actually running on the CPU1 (or the application running normally on the CPU1); the CPU1 application temporary storage area is used to store the program that the CPU1 is about to upgrade; the CPU2 application backup area is used to back up the complete CPU2 program. The second flash memory module 114 is also divided into four areas: the first area is the CPU2 boot loader (BootLoader) area, the second area is the CPU2 application execution area, the third area is the CPU2 application temporary storage area, and the fourth area is the CPU1 application backup area. Among them, the CPU2 boot loader (BootLoader) area is a fixed program, which is used to perform upgrades; the CPU2 application execution area is used to store the application actually running on CPU2 (or the application running normally on CPU2); the CPU2 application temporary storage area is used to store the program to be upgraded by CPU2; the CPU1 application backup area is used to back up the complete CPU1 program. That is to say, the CPU1 boot loader area and the CPU2 boot loader area are respectively used to store the boot loader of the CPU corresponding thereto, and are respectively used to receive the upgrade application of the CPU corresponding thereto and perform the upgrade; the CPU1 application execution area and the CPU2 application execution area are respectively used to store the application actually running on the CPU corresponding thereto; the CPU1 application temporary storage area and the CPU2 application temporary storage area are respectively used to store the program to be upgraded by the CPU corresponding thereto; the CPU1 application backup area and the CPU2 application backup area are respectively used to back up the complete program of the other CPU, that is, to back up the CPU2 program in CPU1 and to back up the CPU1 program in CPU2.

[0022] exist Figure 1 In the specific embodiment shown, the first flash memory module 112 is located inside the first central processing unit CPU1, that is, the first flash memory module 112 is the internal Flash of the first central processing unit CPU1; the second flash memory module 114 is located inside the second central processing unit CPU2, that is, the second flash memory module 114 is the internal Flash of the second central processing unit CPU2.

[0023] There are two peripherals related to the upgrade, one is an internal communication bus, which connects CPU1 and CPU2 and is used for communication between CPU1 and CPU2; the other is an external communication bus, which can be I2C, SPI, SCI, CAN, etc., which is used for communication (or communication) between the dual-core chip 110 and the external communication device 120.

[0024] Please refer to Figure 2 As shown, it is Figure 1 The diagram shown is a flow chart of a program recovery method for a dual-core chip in one embodiment. Figure 2 The program recovery method of the dual-core chip shown is that the dual-core chip 110 finds the program abnormality and actively recovers it. Taking CPU1 as an example, the following is specifically introduced. Figure 1 The program recovery method of CPU1 in the dual-core chip shown includes the following steps.

[0025] Step 201, CPU1 detects whether the system is normal (or whether the CPU1 self-check program is normal). If it is normal (yes), continue to detect; if it is abnormal (no), go to step 2.

[0026] Step 202: CPU1 stops working and starts the recovery program.

[0027] Step 203: CPU1 notifies CPU2 to stop working via the internal communication bus.

[0028] Step 204 , CPU2 sends the CPU1 program in the CPU1 application program backup area backed up in the FLASH (ie, the second flash memory module) 114 of CPU2 to CPU1 through the internal communication bus.

[0029] Step 205 , CPU1 starts to verify the received CPU1 program. If the program passes the verification (yes), the process proceeds to step 208 ; if the program fails the verification (no), the process proceeds to step 206 .

[0030] Step 206, determine whether the verification fails more than three times, if more than three times (yes), go to step 207, if not more than three times (no), go to step 204.

[0031] Step 207: Send a recovery failure instruction via the external communication bus, and end.

[0032] Step 208 , CPU1 writes the received CPU1 program into the CPU1 application program temporary storage area of ​​the FLASH (ie, the first flash memory module) 112 of CPU1 .

[0033] Step 209: CPU1 sets the program update flag high.

[0034] Step 210: CPU1 and CPU2 restart and enter their respective BootLoaders.

[0035] Step 211, CPU1 moves the CPU1 program from the CPU1 program temporary storage area of ​​its internal FLASH (ie, the first flash memory module) 112 to the CPU1 program execution area.

[0036] Step 212: CPU 1 resets the program update flag.

[0037] Step 213: CPU1 and CPU2 restart and enter their respective BootLoaders (boot loaders).

[0038] Step 214: CPU1 and CPU2 run normally. Specifically, CPU1 and CPU2 load their respective application program execution area data and start running normally. For example, CPU1 loads the data of the CPU1 program execution area of ​​its internal Flash (i.e., the first flash memory module) 112; CPU2 loads the data of the CPU1 program execution area of ​​its internal Flash (i.e., the second flash memory module) 114.

[0039] Step 215: CPU1 sends a recovery success instruction via the external communication bus, and the process ends.

[0040] It should be noted that Figure 1 The program recovery method of CPU2 in the dual-core chip shown is the same as the above Figure 2 The program recovery method of CPU1 in the dual-core chip shown is similar, so it will not be repeated here.

[0041] Please refer to Figure 3 As shown, it is Figure 1 The diagram shown is a flow chart of a program recovery method for a dual-core chip in another embodiment. Figure 3 The program recovery method of the dual-core chip shown is to send instructions through external communication to recover the programs of CPU1 and CPU2. Figure 3 The program recovery method of the dual-core chip shown includes the following steps.

[0042] Step 301 : CPU 1 receives a program recovery instruction based on an external communication bus and starts to execute recovery.

[0043] Step 302: CPU1 stops working.

[0044] Step 303: CPU1 notifies CPU2 to stop working via the internal communication bus.

[0045] Step 304 , CPU2 sends the CPU1 program in the CPU1 application program backup area backed up in the FLASH (ie, the second flash memory module) 114 of CPU2 to CPU1 through the internal communication bus.

[0046] Step 305 , CPU1 starts to verify the received CPU1 program. If the program passes the verification (yes), the process proceeds to step 308 ; if the program fails the verification (no), the process proceeds to step 306 .

[0047] Step 306, determine whether the verification fails more than three times, if more than three times (yes), go to step 307, if not more than three times (no), go to step 304.

[0048] Step 307: Send a recovery failure instruction via the external communication bus, and end.

[0049] Step 308 , CPU1 writes the received CPU1 program into the CPU1 application program temporary storage area of ​​the FLASH (ie, the first flash memory module) 112 of CPU1 .

[0050] Step 309 , CPU1 sends the CPU2 program in the CPU2 application program backup area backed up in the FLASH (ie, the first flash memory module) 112 of CPU1 to CPU2 via the internal communication bus.

[0051] Step 310, CPU2 starts to verify the received CPU2 program. If the program passes the verification (yes), it goes to step 312; if the program fails the verification (no), it goes to step 311.

[0052] Step 311, determine whether the verification fails more than three times, if more than three times (yes), go to step 307, if not more than three times (no), go to step 309.

[0053] Step 312 , CPU2 writes the received CPU2 program into the CPU2 application program temporary storage area of ​​the FLASH (ie, the second flash memory module) 114 of CPU2 .

[0054] Step 313: CPU1 and CPU2 set the program update flag high.

[0055] Step 314: CPU1 and CPU2 restart and enter their respective BootLoaders.

[0056] Step 315, CPU1 and CPU2 move (or copy) data from the program temporary storage area of ​​their respective internal Flash to the program execution area. Specifically, CPU1 and CPU2 determine that the program update flag is high, and start copying data from their respective program temporary storage areas to the program execution area. For example, CPU1 copies data (for example, the aforementioned CPU1 program) from the CPU1 application temporary storage area of ​​its internal Flash (i.e., the first flash memory module) 112 to the CPU1 program execution area; CPU2 copies data (for example, the aforementioned CPU2 program) from the CPU2 application temporary storage area of ​​its internal Flash (i.e., the second flash memory module) 114 to the CPU2 program execution area.

[0057] Step 316: CPU1 and CPU2 reset the program update flag.

[0058] Step 317: CPU1 and CPU2 restart and enter their respective BootLoaders (boot loaders).

[0059] Step 318: CPU1 and CPU2 run normally. Specifically, CPU1 and CPU2 load their respective application program execution area data and start running normally. For example, CPU1 loads the data of the CPU1 program execution area of ​​its internal Flash (i.e., the first flash memory module) 112; CPU2 loads the data of the CPU1 program execution area of ​​its internal Flash (i.e., the second flash memory module) 114.

[0060] Step 319: CPU1 sends a recovery success instruction via the external communication bus and ends.

[0061] Please refer to Figure 4 As shown, it is Figure 1 The diagram shown is a flow chart of a program backup method for a dual-core chip in one embodiment. Figure 4 The program backup method of the dual-core chip shown is to send instructions through external communication to back up the programs of CPU1 and CPU2. Figure 4 The program backup method of the dual-core chip shown includes the following steps.

[0062] Step 401 : CPU 1 receives a program backup instruction based on an external communication bus and starts to perform backup.

[0063] Step 402, CPU2 sends the CPU2 program in the CPU2 application program execution area in the CPU2 internal FLASH (i.e., the second flash memory module) 114 to CPU1 via the internal communication bus;

[0064] Step 403, CPU1 starts to verify the received CPU2 program. If the program passes the verification (yes), it goes to step 406; if the program fails the verification (no), it goes to step 404.

[0065] Step 404, determine whether the verification fails more than three times (or is repeated three times), if more than three times (yes), go to step 405, if not more than three times (no), go to step 402.

[0066] Step 405: Send a backup failure instruction via the external communication bus, and end.

[0067] Step 406 : CPU1 writes the received CPU2 program into the CPU2 application program backup area of ​​the FLASH (ie, the first flash memory module) 112 of CPU1 .

[0068] Step 407, CPU1 sends the CPU1 program in the CPU1 application program execution area in the CPU1 internal FLASH (i.e., the first flash memory module) 112 to CPU2 via the internal communication bus;

[0069] Step 408 , CPU2 starts to verify the received CPU1 program. If the program passes the verification (yes), it goes to step 410 ; if the program fails the verification (no), it goes to step 409 .

[0070] Step 409, determine whether the verification fails more than three times (or is repeated three times), if more than three times (yes), go to step 405, if not more than three times (no), go to step 407.

[0071] Step 410 , CPU2 writes the received CPU1 program into the CPU1 application program backup area of ​​the FLASH (ie, the second flash memory module) 114 of CPU2 .

[0072] Step 411: Send a backup success instruction via the external communication bus, and end.

[0073] In summary, the dual-core chip in the present invention realizes program backup and recovery simply and reliably by utilizing the internal Flash space of the chip, thereby improving the MTBF (mean time between failures) of the entire system and improving the anti-interference recovery capability of the entire embedded system.

[0074] In the present invention, words such as "connect", "connected", "connect", "connected" and the like indicating electrical connection or communication connection, unless otherwise specified, indicate direct or indirect electrical or communication connection. "Coupled" herein refers to indirect or direct electrical connection, and indirect connection may be electrical connection through one or more electrical devices (such as resistors, capacitors, inductors, etc.).

[0075] The above description has fully disclosed the specific embodiments of the present invention. It should be pointed out that any changes made by those skilled in the art to the specific embodiments of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the above specific embodiments.

Claims

1. A dual-core chip, characterized in that: It includes: A first central processing unit CPU1, referred to as CPU1; A second central processing unit CPU2, which is referred to as CPU2; A first flash memory module, which is operated by the first central processing unit CPU1, and includes a CPU1 boot loader area, a CPU1 application execution area, a CPU1 application temporary storage area, and a CPU2 application backup area; A second flash memory module, which is operated by the second central processing unit CPU2, and includes a CPU2 boot loader area, a CPU2 application execution area, a CPU2 application temporary storage area and a CPU1 application backup area; An internal communication bus, which is used for communication connection between the first central processing unit CPU1 and the second central processing unit CPU2; The external communication bus is used for the first central processing unit CPU1 and the second central processing unit CPU2 to communicate with the outside world. The CPU1 boot loader area and the CPU2 boot loader area are used to perform upgrades on the corresponding CPUs respectively; The CPU1 application program execution area and the CPU2 application program execution area are respectively used to store the application programs actually run by the corresponding CPUs; The CPU1 application temporary storage area and the CPU2 application temporary storage area are respectively used to store the programs to be upgraded by the corresponding CPUs; The CPU1 application backup area is used to back up the complete CPU1 program, and the CPU2 application backup area is used to back up the complete CPU2 program. The CPU1 is used to detect whether the system is normal. If it is normal, the detection continues. Otherwise, the CPU1 stops working. The CPU1 is also used to notify the CPU2 to stop working after stopping working. The CPU2 is used to send the CPU1 program backed up in the CPU1 application backup area of ​​the second flash memory module to the CPU1. The CPU1 is also used to write the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module. The CPU1 is also used to perform program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module, or The CPU1 is used to receive a program recovery instruction and stop working; the CPU1 is also used to notify the CPU2 to stop working after stopping working; the CPU2 is used to send the CPU1 program backed up in the CPU1 application backup area in the second flash memory module to the CPU1; the CPU1 is also used to write the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module; the CPU1 is also used to send the CPU2 program backed up in the CPU2 application backup area in the first flash memory module to the CPU2; the CPU2 is also used to write the received CPU2 program into the CPU2 application temporary storage area of ​​the second flash memory module; the CPU1 is also used to perform program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module, and the CPU2 is also used to perform program recovery based on the CPU2 program stored in the CPU2 application temporary storage area of ​​the second flash memory module, The CPU1 is used to receive a program backup instruction; the CPU2 is used to send the CPU2 program in the CPU2 application execution area in the second flash memory module to the CPU1; the CPU1 is also used to write the received CPU2 program into the CPU2 application backup area of ​​the first flash memory module; The CPU1 is further configured to send the CPU1 program in the CPU1 application execution area in the first flash memory module to the CPU2; the CPU2 is further configured to write the received CPU1 program into the CPU1 application backup area in the second flash memory module.

2. The dual-core chip according to claim 1 is characterized in that: The first flash memory module is located inside the first central processing unit CPU1; The second flash memory module is located inside the second central processing unit CPU2.

3. The program recovery method of a dual-core chip according to any one of claims 1-2, characterized in that: It includes: The CPU 1 detects whether the system is normal, and if it is normal, the CPU 1 continues to detect, otherwise, the CPU 1 stops working; After the CPU1 stops working, it notifies the CPU2 to stop working; The CPU2 sends the CPU1 program backed up in the CPU1 application program backup area of ​​the second flash memory module to the CPU1; The CPU1 writes the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module; The CPU1 performs program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module.

4. The program recovery method of a dual-core chip according to claim 3, characterized in that: The method comprises the steps of performing a program check on the received CPU1 program before the CPU1 writes the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module. The step of CPU1 performing program verification on the received CPU1 program includes: The CPU1 starts to verify the received CPU1 program. If the program passes the verification, the CPU1 enters the step of "the CPU1 writes the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module". Otherwise, it is determined whether the verification fails for more than a predetermined number of times; If the predetermined number of times is exceeded, a recovery failure instruction is sent through the external communication bus, otherwise the process returns to the step of "the CPU2 sends the CPU1 program backed up in the CPU1 application backup area of ​​the second flash memory module to the CPU1".

5. The program recovery method of a dual-core chip according to claim 3, characterized in that: The step of "the CPU1 performs program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module" includes: The CPU1 sets the program update flag high; The CPU1 and CPU2 restart and enter their respective boot loaders; The CPU1 moves the CPU1 program from the CPU1 program temporary storage area of ​​the first flash memory module to the CPU1 program execution area; The CPU1 resets the program update flag; The CPU1 and CPU2 restart again and enter their respective boot loaders; CPU1 and CPU2 load the CPU program in the application execution area of ​​their corresponding flash memory modules and start normal operation Send a recovery success command via the external communication bus.

6. The program recovery method of a dual-core chip according to any one of claims 1-2, characterized in that: It includes: The CPU 1 receives a program recovery instruction; The CPU1 stops working; After the CPU1 stops working, the CPU2 is notified to stop working; The CPU2 sends the CPU1 program backed up in the CPU1 application program backup area in the second flash memory module to the CPU1; The CPU1 writes the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module; The CPU1 sends the CPU2 program backed up in the CPU2 application program backup area in the first flash memory module to the CPU2; The CPU2 writes the received CPU2 program into the CPU2 application temporary storage area of ​​the second flash memory module; The CPU1 performs program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module, and the CPU2 performs program recovery based on the CPU2 program stored in the CPU2 application temporary storage area of ​​the second flash memory module.

7. The program recovery method of a dual-core chip according to claim 6, characterized in that: The method comprises the steps of performing a program check on the received CPU1 program before the CPU1 writes the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module. The step of CPU1 performing program verification on the received CPU1 program includes: The CPU1 starts to verify the received CPU1 program. If the program passes the verification, the CPU1 enters the step of "the CPU1 writes the received CPU1 program into the CPU1 application temporary storage area of ​​the first flash memory module". Otherwise, it is determined whether the verification fails for more than a predetermined number of times; If the predetermined number of times is exceeded, a recovery failure instruction is sent through the external communication bus, otherwise the process returns to the step of "the CPU2 sends the CPU1 program backed up in the CPU1 application backup area in the second flash memory module to the CPU1".

8. The program recovery method of a dual-core chip according to claim 6, characterized in that: The method includes the step of performing a program check on the received CPU2 program before the CPU2 writes the received CPU2 program into the CPU2 application temporary storage area of ​​the second flash memory module. The step of CPU2 performing program verification on the received CPU2 program includes: The CPU2 starts to verify the received CPU2 program. If the program passes the verification, the CPU2 enters the step of "the CPU2 writes the received CPU2 program into the CPU2 application temporary storage area of ​​the second flash memory module". Otherwise, it is determined whether the verification fails for more than a predetermined number of times. If the predetermined number of times is exceeded, a recovery failure instruction is sent through the external communication bus, otherwise the process returns to the step of "the CPU1 sends the CPU2 program backed up in the CPU2 application backup area in the first flash memory module to the CPU2".

9. The program recovery method of a dual-core chip according to claim 6, characterized in that: The step of "the CPU1 performs program recovery based on the CPU1 program stored in the CPU1 application temporary storage area of ​​the first flash memory module, and the CPU2 performs program recovery based on the CPU2 program stored in the CPU2 application temporary storage area of ​​the second flash memory module" includes: The CPU1 and CPU2 set the program update flag high; The CPU1 and CPU2 restart and enter their respective boot loaders; The CPU1 and CPU2 move the corresponding CPU programs from the program temporary storage area in the corresponding flash memory module to the program execution area; The CPU1 and CPU2 reset the program update flag; The CPU1 and CPU2 restart again and enter their respective boot loaders; The CPU1 and CPU2 load the CPU programs in the application program execution areas in the corresponding flash memory modules and start normal operation; Send the upgrade success instruction through the external communication bus.

10. The program backup method of a dual-core chip according to any one of claims 1-2, characterized in that: It includes: The CPU 1 receives a program backup instruction; The CPU2 sends the CPU2 program in the CPU2 application program execution area in the second flash memory module to the CPU1; The CPU1 writes the received CPU2 program into the CPU2 application program backup area of ​​the first flash memory module; The CPU1 sends the CPU1 program in the CPU1 application program execution area in the first flash memory module to the CPU2; The CPU2 writes the received CPU1 program into the CPU1 application program backup area of ​​the second flash memory module.

11. The program backup method of a dual-core chip according to claim 10, characterized in that: The method comprises the steps of: before the CPU1 writes the received CPU2 program into the CPU2 application program backup area of ​​the first flash memory module, the CPU1 performs a program check on the received CPU2 program; The step of CPU1 performing program verification on the received CPU2 program includes: The CPU1 starts to verify the received CPU2 program. If the program passes the verification, the CPU1 enters the step of "the CPU1 writes the received CPU2 program into the CPU2 application program backup area of ​​the first flash memory module". Otherwise, it is determined whether the verification fails for more than a predetermined number of times. If the predetermined number of times is exceeded, a recovery failure instruction is sent through the external communication bus, otherwise the process returns to the step of "the CPU2 sends the CPU2 program in the CPU2 application execution area in the second flash memory module to the CPU1".

12. The program backup method of a dual-core chip according to claim 10, characterized in that: The method comprises the steps of: before the CPU2 writes the received CPU1 program into the CPU1 application program backup area of ​​the second flash memory module, the CPU2 performs a program check on the received CPU1 program; The step of CPU2 performing program verification on the received CPU1 program includes: The CPU2 starts to verify the received CPU1 program. If the program passes the verification, the CPU2 enters the step of "the CPU2 writes the received CPU1 program into the CPU1 application program backup area of ​​the second flash memory module". Otherwise, it is determined whether the verification fails for more than a predetermined number of times. If the predetermined number of times is exceeded, a recovery failure instruction is sent through the external communication bus, otherwise the process returns to the step of "the CPU1 sends the CPU1 program in the CPU1 application execution area in the first flash memory module to the CPU2".

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