Method, apparatus, electronic device and computer storage medium for detecting a deep learning chip

Abstract

Embodiments of the present disclosure relate to a method, apparatus, electronic device, and computer-readable storage medium for detecting a deep learning chip. The method includes detecting a plurality of logic units in the deep learning chip, where the plurality of logic units are used to perform at least one of an inference operation and a training operation of deep learning. The method further includes obtaining error units that fail the detection among the plurality of logic units. In addition, the method may further include determining that the deep learning chip is a qualified chip in response to a ratio of the number of error units to the total number of the plurality of logic units being lower than or equal to a predetermined ratio. The technical solution of the present disclosure makes use of the characteristic that a deep learning chip includes a plurality of identical or repeated logic units, thereby significantly improving the chip utilization rate.

Description

Technical Field

[0001] Embodiments of the present disclosure mainly relate to the field of chip detection, and more specifically, to methods, devices, electronic devices, and computer-readable storage media for detecting deep learning chips. Background Art

[0002] The availability rate (or "yield rate") of a chip generally refers to the ratio between the chips that pass the test and the total chips within a wafer, a batch, or the life cycle of a product. Due to the possible presence of randomly dropped dust or other particles in the production environment, and the possible defects in the integrated circuit design process, the chip utilization rate is relatively low. For current deep learning chips (or "artificial intelligence chips"), they usually contain multiple inference logic units and multiple training logic units. If any logic unit in the chip has a flaw, the chip will be marked as failed the test. The cost of a chip is linearly related to the chip utilization rate. The lower the utilization rate, the higher the cost. Therefore, the chip utilization rate has a huge impact on the chip cost, and improving the chip utilization rate is very important for enhancing the competitiveness of the chip. Summary of the Invention

[0003] According to an exemplary embodiment of the present disclosure, a solution for detecting a deep learning chip is provided.

[0004] In a first aspect of the present disclosure, a method for detecting a deep learning chip is provided. The method includes detecting a plurality of logic units in the deep learning chip, where the plurality of logic units are used to perform at least one of the inference operation and the training operation of deep learning. The method further includes obtaining error units that fail the detection among the plurality of logic units. In addition, the method may further include determining the deep learning chip as a qualified chip in response to the ratio of the number of error units to the total number of the plurality of logic units being less than or equal to a predetermined ratio.

[0005] In a second aspect of the present disclosure, a device for detecting a deep learning chip is provided. The device includes: a logic unit detection module configured to detect a plurality of logic units in the deep learning chip, where the plurality of logic units are used to perform at least one of the inference operation and the training operation of deep learning; an error unit obtaining module configured to obtain error units that fail the detection among the plurality of logic units; and a qualified chip determination module configured to determine the deep learning chip as a qualified chip in response to the ratio of the number of error units to the total number of the plurality of logic units being less than or equal to a predetermined ratio.

[0006] In a third aspect of the present disclosure, there is provided a device, including one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement the method according to the first aspect of the present disclosure.

[0007] In a fourth aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the method according to the first aspect of the present disclosure.

[0008] In a fifth aspect of the present disclosure, there is provided a computer program product including a computer program, which, when executed by a processor, implements the method according to the first aspect.

[0009] It should be understood that the content described in the Summary of the Invention section is not intended to limit the key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0011] Figure 1 A schematic diagram showing an example environment in which multiple embodiments of the present disclosure can be implemented;

[0012] Figure 2 A schematic diagram showing a deep learning chip according to an embodiment of the present disclosure;

[0013] Figure 3 A flowchart showing a process for detecting a deep learning chip according to an embodiment of the present disclosure;

[0014] Figure 4 A schematic block diagram showing a device for detecting a deep learning chip according to an embodiment of the present disclosure; and

[0015] Figure 5 A block diagram showing a computing device capable of implementing multiple embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure.

[0017] In the description of the embodiments of the present disclosure, the term "comprising" and its like should be understood as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0018] As mentioned above, there is an urgent need for a deep learning chip detection method to quickly, efficiently and low-costly detect deep learning chips, thereby improving chip utilization. Traditional deep learning chip detection methods usually detect deep learning chips. Once the deep learning chip fails the detection, it is considered that the deep learning chip is unavailable. Even if only one logic unit in the deep learning chip is a faulty unit and the rest of the logic units are intact, the deep learning chip will still be regarded as a faulty chip. Therefore, traditional deep learning chip detection methods cause a great waste of deep learning chips.

[0019] According to an embodiment of the present disclosure, a solution for detecting a deep learning chip is proposed. In this solution, multiple logic units in the deep learning chip to be tested can be detected. Once a faulty unit is found, the ratio of the number of faulty units to the total number of logic units on the deep learning chip is compared with a predetermined ratio. If it does not exceed the predetermined threshold, it is considered that the deep learning chip is still a qualified chip. Specifically, multiple inference logic units of the deep learning chip can be detected. Since there are limitations in power consumption for current deep learning chips, not all of the inference logic units on them usually work. Therefore, even if an individual inference logic unit is detected as a faulty unit, only the information of the faulty chip needs to be stored, and the faulty unit is disabled when the deep learning chip is used. Since the chip detection solution of the present disclosure refines the criteria for determining that a chip is unqualified, the chip utilization rate is improved and the cost reduction is extremely significant.

[0020] Embodiments of the present disclosure will be specifically described below with reference to the accompanying drawings. Figure 1 A schematic diagram of an example environment 100 in which multiple embodiments of the present disclosure can be implemented is shown. As Figure 1As shown, the example environment 100 includes a detection device 110, a chip under test 120, and a detection result 130. The chip under test 120 can be a deep learning chip applied in a data center, which can support business scenarios based on deep learning algorithms such as speech recognition, image processing, machine translation, search recommendation, etc. The detection device 110 can receive the chip under test 120 and determine the detection result 130 of the chip under test 120 through techniques such as automatic test equipment (ATE) scanning.

[0021] In Figure 1 , the key to generating the detection result 130 of the chip under test 120 lies in two points. First, the detection device 110 detects multiple logic units on the chip under test 120. It should be noted that the chip under test 120 used for detection here can be a chip that has never been detected or a chip that has not passed the detection of traditional detection devices. Second, after detecting a faulty logic unit, the detection device 110 needs to further determine whether the ratio of the faulty unit to all logic units is small enough. If it is small enough, the chip under test 120 can still be determined to be a qualified chip, thereby significantly improving the chip utilization rate reflected in the test result 130. The following will use Figure 2 to describe in detail the structure of the chip under test 120 containing multiple logic units.

[0022] Figure 2 shows a schematic diagram of the deep learning chip 120 according to an embodiment of the present disclosure. As Figure 2 shown, the deep learning chip 120 includes multiple inference logic units 210, 211, …, M for performing inference operations of deep learning and training logic units 220, 221, … N for performing training operations of deep learning. In addition, the deep learning chip 120 further includes a storage unit 230 such as an on-chip electrically programmable fuse (eFUSE) for recording information of faulty units.

[0023] For the purpose of clarity, the Figure 2 of the present disclosure only shows several logic units and the storage unit, and does not show other functional units. In addition, it should be understood that only for illustrative purposes, describing the structure and function of the deep learning chip 120 is not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. As an example, in addition to the storage unit 230 and other necessary components, the deep learning chip 120 can only include multiple inference logic units 210, 211, …, M for performing inference operations of deep learning or training logic units 220, 221, … N for performing training operations of deep learning. To more clearly explain the principle of the above solution, the following will refer to Figure 3 to describe in more detail the process of detecting the deep learning chip.

[0024] Figure 3 FIG. 300 is a flowchart of a process for detecting a deep learning chip according to an embodiment of the present disclosure. The process 300 may be implemented by a Figure 1 detection device 110. For the convenience of discussion, the process 300 will be described in conjunction with Figure 1 and Figure 2 .

[0025] At 310, the detection device 110 detects a plurality of logic units in the deep learning chip that is the chip 120 to be tested. As an example, if the chip 120 to be tested is an inference chip for deep learning, then at this time, the plurality of logic units are used to perform inference operations of deep learning. In addition, the chip 120 to be tested may also be a training chip for deep learning, then at this time, the plurality of logic units are used to perform training operations of deep learning. In addition, the chip 120 to be tested may also be an inference and training chip, which is used to perform at least one of inference operations and training operations. As Figure 2 shown, the detection device 110 detects the inference logic units 210, 211, …, M for performing inference operations of deep learning and the training logic units 220, 221, … N for performing training operations of deep learning included in the chip 120 to be tested.

[0026] At 320, the detection device 110 obtains the error units that fail the detection among the above-mentioned plurality of logic units. As an example, Figure 2 any of the inference logic units 210, 211, …, M or any of the training logic units 220, 221, … N in

[0027] At 330, the detection device 110 compares the ratio of the number of faulty units to the total number of logic units on the chip 120 to be tested with a predetermined ratio. As an example, the predetermined ratio can be 5%, 10%, 15% or other ratios, and the magnitude of the predetermined ratio depends on the power limit of the chip 120 to be tested. Taking the inference logic units as an example, since the chip 120 to be tested, as a deep learning chip, has a power limit, not all the inference logic units in the chip 120 to be tested will work simultaneously. Therefore, there are almost always idle inference logic units in the chip 120 to be tested for replacing faulty units. Thus, as long as the number of faulty units is not too high, there will be enough idle inference logic units to replace the faulty units. Also, traditional redundancy design methods are not applicable to the various logic units in deep learning chips because this will cause a significant increase in the manufacturing cost of the chip. Next, if the ratio is lower than or equal to the predetermined ratio, the process proceeds to 340.

[0028] At 340, the detection device 110 determines the deep learning chip, which is the chip 120 to be tested, as a qualified chip. Taking the inference logic units as an example, if the above-mentioned multiple logic units in the chip 120 to be tested only include multiple inference logic units for performing inference operations, and if the ratio of the number of faulty units to the total number of inference logic units on the chip 120 to be tested is lower than or equal to the predetermined ratio, the information of the faulty units is recorded in the storage unit 230 of the chip 120 to be tested so as to disable the faulty units when the chip 120 to be tested is used to perform inference operations. In this way, a large part of the chips that fail to pass the traditional detection device can be reused, avoiding unnecessary waste.

[0029] In addition, taking the training logic units as an example, if the above-mentioned multiple logic units in the chip 120 to be tested only include multiple training logic units for performing training operations, and if the ratio of the number of faulty units to the total number of training logic units on the chip 120 to be tested is lower than or equal to the predetermined ratio, the information of the faulty units is recorded in the storage unit 230 of the chip 120 to be tested so as to disable the faulty units when the chip 120 to be tested is used to perform training operations. In this way, the chip utilization rate can also be improved and waste can be avoided.

[0030] In some embodiments, the chip 120 to be tested can be a deep learning chip that includes both inference logic units and training logic units. Therefore, the above-mentioned multiple logic units can be as Figure 2The illustration includes multiple inference logic units 210, 211, …, M for performing inference operations and multiple training logic units 220, 221, … N for performing training operations. At this time, if there are faulty units among the multiple inference logic units 210, 211, …, M, the chip under test 120 is set to be only used for performing deep learning training operations, and if there are faulty units among the multiple training logic units 220, 221, … N, the chip under test 120 is set to be only used for performing deep learning inference operations. Alternatively or additionally, if there are no faulty units among the multiple training logic units 220, 221, … N, the chip under test 120 is set to be used for performing at least one of deep learning inference operations and training operations. In this way, some functions of the deep learning chip can be selectively discarded, but other parts of the deep learning chip are still available.

[0031] In some embodiments, if the ratio of the number of faulty units to the total number of logic units is higher than a predetermined ratio, the detection device 110 determines the deep learning chip as the chip under test 120 to be a faulty chip.

[0032] In the present disclosure, the storage unit 230 can be an on-chip electrically programmable fuse, and the multiple inference logic units 210, 211, …, M can be at least one of the artificial intelligence co-processing unit SDCDNN and the artificial intelligence processor XPU.

[0033] According to one or more embodiments of the present disclosure, the detection result 130 can be obtained. Due to the utilization of the characteristic that the deep learning chip contains multiple identical or repetitive logic units, the detection device 110 tolerates the situation where there are a small number of faulty units in the chip under test 120, making the chip utilization rate of the detection result 130 significantly higher than that of the detection results of traditional detection devices.

[0034] Compared with the traditional technology, the significance of the solution of the present disclosure lies in that by refining the chip detection operation to detect each logic unit in the deep learning chip, without increasing the chip area and without affecting the normal working performance of the chip, it is possible for the logic units other than SRAM on the deep learning chip mentioned above, which account for 70% of the chip area, to have production errors, and most of the chips with faulty units can be utilized, thus significantly improving the utilization rate of the deep learning chip, reducing the chip cost, and further increasing the market competitiveness of the chip.

[0035] The above discussion has presented a detection scheme for a deep learning chip that integrates an inference logic unit and a training logic unit in some example scenarios. However, it should be understood that the description of these scenarios is only for illustrative purposes to explain the embodiments of the present disclosure. Depending on actual needs, different detection objects can also be selected in different or similar scenarios. The technical solution of the present disclosure can also have various advantages mentioned above when applied to detecting other repetitive units in a deep learning chip.

[0036] Figure 4 FIG. 4 shows a schematic block diagram of a device 400 for detecting a deep learning chip according to an embodiment of the present disclosure. The device 400 may be included in Figure 1 the detection device 110, or may be implemented as the detection device 110. As Figure 4 shown, the device 400 may include a logic unit detection module 410 configured to detect a plurality of logic units in the deep learning chip, the plurality of logic units being configured to perform at least one of an inference operation and a training operation of deep learning. The device 400 may further include an error unit acquisition module 420 configured to acquire error units that fail the detection among the plurality of logic units. In addition, the device 400 may further include a qualified chip determination module 430 configured to determine the deep learning chip as a qualified chip in response to a ratio of the number of error units to the total number of the plurality of logic units being less than or equal to a predetermined ratio.

[0037] In some embodiments, the plurality of logic units may include a plurality of inference logic units for performing inference operations, and the qualified chip determination module 430 may include a first information recording module (not shown) configured to record information of the error units in a storage unit of the deep learning chip so as to disable the error units when the deep learning chip is used to perform inference operations.

[0038] In some embodiments, the plurality of logic units may include a plurality of training logic units for performing training operations, and the qualified chip determination module 430 may include a second information recording module (not shown) configured to record information of the error units in a storage unit of the deep learning chip so as to disable the error units when the deep learning chip is used to perform training operations.

[0039] In some embodiments, the multiple logic units may include multiple inference logic units for performing inference operations and multiple training logic units for performing training operations. The apparatus 400 may further include a training operation setting module (not shown), which is configured to set the deep learning chip to be only used for performing deep learning training operations in response to the presence of faulty units among the multiple inference logic units. Alternatively, the apparatus 400 may further include an inference operation setting module (not shown), which is configured to set the deep learning chip to be only used for performing deep learning inference operations in response to the presence of faulty units among the multiple training logic units.

[0040] In some embodiments, the apparatus 400 may further include an operation setting module (not shown), which is configured to set the deep learning chip to be used for performing at least one of deep learning inference operations and training operations in response to the absence of faulty units among the multiple training logic units.

[0041] In some embodiments, the apparatus 400 may further include a faulty chip determination module (not shown), which is configured to determine the deep learning chip as a faulty chip in response to the ratio of the number of faulty units to the total number of multiple logic units being higher than a predetermined ratio.

[0042] In some embodiments, the storage unit may be an on-chip electrically programmable fuse, and the multiple inference logic units may include at least one of the following: an artificial intelligence co-processing unit SDCDNN; and an artificial intelligence processor XPU.

[0043] According to one or more embodiments of the present disclosure, since the apparatus 400 of the above embodiments utilizes the characteristic that the deep learning chip includes multiple identical or repetitive logic units, the apparatus 400 tolerates the situation where a small number of faulty units exist in the deep learning chip, making the chip utilization rate of the detection result significantly higher than that of traditional detection devices.

[0044] Figure 5 A schematic block diagram of an example device 500 that can be used to implement the embodiments of the present disclosure is shown. The device 500 can be used to implement Figure 1 the computing device 110. As shown, the device 500 includes a central processing unit (CPU) 501, which can execute various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 502 or computer program instructions loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The CPU 501, ROM 502, and RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0045] Multiple components in device 500 are connected to I / O interface 505, including: input unit 506, such as a keyboard, mouse, etc.; output unit 507, such as various types of displays, speakers, etc.; storage unit 508, such as a disk, optical disc, etc.; and communication unit 509, such as a network card, modem, wireless communication transceiver, etc. Communication unit 509 allows device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0046] Processing unit 501 executes the various methods and processes described above, such as process 300. For example, in some embodiments, process 300 may be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed onto device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by CPU 501, one or more steps of process 300 described above may be executed. Alternatively, in other embodiments, CPU 501 may be configured to execute process 300 by any other suitable means (e.g., by means of firmware).

[0047] The functions described above herein may be performed, at least in part, by one or more hardware logic components. By way of example and not limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0048] The program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0049] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0050] Moreover, although the operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the present disclosure. Certain features described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately or in any suitable sub-combination in multiple implementations.

[0051] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for detecting a deep learning chip, comprising: Detecting a plurality of logic units in the deep learning chip, the plurality of logic units being configured to perform at least one of an inference operation and a training operation of deep learning; Obtaining error units that fail the detection among the plurality of logic units; And In response to a ratio of the number of the error units to the total number of the plurality of logic units being lower than or equal to a predetermined ratio, determining the deep learning chip as a qualified chip, Wherein the plurality of logic units includes a plurality of inference logic units for performing the inference operation and a plurality of training logic units for performing the training operation, and the method further includes: In response to the error units existing among the plurality of inference logic units, setting the deep learning chip to be only used for performing the training operation of deep learning; Or In response to the error units existing among the plurality of training logic units, setting the deep learning chip to be only used for performing the inference operation of deep learning.

2. The method according to claim 1, wherein determining the deep learning chip as the qualified chip includes: Recording information of the error units in a storage unit of the deep learning chip so as to disable the error units when the deep learning chip is used to perform the inference operation.

3. The method according to claim 1, wherein determining the deep learning chip as the qualified chip includes: Recording information of the error units in a storage unit of the deep learning chip so as to disable the error units when the deep learning chip is used to perform the training operation.

4. The method according to claim 1, further comprising: In response to no error units existing among the plurality of training logic units, setting the deep learning chip to be used for performing at least one of the inference operation and the training operation of deep learning.

5. The method according to claim 1, further comprising: In response to a ratio of the number of the error units to the total number of the plurality of logic units being higher than the predetermined ratio, determining the deep learning chip as a faulty chip.

6. The method according to claim 2, wherein the storage unit is an on-chip electrically programmable fuse, and the plurality of inference logic units includes at least one of the following: Artificial intelligence co-processing unit SDCDNN; and Artificial intelligence processor XPU.

7. A device for detecting a deep learning chip, comprising: A logic unit detection module configured to detect a plurality of logic units in the deep learning chip, the plurality of logic units being configured to perform at least one of an inference operation and a training operation of deep learning; An error unit obtaining module configured to obtain error units that fail the detection among the plurality of logic units; And A qualified chip determining module configured to, in response to a ratio of the number of the error units to the total number of the plurality of logic units being lower than or equal to a predetermined ratio, determine the deep learning chip as a qualified chip, Wherein the multiple logic units include multiple inference logic units for performing the inference operation and multiple training logic units for performing the training operation, and the device further includes: A training operation setting module, configured to set the deep learning chip to only perform the training operation of deep learning in response to the presence of the error unit in the multiple inference logic units; Or An inference operation setting module, configured to set the deep learning chip to only perform the inference operation of deep learning in response to the presence of the error unit in the multiple training logic units.

8. The device according to claim 7, wherein the multiple logic units include multiple inference logic units for performing the inference operation, and wherein the qualified chip determination module includes: A first information recording module, configured to record the information of the error unit in the storage unit of the deep learning chip so as to disable the error unit when the deep learning chip is used to perform the inference operation.

9. The device according to claim 7, wherein the multiple logic units include multiple training logic units for performing the training operation, and wherein the qualified chip determination module includes: A second information recording module, configured to record the information of the error unit in the storage unit of the deep learning chip so as to disable the error unit when the deep learning chip is used to perform the training operation.

10. The device according to claim 7, further includes: An operation setting module, configured to set the deep learning chip to perform at least one of the inference operation and the training operation of deep learning in response to the absence of the error unit in the multiple training logic units.

11. The device according to claim 7, further includes: A faulty chip determination module, configured to determine the deep learning chip as a faulty chip in response to the ratio of the number of error units to the total number of the multiple logic units being higher than the predetermined ratio.

12. The device according to claim 8, wherein the storage unit is an on-chip electrically programmable fuse, and the multiple inference logic units include at least one of the following: An artificial intelligence coprocessor SDCDNN; and An artificial intelligence processor XPU.

13. An electronic device, the electronic device includes: One or more processors; And A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enabling the one or more processors to implement the method according to any one of claims 1-6.

14. A computer-readable storage medium, having a computer program stored thereon, the program when executed by a processor implements the method according to any one of claims 1-6.

15. A computer program product, including a computer program, the computer program when executed by a processor implements the method according to any one of claims 1-6.

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