Method for dividing strips of one or more devices

Abstract

A method for dividing a strip of one or more devices. The strip is composed of an island-shaped III-nitride-based semiconductor layer grown on a substrate using a growth limit mask; the island-shaped III-nitride-based semiconductor layer is removed from the substrate using an epitaxial lateral overgrowth (ELO) method; and then the strip is divided into one or more devices using a cleaving method.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the following co-pending and commonly assigned applications pursuant to 35 U.S.C. Section 119(e):

[0003] U.S. Provisional Application Serial No. 62 / 672,913, filed May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES,” Attorney Docket No. G&C 30794.0681USP1 (UC 2018-605-1);

[0004] This application is incorporated herein by reference.

[0005] This application is related to the following co-pending and co-assigned applications:

[0006] PCT International Patent Application No. PCT / US18 / 31393, filed May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, and entitled “METHOD OF REMOVING A SUBSTRATE,” and attorney docket no. 30794.0653WOU1 (UC 2017-621-2), which claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 502,205, filed May 5, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, and entitled “METHOD OF REMOVING ASUBSTRATE,” and attorney docket no. 30794.0653USP1 (UC 2017-621-1), pursuant to 35 U.S.C. Section 119(e); and

[0007] PCT International Patent Application No. PCT / US18 / 51375, filed on September 17, 2018, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” and attorney docket number 30794.0659WOU1 (UC 2018-086-2), which claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 559,378, filed on September 15, 2017, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” and attorney docket number 30794.0659USP1 (UC 2018-086-1), pursuant to 35 U.S.C. Section 119(e);

[0008] All of the applications described are incorporated herein by reference. Technical Field

[0009] The present invention relates to a method of dividing strips of one or more devices. Background Art

[0010] Today, there are many methods to divide wafers into chips, such as cleaving, laser scribing, dry etching, etc. The present invention focuses on the cleaving method for making laser facets.

[0011] Some device manufacturers have used Group III nitride-based substrates (such as GaN substrates) to manufacture laser diodes (LDs) and light-emitting diodes (LEDs) for light emission, optical storage, etc. In general, in order to manufacture these devices, a wafer needs to be divided into multiple chips. Here, a wafer is formed using a semiconductor layer on a Group III nitride-based substrate.

[0012] However, even if a wafer grown with a homogeneous epitaxial layer on a substrate is used, it is not easy to divide the wafer into multiple chips. This is because the quality of III-nitride-based substrates (such as GaN substrates) is still not good enough for dividing the wafer into chips by splitting the crystal of the substrate. Several defects (such as dislocations and stacking faults) and damage on the surface of the substrate (such as sunken parts and pits) prevent the wafer from being properly split, for example, because the dividing line is not a straight line.

[0013] According to Phys. Status Solid C8 No. 7-8 2226-2228 (2011) by MTHardy et al., an AlGaN layer having a higher Al content of 10% or more can be used as a cleavage assist layer (CAL), wherein the thickness of the CAL is 0.6 μm. In this case, tension is applied from the CAL to the epitaxial layer on the substrate, resulting in stacking faults, dislocations, etc. of the active layer. In the worst case, the tension causes many cracks in the epitaxial layer.

[0014] Accordingly, there is a need in the art for improved methods of dividing epitaxial layers grown on a wafer or substrate into devices. Summary of the invention

[0015] To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a method of dividing an epitaxial layer grown on a wafer or substrate into devices using a cleaving method.

[0016] Specifically, the present invention performs the following steps: growing an island-shaped III-nitride-based semiconductor layer on a substrate using a growth restriction mask and an epitaxial lateral overgrowth (ELO) method; removing the island-shaped III-nitride-based semiconductor layer from the substrate using a polymer film; and then dividing the island-shaped III-nitride-based semiconductor layer into devices using a cleavage method.

[0017] The island-shaped III-nitride semiconductor layers can be grown by metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), etc., and sized so that one or more of the island-shaped III-nitride semiconductor layers form strips (known as semiconductor strips or device strips). By doing so, the cleavage method is not affected by perturbations of the substrate (such as pits, defects, and surface damage). Therefore, a high yield can be obtained with an atomically smooth surface at the cleavage plane.

[0018] In addition, the present invention can use a foreign substrate to grow a III-nitride semiconductor layer in the form of stripe islands. For example, the present invention can use a GaN template grown on a foreign substrate (such as sapphire, Si, GaAs, SiC, etc.).

[0019] In the prior art, when a foreign substrate is used, atomically smooth cleavage facets cannot be obtained due to the difference in cleavage planes between the foreign substrate and the crystal of the epitaxial layer. This is a key issue in the manufacture of laser diode devices, which require atomically smooth facets for lasing. Therefore, laser diode devices using foreign substrates have not yet been commercially manufactured.

[0020] However, with the present invention, even when a foreign substrate is used, a laser diode device having atomically smooth facets suitable for resonance can be obtained. In addition, because the facets are formed after the epitaxial layer is removed from the foreign substrate, the type of substrate does not affect the cleavage method. This advantage of using a foreign substrate will have a significant impact on the large-scale production of devices.

[0021] For example, a substrate of lower cost and larger size than a free-standing GaN substrate can be used, such as sapphire or silicon. This results in a lower cost device. In addition, sapphire, GaAs and other substrates are known as low thermal conductivity materials, so devices using such substrates also have low thermal conductivity. However, because the device is removed from the foreign substrate by using the present invention, it no longer has low thermal conductivity.

[0022] Furthermore, the use of the ELO method can significantly reduce the dislocation density and stacking fault density, which can become critical issues when using foreign substrates.

[0023] Thus, the present invention can simultaneously solve many classes of problems caused by using foreign substrates. For example, in laser diode devices, the cleavage facets can be used as facets of the resonator. In other devices (such as LEDs, etc.), the method of dividing the strips of the device is not affected by the perturbations of the substrate type and substrate quality. Instead, the method can divide the device in an accurate and easy manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Referring now to the drawings, wherein like reference numerals indicate corresponding parts throughout:

[0025] FIG. 1( a ) is a schematic diagram of a substrate, a growth restriction mask, and an epitaxial layer according to an embodiment of the present invention.

[0026] 1( b ) and 1 ( c ) illustrate how island-shaped Group III nitride-based semiconductor layers may be divided after the island-shaped Group III nitride-based semiconductor layers are merged according to one embodiment of the present invention.

[0027] Figure 2 is a schematic diagram of a foreign substrate, a growth restriction mask and an epitaxial layer according to an embodiment of the present invention.

[0028] Figures 3(a), 3(b), 3(c), 3(d), 3(e) and 3(f) are scanning electron microscope (SEM) images of an island-shaped Group III nitride-based semiconductor layer according to an embodiment of the present invention.

[0029] Figure 4 is a cross-sectional view of a laser diode device formed of an island-shaped Group III nitride-based semiconductor layer according to one embodiment of the present invention.

[0030] Figure 5(a), Figure 5(b), Figure 5(c) and 5(d) It is shown how divided support areas can be formed with periodic lengths along the strips of the device according to one embodiment of the invention.

[0031] Figures 6(a) and 6(b) also illustrate how partitioned support regions may be formed at periodic lengths along a strip of a device according to one embodiment of the present invention.

[0032] 7( a ) and 7 ( b ) show SEM images of the back side of the strips of the device after being removed and the surface of the substrate after removing the strips of the device for the (1-100) just, (20-21) and (20-2-1) planes, respectively.

[0033] Figures 8(a), 8(b), 8(c), 8(d), 8(e), 8(f) and 8(g) illustrate the process of removing a strip of a device according to one embodiment of the present invention.

[0034] 9(a) and 9(b) are SEM images of strips of the device from different substrate planes.

[0035] Figure 10(a), Figure 10(b), Figure 10(c), Figure 10(d) and 10(e) is a SEM image of a strip of the device from the c-plane (0001) substrate plane.

[0036] 11(a) and 11(b) illustrate a growth limit mask for multiple stripes of multiple devices according to one embodiment of the present invention.

[0037] Fig.12 SEM image showing a very smooth surface with no mis-cut oriented (1-100) planes after removal of the strip of the device.

[0038] Fig.13 Shown is a SEM image of the surface of a substrate having a 0.7 degree miscut orientation towards the m-plane after removing a strip of the device of the (0001) plane.

[0039] Fig.14 Shown are SEM images and material properties of the surface of the (20-21) freestanding GaN substrate after removal of the strips of the device.

[0040] Figures 15(a), 15(b), 15(c), 15(d), 15(e) and 15(f) illustrate the process of dividing strips of a device after the strips have been removed from a substrate using polymer tape according to an embodiment of the present invention.

[0041] 16(a) and 16(b) illustrate how multiple strips disposed laterally and longitudinally may be cleaved and broken into separate devices at dividing support regions according to one embodiment of the present invention.

[0042] Fig.17 The diagram illustrates a coating process of a facet of a device according to an embodiment of the present invention.

[0043] 18(a), 18(b), and 18(c) illustrate how a wire bond is attached to a device and how a heat sink plate is divided at grooves, according to one embodiment of the present invention.

[0044] 19(a) and 19(b) illustrate how a heat sink plate may be divided into separate devices according to one embodiment of the present invention.

[0045] 20(a) and 20(b) illustrate a testing apparatus for a device according to an embodiment of the present invention.

[0046] Fig.21 A TO-can package of a laser diode device according to an embodiment of the present invention is illustrated.

[0047] Fig. 22 A package of a device including a heat sink plate according to an embodiment of the present invention is illustrated.

[0048] 23(a) and 23(b) illustrate etching of a layer in a layer bending region according to one embodiment of the present invention.

[0049] 24( a ) and 24 ( b ) illustrate the structure of a polymer film according to one embodiment of the present invention.

[0050] 25(a), 25(b), and 25(c) are SEM images illustrating facets of various layers before and after cleaving.

[0051] 26(a), 26(b), 26(c) and 26(d) illustrate a method of manufacturing a device without using an ELO growth method according to an embodiment of the present invention.

[0052] 27(a) and 27(b) illustrate the use of a cleave assist layer (CAL) according to one embodiment of the present invention.

[0053] Fig.28 is a flow chart illustrating a method of partitioning a stripe of one or more devices. DETAILED DESCRIPTION

[0054] In the following description of the preferred embodiments, reference is made to specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0055] Overview

[0056] The present invention describes a method of dividing a device into strips and manufacturing a semiconductor device according to the following steps. In one example, the semiconductor device includes a Group III nitride laser device.

[0057] FIG. 1( a ) illustrates a method, which includes providing a Group III nitride based substrate 101 , such as a bulk GaN substrate 101 .

[0058] Growth restriction mask 102 is formed on or over GaN-based substrate 101. Specifically, growth restriction mask 102 is disposed in direct contact with substrate 101, or is disposed indirectly through an intermediate layer made of a Group III nitride-based semiconductor deposited on substrate 101 grown by metal organic chemical vapor deposition (MOCVD) or the like.

[0059] The growth limiting mask 102 can be formed by an insulator film, such as a SiO2 film deposited on the base substrate 101 by a plasma chemical vapor deposition (CVD) method, sputtering, ion beam deposition (IBD), etc., wherein the SiO2 film is then patterned by the following photolithography method: using a predetermined photomask and etching to include an opening area 103, and a no-growth area 104 (which may or may not be patterned).

[0060] An epitaxial III-nitride layer 105, such as a GaN-based layer 105, is grown by ELO on a GaN substrate 101 and a growth limiting mask 102. Growth of the ELO GaN-based layer 105 occurs first in the opening region 103, on the GaN-based substrate 101, and then laterally from the opening region 103 over the growth limiting mask 102. Growth of the ELO GaN-based layer 105 stops or is interrupted before the ELO GaN-based layer 105 adjacent to the opening region 103 can merge on top of the growth limiting mask 102. This interrupted growth results in a no-growth region 104 between adjacent ELO GaN-based layers 105.

[0061] Additional Group III nitride semiconductor device layers 106 are deposited on or over the ELO GaN based layer 105 and may include an active region 106a, an electron blocking layer (EBL) 106b, and a cladding layer 106c, among other layers.

[0062] The thickness of the ELO GaN based layer 105 is important because it determines the width of the one or more planar surface regions 107 and the layer bending regions 108 at their edges adjacent to the no growth regions 104. The width of the planar surface regions 107 is preferably at least 5 μm, and more preferably 10 μm or more, and most preferably 20 μm or more.

[0063] The ELO GaN-based layer 105 and the additional Group III nitride-based semiconductor device layer 106 separated by the no-growth region 104 are referred to as island-shaped Group III nitride-based semiconductor layers 109. The distance between the island-shaped Group III nitride-based semiconductor layers 109 is the width of the no-growth region 104. The distance between the island-shaped Group III nitride-based semiconductor layers 109 adjacent to each other is generally 20 μm or less, and preferably 5 μm or less, but is not limited to these values.

[0064] Each of the island-shaped Group III nitride semiconductor layers 109 may be processed into a separate device 110. The device 110, which may be a light emitting diode (LED), a laser diode (LD), a Schottky barrier diode (SBD), or a metal oxide semiconductor field effect transistor (MOSFET), is processed on the flat surface region 107 and / or the opening region 103. In addition, the shape of the device 110 generally includes a stripe.

[0065] There are many methods for removing the strips of the device 110 from the substrate 101. For example, the present invention may utilize an ELO method to remove the strips of the device 110. In general, the ELO method is utilized to reduce the defect density in the island-shaped Group III nitride semiconductor layer 109 on a foreign substrate.

[0066] In the present invention, the bonding strength between the substrate 101 and the ELO GaN-based layer 105 is weakened by the growth restriction mask 102. In this case, the bonding region between the substrate 101 and the ELO GaN-based layer 105 is the opening region 103, wherein the width of the opening region 103 is narrower than that of the ELO GaN-based layer 105. Therefore, the bonding region is reduced by the growth restriction mask 102, and thus this method is preferable for removing the epitaxial layers 105, 106, 109.

[0067] In one embodiment, as shown in Figures 1(b) and 1(c), the ELO GaN-based layers 105 are allowed to merge with each other, as shown in Figure 1(b). After the ELO GaN-based layers 105 are merged and the subsequent III-nitride semiconductor device layer 106 is deposited, the island-shaped III-nitride semiconductor layer 109 can be divided using a dry etching method, as shown in Figure 1(c).

[0068] The manufacturing steps of the present invention are described in more detail below:

[0069] Step 1: Form a growth restriction mask 102 having a plurality of stripe-shaped opening regions 103 directly or indirectly on a substrate 101 , wherein the substrate 101 is a III-nitride-based semiconductor or a foreign substrate.

[0070] Step 2: Growing a plurality of epitaxial layers 105 , 106 and 109 on substrate 101 using growth restriction mask 102 such that the growth extends in a direction parallel to stripe-shaped opening regions 103 of growth restriction mask 102 , wherein ELO GaN-based layers 105 do not merge.

[0071] Step 3: A device 110 is fabricated by a conventional method in the flat surface region 107 , in which a ridge structure, a p-electrode, an n-electrode, a pad, etc. are provided on the island-shaped Group III nitride semiconductor layer 109 at a predetermined position.

[0072] Step 4: Forming structures for cleaving at the planar surface region 107 and one or more side facets of the device 110.

[0073] Step 5: Dissolve the growth limit mask 102 by wet etching.

[0074] Step 6: Removing the strip of device 110 from substrate 101 .

[0075] Step 6.1: Attaching the polymer film to the strips of device 110.

[0076] Step 6.2: Apply pressure to the polymer film and substrate 101.

[0077] Step 6.3: The temperature of the membrane and substrate 101 is reduced while applying pressure.

[0078] Step 6.4: Exploiting the difference in thermal coefficient between the film and the substrate 101 to remove the strips of the device 110.

[0079] Step 7: Fabricate n-electrodes at separate regions of the device 110 .

[0080] Step 8: Breaking the strip into devices 110 .

[0081] Step 9: Mount each device 110 on a heat sink plate (such as SiC, AlN, etc.).

[0082] Step 10: Coating facets of device 110 (which is a laser diode).

[0083] Step 11: Divide the Heat Sink Plate.

[0084] Step 12: Screening device 110.

[0085] Step 13: Mounting the device 110 on / into a package.

[0086] These steps are explained in more detail below.

[0087] Step 1: Forming a Growth Limiting Mask

[0088] In one embodiment, a GaN based layer 105 is grown by ELO on a Group III nitride substrate 101, such as an m-plane GaN substrate 101, patterned with a growth limit mask 102 comprising SiO2, wherein the GaN based layer 105 does not merge on top of the SiO2.

[0089] The growth restriction mask 102 includes stripe-shaped opening regions 103, wherein the SiO2 stripes of the growth restriction mask 102 between the opening regions 103 have a width of 20 μm and a spacing of 150 μm, and the opening regions 103 are arranged along the <0001> Axis orientation. If a semipolar (20-21) or (20-2-1) plane is used, the opening region 103 is oriented in a direction parallel to [-1014] or [10-14], respectively. Other planes may also be used, with the opening region 103 oriented in other directions.

[0090] When using a III-nitride substrate 101, the present invention can obtain high-quality III-nitride semiconductor layers 105, 106, 109 and avoid the bowing or curvature of the substrate 101 caused by homogeneous epitaxial growth during epitaxial growth. Therefore, the present invention can also easily obtain a device 110 with a reduced density of defects such as dislocations and stacking faults.

[0091] In addition, if Figure 2 As shown in , these techniques can be used with a foreign substrate 201 (such as sapphire, SiC, LiAlO2, Si, etc.) as long as it allows the growth of the ELO GaN-based layer 105 through the growth confinement mask 102. In one embodiment, the Group III nitride template 202 (such as a GaN underlayer) can be deposited on the foreign substrate 201 before the growth confinement mask 102 or the ELO GaN-based layer 105.

[0092] Step 2: Grow multiple epitaxial layers on the substrate using a growth-limiting mask

[0093] In step 2, a Group III nitride semiconductor device layer 106 is grown in the flat region 107 on the ELO GaN-based layer 105 by a conventional method. In one embodiment, MOCVD is used for epitaxial growth of an island-shaped Group III nitride-based semiconductor layer 109, which includes the ELO GaN-based layer 105 and the Group III nitride semiconductor device layer 106. The island-shaped Group III nitride-based semiconductor layers 109 are separated from each other because the MOCVD growth stops before the ELO GaN-based layer 105 merges.

[0094] Trimethylgallium (TMGa), trimethylindium (TMIn) and triethylaluminum (TMAl) are used as Group III element sources. Ammonia (NH3) is used as a raw gas to supply nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases for Group III element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface epitaxial layer.

[0095] Salt water and bis(cyclopentadienyl) magnesium (Cp2Mg) are used as n-type and p-type dopants. The pressure setting is typically 50 to 760 Torr. The semiconductor layer based on the Group III nitride is generally 700 to 1250 temperature range of growth.

[0096] For example, the growth parameters include the following: TMG is 12 sccm, NH3 is 8 slm, carrier gas is 3 slm, SiH4 is 1.0 sccm, and the Group V / Group III ratio is about 7700.

[0097] ELO of Group III Nitride Layers by Confined Area Epitaxy (LAE)

[0098] In the prior art, several pyramid-like hillocks have been observed on the surface of the m-plane Group III nitride film after growth. See, for example, US Patent Application Publication No. 2017 / 0092810. In addition, a corrugated surface and sunken portions have appeared on the growth surface, which deteriorate the surface roughness. This is a serious problem when a laser diode device structure is manufactured on the surface. Therefore, it is better to grow the epitaxial layers 105, 106, 109 on a non-polar and semi-polar substrate 101, which is known to be difficult.

[0099] For example, according to some papers, a smooth surface can be obtained by controlling the off-angle (>1 degree) of the growth surface of the substrate, and using N2 carrier gas conditions. However, these are very restrictive conditions for large-scale production because of high production costs. In addition, GaN substrates have large perturbations of the off-angle originating from their manufacturing methods. For example, if the substrate has a large off-angle in-plane distribution, these points in the wafer have different surface morphologies. In this case, the yield is reduced due to the large off-angle in-plane distribution. Therefore, the present technology does not necessarily rely on the off-angle in-plane distribution.

[0100] The present invention solves these problems as described below.

[0101] 1. From the edge of the substrate 101 , the growth area is limited by the area of ​​the growth limit mask 102 .

[0102] 2. The substrate 101 is a non-polar or semi-polar III-nitride substrate 101 having an off-angle orientation ranging from -16 degrees to +30 degrees from the m-plane toward the c-plane. Alternatively, a foreign substrate 201 having a III-nitride-based semiconductor layer 202 deposited thereon may be used, wherein the layer 202 has an off-angle orientation ranging from +16 degrees to -30 degrees from the m-plane toward the c-plane.

[0103] 3. The island-shaped Group III nitride-based semiconductor layer 109 has a long side perpendicular to the a-axis of the Group III nitride-based semiconductor crystal.

[0104] 4. During MOCVD growth, a hydrogen atmosphere can be used.

[0105] 5. The island-shaped Group III nitride-based semiconductor layers 109 are not merged with each other.

[0106] Using at least the above #1, #2 and #3, a strip of the device 110 having a smooth surface is obtained. It is more preferred to perform each of #1, #2, #3, #4 and #5.

[0107] like Figure 3(a)-Figure 3(f) As shown, the present invention can obtain an island-shaped Group III nitride-based semiconductor layer 109 having a smooth top surface without pyramid-shaped hillocks and sunken portions, and various planes and various off-angles. The results are explained below.

[0108] FIG3(a) shows a microscope image of an island-shaped III-nitride-based semiconductor layer 109 on an m-plane. FIG3(b) shows images of an island-shaped III-nitride-based semiconductor layer 109 having different miscut orientations of the m-plane, including (1) 0 degrees, (2) -0.45 degrees, (3) -0.6 degrees, and (4) -1.0 degrees. FIG3(c) shows images of an island-shaped III-nitride-based semiconductor layer 109 having different offset angles from the m-plane toward the +c-plane, including (1) a (10-10) plane at 0 degrees, (2) a (30-31) plane at +10 degrees, and (3) a (20-21) plane at +15 degrees. FIG3(d) shows an image of an island-shaped III-nitride-based semiconductor layer 109 having different off-angles from the m-plane toward the -c-plane, including (1) a (10-10) plane at 0 degrees, (2) a (20-2-1) plane at -15 degrees, and (3) a (10-1-1) plane at -28 degrees. FIG3(e) shows an image of an island-shaped III-nitride-based semiconductor layer 109 having different miscut orientations from the c-plane toward the m-plane, including (1) a 0.2 degree miscut and (2) a 0.8 degree miscut. FIG3(f) shows an image of an island-shaped III-nitride-based semiconductor layer 109 having an AlGaN layer on various planes, including (1-100), (20-21), (20-2-1), (1-100), (20-21), and (20-2-1), wherein the Al composition of the AlGaN layer is 3%-5%. As shown in FIG. 3( f ), using the AlGaN layer, a smooth surface can be obtained for the island-shaped Group III nitride-based semiconductor layer 109 .

[0109] Said results have been obtained by observing the following growing conditions.

[0110] In one embodiment, the growth pressure ranges from 60 to 760 Torr, although the growth pressure preferably ranges from 100 to 300 Torr to obtain a wide width of the island-shaped III-nitride-based semiconductor layer 109; the growth temperature ranges from 900 to 1200°C; the V / III ratio ranges from 1000–30,000, and more preferably 3000–10000; TMG is from 2–20 sccm; NH3 ranges from 3 to 10 slm; and the carrier gas is only hydrogen, or both hydrogen and nitrogen. To obtain a smooth surface, the growth conditions of each plane need to be optimized by conventional methods.

[0111] After growing for about 2-8 hours, the ELO GaN-based layer 105 has a thickness of about 8-50 μm and a stripe width of about 20-150 μm, where the stripe width includes the width of the island-shaped Group III-nitride-based semiconductor layer 109 .

[0112] Step 3: Make the device

[0113] In step 3, a device 110 is fabricated on the flat surface region 107 by conventional methods, wherein a ridge structure, a p-electrode, an n-electrode, a pad, etc. are arranged at a predetermined position on the island-shaped Group III nitride semiconductor layer 109. The device 110 may include a laser diode device 110, such as Figure 4 as shown in .

[0114] The laser diode device 110 is composed of the following Group III nitride semiconductor device layers 106, which are stacked one above the other in the stated order, grown on an ELO GaN based layer 105 deposited on a growth confinement mask 102: n-Al 0.06 GaN cap layer 401 , n-GaN guide layer 402 , InGaN / GaN multiple quantum well (MQW) active layer 403 , AlGaN EBL layer 404 , p-GaN waveguide layer 405 , ITO cap layer 406 , SiO 2 current confinement layer 407 and p-electrode 408 .

[0115] The optical resonator is composed of a ridge stripe structure consisting of an ITO capping layer 406, a SiO2 current confinement layer 407 and a p-electrode 408. The optical resonator provides optical confinement in the horizontal direction. The width of the ridge stripe structure is of the order of 1.0 to 30 μm and is typically 10 μm.

[0116] The ridge stripe structure can be fabricated using conventional methods such as photolithography and dry etching. The ridge depth (from the surface to the ridge bottom) is in the p-GaN waveguide layer 405. The ridge depth is predetermined before dry etching is performed based on simulations or previous experimental data.

[0117] In one embodiment, the p-electrode 408 may be composed of one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W, Ag, Au, etc. For example, the p-electrode 408 may include Pd-Ni-Au (having a thickness of 3-30-300 nm). These materials may be deposited by electron beam vaporization, sputtering, thermal vaporization, etc. In addition, the p-electrode 408 is typically deposited on the ITO coating 406.

[0118] Step 4: Forming structures for cleaving on the flat surface area and side facets

[0119] like Figure 5(a) , 5(b), 5(c) and 5(d), the purpose of this step is to prepare the strip 501 of the device 110 before the strip 501 of the device 110 is removed from the substrate 101. The divided support region 502 is formed with a periodic length, where each period is determined by the length of the device 110. For example, in the case of the laser diode device 110, one period is set to 300-1200 μm.

[0120] The division support region 502 is a line scribed by a diamond tip scriber or a laser scriber, as shown in FIG5(a); or a groove formed by dry etching such as RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma), as shown in FIG5(b); but is not limited to the method. The division support region 502 may be formed on both sides of the strip 501 or on one side of the strip 501. The depth of the division support region 502 is preferably 1 μm or more.

[0121] In both cases, the strip 501 can be divided into separate devices 110 at the dividing support region 502 because the dividing support region 502 is weaker than any other portion. The dividing support region 502 prevents the strip 501 from breaking at an unexpected location, so it can accurately determine the length of the device 110.

[0122] The partitioned support region 502 is created at the flat surface region 107 in a manner avoiding the current injection region 503 in the ridge structure, as well as the p-electrode 408 and the layer bending region 108 , although possibly covering at least a portion of the SiO 2 current confinement layer 407 .

[0123] As shown in Figures 5(a) and 5(b), the division support region 502 is formed at the first facet 504 and optionally at the second facet 505 because they are flat areas and thus easy to process. The third facet 506 may be avoided.

[0124] 5(c), the division support region 502 may preferably be formed only at the second facet 505, in which case it is necessary to use a small width of the island-shaped Group III nitride-based semiconductor layer 109. In this case, the strips 501 of the device 110 can be accurately divided.

[0125] Furthermore, as shown in Fig. 5(d), the p-electrode 408, the dielectric layer 407, and the p-pad for wire bonding, etc. can be avoided from the partition support region 502. By doing so, Fig. 6(a) is changed as shown in Fig. 6(b).

[0126] As shown in the SEM images of Figures 7(a) and 7(b), after being removed, the back side of strip 501 has two different parts: one is the separation area, between the two white dashed lines; the other is the wing area outside the separation area. The two different parts have different surface morphologies, which may be an opportunity to prevent the cleavage line from running straight. In addition, due to the interaction between the mask and the back side surface of the island-shaped III-nitride semiconductor layer, there are some disturbances in the wing area.

[0127] Therefore, the division support region 502 is preferably formed on the first facet 504 and / or the second facet 505, as shown in FIG. 5( b), FIG. 5( c), and FIG. 5( d). By doing so, the shape of the division support region 502 is uniformly formed. The blade for breaking the strip 501 preferably contacts the back side of the strip 501. By doing so, cleavage starts from the division support region 502 at the top surface of the strip 501.

[0128] Step 5: Dissolve the growth limit mask by wet etching

[0129] The method may further comprise the step of removing at least part, or preferably almost all, or most preferably all, of the growth limit mask 102 by dissolving it by a wet etchant.

[0130] The growth limit mask 102 is removed using a chemical solvent such as hydrofluoric acid (HF) or buffered HF (BHF). This allows the device 110 to be easily removed from the substrate 101. This process is preferably performed before removing the III-nitride epitaxial layers 105, 106, 109 from the substrate 101. It is also preferably performed before processing the device 110 in step 3.

[0131] Step 6: Remove the strips of the device from the substrate

[0132] From here, the process of removing the strip 501 is explained using FIG. 8( a ), FIG. 8( b ), FIG. 8( c ), FIG. 8( d ), FIG. 8( e ), FIG. 8( f ), and FIG. 8( g ).

[0133] Step 6.1 includes attaching a polymer film 801 to the strip 501 of the device 110, as shown in FIG8(a). In this embodiment, the polymer film 801 is composed of a base film 802, an adhesive 803 and a backing film 804.

[0134] Step 6.2 includes applying pressure 805 to the polymer film 801 and the substrate 101 using a plate 806, as shown in FIG8(b). The purpose of applying pressure 805 is to place the polymer film 801 between the strips 501 of the device 110. The polymer film 801 is softer than the strips 501 of the device 110, so the polymer layer 801 can easily surround the strips 501 of the device 110. Preferably, the polymer film 801 is heated to soften so that the polymer film 801 can easily cover the strips 501 of the device 110.

[0135] Step 6.3 comprises reducing the temperature of the polymer film 801 and the substrate 101 while maintaining the applied pressure 805. It is not necessary to apply the pressure 805 during the change of temperature.

[0136] Step 6.4 includes taking advantage of the difference in thermal coefficients between the polymer film 801 and the substrate 101 to remove the strip 501 of the device 110.

[0137] As shown in Fig. 8(c), the polymer film 801 shrinks as the temperature decreases. Therefore, the bottom of the polymer film 801 is lower than the top of the strip 501 of the device 110, as shown in Fig. 8(d).

[0138] 8(c), the polymer film 801 may apply pressure 805 at the side facets of the strips 501 of the device 110 in a horizontal direction, exposing a cleavage point 807 and causing the strips 501 of the device 110 to tilt diagonally downward 808. This pressure 805 applied from the side facets allows the strips 501 of the device 110 to be effectively removed from the substrate 101. During low temperatures, the polymer film 801 maintains the pressure 805 applied from the top of the polymer film 801 to the strips 501 of the device 110.

[0139] Various methods can be used to reduce the temperature. For example, the substrate 101 and the polymer film 801 can be placed in liquid N2 (e.g., 77 ° K) while applying pressure 805. The temperature of the substrate 101 and the polymer film 801 can also be controlled by a piezoelectric transducer. In addition, the plate 806 that applies pressure 805 to the polymer film 801 can be cooled to a low temperature before and / or during contact with the polymer film 801. By doing so, due to the large thermal expansion coefficient, the polymer film 801 is cooled, and pressure 805 can be applied to the strip 501 of the device 110.

[0140] When the temperature is lowered, the substrate 101 and the polymer film 801 may be wetted by atmospheric moisture. In this case, the temperature reduction may be in a dry air atmosphere or a dry N2 atmosphere, which prevents the substrate 101 and the polymer film 801 from being wetted.

[0141] Thereafter, the temperature is increased to, for example, room temperature, and the pressure 805 is no longer applied to the polymer film 801. At this point, the strip 501 of the device 110 has been removed from the substrate 101, and the polymer film 801 is then separated from the substrate 101. As shown in FIG. 8( e), when the polymer film 801 is used, especially the polymer film 801 having the adhesive 803, the strip 501 of the device 110 can be removed in an easy and quick manner using the polymer film 801.

[0142] As shown in Fig. 8(f), depending on the growth conditions, there may be a situation where the strips 501 of the device 110 have different heights t. In this case, the removal method using the polymer film 801 is good at removing the strips 501 of different heights of the device 110 because these films 801 are flexible and soft, as shown in Fig. 8(g).

[0143] How to remove the bar

[0144] By taking advantage of the different thermal expansion coefficients between the polymer film 801 and the semiconductor material of the device 110, the pressure in the horizontal direction is uniformly applied to the entire substrate 101. The strip 501 of the device 110 can be removed from the substrate 101 without breaking the strip 501 of the device 110. This has been demonstrated by the high yield achieved when removing the strip 501.

[0145] As shown in the SEM images of Figures 9(a), 9(b), 10(a), 10(b), 10(c), 10(d) and 10(e), the method can remove the strip 501 of the device 110 from many different substrate 101 planes, such as (1-100) just, (20-21), (20-2-1) and (0001). In these examples, the length of the strip 501 is about 1.2 mm. In addition, even if the (20-21) and (20-2-1) planes are not split planes of the bulk GaN substrate 101, the method can still remove the strip 501 in an easy manner without breaking the strip 501. In other words, the advantage of the method is that the strip 501 can be removed from different substrate 101 planes using the same method because the method does not depend on the substrate 101 plane. More preferably, it can utilize the splitting of the m-plane on the GaN crystal when removing the strip 501. In the case where the substrate 101 is not an m-plane substrate 101, such as (20-21), (20-2-1), or (0001), the surface of the separated region after removal contains an m-plane as a part of its surface, and the strip 501 can be removed with less pressure.

[0146] The strip 501 of the device 110 is rectangular in shape, having long sides and short sides, as shown in FIGS. 11( a) and 11( b). Pressure is applied to the strip 501 of the device 110 having such a shape from the vertical direction and in the horizontal direction against the long sides of the strip 501, as shown in FIG. 8( c). By doing so, an effective influence can be given to the cleavage point 807, which removes the strip 501 of the device 110 from the substrate 101. Before attaching the polymer film 801 to the strip 501 of the device 110, the growth restriction mask 102 is preferably eliminated from the substrate 101 by wet etching or the like. Eliminating the growth restriction mask 102 creates a space under the strip 501 of the device 110 to apply pressure at the cleavage point 807, which can cause the strip 501 of the device 110 to tilt diagonally downward 808, as shown in FIG. 8( c).

[0147] This method using polymer film 801 can apply pressure 805 to strip 501 of device 110 uniformly and in an appropriate amount over a large area. By selecting the type and / or temperature of polymer film 801 and the ramp-up and / or ramp-down rate of the temperature, the amount of pressure 805 applied to strip 501 of device 110 can be controlled. In addition, the present invention is not limited by the ramp-up and / or ramp-down rate of the temperature, and a thermosetting resin film can be used to remove strip 501 of device 110 at an elevated temperature. Again, this results in a high yield rate for removing strip 501.

[0148] In mass production, it is sometimes difficult to remove each strip 501 of the device 110 on the substrate 101, especially a strip having a wide area. Sometimes, there are cases where some strips 501 of the device 110 remain on the substrate 101 after removing one or more strips 501 of the device 110. In the above-mentioned prior art method, it is difficult to repeat the removal process due to the metal bonding process between the wafer and the supporting metal.

[0149] On the other hand, this removal method using polymer film 801 and substrate 101 with ELO GaN-based layer 105 can be repeated many times. When some strips 501 of device 110 remain on substrate 101, repeating the method allows the remaining strips 501 of device 110 to be completely removed from substrate 101.

[0150] Because the removal method does not include catastrophic processes (such as metal bonding), it can be a repeatable process. By repeating the removal method, almost all of the strips 501 of the device 110 can be removed from the substrate 101, including substrates 101 such as 2 inches, 4 inches or other wafer sizes.

[0151] Cleavage is performed at the separated regions of the m-plane

[0152] Here, the cleaving method using the m-plane faceting is explained. FIG7(a) and FIG7(b) show SEM images of the back side of the strip 501 of the device after being removed and the surface of the substrate 101 after removing the strip 501 of the device 110 for (1-100) just, (20-21) and (20-2-1), respectively. It can be seen that the back side of the strip 501 of the (1-100) just plane is a relatively smooth surface compared to other planes, as shown in the enlargement in FIG7(a) and FIG7(b), and for the (1-100)-plane, the surface of the substrate 101 is also a relatively smooth surface after removing the strip 501.

[0153] like Fig.12 As shown in the image of , after removing the strip 501 of the device 110, a very smooth surface can be obtained for the (1-100) plane without miscut orientation, wherein the surface is smooth enough to be used as a facet for a VCSEL. Fig.13 As shown in the image of , for the (0001) plane, the surface of the substrate 101 after removing the strips 501 of the device 110 is pitted with a miscut orientation of 0.7 degrees toward the m-plane.

[0154] As shown in Figures 7(a) and 7(b), for the semipolar (20-21) and (20-2-1) planes, the back side of the strip 501 of the device 110 has periodic concavity and convexity. In these results, the interface at the cleavage point is an m-plane facet. The cleavage interface was measured using a laser scanning confocal microscope (LSCM).

[0155] Fig.14 , including SLCM measurements, shows the surface of a (20-21) freestanding GaN substrate 101 after removing a strip 501 of a device 110. The surface of the trapped region is tilted 15 degrees from the surface of the (20-21) substrate 101, where the surface of the (20-21) substrate 101 is tilted 15 degrees from the m-plane. Therefore, the surface of the trapped region is the m-plane. The m-plane of bulk GaN is well known as a facet with high cleavage, and it is very important and useful to utilize the cleavage of the m-plane to remove the strip 501. The method of removing the strip 501 can effectively utilize the cleavage of the m-plane even though the semipolar (20-21) substrate 101 does not have an m-plane as a major surface.

[0156] like Fig.14As shown, after being removed from substrate 101, strip 501 including a semipolar III-nitride-based semiconductor layer preferably has a periodic concavity and convexity shape. By separating in this way, strip 501 can avoid excessive and uneven pressure. Therefore, strip 501 can be divided from substrate 101 without breaking into short dimensions. The back side of strip 501 is more preferably composed of a semipolar III-nitride-based semiconductor layer having an m-plane as at least a part of the back surface. This method can be adopted in the same way for different semipolar planes, which is important in industry.

[0157] Cleavage is performed at the separation area of ​​the c-plane

[0158] The present invention also attempts the removal method on a c-plane GaN substrate 101 , as shown in FIG. 10( a ).

[0159] As shown in Fig. 10(b) and Fig. 10(c), the growth restriction mask 102 and the opening region 103 are designed as shown in Fig. 11(a) without a separation region. The length of the long side of the opening region 103 is set to 15 mm.

[0160] The image of FIG10( d ) (which is magnified in FIG10( e ) ) shows the surface of the substrate 101 after removing the strip 501 of the device 110. The c-plane is one of the cleavage planes in bulk GaN, so the separated area on the back side of the strip 501 is very smooth. This shows that the removal method can also be used in the case of a c-plane GaN substrate 101.

[0161] Step 7: Fabrication of n-electrodes at separate regions of the device

[0162] Steps 7, 8, 9 and 10 are as follows Figure 15(a)-15(f) , Figure 16(a)-16(b) and Fig.17 shown.

[0163] After removing the strip 501 from the substrate 101 , the strip 501 remains attached to the polymer film 801 , shown with the strip 501 positioned upside down on the film 801 , as shown in FIG. 15( a ).

[0164] 15(b) shows the back side of the strip 501 as a schematic diagram and SEM image, which has a separation region 1501 between the partition support regions 502. The separation region 1501 contacts the substrate 101, or directly contacts the bottom layer, but is not on the growth limit mask 102. The cleaving edge 1502 is used at the partition support region 502.

[0165] Then, as shown in FIG. 15( c ), a metal mask 1503 may be used to provide an n-electrode 1504 on the back side of the device 110 .

[0166] In the case where the n-electrode 1504 on the back side of the strip 501 is formed after the strip 501 is removed from the substrate 101, the n-electrode 1504 is preferably formed on the separation region 1501. This separation region 1501 is kept in good surface condition for the n-electrode 1504 to obtain low contact resistance. The present invention keeps this region 1501 clean until the island-shaped Group III nitride semiconductor layer 109 is removed.

[0167] The n-electrode 1504 may also be disposed on the top surface of the strip 501 , which is the same surface fabricated for the p-electrode 408 .

[0168] Typically, the n-electrode 1504 is made of the following materials: Ti, Hf, Cr, Al, Mo, W, Au. For example, the n-electrode may be made of Ti-Al-Pt-Au (having a thickness of 30-100-30-500 nm), but is not limited to those materials. The deposition of these materials may be performed by electron beam evaporation, sputtering, thermal evaporation, etc.

[0169] Step 8: Breaking the Strip into Separate Devices

[0170] After the n-electrode 1504 is provided, each strip 501 is divided into a plurality of devices 110, as shown in FIG15( d). The dividing support region 502 helps divide the strip 501 into the devices 110, as shown in FIG15( b). A rupture method may be used, as well as other conventional methods, but is not limited to these methods. Preferably, the cleaving blade 1502 contacts the side of the strip 501 that is not formed by the dividing support region 502 at the location of the dividing support region 502.

[0171] As shown in Fig. 16(a), the plurality of strips 501 disposed laterally may be cleaved and broken at the division support region 502 into the division support separate devices 110. Furthermore, as shown in Fig. 16(b), the plurality of strips 501 disposed laterally and longitudinally may also be cleaved at the division support region 502. In addition, the division support region 502 may be disposed on both sides 1601 or on one side 1602 of the strip 501.

[0172] Step 9: Mount the Device on the Heat Sink Plate

[0173] After step 8, the divided strips 501 are still on the polymer film 801. In one embodiment, the polymer film 801 is an ultraviolet (UV) light sensitive cutting tape, which is exposed to UV light, and the UV light reduces the adhesive strength of the film 801, as shown in Figure 15 (e). This makes it easy to remove the device 110 from the film 801.

[0174] In this step, a heat sink plate 1505 composed of AlN is prepared. Au-Sn solder 1506 is provided on the heat sink plate 1505, the heat sink plate 1505 is heated to exceed the melting temperature of the solder 1506, and the device 110 on the polymer film 801 is bonded to the heat sink plate 1505 using the Au-Sn solder 1506. The device 110 can be mounted on the heat sink plate 1505 in two ways: (1) n-electrode 1504 side down or (2) p-electrode 408 side down. FIG. 15( f) shows the device 110 mounted to the heat sink plate 1505 using the solder 1506, with the n-electrode 1504 side down. Grooves 1507 in the heat sink plate 1505 separate the devices 110, wherein the grooves 1507 are used to divide the heat sink plate 1505, as described in more detail below.

[0175] Step 10: Coating the Subsurfaces of the Device

[0176] The next step of device processing includes coating the facet 504 of the device 110. When the laser diode device 110 emits a laser, light in the device 110 that passes through the facet 504 of the device 110 to the outside of the device 110 is absorbed by the non-radiative recombination center at the facet 504, so the facet temperature continues to increase. Therefore, the temperature increase may cause catastrophic optical damage (COD) of the facet 504.

[0177] Coating the facets 504 can reduce non-radiative recombination centers. To prevent COD, it is necessary to coat the facets with a dielectric layer (such as AlN, AlON, Al2O3, SiN, SiON, SiO2, ZrO2, TiO2, Ta2O5, etc.). In general, the coating film is a multilayer structure composed of the above materials. The structure and thickness of the layer are determined by the predetermined reflectivity.

[0178] In the present invention, the strip 501 of the device 110 may have been divided in step 8 to obtain split facets of a plurality of devices 110. Therefore, the coating facet 504 method needs to be performed on a plurality of devices 110 simultaneously in an easy manner. In one embodiment, the device 110 is mounted on the heat sink plate 1505 in a horizontally offset manner, for example, toward one side of the heat sink plate 1505, as shown in FIG. 15( f). Then, as shown in FIG. Fig.17 As shown, the device 110 and the heat sink plate 1505 are placed on a spacer plate 1701 , and a plurality of spacer plates 1701 are stored in a coating holder 1702 .

[0179] Note that the spacer plate 1701 does not always have to be used, and the heat sink plate 1505 may be used alone. Alternatively, the heat sink plate 1505 may be mounted on another strip or plate, which is then placed on the spacer plate 1701.

[0180] By doing so, the facets 504 of several devices 110 can be coated simultaneously. In one embodiment, the facet 504 coating is performed at least twice—once for the front facet 504 of the device 110, and once for the back facet 504 of the device 110. The length of the heat sink plate 1505 can be sized to about the cavity length of the laser diode device 110, making it quick and easy to perform the facet 504 coating twice.

[0181] Once the spacer plate 1701 is set in the coating holder 1702, the two facets 504 of the device 110 can be coated without setting the spacer plate 1701 in the coating holder 1702 again. In one embodiment, the first coating is performed on the front facet 504 that emits the laser, and the second coating is performed on the rear facet 504 that reflects the laser. Before the second coating of the coating film is deposited in the facility, the coating holder 1702 is reversed. This greatly reduces the lead time of the process.

[0182] Step 11: Divide the Heat Sink Plate

[0183] As shown in FIG. 18( a), wire bonds 1801 and 1802 are attached to the device 110, and then the heat sink plate 1505 is divided at the groove 1507 (e.g., between one or more of the devices 110). FIG. 18( b) is a top view of FIG. 18( a), which shows the relative placement and positioning of the device 110, the groove 1507, and the bonds 1801, 1802. FIG. 18( c) shows the separate probe 1803 and wire bond 1804 used with the device 110.

[0184] 19(a) and 19(b) also show how the heat sink plate 1505 can be divided into separate devices 110, which can occur before or after attaching the wire bonds 1801, 1802. By doing so, it is easy to separate the devices 110 after the coating process has been completed.

[0185] Step 12: Screening Device

[0186] This step distinguishes defective and non-defective devices 110. First, various characteristics of the device 110 are checked under given conditions; such as output power, voltage, current, resistance, FFP (Far Field Pattern), slope-efficiency, etc. At this point, the device 110 has been mounted on the heat sink plate 1505, so it is easy to check these characteristics.

[0187] 20(a) and 20(b) show a test apparatus 2001 in which the p-electrode 408 and solder 1506 having electrical continuity to the n-electrode 1504 are contacted by probes 2002, 2003. Then, defect-free devices can be selected and screened by a burn-in test (life test).

[0188] In one embodiment, it is preferred that the test apparatus 2001 comprises a box or other container so that the aging test can be performed with the device 110 sealed in a dry air or nitrogen atmosphere. In addition, a heating stage 2004 can be used to maintain the temperature of the device 110 during the screening test, for example, 60 degrees, 80 degrees, etc. The photodetector 2005 can be used to measure the optical output power 2006, which identifies a non-defective device 110 with a constant output power, or identifies a defective device 110.

[0189] In particular, in the case of the III-nitride-based semiconductor laser diode device 110, it is known that when the laser diode oscillates in an atmosphere containing moisture, it deteriorates. This degradation is caused by moisture and siloxane in the air, so the III-nitride-based semiconductor laser diode device 110 needs to be sealed in dry air during the aging test.

[0190] Therefore, if Fig.21 As shown, when the III-nitride based laser diode 2100 is shipped from the manufacturer, the chip 2101 itself is mounted on a stem 2102 and sealed in a dry air atmosphere using a TO can package 2103, wherein the package 2103 includes a window 2104 for light emission.

[0191] Generally speaking, screening or burn-in testing is performed before shipping in order to screen out defective devices 110. For example, screening conditions are performed according to the specifications of the laser diode device 110, such as high temperature and high power.

[0192] Furthermore, the burn-in test may be performed with the device 110 mounted on / in the package 2100, which is sealed in dry air and / or dry nitrogen prior to screening. This results in limited flexibility in packaging and mounting the laser device.

[0193] In the prior art, if a defective product occurs, the defective product is discarded with the entire TO can package 2100, which is a significant loss for production. This makes it difficult to reduce the production cost of the laser diode device 110. There is a need to detect the defective device 110 at an earlier step.

[0194] In the present invention, the facets 504 of the device 110 are coated using a heat sink plate 1505, a plurality of devices 110 can be mounted at a low level on the heat sink plate 1505, and then, after the coating process, the heat sink plate 1505 and the device 110 are divided using grooves 1507, allowing the device 110 together with the sub-mount of the heat sink plate 1505 to be inspected in a screening test in a dry air or nitrogen atmosphere.

[0195] When the screening test is performed, the device 110 already has two contacts, namely, the p-electrode 408 and the solder 1506 on the heat sink plate 1505, or in the case of flip chip bonding, the n-electrode 1504 and the solder 1506 on the heat sink plate 1505. In addition, when the device 110 is composed of only the chip and the bottom mounting part, the present invention can select defective products using the screening test. Therefore, in the case of discarding defective products, the present invention can reduce losses more than the prior art, which is of great value.

[0196] In the case of screening high power laser diode devices 110, the heat sink plate 1505 may preferably have two parts of solder 1506 without electrical continuity. One part of the solder 1506 is connected to the p-electrode 408 with a lead (not shown), and the other part of the solder 1506 is connected to the n-electrode 1504 with a lead (not shown). In addition, the p-electrode 408 and the n-electrode 1504 may preferably be connected to the solder part 1506 by two or more leads, for example, as shown in FIG. 18 (c), which shows the p-electrode 408 connected to the solder 1506 by two or more leads 180. In this way, the probe 1803 used to apply current to the device 110 can avoid directly contacting the p-electrode 408 (or the n-electrode 1504), which is critical in the case of screening high power laser diodes. Specifically, the probe 1803 may break the contacted part, especially in the case of applying a high current density.

[0197] Step 13: Mounting the Device on / Into the Package

[0198] like Fig. 22 As shown, the device 110 (including the heat sink plate 1505) can be mounted in the package 2201 using solder or another metal to bond the device 110 at the bottom of the package 2201. The pins 2202 of the package 2201 are connected to the device 110 by the leads 2203. By doing so, current from an external power supply can be applied to the device 110.

[0199] This is more preferable than bonding using metal (such as Au-Au, Au-In, etc.) between the package 2201 and the heat sink plate 1505. This method requires flatness at the surface of the package 2201 and the back side of the heat sink plate 1505. However, without solder, this configuration achieves high thermal conductivity and low temperature bonding, which is a big advantage for device processing.

[0200] Thereafter, a cover 2204 may close the package 2201. In addition, a phosphor 2205 may be provided outside and / or inside the package 2201, and a window 2206 allows light to be emitted out of the package 2201. By doing so, the package 2201 may be used as a light bulb or a headlight of a car.

[0201] As presented herein, these processes provide an improved method for obtaining laser diode devices 110. Furthermore, once the devices 110 are removed from the substrate 101, the substrate 101 can be recycled several times. This achieves the goals of environmentally friendly production and low-cost models. These devices 110 can be used as lighting devices such as light bulbs, data storage devices, optical communication devices such as Li-Fi, and the like.

[0202] It is difficult to package multiple different types of laser devices 110 in one package 2201. However, this method can overcome this problem because it can perform aging testing without packaging. Therefore, it is easy to install different types of devices 110 in one package 2201.

[0203] Manufacturing LED devices

[0204] In the case of making LED devices, the same process can be used until step 3. This discussion briefly explains how to make two types of LEDs. Type 1 LEDs have two electrodes (p-electrode and n-electrode) on one side of the chip, while Type 2 LEDs have electrodes on the opposite side of the chip.

[0205] First, in the case of type 1 LED, p-electrode and n-electrode are formed on the top surface of the device in step 3. Then, it is the same process from step 4 to step 8. In step 9, the removed chip is mounted on the package and heat sink. Ag paste is used to bond the backside surface of the chip, the package and the heat sink.

[0206] Next, in the case of type 2 LED, almost the same process is used until step 10, where the ITO electrode is formed on the p-GaN contact layer. In this case, the method of dividing the strips is the same. In addition, preferably, the layer bending area is eliminated.

[0207] Definition of terms

[0208] Group III Nitride-Based Substrates

[0209] The III-nitride-based substrate 101 may include any type of III-nitride-based substrate, as long as the III-nitride-based substrate allows the growth of III-nitride-based semiconductor layers 105, 106, 109 through the growth restriction mask 102, and any GaN substrate 101 sliced ​​from bulk GaN and AlN crystals on {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} planes, etc. or other planes may be used.

[0210] Heterogeneous Substrate

[0211] In addition, the present invention can also use a foreign substrate 201. For example, a GaN template 202 or other semiconductor layer 202 based on a group III nitride can be grown on a foreign substrate 201 (such as sapphire, Si, GaAs, SiC, etc.) before the growth restriction mask 102. The GaN template 202 or other semiconductor layer 202 based on a group III nitride is typically grown on the foreign substrate 201 to a thickness of about 2-6 μm, and then the growth restriction mask 102 is set on the GaN template 202 or other semiconductor layer 202 based on a group III nitride.

[0212] Growth restriction mask

[0213] The growth restriction mask 102 includes a dielectric layer, such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, etc., or a refractory metal or a noble metal, such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc. The growth restriction mask may be a laminated structure selected from the above materials. It may also be a plurality of stacked layer structures selected from the above materials.

[0214] In one embodiment, the thickness of the growth limit mask is about 0.05-3 μm. The width of the mask is preferably greater than 20 μm, and more preferably, the width is greater than 40 μm. The growth limit mask is deposited by sputtering, electron beam vaporization, plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), etc., but not limited to the methods described.

[0215] On an m-plane free-standing GaN substrate 101, the growth limiting mask 102 shown in FIG. 11(a) and FIG. 11(b) includes a plurality of opening regions 103, which are periodically arranged at intervals p1 and p2 in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 0001 direction of the substrate 101, respectively, and extend in the second direction. The length of the opening region 103 is, for example, 200 to 35000 μm; the width b is, for example, 2 to 180 μm; the interval p1 of the opening region 103 is, for example, 20 to 180 μm; and the interval p2 is, for example, 200 to 35000 μm. The width b of the opening region 103 is typically constant in the second direction, but may be changed in the second direction as desired.

[0216] On the c-plane free-standing GaN substrate 101 , the opening regions 103 are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 1-100 direction of the substrate 101 .

[0217] On a semipolar (20-21) or (20-2-1) GaN substrate 101, the opening regions 103 are arranged in directions parallel to [-1014] and [10-14], respectively.

[0218] Alternatively, a foreign substrate 201 may be used. When the c-plane GaN template 202 is grown on the c-plane sapphire substrate 201, the opening region 103 is in the same direction as the c-plane free-standing GaN substrate; when the m-plane GaN template 202 is grown on the m-plane sapphire substrate 201, the opening region 103 is in the same direction as the m-plane free-standing GaN substrate 101. By doing so, the m-plane cleavage plane can be used to divide the strips 501 of the device 110 having the c-plane GaN template 202, and the c-plane cleavage plane can be used to divide the strips 501 of the device 110 having the m-plane GaN template 202; this is far more preferred.

[0219] Group III nitride-based semiconductor layers

[0220] The ELO GaN-based layer 105 , the Group III nitride semiconductor device layer 106 , and the island-shaped Group III nitride-based semiconductor layer 109 may contain In, Al, and / or B and other impurities such as Mg, Si, Zn, O, C, H, and the like.

[0221] The semiconductor device layer 106 based on Group III nitride generally includes more than two layers, including at least one of an n-type layer, an undoped layer, and a p-type layer. The semiconductor device layer 106 based on Group III nitride specifically includes a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, and the like. In the case where the device has a plurality of semiconductor layers based on Group III nitride, the distance between island-shaped Group III nitride semiconductor layers 109 adjacent to each other is generally 30 μm or less, and preferably 10 μm or less, but is not limited to these numbers. In the semiconductor device, several electrodes according to the type of the semiconductor device are set at predetermined positions.

[0222] Advantages of epitaxial lateral overgrowth

[0223] The crystallinity of the island-shaped Group III nitride-based semiconductor layer 109 grown on the growth restriction mask 102 from the stripe-shaped openings 103 of the growth restriction mask 102 using epitaxial lateral overgrowth (ELO) is high.

[0224] In addition, two advantages can be obtained by using the Group III nitride-based substrate 101. One advantage is that a high-quality island-shaped Group III nitride-based semiconductor layer 109 can be obtained, such as having a very low defect density compared to using the sapphire substrate 201.

[0225] Another advantage of using similar or identical materials for both epitaxial layers 105, 106, 109 and substrate 101 is that the tension in epitaxial layers 105, 106, 109 can be reduced. In addition, due to similar or identical thermal expansion, the method can reduce the amount of bending of substrate 101 during epitaxial growth. As above, the effect is that production yield can be high in order to improve temperature uniformity.

[0226] The use of foreign substrates 201 (such as sapphire (m-plane, c-plane), LiAlO2, SiC, Si, etc.) for the growth of epitaxial layers 105, 106, 109 is that these substrates 201 are low-cost substrates. This is an important advantage for large-scale production.

[0227] As for the quality of the device 110, the use of a free-standing III-nitride-based substrate 101 is more preferred for the above reasons. On the other hand, the use of a foreign substrate 201 makes it easy to remove the III-nitride-based semiconductor layers 105, 106, 109 due to the weaker bonding strength at the cleavage point 807.

[0228] In addition, when growing a plurality of island-shaped III-nitride-based semiconductor layers 109, these layers 109 are separated from each other, i.e., formed in isolation, so that the tensile stress or compressive stress generated in each island-shaped III-nitride-based semiconductor layer 109 is confined within the layer 109, and the effect of the tensile stress or compressive stress does not fall on other III-nitride-based semiconductor layers.

[0229] In addition, since the growth restriction mask 102 and the ELO GaN based layer 105 are not chemically bonded, stress in the ELO GaN based layer 105 may be released by slippage caused at the interface between the growth restriction mask 102 and the ELO GaN based layer 105 .

[0230] In addition, there is a gap between each island-shaped Group III nitride-based semiconductor layer 109, as shown in the no-growth area 104 in Figure 1(a), resulting in a substrate 101 having a plurality of rows of island-shaped Group III nitride-based semiconductor layers 109, which provides flexibility, and the substrate 101 is easily deformed and can be bent when an external force is applied.

[0231] Therefore, even if slight warping, bending or deformation occurs in the substrate 101, this can be easily corrected by a small external force, avoiding cracks. Therefore, the substrate 101 can be handled by the vacuum chuck, which makes the manufacturing process of the semiconductor device 110 easier to perform.

[0232] As explained, the island-shaped III-nitride-based semiconductor layer 109 made of high-quality semiconductor crystals can grow by suppressing the curvature of the substrate 101, and in addition, even when the III-nitride-based semiconductor layers 105, 106, 109 are thick, the occurrence of cracks, etc. can be suppressed, and thereby a large-area semiconductor device 110 can be easily realized.

[0233] Flat surface area

[0234] The flat surface area 107 is between the layer bending areas 108. Furthermore, the flat surface area 107 is in the area of ​​the growth limit mask 102.

[0235] The semiconductor device 110 is mainly manufactured on the flat surface region 107. The width of the flat surface region 107 is preferably at least 5 μm, and more preferably 10 μm or more. The flat surface region 107 has a highly uniform thickness for each of the semiconductor layers 105, 106, 109 in the flat surface region 107.

[0236] Layer bending area

[0237] 23(a) and 23(b) illustrate the layer bending region 108. If a non-polar or semi-polar substrate 101 is used, there may be a first facet 2301 in the flat surface region 107 as the main region for forming a ridge structure, and a second facet 2302, and possibly a third facet 2303, in the layer bending region 108.

[0238] If the layer bending region 108 including the active layer 106b remains in the LED device 110, a portion of light emitted from the active layer 106b is reabsorbed. Therefore, at least a portion of the active layer 106b in the layer bending region 108 is preferably removed by etching.

[0239] If the layer bending region 108 including the active layer 106b remains in the laser diode device 110, the laser mode may be affected by the layer bending region 108 due to the low refractive index (eg, InGaN layer). Therefore, at least a portion of the active layer 106b in the layer bending region 108 is preferably removed by etching.

[0240] Two etches may be performed to remove the active layer 106 b , wherein a first etch is performed to remove the active layer 106 b in the region of the second facet 2302 before removing the epitaxial layers 105 , 106 , 109 from the substrate 101 , and a second etch is performed to remove the active layer 106 b in the region of the third facet 2303 after removing the epitaxial layers 105 , 106 , 109 from the substrate 101 .

[0241] The emission region formed by the active layer 106b is a current injection region. In the case of the laser diode device 110, the emission region is a ridge structure. In the case of an LED, the emission region is a region for forming a p-contact electrode.

[0242] For both LDs and LEDs, the edge of the emission region should be at least 1 μm or more from the edge of the layer bending region 108, and more preferably 5 μm.

[0243] On the other hand, the epitaxial layer of the flat surface region 107 excluding the opening region 103 has a lower defect density than the epitaxial layer of the opening region 103. Therefore, more preferably, the ridge stripe structure should be formed in the flat surface region 107 included on the wing region.

[0244] Semiconductor devices

[0245] The semiconductor device is, for example, a Schottky diode, a light emitting diode, a semiconductor laser, a photodiode, a transistor, etc., but is not limited to these devices. The present invention is particularly useful for micro LEDs and laser diodes, such as side-emitting lasers and vertical cavity surface emitting lasers (VCSELs). The present invention is particularly useful for semiconductor lasers with cleaved facets.

[0246] Polymer film

[0247] The polymer film 801 is used to remove the island-shaped III-nitride-based semiconductor layer 109 from the III-nitride-based substrate 101 or GaN template used with the foreign substrate 201. In the present invention, cutting tape (including commercially sold UV-sensitive cutting tape) can be used as the polymer film 801. For example, the structure of the polymer film 801 may include three layers 802, 803, 804 or double layers 803, 804, as shown in Figures 24 (a) and 24 (b), but is not limited to these examples. For example, the base film 802 material with a thickness of about 80 μm can be made of polyvinyl chloride (PVC). For example, the back film 804 material with a thickness of about 38 μm can be made of polyethylene terephthalate (PET). For example, the adhesive layer 803 with a thickness of about 15 μm can be made of an acrylic UV-sensitive adhesive.

[0248] When the polymer film 801 is a UV-sensitive dicing tape and exposed to UV light, the tackiness of the film 801 is significantly reduced. After removing the island-shaped Group III nitride-based semiconductor layer 109 from the substrate 101, the polymer film 801 is exposed to UV light, allowing easy removal.

[0249] Heat sink plate

[0250] As described above, the removed strip 501 may be transferred to a heat sink plate 1505, which may be AlN, SiC, Si, Cu, CuW, etc. As shown in FIG. 15( e), a solder 1506 for bonding (which may be Au-Sn, Su-Ag-Cu, Ag paste, etc.) is provided on the heat sink plate 1505. Then, the n-electrode 1504 or the p-electrode 408 is bonded to the solder 1506. The device 110 may also be a flip chip bonded to the heat sink plate 1505.

[0251] In the case of bonding the LED device 110 to the heat sink plate 1505 , the size of the heat sink plate 1505 does not matter and can be designed as desired.

[0252] In the case of bonding the laser diode device 110 to the heat sink plate 1505, preferably, for the facet 504 coating process, the length of the heat sink plate 1505 may be the same as or shorter than the length of the laser diode device 110, wherein the length of the laser diode device 110 is almost the same as the length of the laser cavity. By doing so, it is easy to coat both facets 504 of the laser cavity. If the length of the heat sink plate 1505 is longer than the laser cavity, the heat sink plate 1505 may hinder uniform coating of the laser facets 504.

[0253] Long and wide heat sink plate

[0254] The longer width of the heat sink plate 1505 allows for more efficient manufacturing of the laser device 110. Fig.17 As shown, the heat sink plate 1505 is placed on the spacer plate 1701, and then both are stacked with other heat sink plates 1505 and spacer plates 1701 in the coating holder 1702 to simultaneously coat multiple devices 110. Thus, a single coating process can coat a large number of devices 110.

[0255] Heat sink plate with grooves

[0256] Preferably, the heat sink plate 1505 has grooves 1507 for dividing the device 110, as shown in Figures 15 (e) and 15 (f). This structure is useful after the facet 504 coating process, and the heat sink plate 1505 is divided into one or more devices 110, for example, a single device 110 or an array of devices 110. After dividing the heat sink plate 1505, the device 110 can be manufactured as a package or a module, such as a light-emitting module. The grooves 1507 in the heat sink plate 1505 guide the division into the device 110. The grooves 1507 can be made by a wet etching method and machined before the device 110 is mounted on the heat sink plate 1505. For example, if the heat sink plate 1505 is made of silicon, wet etching can be used to form the grooves 1507. Using the grooves 1507 in this way reduces the lead time of the process.

[0257] Heat sink plate with solder

[0258] Preferably, the length of solder 1506 is shorter than the length of device 110 on heat sink plate 1505, as shown in FIG15(f). This prevents any wrapping of solder 1506 around bisecting surface 504, which may result in degradation of the characteristics of device 110. In particular, wrapping should be avoided for flip chip mounting.

[0259] As shown in FIG. 18( b), after the coating process, the heat sink plate 1505 has wrapping areas, which are areas surrounded by dotted lines. The wrapping areas have a width W of about 10–20 μm. The coating film will have coated these areas. It is also difficult to avoid coating the solder 1506 with the coating film. In general, the coating film is selected from one or more dielectric materials, so this area is not conductive. When the lead 1802 is bonded to the solder 1506, this is a problem for both conductivity and adhesion. Therefore, the lead 1802 is preferably set to avoid the wrapping area. At least, the wire bond body 1802 should be set about 25 μm from the edge of the heat sink plate 1505.

[0260] Alternative Embodiments

[0261] First embodiment

[0262] The Group III nitride based semiconductor device 110 and the method for manufacturing the same are explained according to the first embodiment.

[0263] In the first embodiment, as shown in FIG. 1 , a base substrate 101 is first provided, and a growth restriction mask 102 having a plurality of stripe-shaped opening regions 103 is formed on the substrate 101 .

[0264] In this embodiment, the base substrate 101 is an m-plane substrate 101 formed of a semiconductor based on a group III nitride, which has no miscut orientation. As shown in FIG. 3(a), image (1) of FIG. 3(b), and image (1) of FIG. 3(c), the island-shaped group III nitride-based semiconductor layer 109 is substantially uniform and has a very smooth surface. Thereafter, as shown in FIG. 25(a) and FIG. 9, the island-shaped group III nitride semiconductor layer 109 has been used Figure 8(a)-8(e) Remove using the method shown in .

[0265] Then, the island-shaped III-nitride semiconductor layer 109 is divided into devices 110 using a rupture method. Fig. 25(a) shows the m-plane (1-100) facet 2501 and the c-plane (0001) facet 2502 of the island-shaped III-nitride semiconductor layer 109 after cleavage, wherein the facet 2502 is atomically smooth because it is made by cleavage.

[0266] It is believed that there are several reasons why these methods achieve better results. First, the island-shaped III-nitride-based semiconductor layer 109 is removed from the m-plane GaN substrate 101. The free-standing GaN substrate 101 has many defects, such as dislocations and stacking faults. These defects prevent the cleavage direction from being straight; instead, the cleavage direction bends where the defects exist.

[0267] However, in the present invention, the island-shaped Group III nitride semiconductor layer 109 is divided after removing the substrate 101. Therefore, the cleavage is not affected by the substrate 101 having disturbances distributed in the plane. In addition, the island-shaped Group III nitride semiconductor layer 109 is made by MOCVD, so they have extremely high crystal quality. This is one of the reasons why smooth facets are obtained.

[0268] Second, the width of the cleavage region and the height of the cleavage region are very narrow and short, which makes it easy to obtain smooth facets. The width is about 40-180 μm, and the height is about 10-180 μm. In the prior art, the width of the cleavage region is typically more than a few centimeters, which is 100 times longer than the present invention.

[0269] The island-shaped semiconductor layer 109 can be processed through steps 1 to 13 of the above method to obtain the laser diode device 110 .

[0270] Second embodiment

[0271] In the second embodiment, the AlGaN layer is used as an island-shaped III-nitride-based semiconductor layer 109. The AlGaN layer can be grown as an ELO III-nitride layer 105 on various bias angle substrates 101, and the Al composition is set to 0.03-0.05. As shown in Figure 3(f), using the present invention, the AlGaN layer 109 can have a very smooth surface. Using the present invention, the AlGaN layer 109 can be removed from various bias angle substrates 101 as an island-shaped III-nitride-based semiconductor layer 109. As shown in Figure 25(b), the AlGaN layer 109 provides a smooth facet 2502 to split the strips 501 of the device 110.

[0272] Third embodiment

[0273] In a third embodiment, an ELO GaN-based layer 105 is grown on various bias angle substrates 101. FIG. 3(c) and FIG. 3(d) each contain three SEM images of various bias angle substrates 101 used with island-shaped Group III nitride semiconductor layers 109. The bias angle orientation range is from 0 to +15 degrees in FIG. 3(c) and from 0 to -28 degrees (from the m-plane toward the c-plane) in FIG. 3(d). The present invention can remove the strips 501 from the various bias angle substrates 101 without breaking the strips, as shown in FIG. 9.

[0274] When a semipolar substrate 101 is used, as Figure 5(a)-5(d) As shown, a division support region 502 can be used to help the strip 501 obtain a smooth facet 504.

[0275] Fourth embodiment

[0276] In the fourth embodiment, the ELO GaN-based layer 105 is grown on a c-plane substrate 101 having two different mis-cut orientations. FIG3(e) shows SEM images of two different mis-cut orientation substrates 101 having island-shaped III-nitride-based semiconductor layers 109. As shown in FIG25(c), the island-shaped III-nitride semiconductor layers 109 have been grown using Figure 8(a)-8(e) Remove using the method shown in .

[0277] Then, the island-shaped III-nitride semiconductor layer 109 is divided into devices 110 using a rupture method. Fig. 25(c) shows an m-plane facet 2503 of the island-shaped III-nitride semiconductor layer 109 after cleavage, as well as a backside surface 2504 and a separation region 2505. The facet 2503 is atomically smooth because the facet 504 is made by the cleavage method.

[0278] Fifth embodiment

[0279] In the fifth embodiment, a sapphire substrate 201 is used as the foreign substrate 201 . Figure 2 The structure of an island-shaped III-nitride-based semiconductor layer 109 on a foreign substrate 201 is shown. The structure is almost the same as the first embodiment except that a sapphire substrate 201 and a buffer layer 202 are used. The buffer layer 202 is generally used together with the III-nitride-based semiconductor layers 105, 106, and 109 grown on the sapphire substrate 201. In this embodiment, the buffer layer 202 may include both the buffer layer 202 and the n-GaN layer or the undoped GaN layer. The buffer layer 202 is grown at a low temperature of about 500-700°C. The n-GaN layer or the undoped GaN layer is grown at a higher temperature of about 900-1200°C. The total thickness is about 1-3μm. Then, a growth restriction mask 102 is set on the buffer layer 202 and the n-GaN layer or the undoped GaN layer. The remaining processes for completing the device 110 are the same as the first embodiment.

[0280] On the other hand, the buffer layer 202 is not necessarily used. For example, the growth limiting mask 102 may be directly disposed on the foreign substrate 201. Thereafter, the ELO GaN-based layer 105 and / or the Group III nitride-based semiconductor device layer 106 may be grown. In this case, the interface between the surface of the foreign substrate 201 and the bottom surface of the ELO GaN-based layer 105 is easily divided due to the foreign interface containing many defects.

[0281] With the present invention, even when using a foreign substrate 201, atomically smooth facets for resonance can be obtained because facets 504 are formed after removing epitaxial layers 105, 106, 109 from foreign substrate 201. In this case, the type of substrate 201 does not affect the division of support region 502. Using a foreign substrate 201 has a large impact on mass production.

[0282] For example, the substrate 201 used can be a low-cost and large-size substrate 201 such as sapphire, GaAs, and Si, compared to a free-standing GaN substrate 101. This results in a low-cost device 110. In addition, sapphire and GaAs substrates 201 are materials known to have low thermal conductivity, so devices using these substrates 201 have thermal problems. However, using the present invention, these thermal problems can be avoided because the device 110 is removed from the foreign substrate 201.

[0283] Furthermore, in the case of using the ELO growth method to remove the strips 501 of the device 110 , the method can significantly reduce the dislocation density and stacking fault density, which have been critical issues in the case of using the foreign substrate 201 .

[0284] Therefore, the present invention can solve many problems caused by using a foreign substrate 201.

[0285] Sixth embodiment

[0286] In the sixth embodiment, the method of manufacturing the device 110 does not use the ELO growth method. As shown in Figures 26(a), 26(b), 26(c) and 26(d), this embodiment uses a substrate 101 from bulk GaN and AlN crystal, and the substrate 101 has a growth surface including a {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11} or {10-1-1} plane, or other planes.

[0287] First, as shown in FIG26(a), an island-shaped Group III nitride semiconductor layer 109 is grown on a substrate 101. Then, the method of the first embodiment can be used to process a device 110 from step 3.

[0288] FIG. 26( b ) shows how a ridge structure 2601 is provided on an island-shaped Group III nitride-based semiconductor layer 109 at a predetermined position.

[0289] The strips 501 of the device 110 are then fabricated using a dry etching method 2602, as shown in FIG26(c). At this point, the dimensions of the strips 501 of the device 110 are set to enable the strips 501 to be removed in step 6. The dimensions of the strips 501 of the device 110 are shown in FIG26(d), and may include, for example, a strip 501 height of 5 μm, a strip 501 length of 1 mm, and a strip 501 width of 30-50 μm. The dimensions of the strips 501 of the device 110 may be optimized by the removal method and the desired device 110 dimensions.

[0290] Step 5 to step 13 are the same as those in other embodiments.

[0291] Using this embodiment, the present invention can manufacture the device 110 without using the ELO method.

[0292] Furthermore, this embodiment may use a foreign substrate 201. In this case, dry etching preferably reaches below the surface of the foreign substrate 201. The interface between the foreign substrate 201 interface and the buffer layer 202 has a weaker bonding strength than other interfaces, so the substrate 201 is easily removed.

[0293] Seventh embodiment

[0294] In the seventh embodiment, an AlGaN layer may be used as a cleavage assist layer (CAL). Preferably, the CAL has an Al composition of 3% or more and a thickness of 0.2 μm or more, depending on the Al composition. For example, the Al composition and thickness of the CAL may include 12% and 0.6 μm, 3% and 12 μm, and so on.

[0295] There are several ways to include CAL in the structure. One way is to include a significant amount of Al into the ELO Group III nitride layer 105, for example, more than 1% Al may be included when growing the ELO Group III nitride layer 105. Alternatively, the CAL may be embedded in the ELO Group III nitride layer 105, or the CAL may include a layer 106 grown on top of the ELO Group III nitride layer 105.

[0296] 27(a) and 27(b) illustrate the use of a CAL 2701, which may be formed on or within the side facets 2302, 2303 of the island-shaped III-nitride-based semiconductor layer 109. Specifically, the CAL 2701 may include one or more of the epitaxial layers 105, 106 that include the island-shaped III-nitride-based semiconductor layer 109 to assist in cleaving.

[0297] Process steps

[0298] Fig.28 is a flow chart illustrating a method for dividing strips of one or more devices, wherein the strips are composed of island-shaped Group III nitride-based semiconductor layers grown on a substrate using a growth limit mask; the island-shaped Group III nitride-based semiconductor layers are removed from the substrate using an epitaxial lateral overgrowth (ELO) method; and then the strips are divided into one or more devices using a cleaving method.

[0299] Block 2801 represents the step of providing a base substrate 101. In one embodiment, the base substrate 101 is a Group III nitride based substrate 101, such as a GaN based substrate 101.

[0300] Block 2802 represents an optional step of depositing an intermediate layer on substrate 101. In one embodiment, the intermediate layer is a Group III nitride based layer, such as a GaN based layer.

[0301] Box 2803 represents the step of forming a growth restriction mask 102 on or over the substrate 101 (ie, on the substrate 101 itself or on an intermediate layer). The growth restriction mask 102 is patterned to include a plurality of opening regions 103.

[0302] Block 2804 represents the step of growing one or more III-nitride based layers 105 on or over growth limit mask 102 using epitaxial lateral overgrowth (ELO), wherein the epitaxial lateral overgrowth of III-nitride layers 105 extends in a direction parallel to opening regions 103 of growth limit mask 102, and the epitaxial lateral overgrowth stops before III-nitride layers 105 merge on strips 102a of growth limit mask 102. In one embodiment, ELO III-nitride based layers 105 are ELO GaN based layers 105.

[0303] Box 2805 represents the step of forming strips 501 by growing one or more additional III-nitride-based semiconductor device layers 106 on ELO III-nitride-based layer 105. These additional III-nitride-based semiconductor device layers 106, together with ELO III-nitride-based layer 105, produce one or more of the island-shaped III-nitride-based semiconductor layers 109.

[0304] Block 2806 represents the step of forming one or more division support regions 502 along the strip 501. The division support regions 502 may be formed on the first facet 504 and / or the second facet 505 of the strip 501. In addition, the division support regions 502 may be formed on one or both sides of the strip 501. The division support regions 502 are formed with periodic lengths, wherein each period is determined by the length of the device, and each of the division support regions 502 includes a scribe line. In addition, the division support regions 502 are generated at the flat surface region 107 in a manner to avoid current injection into the region 503.

[0305] Box 2807 represents a step of applying a polymer film 801 to the strips 501 to remove the strips 501 from the substrate 101 using a cleaving technique on the surface of the substrate 101, which includes mechanically separating or peeling the island-shaped Group III nitride-based semiconductor layer 109 from the substrate 101. The polymer film 801 is applied to the strips 501 by applying pressure to the film 801 and the substrate 101 using a plate 806. The method may also include changing the temperature of the film 801 and the substrate 101 while applying the pressure, thereby utilizing the difference in thermal coefficient between the film 801 and the substrate 101 to remove the strips 501 from the substrate 101.

[0306] Block 2808 represents the step of dividing the strip 501 into one or more devices 110 by cleaving at the dividing support regions 502 formed along the strip 501. This step may also include creating one or more facets 504 on each of the laser diode devices 110.

[0307] Block 2809 represents the step of mounting each device 110 on the heat sink plate 1505 to coat the one or more facets 504 of the device 110 resulting from the cleaving. This step also includes separating the devices 110 by splitting the heat sink plate 1505 at the grooves 1507 in the heat sink plate 1505. The heat sink plate 1505 may be split before or after the wire bonds 1801, 1802 are attached to the devices 110.

[0308] Box 2810 represents the resulting products of the method, namely, one or more Group III nitride based semiconductor devices 110 fabricated according to the method, and a substrate 101 that has been removed from the device 110 and is available for recycling and reuse.

[0309] Advantages and Benefits

[0310] The present invention provides several advantages and benefits:

[0311] • The expensive Group III-nitride based substrate 101 can be reused after removing the substrate 101 from the device 110 layer.

[0312] Using the same or similar material for substrate 101 allows obtaining high quality layers 105, 106, 109 with very low defect density.

[0313] • Using the same or similar materials for both the substrate 101 and the layers 105 , 106 , 109 may reduce the strain in the layers 105 , 106 , 109 .

[0314] • Using materials with the same or similar thermal expansion for both the substrate 101 and the layers 105, 106, 109 can reduce bowing of the substrate 101 during epitaxial growth.

[0315] The layer 105 grown by ELO is of high quality.

[0316] • The ELO GaN based layers 105 do not merge with each other and the internal tension is released, which helps to avoid any cracks from occurring. This is very useful for the device layer 106 being an AlGaN layer, especially in the case of a high Al content layer.

[0317] The island-shaped Group III nitride based semiconductor layers 109 are isolatedly formed, and thus tensile stress or compressive stress does not occur on other island-shaped Group III nitride based semiconductor layers 109 .

[0318] In addition, the growth limit mask 102 and the ELO GaN based layer 105 are not chemically bonded, so stress in the ELO GaN based layer 105 and the additional device layer 106 can be released by slip generated at the interface between the growth limit mask 102 and the ELO GaN based layer 105 .

[0319] The presence of the no-growth region 104 between each of the island-shaped Group III nitride-based semiconductor layers 109 provides flexibility, and the substrate 101 is easily deformed and can be bent when an external force is applied. Therefore, even if there is a slight bend, curvature, or deformation in the substrate 101, this can be easily corrected by a small external force to avoid cracks. Therefore, the substrate 101 can be processed with a vacuum chuck, so that the manufacturing process of the semiconductor device can be performed more easily.

[0320] The no-growth regions 104 make it easy to dissolve the growth limit mask 102 over a large area.

[0321] The layers 105, 106, 109 of high-quality semiconductor crystal can be grown by suppressing the curvature of the substrate 101, and in addition, even when the layers 105, 106, 109 are thick, the occurrence of cracks and the like can be suppressed, and thus a large-area semiconductor device can be easily manufactured.

[0322] • The manufacturing method can also be easily adapted to large size wafers (>2 inches).

[0323] Modifications and Replacements

[0324] Several modifications and substitutions may be made without departing from the scope of the invention.

[0325] For example, the present invention can be used with other oriented Group III nitride substrates. Specifically, the substrate can be of the basic non-polar m-plane {1 0 -1 0} family; and a semi-polar plane family having at least two non-zero h, i or k Miller indices and a non-zero l Miller index, such as the {2 0 -2 -1} plane. The (20-2-1) semi-polar substrate is particularly useful because of the wide area of ​​flat ELO growth.

[0326] In another example, the present invention is described as being used to manufacture different optoelectronic device structures, such as light emitting diodes (LEDs), laser diodes (LDs), Schottky barrier diodes (SBDs), or metal oxide semiconductor field effect transistors (MOSFETs). The present invention can also be used to manufacture other optoelectronic devices, such as micro-LEDs, vertical cavity surface emitting lasers (VCSELs), side emitting laser diodes (EELDs), and solar cells.

[0327] in conclusion

[0328] This concludes the description of the preferred embodiments of the present invention. The foregoing description of one or more embodiments of the present invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The scope of the present invention is not intended to be limited by this detailed description, but rather by the appended claims.

Claims

1. A method for dividing a strip of one or more devices, comprising: preparing a strip comprising one or more Group III nitride-based semiconductor layers having a layer bending region on or above a substrate; forming one or more divided support regions along the strip, at least in a portion of the layer bending region of the strip; removing the strips from the substrate after forming the one or more divided support regions; as well as After removing the strip from the substrate, the strip is divided into one or more devices by cleaving at the division support regions formed along the strip.

2. The method of claim 1, wherein the partition support area is formed on a first facet and / or a second facet of the strip. The method of claim 1 , wherein the partition support area is formed on one side of the strip. The method of claim 1 , wherein the partition support area is formed on both sides of the stripe.

5. The method of claim 1, wherein the partitioned support region is formed with periodic lengths, wherein each period is determined by a length of the device. The method of claim 1 , wherein each of the partition support regions comprises a scribe line. 7 . The method of claim 1 , wherein the partition support region is generated at a flat surface region in a manner avoiding a current injection region.

8. The method of claim 1, wherein a film is applied to the strip to remove the strip from the substrate, and the film is applied to the strip by applying pressure to the film and the substrate using a plate.

9. The method of claim 8, further comprising changing the temperature of the membrane and the substrate while applying the pressure.

10. The method of claim 9, further comprising utilizing a difference in thermal coefficient between the film and the substrate to remove the strip from the substrate.

11. The method of claim 1, wherein said cleaving further comprises creating one or more facets on each of said devices.

12. The method of claim 11, further comprising mounting each of the devices on a heat sink plate to coat one or more of the facets of the device resulting from the cleaving. 13 . The method of claim 12 , further comprising separating the devices in the heat sink plate by dividing the heat sink plate at grooves.

14. The method of claim 13, wherein the heat sink plate is singulated before or after a wire bond is attached to the device.

15. A device manufactured by the method of claim 1.

16. A method for partitioning a strip of one or more devices, comprising: preparing a strip composed of a plurality of island-shaped Group III nitride-based semiconductor layers on or above a substrate; forming one or more divided support regions along the strip, at least in a portion of the layer bending region; as well as The strip is removed from the substrate by cleaving into one or more devices at the partitioned support region.

17. The method of claim 16, further comprising forming the one or more division support regions before dividing the strips, and cleaving into one or more devices at the division support regions to form facets of the devices.

18. The method of claim 17, further comprising mounting the device on a heat sink plate prior to coating the facets.

19. A method for partitioning a strip of one or more devices, comprising: preparing a strip composed of an island-shaped Group III nitride-based semiconductor layer grown on or over a substrate using a growth confinement mask; dividing the strip into one or more devices at one or more division support regions formed at least in a portion of a layer bending region of the island-shaped Group III nitride based semiconductor layer; as well as After dividing the strip into one or more devices, the island-shaped Group III nitride-based semiconductor layer of the device is removed from the substrate. 20 . The method of claim 19 , further comprising stopping growth of the island-shaped Group III nitride based semiconductor layer before the island-shaped Group III nitride based semiconductor layer is merged.

21. A method for partitioning a strip of one or more devices, comprising: growing one or more Group III nitride-based semiconductor layers on or over a substrate using an epitaxial lateral overgrowth (ELO) technique, wherein the Group III nitride-based semiconductor layers form one or more strips separated from each other on the substrate; removing said strip from said substrate without substantially including any of said substrate; as well as The removed strip is cleaved at one or more dividing support regions formed at least in a portion of a layer bending region of the Group III nitride-based semiconductor layer to form one or more devices, wherein the one or more dividing support regions are formed along the strip before removing the strip from the substrate.

22. The method of claim 21, wherein the partition support area is formed on a first facet and / or a second facet of the strip.

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