Time-interleaved digital-to-analog converter and conversion method thereof

Abstract

The present invention discloses a time-interleaved digital-to-analog converter for converting a digital signal into an analog signal, comprising: a digital processing circuit for generating a plurality of data sequences according to a digital signal of the time-interleaved digital-to-analog converter, wherein the plurality of data sequences include a first data sequence and a second data sequence; a time-domain dynamic element matching circuit for exchanging a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence; a plurality of digital-to-analog converters, each of which has at least one digital-to-analog converter unit; and a combining circuit for generating an analog signal by combining the analog outputs of the plurality of digital-to-analog converters. The present invention can reduce distortion caused by gain mismatch, offset mismatch and / or timing mismatch between different DAC channels used by the time-interleaved analog converter.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a time-interleaved analog-to-digital converter and a conversion method thereof. Background Art

[0002] Various applications have great demands for high-speed and large-bandwidth digital-to-analog converters (DACs). Time-interleaved DACs can achieve high-speed digital-to-analog conversion operations, but they cause distortion due to mismatches between different DAC channels. Therefore, an innovative time-interleaved DAC architecture is needed that can mitigate distortion caused by gain mismatch, offset mismatch, and / or timing mismatch between different DAC channels. Summary of the invention

[0003] In view of this, the present invention provides a time-interleaved analog-to-digital converter and a conversion method thereof to mitigate distortion caused by gain mismatch, offset mismatch and / or timing mismatch between different DAC channels.

[0004] According to a first aspect of the present invention, a time-interleaved digital-to-analog converter is disclosed, for converting a digital signal into an analog signal, comprising:

[0005] A digital processing circuit, configured to generate a plurality of data sequences according to the digital signal of the time-interleaved digital-to-analog converter, wherein the plurality of data sequences include a first data sequence and a second data sequence;

[0006] A time-domain dynamic element matching circuit, configured to exchange a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence, wherein the first adjusted data sequence includes a first bit of the first data sequence and a first bit of the second data sequence, and the second adjusted data sequence includes a second bit of the first data sequence and a second bit of the second data sequence;

[0007] a plurality of digital-to-analog converters, each digital-to-analog converter having at least one digital-to-analog converter unit, wherein the plurality of digital-to-analog converters include a first digital-to-analog converter unit operating in response to a first adjusted data sequence and a second digital-to-analog converter unit operating in response to a second adjusted data sequence; and

[0008] The combining circuit is used to generate an analog signal by combining the analog outputs of the plurality of digital-to-analog converters.

[0009] According to a second aspect of the present invention, a time-interleaved digital-to-analog conversion method is disclosed, for converting a digital signal into an analog signal, comprising:

[0010] generating a plurality of data sequences according to the digital signal, wherein the plurality of data sequences include a first data sequence and a second data sequence;

[0011] Performing a time-domain dynamic element matching operation by exchanging a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence, wherein the first adjusted data sequence includes: a first bit of the first data sequence and a first bit of the second data sequence, and the second adjusted data sequence includes a second bit of the first data sequence and a second bit of the second data sequence; and

[0012] An analog signal is generated by combining analog outputs of a plurality of digital-to-analog converters, each having at least one digital-to-analog converter unit, wherein the plurality of digital-to-analog converters include a first digital-to-analog converter unit and a second digital-to-analog converter, the first digital-to-analog converter including a first digital-to-analog converter unit operating in response to the first adjusted data sequence, and the second digital-to-analog converter including a second digital-to-analog converter unit operating in response to the second adjusted data sequence.

[0013] The time-interleaved digital-to-analog converter of the present invention includes a time-domain dynamic element matching circuit, which is used to exchange a part of the first data sequence with a part of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. In this way, the gain and offset are smoother, for example, the gain and offset of each cycle of the analog signal are more averaged, avoiding large fluctuations in gain and offset; therefore, the present invention can reduce the distortion caused by gain mismatch, offset mismatch and / or timing mismatch between different DAC channels of the time-interleaved analog converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram illustrating a time-interleaved digital-to-analog converter (DAC) with time-domain dynamic element matching (TDEM) according to an embodiment of the present invention.

[0015] Figure 2 is a diagram showing an embodiment of the present invention Figure 1 A diagram showing the operation of the combinational circuit.

[0016] Figure 3is a block diagram illustrating a DAC used in a time-interleaved DAC according to an embodiment of the present invention.

[0017] Figure 4 is a diagram illustrating a time-interleaved DAC operation without TDEM according to an embodiment of the present invention.

[0018] Figure 5 is a diagram illustrating a time-interleaved DAC operation using TDEM according to an embodiment of the present invention.

[0019] Figure 6 is a block diagram illustrating another time-interleaved DAC with TDEM according to an embodiment of the present invention.

[0020] Figure 7 is a diagram illustrating another time-interleaved DAC operation without TDEM according to an embodiment of the present invention.

[0021] Figure 8 is a diagram illustrating another time-interleaved DAC operation using TDEM according to an embodiment of the present invention.

[0022] Fig. 9 is a diagram showing an embodiment of the present invention Figure 1 and Figure 6 A block diagram of an exemplary design of a TDEM circuit is shown.

[0023] Fig.10 is a diagram illustrating a random sequence exchange operation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] Certain terms are used throughout the following description and claims to refer to specific components. As will be appreciated by those skilled in the art, electronic device manufacturers may refer to components by different names. This document is not intended to distinguish between components that have different names but the same function. In the following description and claims, the terms "include" and "comprising" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". Similarly, the term "coupled" is intended to mean an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0025] Figure 11 is a block diagram showing a time-interleaved digital-to-analog converter (DAC) with time-domain dynamic element matching (TDEM) according to an embodiment of the present invention. The time-interleaved DAC 100 (time-interleaved DAC 100) includes a digital processing circuit 102, a TDEM circuit 104, a plurality of DACs 106_1 to 106_K, and a combination circuit 108. Each DAC 106_1 to 106_K (each of the DACs 106_1-106_K) can be regarded as a DAC element (or sub-DAC) of the time-interleaved DAC 100. The time-interleaved DAC 100 is used to convert a digital signal D_IN into an analog signal V_OUT. In the present embodiment, the time-interleaved DAC 100 may be a K-channel N-bit time-interleaved DAC, and each DAC 106_1-106_K (each of the DACs 106_1-106_K) may have M DAC units, where K, M and N are positive integers, K>1, N≥1, and M=2N-1. The digital processing circuit 102 is arranged to generate a plurality of digital inputs D1 to DK according to the digital signal D_IN, where each digital input D1-DK (each of the digital inputs D1-DK) includes M data sequences. For example, the digital input Di includes data sequences Di_1 to Di_M, where For example, considering the case where K=2, the digital input D1 includes a data sequence D1_1 to D1_M, and the digital input D2 (ie, DK=D2) includes a data sequence D2_1 to D2_M.

[0026] The TDEM circuit 104 is arranged to adopt the TDEM scheme proposed by the present invention to adjust the digital inputs D1-DK to generate adjusted digital inputs (or adjusted digital inputs) D'1-D'K, wherein each adjusted digital input D'1-D'K includes M adjusted data sequences (or adjusted data sequences). For example, the adjusted digital input D'i includes adjusted data sequences D'i_1-D'i_M, wherein For example, considering the case where K=2, the adjusted digital input D'1 includes the adjusted data sequence D'1_1-D'1_M, and the adjusted digital input D'2 (i.e., D'K=D'2) includes the adjusted data sequence D'2_1-D'2_M. In this embodiment, the TDEM circuit 104 may include a portion of the data sequence (e.g., D1_j, where ) and a portion of a data sequence (e.g., DK_j, where ) to generate an adjusted data sequence (eg, D'1_j, where ) and an adjusted data sequence (eg, D'K_j, where ). Therefore, an adjusted data sequence (e.g., D'1_j, where ) includes a data sequence (e.g., D1_j, where ) and another data sequence (e.g., DK_j, where ), another adjusted data sequence (e.g., D'k_j, where ) includes a data sequence (for example, D1_j, where ) and another data sequence (e.g., DK_j, where In another embodiment, the TDEM circuit 104 may also include a portion of the data sequence (eg, D1_j, where ) and a portion of a data sequence (e.g., DK_p, where and j may be equal to or not equal to p) to generate an adjusted data sequence (eg, D'1_j, where ) and an adjusted data sequence (eg, D'K_p, where Similarly, j may be equal to or not equal to p). That is, when the bits or DAC units in the adjusted data sequence are exchanged, the exchanged bits or DAC units may be located at the same position (same order or same rank), or may not be located at the same position (same order or same rank); the values ​​of the exchanged bits (e.g., 0 or 1) only need to be equal (or the states of the exchanged DAC units only need to be the same).

[0027] The DACs 106_1-106_K are arranged to receive conditioned digital inputs D'1-D'K and convert the conditioned digital inputs D'1-D'K into analog outputs VOUT_1-VOUT_K, respectively. The combining circuit 108 is arranged to generate an analog signal V_OUT by combining the analog outputs VOUT_1-VOUT_K of the DACs 106_1-106_K.

[0028] For example, the combining circuit 108 may generate the analog signal V_OUT by applying interleaving to the analog outputs VOUT_1 - VOUT_K. Figure 2 1 is a diagram showing the operation or operation of a combinational circuit according to an embodiment of the present invention. It is assumed that the time-interleaved DAC 100 is a two-channel time-interleaved DAC, where K=2. Therefore, the time-interleaved DAC 100 includes two DACs 106_1 and 106_2 (also referred to as "P-DAC" and "N-DAC"), which are used to apply digital-to-analog conversion to the adjusted data inputs D'1 and D'2, respectively. A key difference between the time-interleaved DAC 100 proposed by the present invention and the conventional time-interleaved DAC is that the digital inputs of the DACs 106_1 and 106_2 are generated via the TDEM scheme proposed by the present invention. The conversion voltage generated at the DAC 106_1 is sampled and output at the rising edge of the clock cycle CLK_S (with a period Ts), and the conversion voltage generated at the DAC 106_2 is sampled and output at the falling edge of the clock CLK_S. Therefore, the analog output VOUT_1 of the DAC 106_1 and the analog output VOUT_2 of the DAC 106_2 are interleaved at the combinational circuit 108 to generate an analog signal V_OUT.

[0029] Combination Figure 1 As shown, in this embodiment, each DAC 106_1-106_K may have M DAC units, and the digital processing circuit 102 may have an encoder 110, which is used to encode each N-bit codeword of the digital signal D_IN into an M-bit thermometer code, wherein the M bits of one thermometer code are respectively allocated to the M data sequences included in one of the digital inputs D1-DK. In other words, the digital inputs D1-DK contain different bits of the same thermometer code. The bits of one thermometer code are used to control the on / off state of the DAC unit. Figure 3 1 is a block diagram showing a DAC used in a time-interleaved DAC according to an embodiment of the present invention. Each DAC 106_1-106_K may have the same structure. For clarity and simplicity, Figure 3Only DAC 106_1 is shown in the figure. DAC 106_1 includes a plurality of DAC units 302_1-302_M, which operate or run (operate, run or work) in response to the adjusted data sequence D'1_1, D'1_2, D'1_3, ..., D'1_M included in the adjusted digital input D'1, which is generated from the TDEM circuit 104. Since the adjusted digital inputs D'1-D'K are obtained by applying the TDEM technology to the digital inputs D1-DK, the distortion caused by the gain mismatch (or mismatch), offset mismatch and / or timing mismatch between the DACs 106_1-106_K used by different DAC channels (channels) of the time-interleaved DAC 100 can be alleviated. More details of the TDEM scheme proposed by the present invention will be described as follows.

[0030] Figure 4 FIG. 1 is a diagram showing the operation of a time-interleaved DAC without TDM according to an embodiment of the present invention. Assume that the time-interleaved DAC 100 is as follows Figure 2The 2-channel 3-bit time-interleaved DAC shown, considering the case where the TDEM circuit 104 directly bypasses the digital inputs D1 and D2 to the DACs 106_1 and 106_2, respectively, the DAC units of the DAC 106_1 (“P-DAC”) can operate or run (operate) in response to each bit of the even thermometer code C0, C2, C4, C6, C8, C10 generated by the encoder 110, and the DAC units of the DAC 106_2 (“N-DAC”) can operate or run (operate, run or work) in response to each bit of the odd thermometer code C1, C3, C5, C7, C9, C11 generated from the encoder 110. In this example, the thermometer code C0 from the most significant bit (MSB) to the least significant bit (LSB) may be "0000001", the thermometer code C1 from MSB to LSB may be "0000111", the thermometer code C2 from MSB to LSB may be "0011111", the thermometer code C3 from MSB to LSB may be "0001111", the thermometer code C4 from MSB to LSB may be "1111111", and the thermometer code C5 from MSB to LSB may be " 0001111", thermometer code C6 from MSB to LSB can be "0000011", thermometer code C7 from MSB to LSB can be "0011111", thermometer code C8 from MSB to LSB can be "0000111", thermometer code C9 from MSB to LSB can be "0000011", thermometer code C10 from MSB to LSB can be "0001111", and thermometer code C11 from MSB to LSB can be "0000111".

[0031] In this example, the TDEM function is not enabled (directly to the DAC without passing through the TDEM circuit). When the DAC cells (denoted as "cell-1", "cell-2", "cell-3", "cell-4", "cell-5", "cell-6", and "cell-7") of DAC 106_1 ("P-DAC") receive a bit of the thermometer code, any DAC cell receiving "1" is turned on, and any DAC cell receiving "0" is turned off. When the DAC cells (denoted as "cell-1", "cell-2", "cell-3", "cell-4", "cell-5", "cell-6", and "cell-7") of DAC 106_2 ("N-DAC") receive a bit of the thermometer code, any DAC cell receiving "1" is turned on, and any DAC cell receiving "0" is turned off. For example, when the DAC cells of DAC 106_1 (“P-DAC”) receive bits of thermometer code C0, DAC cell “cell-1” is turned on, while DAC cells “cell-2” to “cell-7” are turned off; when the DAC cells (represented as “cell-1”, “cell-2”, “cell-3”, “cell-4”, “cell-5”, “cell-6” and “cell-7”) of DAC 106_2 (“N-DAC”) receive bits of thermometer code C1, then DAC cells “cell-1” to “cell-3” are turned on, while DAC cells “cell-4” to “cell-7” are turned off.

[0032] The data sequence D1_1-D1_M (M=7) in the DAC cells "cell-1" to "cell-7" fed into the DAC 106_1 ("P-DAC") is set by thermometer codes C0, C2, C4, C6, C8, and C10. In addition, the data sequence D2_1-D2_M (M=7) in the DAC cells "cell-1" to "cell-7" fed into the DAC 106_2 ("N-DAC") is set by thermometer codes C1, C3, C5, C7, C9, and C11. For example, the data sequence D1_1 in the DAC cell "cell-1" fed into the DAC 106_1 ("P-DAC") is set by "111111", and the data sequence D2_1 in the DAC cell "cell-1" fed into the DAC 106_2 ("N-DAC") is set by "111111". For another example, the data sequence D1_2 in the DAC cell "cell-2" fed to the DAC 106_1 ("P-DAC") is set by "011111", and the data sequence D2_2 in the DAC cell "cell-2" fed to the DAC 106_2 ("N-DAC") is set by "111111".

[0033] In order to dither the gain mismatch (or mismatch), offset mismatch and / or timing mismatch between DAC elements used by different DAC channels of a time-interleaved DAC, the present invention proposes a TDEM scheme. Figure 5 FIG. 1 is a diagram showing the operation of a time interleaved DAC using TDM according to an embodiment of the present invention. Assume that the time interleaved DAC 100 is as follows Figure 2 2-channel time-interleaved DAC shown. In this example, the TDEM circuit 104 is enabled to apply the TDEM technique to the digital inputs D1 and D2 to generate adjusted digital inputs D'1 and D'2 to be respectively given to the DACs 106_1 and 106_2, wherein the DAC cells "cell-1" to "cell-7" of the DAC 106_1 ("P-DAC") operate or run (operate, operate or work) in response to the adjusted data sequences D'1_1-D'1_M (M=7), respectively, and the DAC cells "cell-1" to "cell-7" of the DAC 106_2 ("N-DAC") operate or run in response to the adjusted data sequences D'2_1-D'2_M (M=7), respectively.

[0034] like Figure 5As shown, by turning on the DAC cell "cell-1" of the DAC 106_2 ("N-DAC") and turning off the DAC cells "cell-2"-"cell-5" of the DAC 106_1 ("P-DAC") and the DAC cells "cell-6"-"cell-7" of the DAC 106_2 ("N-DAC"), a voltage level representing the thermometer code C0 is output; by turning on the DAC cell "cell-1" ("P-DAC") of the DAC 106_1 and the DAC cells "cell-2"-"cell-3" of the DAC 106_2 ("N-DAC") and turning off the DAC cells "cell-4"-"cell-5" of the DAC 106_2 ("N-DAC") and the DAC cells "cell-6"-"cell-7" of the DAC 106_1 ("P-DAC"), a voltage level representing the thermometer code C1 is output; and by turning on the DAC DAC cells "cell-1" and "cell-3" of DAC 106_2 ("N-DAC") and DAC cells "cell-2", "cell-4" and "cell-5" of DAC 106_1 ("P-DAC"), and DAC cell "cell-6" of DAC 106_1 ("P-DAC") and DAC cell "cell-7" of DAC 106_2 ("N-DAC") are turned off to output a voltage level representing the thermometer code C2; ​​and so on. According to the TDEM scheme proposed in the present invention, the first bit and the second bit processed successively by the DAC cells of the first DAC and the DAC cells of the second DAC are interchanged or swapped in the time domain, so that the second bit and the first bit are processed successively by the DAC cells of the first DAC and the DAC cells of the second DAC. In addition, in Figure 5 In the example shown ( Figure 5 As shown in the table on the right, cell-7 in the cycle where thermometer code C0 is located is exchanged with cell-7 in the cycle where thermometer code C1 is located, and cell-6 of thermometer code C0 is exchanged with cell-6 of thermometer code C1. However, in some embodiments, cell-7 in the cycle where thermometer code C0 is located can also be exchanged with cell-6 in the cycle where thermometer code C1 is located. That is to say, in the exchange in this embodiment, the bits or DAC units in the same position (same order or same rank) are not necessarily exchanged, as long as the values ​​or states of the two are the same. For example, in one example, cell-3 in the cycle where thermometer code C2 is located can also be exchanged with cell-4 in the cycle where thermometer code C3 is located. In addition, in this embodiment, the number of bits or DAC units exchanged between the two cycles is at least one, and at most depends on the same bits or DAC units between the two cycles. The specific number can be random ( Figure 5 The number of exchanges is random), which is not limited in the present invention.

[0035] In the prior art, for example Figure 5 As shown in the table on the left, in one time period, such as the period in which the thermometer code C0 is located, the analog signal or analog output V_OUT is determined by DAC 106_1 ("P-DAC"), and the DAC units in DAC 106_1 ("P-DAC") (e.g., cell-1 to cell-7 in DAC 106_1) have fixed gain and offset; in the next time period, such as the period in which the thermometer code C1 is located, the analog signal or analog output V_OUT is determined by DAC 106_2 ("N-DAC"), and the DAC units in DAC 106_2 ("P-DAC") (e.g., cell-1 to cell-7 in DAC 106_2) have fixed gain and offset (generally different from the gain and offset in the period in which the thermometer code C0 is located). The above description also applies to the periods in which the thermometer codes C2 to C11 are located. Therefore, for each time period, the output analog signal V_OUT has corresponding gain and offset, which causes distortion due to the mismatch between different DAC channels. In the embodiment of the present invention, in one time period (for example, the period in which the thermometer code C0 is located), the DAC units with the same or equal states or values ​​in one time period and the next time period are interchanged according to the states or values ​​of the corresponding DAC units in the next time period (for example, the period in which the thermometer code C1 is located), so that the analog signal V_OUT obtained will not change, but because the DAC units used have changed, the fixed gain and offset of the output analog signal V_OUT have changed compared with the previous technology, that is, the gain and offset can be made smoother in this way (for example, the gain and offset of the analog signal V_OUT in each period are more average, avoiding large fluctuations in gain and offset). Therefore, the embodiment of the present invention scrambles (dither) the DAC units used by the DAC channels of the time-interleaved DAC, thereby reducing the distortion caused by the gain mismatch, offset mismatch and / or timing mismatch between the DAC channels used by the time-interleaved analog converter.

[0036] In some embodiments of the present invention, the TDEM scheme proposed by the present invention may cooperate with a typical DEM scheme to further reduce the element matching error of a single-channel DAC and improve the performance of a time-interleaved DAC.

[0037] Figure 6is a block diagram showing another time-interleaved DAC with TDEM according to an embodiment of the present invention. The main difference between the time-interleaved DACs 100 and 600 is that the digital processing circuit 602 includes a DEM circuit 610, which is arranged to adopt a DEM scheme different from the TDEM scheme proposed above in the present invention. The DEM circuit 610 is arranged to set the digital inputs D1-DK by applying a DEM algorithm to each thermometer code generated from the encoder 110. As an example and not a limitation, the DEM algorithm adopted by the DEM circuit 610 can be a data weighted averaging (DWA) algorithm, a random scrambling algorithm, or other available DEM algorithms. The DEM circuit 610 sets M data sequences of a digital input Di according to the DEM algorithm executed by the M DAC units based on the corresponding DAC 106_i, where

[0038] Figure 7 FIG. 1 is a diagram showing another time interleaved DAC operation without TDM according to an embodiment of the present invention. Assume that the time interleaved DAC 100 is as follows Figure 2 2-channel (two-channel) time-interleaved DAC shown. Considering the case where the TDM circuit 104 directly bypasses the digital inputs D1 and D2 to DACs 106_1 and 106_2, respectively, the DAC unit of DAC 106_1 ("P-DAC") operates or runs in response to the digital output D1, and the DAC unit of DAC 106_2 operates or runs in response to the digital input D2. The DEM circuit 610 applies the DEM algorithm to each thermometer code C0-C11. Therefore, the DAC unit of DAC106_1 operates or runs in response to the DEM results of the even thermometer codes C0, C2, C4, C6, C8, C10, and the DAC unit of DAC 106_2 operates or runs in response to the DEM results of the odd thermometer codes C1, C3, C5, C7, C9, C11.

[0039] According to the DEM algorithm adopted by the present invention, the DEM result of the thermometer code C0 can be "0001000" from MSB to LSB, the DEM result of the thermometer code C1 can be "0100101" from MSB to LSB, the DEM result of the thermometer code C2 can be "0011111" from MSB to LSB, the DEM result of the thermometer code C3 can be "1011010" from MSB to LSB, the DEM result of the thermometer code C4 can be "1111111" from MSB to LSB, and the DEM result of the thermometer code C5 can be "0101010" from MSB to LSB. 1101", the DEM result of thermometer code C6 can be "1000100" from MSB to LSB, the DEM result of thermometer code C7 can be "1011011" from MSB to LSB, the DEM result of thermometer code C8 can be "0000111" from MSB to LSB, the DEM result of thermometer code C9 can be "0100100" from MSB to LSB, the DEM result of thermometer code C10 can be "1101010" from MSB to LSB, and the DEM result of thermometer code C11 can be "1010001" from MSB to LSB.

[0040] In this example, it is assumed that the TDEM function is not enabled. At this time, when the DAC cells (represented by "cell-1", "cell-2", "cell-3", "cell-4", "cell-5", "cell-6" and "cell-7") of DAC 106_1 ("P-DAC") receive a DEM result of a thermometer code, any DAC cell receiving "1" is turned on, and any DAC cell receiving "0" is turned off. When the DAC cells (represented by "cell-1", "cell-2", "cell-3", "cell-4", "cell-5", "cell-6" and "cell-7") of DAC 106_2 ("N-DAC") receive a DEM result of a thermometer code, any DAC cell receiving "1" is turned on, and any DAC cell receiving "0" is turned off. For example, when the DAC unit of DAC 106_1 ("P-DAC") receives the DEM result of thermometer code C0, DAC cell "cell-4" is turned on, while DAC cells "cell-1" to "cell-3" and "cell-5" to "cell7" are turned off; when the DAC unit of DAC 106_2 ("N-DAC") receives the DEM result of thermometer code C1, DAC cells "cell-1", "cell-3" and "cell-6" are turned on, and DAC cells "cell-2", "cell-4", "cell-5" and "cell-7" are turned off.

[0041] The data sequence D1_1-D1_M (M=7) in the DAC cells "cell-1"-"cell-7" fed to the DAC 106_1 ("P-DAC") is set by the DEM results of the thermometer codes C0, C2, C4, C6, C8, and C10. In addition, the data sequence D2_1-D2_M (M=7) in the DAC cells "cell-1"-"cell-7" ("N-DAC") fed to the DAC 106_2 is set by the DEM results of the thermometer codes C1, C3, C5, C7, C9, and C11. For example, the data sequence D1_1 of the DAC cell "cell-1" fed to the DAC 106_1 ("P-DAC") is "011010", and the data sequence D2_1 of the DAC cell "cell-1" fed to the DAC 106_2 ("N-DAC") is "101101". For another example, the data sequence D1_2 of the DAC cell “cell-2” fed to the DAC 106_1 (“P-DAC”) is “011011”, and the data sequence D2_2 of the DAC cell “cell-2” fed to the DAC 106_2 (“N-DAC”) is “010100”.

[0042] In order to scramble the gain mismatch (or mismatch), offset mismatch and / or timing mismatch between DAC elements used by different DAC channels of a time-interleaved DAC, the present invention proposes a TDEM scheme. Figure 8 FIG. 1 is a diagram showing another time interleaved DAC operation using TDM according to an embodiment of the present invention. Assume that the time interleaved DAC 100 is as follows Figure 2 2-channel (two-channel) time-interleaved DAC shown. In this example, the TDEM circuit 104 is enabled to apply the TDEM technique to the digital inputs D1 and D2 to generate adjusted digital inputs D'1 and D'2 to be input to the DACs 106_1 and 106_2, respectively, wherein the digital inputs D1 and D2 are set by the DEM circuit 610, and the DAC cells "cell-1"-"cell-7" of the DAC 106_1 ("P-DAC") respectively operate or run in response to the adjusted data sequences D'1_1-D'1_M (M=7), and the DAC cells "cell-1"-"cell-7" of the DAC 106_2 ("N-DAC") respectively operate or run in response to the adjusted data sequences D'2_1-D'2_M (M=7).

[0043] like Figure 8As shown, by turning on the DAC cell "cell-4" of the DAC 106_1 ("P-DAC") and turning off the DAC cells "cell-1", "cell-3" and "cell-6" of the DAC 106_1 ("P-DAC"), and turning off the DAC cells "cell-2", "cell-5" and "cell-7" of the DAC 106_2 ("N-DAC"), a voltage level representing the thermometer code C0 is output; by turning on the DAC cells "cell-1", "cell-3" and "cell-6" of the DAC 106_2 ("N-DAC") and turning off the DAC cells "cell-2", "cell-5" and "cell-7" of the DAC 106_1 ("P-DAC"), a voltage level representing the thermometer code C1 is output; by turning on the DAC cells "cell-1", "cell-3" and "cell-5" of the DAC 106_1 ("P-DAC") and the DAC cell "cell-7" of the DAC 106_2 ("N-DAC"), a voltage level representing the thermometer code C1 is output. DAC cells "cell-2" and "cell-4" of DAC 106_2 ("N-DAC"), as well as DAC cell "cell-6" of DAC 106_1 ("P-DAC") and DAC cell "cell-7" of DAC 106_2 ("N-DAC"), output a voltage level representing thermometer code C2; ​​etc. According to the TDEM scheme proposed by the present invention, the first bit and the second bit processed successively by the DAC cell of the first DAC and the DAC cell of the second DAC are exchanged in the time domain, so that the second bit and the first bit are processed successively by the DAC cell of the first DAC and the DAC cell of the second DAC.

[0044] about Figure 5 and Figure 8 In the example shown, the TDEM circuit 104 exchanges a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence (fed into a DAC unit of a first DAC located in a first channel of the time-interleaved DAC) and a second adjusted data sequence (fed into a DAC unit of a second DAC located in a second channel of the time-interleaved DAC), such that the first adjusted data sequence includes a first bit of the first data sequence and a first bit of the second data sequence, and the second adjusted data sequence includes a second bit of the first data sequence and a second bit of the second data sequence. In some embodiments of the present invention, the first bit of the second data sequence and the second bit of the first data sequence may be randomly selected to avoid data-dependent noise caused by TDEM.

[0045] In addition, through Figure 5 and 8With appropriate bit swapping as shown, the adjusted data sequence processed by one DAC unit includes bits from a different data sequence of the digital processing circuit 102 / 602. Therefore, the voltage level representing a thermometer code can be determined by using DAC units belonging to different DACs. In this way, distortion caused by gain mismatch, offset mismatch and / or timing mismatch between DAC elements used by different DAC channels can be mitigated by the proposed TDEM scheme.

[0046] The inherent characteristics of the DAC unit may include a setup time, which is the time required to generate a stable analog output in response to a digital input. If two consecutive bits of the DAC unit have different values, the DAC unit may require two setup time periods to generate different stable voltages representing the two consecutive bits. If two consecutive bits of the DAC unit have the same value, the DAC unit may only need one setup time period to continuously generate the same stable voltage representing the two consecutive bits. In order to ensure high-speed DAC operation, the TDEM scheme can further check the bits included in the data sequence to select a suitable bit exchange timing. Specifically, the timing of the bit exchange of different data sequences can be controlled based on the comparison results of the bits included in the data sequence.

[0047] Fig. 9 is a diagram showing an embodiment of the present invention Figure 1 and Figure 6 1 is a block diagram of an exemplary design of a TDEM circuit 104 shown in FIG. In the present embodiment, the TDEM circuit 104 includes a detection circuit 902 and an exchange circuit 904. The detection circuit 902 is arranged to check a first data sequence of a digital input and a second data sequence of another digital input to generate a notification signal. The exchange circuit 904 is arranged to exchange a portion of the first data sequence with a portion of the second data sequence according to the notification signal. For example, the detection circuit 902 detects whether two bits to be processed continuously have the same binary value, wherein the two bits to be processed continuously include a bit belonging to the first data sequence (e.g., a bit of the first thermometer code) and a bit belonging to the second data sequence (e.g., a bit of the second thermometer code immediately following the first thermometer code), and generates a notification signal for notifying the exchange circuit 904 that two bits with the same binary value are detected. In response to the notification signal, the exchange circuit 904 randomly determines whether to exchange a portion of the first data sequence with a portion of the second data sequence. Since the exchange circuit 904 performs random sequence exchange, data-related noise caused by TDEM can be avoided.

[0048] Assume that the time interleaved DAC 100 / 600 is as follows Figure 22-channel time-interleaved DAC shown. The detection circuit 902 may check the data sequence D1_1 of the digital input D1 and the data sequence D2_1 of the digital input D2 to generate a notification signal CS_1, check the data sequence D1_2 of the digital input D1 and the data sequence D2_2 of the digital input DK to generate a notification signal CS_2, and so on. The exchange circuit 904 may apply bit exchange to the data sequences D1_1 and D2_1 to generate adjusted data sequences D'1_1 and D'2_1 after being notified by the notification signal CS_1, may apply bit exchange to the data sequences D1_2 and D2_2 to generate adjusted data sequences D'1_2 and D'2_2 after being notified by the notification signal CS_2, and so on.

[0049] In some embodiments of the present invention, DACs 106_1-106_K may be triggered by clock inputs, respectively. For example, the time-interleaved DAC 100 / 600 may further include Fig. 9 . The clock generation circuit 906 is arranged to generate a plurality of clock inputs RZ_1-RZ_K according to an external clock CLK provided by a clock source (not shown). The switching circuit 904 can be further arranged to adjust the clock inputs RZ_1-RZ_K to generate a plurality of adjusted clock inputs RZ'_1-RZ'_K provided to the DACs 106_1-106_K, respectively. Each of the clock inputs RZ_1-RZ_K includes a plurality of reference clocks for a plurality of DAC units, respectively. Each adjusted clock input RZ'_1-RZ'_K includes a plurality of clocks for controlling the DAC units of the corresponding DAC.

[0050] The exchange circuit 904 can generate a first clock of an adjusted clock input and a second clock of another adjusted clock input by exchanging a portion of a first reference clock of one clock input with a portion of a second reference clock of another clock according to a notification signal. As described above, the exchange circuit 904 randomly determines whether to exchange a portion of the first data sequence with a portion of the second data sequence after being notified by the notification signal. Similarly, in response to the notification signal, the exchange circuit 904 randomly determines whether to exchange a portion of the first reference clock with a portion of the second reference clock. For example, when the exchange circuit 904 decides to exchange a portion of the first data sequence with a portion of the second data sequence, the exchange circuit 904 further exchanges a portion of the first reference clock with a portion of the second reference clock. The time-interleaved DAC with TDEM can operate normally.

[0051] Assume that the time-interleaved DAC 100 is Figure 22-channel 3-bit time-interleaved DAC shown. Clock input RZ_1 includes reference clocks RZ_11-RZ_1M (M=7) originally generated for the M DAC units of DAC 106_1. Clock input RZ_2 includes reference clocks RZ_21-RZ_2M (M=7) originally generated for the M DAC units of DAC 106_2. When the TDEM scheme is enabled to adjust the data inputs D1 and D2 to generate adjusted data inputs D'1 and D'2 for DACs 106_1 and 106_2, respectively, the switching circuit 904 further adjusts the clock inputs RZ_1 and RZ_2 to generate adjusted clock inputs RZ'_1 and RZ'_2 for DACs 106_1 and 106_2, respectively, wherein the M DAC units of DAC 106_1 are clocked by clocks RZ'_11-RZ'_1M included in the adjusted pulse input RZ'_1, and the M DAC units of DAC 106_2 are clocked by clocks RZ'_21-RZ'_2M included in the adjusted clock input RZ'_2. Specifically, the switching circuit 904 may apply clock switching to the reference clocks RZ_11 and RZ_21 to generate input clocks RZ′_11 and RZ′_21 , apply clock switching to the reference clocks RZ_12 and RZ_22 to generate clocks RZ′_12 and RZ′_22 , and so on.

[0052] Fig.10 1 is a diagram showing a random sequence exchange operation according to an embodiment of the present invention. Assume that the time interleaved DAC 100 / 600 is as follows Figure 2 2-channel 3-bit time-interleaved DAC shown. Digital processing circuit 102 / 602 provides data sequences D1_1 and DK_1 (hereinafter, K=2 is used as an example), wherein data sequence D1_1 is part of the digital input D1 originally generated for DAC 106_1, and data sequence DK_1 is part of the digital input DK (K=2) originally generated for DAC 106_2. Clock generation circuit 906 provides reference clocks RZ_11 and RZ_K1 (K=2). TDM circuit 104 generates adjusted data sequences D'1_1 and D'K_1 (K=2) based on data sequences D1_1 and DK_1, and generates clocks RZ'_11 and RZ'_K1 (K=2) and RZ_K1 based on reference clock RZ_11. Specifically, a DAC cell (e.g., "cell-1") of DAC 106_1 is clocked by clock RZ'_11 and operates in response to the adjusted data sequence D'1_1. One DAC cell (eg, “cell- 1 ”) of the DAC 106_2 is clocked by the clock RZ′_K1 (K=2) and operates in response to the adjusted data sequence D′K_1 (K=2).

[0053] Regarding the generation of the adjustment data sequences D'1_1 and D'K_1 (K=2) and the clocks RZ'_11 and RZ'_K1 (K=2), the detection circuit 902 monitors or monitors the data sequences D1_1 and DK_1 (K=2) for sequentially and alternately checking the bits to be processed by the DAC cell (e.g., "cell-1") of the DAC 106_1 and the DAC cell (e.g., "cell-1") of the DAC 106_2. Fig.10 As shown at the top of , the data sequence D1_1 is initially sampled by the rising edge of the reference clock RZ_11, and the data sequence DK_1 (K=2) is initially sampled by the rising edge of the reference clock RZ_K1 (K=2). Therefore, the bits to be processed continuously are "10100101100". The detection circuit 902 finds that the two bits to be processed continuously have the same value "0", and generates a notification signal to notify the exchange circuit 904. After the detection circuit 902 notifies, the exchange circuit 904 randomly determines whether to enable bit exchange to change the bit pattern of the data sequence fed into the DAC cell (e.g., "cell-1") of DAC 106_1 and the DAC cell (e.g., "cell-1") of DAC 106_2, and randomly determines whether to enable clock exchange for changing the clock pulse sequence provided to the DAC cell (e.g., "cell-1") of DAC106_1 and the DAC cell (e.g., "cell-1") of DAC 106_2. In this embodiment, for example, the exchange circuit 904 decides to perform bit exchange and clock exchange in response to a notification signal generated due to detection of two bits having the same value "0". Fig.10 As shown at the bottom of , the swapping circuit 904 generates adjusted data sequences D'1_1 and D'K_1 (K=2) by swapping a portion 1002 of the data sequence D1_1 with a portion 1004 of the data sequence DK_1 (K=2), and generates clocks RZ'_11 and RZ'_K1 (K=2) by swapping a portion 1006 of the reference clock RZ_11 with a portion of the reference clock RZ_K1 (K=2). The adjusted data sequence D'1_1 is sampled by the rising edge of the clock RZ'_11, so that the bit to be processed by one DAC unit (e.g., "cell-1") of the DAC 106_1 is "11110". The adjusted data sequence D'K_1 (K=2) is sampled by the rising edge of the clock RZ'_K1 (K=2), so that the bit to be processed by one DAC unit (e.g., "cell-1") of the DAC 106_K is "000010". It should be noted that the same bit sequence “10100101100” is converted by using the DAC cell (eg, “cell- 1 ”) of the DAC 106_1 and the DAC cell (eg, “cell- 1 ”) of the DAC 106_K.

[0054] The present invention has no restrictions on the design of the DAC unit. Therefore, depending on the actual DAC unit design, the clock exchange can be omitted. That is, the clock exchange function of the exchange circuit 904 can be optional. In addition, in this embodiment, when the bits or DAC units that are not exchanged are not in the same position (same order or same rank), the above-mentioned clock exchange can also be exchanged accordingly according to the bits or DAC units that are exchanged, which will not be repeated here.

[0055] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. A time-interleaved digital-to-analog converter for converting a digital signal into an analog signal, characterized in that: include: A digital processing circuit, configured to generate a plurality of data sequences according to the digital signal of the time-interleaved digital-to-analog converter, wherein the plurality of data sequences include a first data sequence and a second data sequence; A time-domain dynamic element matching circuit, used for exchanging a part of the first data sequence with a part of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence, wherein the first adjusted data sequence includes a first bit of the first data sequence and a first bit of the second data sequence, and the second adjusted data sequence includes a second bit of the first data sequence and a second bit of the second data sequence; wherein the first data sequence is in a time period, and the second data sequence is in a next time period adjacent to the first data sequence; a plurality of digital-to-analog converters, each digital-to-analog converter having at least one digital-to-analog converter unit, wherein the plurality of digital-to-analog converters include a first digital-to-analog converter unit operating in response to a first adjusted data sequence and a second digital-to-analog converter unit operating in response to a second adjusted data sequence; and The combining circuit is used to generate an analog signal by combining the analog outputs of the plurality of digital-to-analog converters.

2. The time-interleaved digital-to-analog converter according to claim 1, wherein: The first bit of the second data sequence and the second bit of the first data sequence are randomly selected.

3. The time-interleaved digital-to-analog converter of claim 1, wherein: The first digital-to-analog converter comprises a plurality of third digital-to-analog converter units, the plurality of data sequences comprise a plurality of third data sequences, the plurality of third digital-to-analog converter units are arranged to respectively operate in response to data sequences derived from the plurality of third data sequences, and the digital processing circuit comprises: The dynamic element matching circuit is arranged to set the plurality of third data sequences according to a dynamic element matching algorithm executed based on the plurality of third digital-to-analog converter units.

4. The time-interleaved digital-to-analog converter according to claim 3, wherein: The second digital-to-analog converter includes a plurality of fourth digital-to-analog converter units, the plurality of data sequences also include a plurality of fourth data sequences, the plurality of fourth digital-to-analog converter units are arranged to operate respectively in response to data sequences derived from the plurality of fourth data sequences, and the dynamic element matching circuit is further arranged to set the plurality of fourth data sequences according to a dynamic element matching algorithm executed based on the plurality of fourth data sequences.

5. The time-interleaved digital-to-analog converter of claim 1, wherein: The time domain dynamic element matching circuit comprises: a detection circuit for checking the first data sequence and the second data sequence to generate a notification signal; and The exchange circuit is used to exchange a part of the first data sequence with a part of the second data sequence according to the notification signal.

6. The time-interleaved digital-to-analog converter of claim 5, wherein: The detection circuit is arranged to detect whether two bits to be processed successively have the same binary value, wherein the two bits include a bit belonging to the first data sequence and another bit belonging to the first data sequence, and the detection circuit is also arranged to generate the notification signal for notifying the switching circuit that the two bits with the same binary value are detected.

7. The time-interleaved digital-to-analog converter of claim 6, wherein: In response to the notification signal, the exchange circuit randomly determines whether to exchange a portion of the first data sequence with a portion of the second data sequence.

8. The time-interleaved digital-to-analog converter of claim 5, wherein: Also includes: A clock generating circuit, configured to generate a plurality of reference clocks, wherein the plurality of reference clocks include a first reference clock and a second reference clock; In which, the first digital-to-analog converter unit is clocked by the first reference clock, the second digital-to-analog converter unit is clocked by the second reference clock, and the switching circuit is also arranged to generate the first reference clock and the second reference clock by exchanging a part of the first reference clock with a part of the second reference clock according to the notification signal.

9. The time-interleaved digital-to-analog converter of claim 8, wherein: The detection circuit is arranged to detect whether two bits to be processed successively have the same binary value, wherein the two bits include a bit belonging to the first data sequence and another bit belonging to the second data sequence, and the detection circuit is also arranged to generate the notification signal for notifying the switching circuit that the two bits with the same binary value have been detected.

10. The time-interleaved digital-to-analog converter of claim 9, wherein: In response to the notification signal, the exchange circuit randomly determines whether to exchange a portion of the first data sequence with a portion of the second data sequence, and to exchange a portion of the first reference clock with a portion of the second reference clock.

11. A time-interleaved digital-to-analog conversion method for converting a digital signal into an analog signal, characterized in that: include: generating a plurality of data sequences according to the digital signal, wherein the plurality of data sequences include a first data sequence and a second data sequence; Performing a time-domain dynamic element matching operation by exchanging a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence, wherein the first adjusted data sequence includes: a first bit of the first data sequence and a first bit of the second data sequence, and the second adjusted data sequence includes a second bit of the first data sequence and a second bit of the second data sequence; wherein the first data sequence is in a time period and the second data sequence is in a next time period adjacent to the first data sequence; and An analog signal is generated by combining analog outputs of a plurality of digital-to-analog converters, each having at least one digital-to-analog converter unit, wherein the plurality of digital-to-analog converters include a first digital-to-analog converter unit and a second digital-to-analog converter, the first digital-to-analog converter including a first digital-to-analog converter unit operating in response to the first adjusted data sequence, and the second digital-to-analog converter including a second digital-to-analog converter unit operating in response to the second adjusted data sequence.

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