Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a first region and a second region; forming a plurality of fins on the substrate; forming an isolation structure between adjacent fins; forming a mask layer on the substrate and the fins; removing the mask layer in the first region to form an opening; removing the isolation structure in the first region along the opening; removing the mask layer; forming a gate structure across the fins, the gate structure covering the first region. The semiconductor structure formed by the method of the present invention can reduce the on-resistance of the semiconductor device, increase the breakdown voltage, and thus improve the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the development of semiconductor technology, power integrated circuits (PIC) are continuously used in many fields. Laterally double-diffused metal oxide semiconductor transistors (LDMOS) have the characteristics of high operating voltage, simple process, and easy process compatibility with complementary metal oxide semiconductors (CMOS). As a power device, they are widely used in power integrated circuits.

[0003] The source-drain breakdown voltage (BVdss) and on-resistance (Ron) characteristics of power devices are crucial for efficient power circuit design. Generally speaking, LDMOS devices require higher source-drain breakdown voltage and lower on-resistance in use to improve device performance. However, the on-resistance and breakdown voltage of LDMOS devices are contradictory indicators. If the on-resistance decreases, the breakdown voltage may decrease, and vice versa.

[0004] Therefore, how to obtain the lowest possible on-resistance to reduce conduction loss through reasonable design while meeting a certain breakdown voltage is an urgent problem to be solved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so that the semiconductor device has a higher breakdown voltage and a lower on-resistance.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a plurality of fins on the substrate; forming an isolation structure between adjacent fins; forming a mask layer on the substrate and the fins; removing the mask layer in the first region to form an opening; removing the isolation structure in the first region along the opening; removing the mask layer; and forming a gate structure across the fins, the gate structure covering the first region.

[0007] Optionally, the mask layer is a silicon nitride layer or a photoresist layer.

[0008] Optionally, the mask layer is formed by chemical vapor deposition.

[0009] Optionally, the step of forming the opening includes: forming a photoresist layer on the mask layer; performing photolithography on the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, etching and removing the mask layer in the first area; removing the patterned photoresist layer to form an opening.

[0010] Optionally, the method of etching the mask layer is dry etching.

[0011] Optionally, the process of removing the isolation structure in the first region is dry etching.

[0012] Optionally, the etching gas for dry etching includes one or more of CF4, C4F8 or CHF3.

[0013] Optionally, in the process of forming the isolation structure, it also includes: injecting first conductive ions into the fin and the substrate under the fin to form a drift region; injecting second conductive ions into the fin on one side of the drift region and the substrate under the fin to form a first doped region.

[0014] Optionally, after forming the gate structure, it also includes: injecting second conductive ions into the fin on one side of the gate structure to form a second doped region, and the second doped region is located on the drift region; forming a source region and a drain region in the fin on both sides of the gate structure, and the second doped region is located between the gate structure and the drain region.

[0015] Optionally, the first conductive ions and the second conductive ions are of opposite types.

[0016] Optionally, the first conductive ions are N-type ions, and the second conductive ions are P-type ions.

[0017] A semiconductor structure formed by the above method includes: a substrate, the substrate including a first region and a second region; a fin located on the substrate; an isolation structure located between adjacent fins in the second region; and a gate structure spanning the fins and covering the first region.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The isolation structure in the first area is removed, and when a gate structure is subsequently formed, the first area where the isolation structure is removed is filled with a gate material to increase the contact area between the gate and the fin, that is, the effective width of the channel is increased. The increase in the channel width makes the current path wider, which can improve the ability of current to pass through, reduce the on-resistance of the semiconductor device, and avoid the current crowding effect, thereby improving the reliability of the device.

[0020] Furthermore, a second conductive ion is implanted into the fin above the drift region to form a second doped region, and the second conductive ion is of opposite type to the doped ion type in the drift region. Generally speaking, the wider the depletion region, the higher the breakdown voltage required. In addition to the depletion region formed by the first doped region and the drift region, an additional ion implantation is performed to form the second doped region, and the second doped region also forms a depletion region with the drift region, so that the depletion region formed by the drift region becomes wider, which can improve the breakdown voltage of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of the structure of an existing fin semiconductor structure;

[0022] Figures 2 to 9 1 is a schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention, wherein: Figure 4 yes Figure 3 The three-dimensional structure shown does not represent a side view of the isolation structure;

[0023] Fig.10 is a schematic structural diagram of a second embodiment of a method for forming a semiconductor structure of the present invention, Figure 8 Schematic diagram of the cross-section structure along the AA direction;

[0024] Fig.11 is a schematic diagram of a three-dimensional structure of a semiconductor structure according to an embodiment of the present invention;

[0025] Fig.12 yes Fig.11 Schematic diagram of the cross-sectional structure along direction BB. DETAILED DESCRIPTION

[0026] As can be seen from the background technology, LDMOS devices require higher source-drain breakdown voltage and lower on-resistance in use to improve device performance. However, the on-resistance and breakdown voltage of LDMOS devices are contradictory indicators. If the on-resistance decreases, the breakdown voltage may decrease, and vice versa.

[0027] like Figure 1 As shown, in the existing fin-type LDMOS, after forming the fins 2 on the substrate 1, an isolation structure 3 is formed between adjacent fins 2 to isolate active devices. After forming the isolation structure 3, a gate structure 4 is formed across the fins 2, and the gate structure covers the isolation structure 3.

[0028] In the semiconductor device of the above structure, a portion of the fin 2 is covered by the isolation material, the contact area between the subsequently formed gate structure 4 and the fin 2 is small, and the effective width of the channel is small. In the subsequent working process, the channel width through which electrons can pass when flowing from the source to the drain is narrow, so that the on-resistance is large, the current passing capacity is weak, and the current crowding effect is prone to occur, affecting the reliability of the semiconductor device.

[0029] In order to enable semiconductor devices to have both a higher breakdown voltage and a smaller on-resistance, the inventors have provided a method for forming a semiconductor structure after research. After forming an isolation structure between adjacent fins, the isolation structure in the first area is removed, and a subsequently formed gate structure covers the first area. The gate material fills the first area, thereby increasing the contact area between the gate structure and the fins, that is, the effective width of the channel is increased, which can improve the current passing capacity and reduce the on-resistance.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] First embodiment

[0032] Figures 2 to 9 1 is a schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention, wherein: Figure 4 yes Figure 3 The three-dimensional structure shown does not represent a side view of the isolation structure.

[0033] refer to Figure 2 , providing a substrate 10, wherein the substrate 10 includes a first region and a second region.

[0034] In this embodiment, the substrate 10 is a silicon substrate; in other embodiments, the substrate 10 can also be at least one of the following materials: germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), stacked silicon on insulator (SSOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0035] Continue to refer Figure 2 , a plurality of fins 20 are formed on the substrate 10 .

[0036] In this embodiment, the method for forming the fin 20 is to form a patterned mask layer (not shown) on the substrate 10, wherein the patterned mask layer corresponds to the position where the fin 20 needs to be formed, and the substrate 10 is partially etched with the patterned mask layer as a mask to form a plurality of discretely arranged fins 20 on the substrate 10.

[0037] refer to Figure 3 , an isolation structure 30 is formed between adjacent fins 20 .

[0038] In this embodiment, the isolation structure 30 is a shallow trench isolation structure; in other embodiments, the isolation structure 30 may also be other isolation structures well known to those skilled in the art.

[0039] In this embodiment, the method for forming the isolation structure 30 includes: depositing an isolation layer (not shown) between adjacent fins 20, wherein the top of the isolation layer is higher than the top of the fin 20; chemically and mechanically polishing the isolation layer until the top of the isolation layer is flush with the top of the fin 20; and etching the isolation layer to form the isolation structure 30, wherein the top of the isolation structure 30 is lower than the top of the fin 20.

[0040] In this embodiment, the isolation layer material is silicon dioxide.

[0041] It should be noted that, after the isolation layer is chemically mechanically polished until the top of the isolation layer is flush with the top of the fin 20 , ion implantation is performed on the fin 20 and the substrate 10 under the fin 20 .

[0042] refer to Figure 4 , first conductive ions are implanted into the fin 20 and the substrate 10 thereunder to form a drift region 11 .

[0043] After the drift region 11 is formed, second conductive ions are implanted into the fin 20 on one side of the drift region 11 and the substrate 10 thereunder to form a first doped region 12 .

[0044] The first conductive ions and the second conductive ions are of opposite types.

[0045] In this embodiment, the first conductive ions are N-type ions, which may be one or more of phosphorus ions, arsenic ions, and antimony ions; the second conductive ions are P-type ions, which may be one or more of boron ions, indium ions, and gallium ions.

[0046] In other embodiments, the first conductive ions may be P-type ions, and the second conductive ions may be N-type ions.

[0047] In this embodiment, the first conductive ions are phosphorus ions, and the ion implantation dose is 3E12atoms / cm 2 To 7E12atoms / cm 2 The ion implantation energy is 50-150keV; the second conductive ion is boron ion, and the ion implantation dose is 2E12atoms / cm 2To 4E12atoms / cm 2 , the ion implantation energy is 5-50keV.

[0048] refer to Figure 5 After forming the isolation structure 30 , a mask layer 40 is formed on the substrate 10 and the fin 20 , and the mask layer covers the isolation structure 30 and the fin 20 .

[0049] In this embodiment, the material of the mask layer 40 is silicon nitride; in other embodiments, the mask layer 40 may also be a photoresist layer, and the photoresist layer is mainly composed of a mixture of resin, photosensitizer, and solvent.

[0050] In this embodiment, the mask layer 40 is formed by chemical vapor deposition.

[0051] refer to Figure 6 After forming the mask layer 40, the mask layer 40 in the first area is removed to form an opening.

[0052] In this embodiment, the step of forming an opening includes: forming a photoresist layer (not shown) on the mask layer; performing photolithography on the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, etching and removing the mask layer 40 in the first area; removing the patterned photoresist layer to form an opening.

[0053] In this embodiment, the method of etching the mask layer 40 is dry etching.

[0054] refer to Figure 7 , removing the isolation structure 30 in the first region along the opening.

[0055] In this embodiment, the method for removing the isolation structure 30 is dry etching.

[0056] In this embodiment, the etching gas for dry etching includes one or more of CF4, C4F8 or CHF3.

[0057] The isolation structure 30 in the first region is removed, and when the gate structure is subsequently formed, the gate material is deposited at a deeper depth, so that the contact area between the gate structure and the fin 20 becomes larger, thereby increasing the effective channel width of the semiconductor device. The increase in the effective channel width can reduce the on-resistance of the device, improve the current passing capacity, and in the process of electrons flowing from the source to the drain, the current crowding effect will not occur due to the increase in the channel area that can pass through, thereby improving the reliability of the semiconductor device.

[0058] refer to Figure 8After removing the mask layer 40 , a gate structure 50 is formed across the fin 20 , and the gate structure 50 covers the first region.

[0059] In this embodiment, the steps of forming the gate structure 50 include: forming a gate oxide layer (not shown) on the surface of the fin 20 ; depositing a gate material layer on the surface of the gate oxide layer; and chemically mechanically polishing the gate material layer to form the gate structure 50 .

[0060] In this embodiment, the gate structure 50 is a metal gate structure.

[0061] The isolation structure 30 is removed from the first region, and the gate material layer fills the groove in the first region after the isolation structure 30 is removed. The depth of the gate structure 50 covering the side of the fin 20 is deepened, thereby increasing the contact area between the gate structure 50 and the fin 20, increasing the effective width of the channel, and reducing the on-resistance.

[0062] refer to Fig. 9 After the gate structure 50 is formed, a source region 21 and a drain region 22 are formed in the fin 20 on both sides of the gate structure 50 .

[0063] In this embodiment, the source region 21 is located in the first doping region 12 , and the drain region 22 is located in the drift region 11 .

[0064] Second embodiment

[0065] Fig.10 yes Figure 8 Schematic diagram of the cross-sectional structure along the AA direction.

[0066] In this embodiment, the process of providing the substrate 10, forming the fin 20, forming the isolation structure 30, removing the isolation structure 30 in the first region, and forming the gate structure 50 is the same as that of the first embodiment and will not be repeated here.

[0067] In this embodiment, the process of implanting ions into the fin 20 and the substrate 10 thereunder to form the drift region 11 and the first doping region 12 is the same as that in the first embodiment, and will not be described in detail herein.

[0068] refer to Fig.10 After forming the gate structure 50 , second conductive ions are implanted into the fin 20 on one side of the gate structure 50 to form a second doping region 13 , and the second doping region 13 is located on the drift region 11 .

[0069] In this embodiment, the second doping region 13 has the same doping type as the first doping region 12 , and has an opposite doping type to the drift region 11 .

[0070] In this embodiment, the ions implanted into the second doping region 13 are boron ions, which are low-concentration doping, and the ion implantation dose is 1E12atoms / cm 2 Up to 5E12atoms / cm 2 .

[0071] The first doped region 12 is located on one side of the drift region 11, and the portion in contact with the drift region 11 forms a first depletion region. Generally, the wider the depletion region is, the higher the breakdown voltage it can withstand. Improving the breakdown voltage of a semiconductor device can be achieved by expanding the depletion region. Therefore, an inversion ion implantation is added to the drift region 11 to form the second doped region 13. The second doped region 13 contacts the drift region 11 to form a second depletion region, which expands the width of the depletion region formed by the drift region 11, thereby improving the breakdown voltage of the semiconductor device.

[0072] refer to Fig.11 , shows a schematic diagram of a three-dimensional structure of an embodiment of a semiconductor structure of the present invention. Accordingly, the present invention also provides a semiconductor structure. The semiconductor includes:

[0073] A substrate 100 including a first region and a second region; a fin 200 located on the substrate 100; an isolation structure 300 located between adjacent fins 200 in the second region; and a gate structure 400 spanning across the fin 200 and covering the first region.

[0074] In this embodiment, the semiconductor structure further has a source region 201 and a drain region 202 , and the source region 201 and the drain region 202 are located in the fin 200 on both sides of the gate structure 400 .

[0075] refer to Fig.12 ,for Fig.11 Schematic diagram of the cross-sectional structure along direction BB.

[0076] In this embodiment, the semiconductor structure also includes: a drift region 101, located in the fin 200 and the substrate 100 thereunder; a first doped region 102, located in the fin 200 and the substrate 100 thereunder on one side of the drift region 101; and a second doped region 103, located on one side of the gate structure 400 and on the drift region 101.

[0077] The drift region 101 is doped with opposite ions to the first doping region 102 and the second doping region 103. In this embodiment, the drift region 101 is doped with N-type ions, and the first doping region 102 and the second doping region 103 are doped with P-type ions.

[0078] The semiconductor structure formed by the method of the embodiment of the present invention, on the one hand, widens the depletion region of the drift region 101, thereby improving the breakdown voltage of the semiconductor device; on the other hand, the isolation structure 300 of the first region is removed, so that the contact area between the subsequently formed gate structure 400 and the fin 200 is increased, the effective width of the channel is increased, and the area for current to pass is larger, thereby reducing the on-resistance, so that the semiconductor device has both a higher breakdown voltage and a lower on-resistance.

[0079] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a plurality of fins on the substrate; forming an isolation structure between adjacent fins, wherein a top of the isolation structure is lower than a top of the fin; forming a mask layer on the substrate and the fin; removing the mask layer in the first area to form an opening; removing the isolation structure of the first region along the opening to form a trench, wherein the trench exposes the substrate of the first region and a portion of the sidewall of the fin portion blocked by the isolation structure; removing the mask layer; A gate structure is formed across the fin, and the gate structure fills the trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: The mask layer is a silicon nitride layer or a photoresist layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The mask layer is formed by chemical vapor deposition.

4. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the opening include: forming a photoresist layer on the mask layer; Performing photolithography on the photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching and removing the mask layer in the first area; The patterned photoresist layer is removed to form an opening.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method of etching the mask layer is dry etching.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the isolation structure in the first region is dry etching.

7. The method for forming a semiconductor structure according to claim 6, wherein: The etching gas for the dry etching includes one or more of CF4, C4F8 or CHF3.

8. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the isolation structure also includes: First conductive ions are implanted into the fin and the substrate under the fin to form a drift region; second conductive ions are implanted into the fin on one side of the drift region and the substrate under the fin to form a first doped region.

9. The method for forming a semiconductor structure according to claim 8, wherein: After forming the gate structure, the method further includes: Injecting second conductive ions into the fin portion on one side of the gate structure to form a second doped region, wherein the second doped region is located on the drift region; A source region and a drain region are formed in the fins at both sides of the gate structure, and the second doped region is located between the gate structure and the drain region.

10. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The first conductive ions and the second conductive ions are of opposite types.

11. The method for forming a semiconductor structure according to claim 10, wherein: The first conductive ions are N-type ions, and the second conductive ions are P-type ions.

12. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; A fin portion, located on the substrate; an isolation structure, located between adjacent fins in the second region; A gate structure spans across the fin, and the gate structure fills the trench in the first region after the isolation structure is removed, and the trench exposes a portion of the sidewall of the fin blocked by the isolation structure.

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