Core ramp detection circuit

Abstract

Various embodiments described herein relate to a device having an output pad that provides an input / output (IO) voltage from an IO power supply. The device may include a core ramp detection circuit that detects a first ramp of the core voltage from the core power supply and provides a core ramp sense signal. The device may include an output logic circuit that couples the output pad to ground after receiving the core ramp sense signal to reduce leakage of the IO power supply.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a core ramp detection circuit. Background Art

[0002] This section is intended to provide information relevant to understanding the various techniques described herein. As the title of this section implies, this is a discussion of related art and in no way implies that it is prior art. Generally, related art may or may not be considered prior art. Therefore, it should be understood that any statements in this section are to be read in this manner and do not constitute any admission that they are prior art.

[0003] Some conventional circuit designs attempt to operate at low power. To achieve this, input / output (IO) circuits may be adapted to support multiple power domains. However, the use of multiple power domains often requires power sequencing for these domains. Power sequencing refers to a strategy that determines the order or sequence in which multiple power supplies are ramped up or down. Furthermore, incorrect power sequencing can cause unnecessary leakage in the IO circuits and / or lead to uncertain states at the outputs. Therefore, there is a need to reduce leakage to improve circuit performance and efficiency. Summary of the Invention

[0004] In a first aspect of the present disclosure, a device is provided, which may include: an output pad providing an IO voltage from an input / output IO power supply; a core ramp detection circuit detecting a first ramp of the core voltage from the core power supply and providing a core ramp sensing signal; and an output logic circuit coupling the output pad to ground after receiving the core ramp sensing signal to reduce leakage of the IO power supply.

[0005] According to a second aspect of the present disclosure, a system is provided, comprising: a first chip having a sensing circuit and a first input / output (IO) unit with a first output pad, the first output pad providing at least one of an input / output voltage from an IO power supply and a core voltage from a core power supply; and a second chip having a second IO unit with a second output pad, the second output pad receiving at least one of the IO voltage and the core voltage from the first output pad, wherein the sensing circuit detects a first slope of the core voltage and couples the first output pad to ground until the core power supply starts to ramp up for the first time, so as to reduce leakage of at least one of the IO voltage and the core voltage to the second output pad.

[0006] A third aspect of the present disclosure provides a method, comprising: providing an input-output (IO) voltage via an output pad; detecting a first slope of a core voltage; generating a slope sensing signal during detection of the first slope of the core voltage; and coupling the output pad to ground after receiving the slope sensing signal so as to reduce leakage of at least one of the IO voltage and the core voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] This document describes various embodiments of the technology with reference to the accompanying drawings. However, it should be understood that the accompanying drawings only illustrate various embodiments described herein and are not intended to limit the embodiments of the technology described herein.

[0008] Figure 1A Diagram showing multiple chips, core circuitry, and input-output (IO) circuitry according to various embodiments described herein.

[0009] Figure 1B Waveform diagrams illustrating power sequencing according to various embodiments described herein.

[0010] Figures 2A to 2D A diagram illustrating circuitry related to core ramp detection according to various embodiments described herein.

[0011] Figure 3 A diagram illustrating a nuclear detection circuit according to various embodiments described herein is shown.

[0012] Figures 4A to 4B A diagram illustrating a core ramp detection circuit according to various embodiments described herein is shown.

[0013] Figures 5A to 5B A diagram illustrating a retention logic circuit according to various embodiments described herein is shown. DETAILED DESCRIPTION

[0014] Various embodiments described herein relate to core ramp detection circuits, including schemes and techniques for improving leakage efficiency with respect to input / output (IO) circuits for various low-power applications. The schemes and techniques described herein can provide an innovative approach to effectively reduce or minimize leakage current caused by independent power sequencing (i.e., the order in which multiple power supplies are ramped up or down) of different power domains in low-power, application-specific system-on-chips (SoCs). For example, the schemes and techniques described herein can be provided to an integrated circuit (IC) to avoid erroneous or indeterminate logic states during power-up or power-down of multiple power domains, and also to avoid unnecessary leakage current from the power supplies by defining a stable state at the outputs during power sequencing operations.

[0015] Various embodiments described herein support power sequencing by using a PVSense cell as part of a power management solution. Based on various parameters of the core circuitry, the PVSense cell detects the availability of both the core and I / O power supplies and tri-states either supply, or maintains the output of the PBID-TX at a predefined value. For example, when a first I / O cell operating in a first voltage domain drives a second I / O cell operating in a second voltage domain, the output of the first I / O cell maintains a predefined value (0 or 1) during power-off in the first voltage domain. This technique ensures that the second I / O cell has a stable power supply that is not compromised by the uncertain state of its input, and that the output of the second I / O cell maintains a deterministic state, rather than an uncertain one. This retention process may work well when there is some previous data to be retained at the first input-output (IO) cell. However, if no valid previous data is available (for example, during the first ramp-up of the core voltage), the retention may not be effective. When the core circuitry is first ramping up, the output of the first I / O cell may be uncertain, and in this case, the retention operation may result in an uncertain state at the output of the first I / O cell. Therefore, the various schemes and techniques described herein attempt to address the issues associated with the first ramp by detecting the first core ramp operation. When the first ramp of the core is detected, the various schemes and techniques described herein enable the weak pull-down logic circuit provided in the first IO cell (until the core power supply begins to ramp up for the first time). Thus, by enabling the weak pull-down logic, the state at the output can be grounded, and thus logic zero, rather than holding the output pad in an indeterminate state of floating (X), and thus power leakage through the second IO cell can be avoided.

[0016] This article will refer to Figures 1A to 5B Various implementations of core ramp detection circuits are described in detail.

[0017] Figure 1A A diagram illustrating multiple chips and core circuit 100A according to various embodiments described herein is shown. In some cases, core circuit 100A can be implemented as a system or device having various circuit components arranged and coupled together as a collection or combination of components of a system providing a package or board-type structure. Furthermore, in some cases, methods of detecting core ramping can involve using the various circuit components described herein to implement improved performance schemes and techniques.

[0018] like Figure 1AAs shown, core circuit 100A may include various components, including one or more semiconductor chips (or dies), such as a first chip (or die) 102A and a second chip (or die) 102B coupled together via a conductive path 120. In various cases, conductive path 120 may be formed by a wire or the like. Further description related to core circuit 100A and its associated various components will be described in more detail below.

[0019] Core circuit 100A may be implemented as one or more integrated circuits (ICs) using various types of memory (e.g., random access memory (RAM), including static RAM (SRAM), and / or any other type of volatile memory) and other logic circuitry. In some cases, each of die 102A, 102B of core circuit 100A may be implemented as an IC with a memory architecture and associated circuitry. In other cases, each of die 102A, 102B of core circuit 100A may be integrated with various types of computing circuitry and associated components on a single chip. Furthermore, each of die 102A, 102B of core circuit 100A may be implemented in various embedded systems for various electronic, mobile, and Internet of Things (IoT) applications, including low-power sensor nodes.

[0020] like Figure 1A As shown, the first chip 102A may include a sensing circuit (PVSense 108) and a first input / output (IO) cell (PBID-TX 112) with a first output pad 118A. The first output pad 118A may be suitable for providing an input / output (IO) signal. The sensing circuit (PVSense 108) may be configured to receive a hold signal (e.g., RET:RETON / RETOFF) from the first core region 104A and provide a core ramp sense signal (CTR) to the first IO cell (PBID-TX 112) based on the hold signal (e.g., RET:RETON / RETOFF). In some cases, the first IO cell (PBID-TX 112) may receive a core data input signal (A) from the first core region 104A. The core data input signal (A) may have a logic value of 1 (e.g., A=1), which facilitates activation of the first IO cell (PBID-TX 112). In some embodiments, the hold signal (RET) refers to the input signal to the sensing circuit (PVSense 108), the core ramp sense signal (CTR) refers to the output of the sensing circuit (PVSense 108), and the CTR signal may refer to a combination of the SNS signal and the RTO signal.

[0021] Likewise Figure 1AAs shown, second chip 102B may have a second IO cell (PBID_RX 114) with a second output pad 118B that receives the IO signal from first output pad 118A. In some cases, second IO cell (PBID_RX 114) may provide a core data output signal (Y) to second core region 104B.

[0022] In some embodiments, the sensing circuit (PVSense 108) can be configured to detect the first ramp of the core voltage (Core_P1) and then couple the first output pad 118A to ground (Gnd or Vss) until the core power supply (Core_P1) begins to ramp up for the first time, thereby reducing leakage of the core voltage (Core_P1 / Core_P2) and / or the IO voltage (IO_P1 / IO_P2) to the second output pad 118B. In some cases, the first IO cell (PBID-TX 112) can be adapted to transmit (TX) IO signals to the second chip 102B via the conductive path 120, and the second IO cell (PBID_RX 114) can be adapted to receive (RX) IO signals from the first IO cell (PBID-TX 112) via the conductive path 120.

[0023] refer to Figure 1A, the first chip 102A and the second chip 102B can be implemented separately using various functional components suitable for performing various operations. For example, as shown, the first chip 102A can be a device that provides a core voltage (Core_P1) on a first power bus 106A (core power), and the first chip 102A can also provide an IO voltage (IO_P1) on a second power bus 106B (IO power). Thus, the first chip 102A can operate in multiple voltage domains, including, for example, a core voltage (Core_P1) on the first bus 106A (core power) and an IO voltage (IO_P1) on the second bus 106B (IO power). The first chip 102A can include a sensing circuit (PVSense 108) that detects a first ramp of the core voltage (Core_P1) and provides a core ramp sense signal (CTR) to the output logic of the first IO unit (PBID-TX 112). In some cases, first chip 102A may include a first IO cell (PBID-TX 112) that, after receiving a core ramp sense signal (CTR), couples first output pad 118A to ground (Gnd or Vss) to reduce leakage of core voltage (Core_P1) and / or IO voltage (IO_P1). Furthermore, first IO cell (PBID-TX 112) may transmit (TX) IO voltage (IO_P1) to second chip 102B via conductive path 120.

[0024] In some cases, the core voltage (Core_P1) on the first bus 106A can be referred to as the core voltage domain (Vdd), and the IO voltage (IO_P1) on the second bus 106B can be referred to as the IO voltage domain (DVdd). Furthermore, the core voltage domain (Vdd) can be related to a corresponding core reference (Gnd or Vss), and the IO voltage domain (DVdd) can be related to a corresponding IO reference (DVss). Furthermore, in some cases, the core power supply provides the core voltage (Core_P1) via the first bus 106A, and the IO power supply provides the IO voltage (IO_P1) via the second bus 106B.

[0025] Second chip 102B may also include a device having a second output pad 118B as a structure for providing another core voltage (Core_P2) on first bus 116A (core power), and second chip 102B may also provide another IO voltage (IO_P2) on second bus 116B (IO power). Thus, second chip 102B may also operate in multiple voltage domains, including, for example, a core voltage (Core_P2) on first bus 116A (core power) and an IO voltage (IO_P2) on second bus 116B (IO power). Second chip 102B may include output logic in a second IO cell (PBID_RX 114), and thus, second chip 102B may include a second IO cell (PBID_RX 114) that may be adapted to receive (RX) IO signals from first chip 102A via conductive path 120.

[0026] In some embodiments, the first IO unit (PBID-TX 112) and the second IO unit (PBID_RX 114) can be referred to as bidirectional IO units. Furthermore, the first bus 116A can be referred to as a core voltage loop coupled to the core power supply, and the second bus 116B can be referred to as an IO voltage loop coupled to the IO power supply. Furthermore, the sensing circuit (PVSense 108) can be referred to as a power management unit, which can be used to reduce unwanted currents associated with the core and IO voltage loops during power sequencing. Furthermore, in some cases, core voltage (Core_P1) refers to the core power supply in the P1 domain, and IO voltage (IO_P1) refers to the IO power supply in the P1 domain. Core voltage (Core_P2) refers to the core power supply in the P2 domain, and IO voltage (IO_P2) refers to the IO power supply in the P2 domain. Generally, an (X) mark can indicate an indeterminate state.

[0027] like Figure 1A As shown, the first chip 102A may include a core region 104A coupled to a core voltage (Core_P1) via a first bus 106A. In addition, the first chip 102A may include a peripheral region 105A coupled to an IO voltage (IO_P1) via a second bus 106B. The peripheral region 105A may include one or more IO ports operating at the IO voltage (IO_P1). Figure 1A As shown, the second chip 102B may include a core region 104B coupled to a core voltage (Core_P2) via a first bus 116A, and the second chip 102B may include a peripheral region 105B coupled to an IO voltage (IO_P2) via a second bus 116B. The peripheral region 105B may include one or more IO ports operating at the IO voltage (IO_P2).

[0028] In some cases, the output pad structures 118A and 118B may be referred to as a shared bus structure (or PAD structure), which can be shared by multiple devices (e.g., the first chip 102A and the second chip 102B). Furthermore, the first bus 106A and 116A (or core voltage bus or ring) provides corresponding core voltages (Core_P1 and Core_P2) in a core voltage domain (Vdd). The first output pad 118A is coupled to the core voltage bus 106A via a first IO cell (PBID-TX 112), and the second output pad 118B is coupled to the core voltage bus 116A via a second IO cell (PBID-RX 114). The second bus 106B and 116B (or IO voltage bus or ring) provides corresponding IO voltages (IO_P1 and IO_P2) in an IO voltage domain (DVdd) that is different from the core voltage domain (Vdd). First output pad 118A may be coupled to IO voltage bus 106B via first IO cell (PBID-TX 112), and second output pad 118B may also be coupled to IO voltage bus 116B via second IO cell (PBID-RX 114). Furthermore, core power supplies provide core voltage (Core_P2) via first bus 116A, and IO power supplies provide IO voltage (IO_P2) via second bus 116B.

[0029] Advantageously, the core circuit 100A (or device / system) can suppress leakage of the core voltage (Core_P1) and / or the IO voltage (IO_P1) due to independent power sequencing of the core voltage (Core_P1) and the IO voltage (IO_P1) in some low-power applications. Furthermore, in some cases, the core circuit 100A (or device / system) can similarly suppress leakage of another core voltage (Core_P2) and / or another IO voltage (IO_P1) due to independent power sequencing of another core voltage (Core_P1) and another IO voltage (IO_P1) in some similar low-power applications.

[0030] According to various embodiments described herein, a memory-type structure may include a core array circuit having an array of memory cells, wherein each memory cell may be referred to as a bit cell. In addition, each memory cell may be configured to store at least one data bit value (e.g., a data value associated with a logical "0" or "1"). In various cases, the memory cell array may include any number of memory cells (or bit cells) arranged in various suitable configurations, such as a two-dimensional (2D) memory array having any number of columns (N columns), and a plurality of memory cells arranged in any number of rows (N rows) in a 2D grid pattern. In various cases, any type of core circuit may be used, including, for example, standard cells, memory cells, flip-flops, latches, level shifters, and the like.

[0031] Figure 1B A waveform diagram 100B illustrates power sequence timing 102C according to various embodiments described herein.

[0032] exist Figure 1B In Figure 1, waveform diagram 100B illustrates power sequence timing 102C for multiple signals, including IO_P1, Core_P1, RETON, RETOFF, and PAD, as well as IO_P2 and Core_P2. Between times Ti0 and Ti1, the signals (IO_P1, Core_P1, RETON, RETOFF, and PAD) are at zero volts (0V). At time Ti1, the IO_P1 signal begins ramping, and then just before time Ti2, the Core_P1 signal begins ramping. During this ramping of the signals (IO_P1, Core_P1) between times Ti0 and Ti1, the PAD voltage remains at zero voltage (0V). In this scenario, leakage from IO_P2 and Core_P2 is zero. Furthermore, the PAD remains at zero voltage (0V) during times Ti1 to Ti2. At time Ti2 , as the Core_P1 signal starts ramping and the RETOFF signal starts ramping, the PAD rises to a logic 1 state (logic 1), and the PAD voltage may remain in the logic 1 state (logic 1) for a time greater than Ti2 .

[0033] refer to Figure 1A The PVSense unit 108, in Figure 1BFIGURE 1 illustrates the operation of PVSense unit 108 during power sequencing 102C. During time Ti1 to Ti2, PVSense unit 108 detects the first ramping condition of Core_P1 and causes PBID-TX unit 112 to weakly pull down PAD 118A to a logic-zero state (logic 0) until the core power supply (Core_P1) begins its first ramp-up. Thus, leakage through PBID-RX unit 114 can be avoided. Furthermore, when the core power supply ramps up during time Ti2 to Ti4, core ramp detection can be automatically disabled, and normal PVSense unit 108 operation can then proceed for subsequent power supply ramps.

[0034] In some embodiments, various schemes and techniques described herein address the core ramp leakage issue. A unique PVSense circuit 108 detects the initial or first core ramp condition occurring in the IO voltage loop. Until the core power supply (Core_P1) begins its first ramp-up, the PVSense circuit 108 outputs SNS=0, RTO=0 (referenced as a hold state) to the first IO cell 112. As described herein, the first IO cell 112 is designed such that upon receiving inputs SNS / RTO=00 at its inputs, the first IO cell 112 enables weak pull-down logic to couple the output pad 118A to ground (Gnd / Vss=0V), rather than leaving the output pad 118A in a floating or indeterminate (X) state. In some cases, the first IO cell 112 can be backwards compatible in that it can be used with existing circuit designs, which may not be able to generate an SNS / RTO=00 condition.

[0035] Figures 2A to 2D FIG2 shows a diagram of circuitry associated with core ramp detection according to embodiments described herein. In particular, Figure 2A shows a diagram of a sensing circuit 200A, Figure 2B FIGURE 2 shows a diagram of a core ramp detection circuit 200B. Figure 2C A diagram showing an output logic circuit 200C, and Figure 2D A diagram showing another portion of the output logic circuit 200D is shown.

[0036] refer to Figure 2A , the sensing circuit 200A refers to Figure 1ASense circuit 200A (PVSense 108). In some embodiments, sense circuit 200A can be implemented as a system or device having various circuit components (or blocks) arranged and coupled together as a collection or some combination of components that provide core ramp detection. Furthermore, methods of core ramp detection can involve the use of various circuit components described herein to achieve improved performance schemes and techniques.

[0037] like Figure 2A As shown, the sensing circuit 200A (PVSense 108) may include various components, including a core detection circuit 210, a core ramp detection circuit 212, a hold logic circuit 214, and an output logic circuit 228. In some cases, the output logic circuit 228 may refer to Figure 1A A weak pull-up of the first IO unit (PBID_TX 112).

[0038] Sensing circuit 200A (PVSense 108) can include output pad structure 118A that provides an IO signal. Core ramp detection circuit 212 can detect the ramp of the core voltage (Core_P1) and provide a core ramp sense signal (CTR or a portion thereof, e.g., SNS). Output logic circuit 228 can couple output pad structure 118A to ground (Gnd or Vss) after receiving the core ramp sense signal (CTR:SNS) to reduce leakage of the core voltage (Core_P1) and / or the IO voltage (IO_P1). In some cases, core ramp detection circuit 212 can be referred to as a first core ramp detection circuit, which operates to prevent leakage on the core voltage (Core_P1) and / or the IO voltage (IO_P1) during the ramp-up period of the first core power supply.

[0039] Core detect circuit 210 can sense the core voltage (Core_P1) and provide a core detect signal (Core_P1_DET) to core ramp detect circuit 212. In some cases, core ramp detect circuit 212 can receive the core detect signal (Core_P1_DET) from core detect 210, receive a hold signal (RET:RETON / RETOFF), and provide a core ramp sense signal (CTR:SNS) to output logic circuit 228 based on the core detect signal (Core_P1_DET) and / or the hold signal (RET:RETON / RETOFF).

[0040] The hold logic circuit 214 can receive a core detect signal (Core_P1_DET) from the core detect circuit 210, receive a hold signal (RET:RETON / RETOFF), and provide an output hold signal (RTO) to the output logic circuit 228. In some cases, the output hold signal (RTO) can be part of the core ramp sense signal (CTR). Thus, the CTR signal can include the SNS signal and / or the RTO signal. The output logic circuit 228 can receive the core ramp sense signal (CTR:SNS) from the core ramp detect circuit 212 and the output hold signal (CTR:RTO) from the hold logic circuit 214. After receiving the core ramp sense signal (CTR:SNS) and after receiving the output hold signal (CTR:RTO), the output pad structure 118A can be coupled to ground (Gnd or Vss) to reduce leakage of the core voltage (Core_P1) and / or the IO voltage (IO_P1).

[0041] The output logic circuit 228 may couple the output pad structure 118A to ground (Gnd or Vss) after receiving the core ramp sense signal (CTR:SNS) at a logic 0 state (logic 0) and after receiving the output hold signal (CTR:RTO) at a logic 0 state (logic 0), thereby reducing leakage of the core voltage (Core_P1) and / or the IO voltage (IO_P1).

[0042] refer to Figure 2B , the core slope detection circuit 200B refers to Figure 2A The core slope detection circuit 212. Figure 2B As shown, core ramp detection circuit 212 may include various components, including core ramp logic circuit 216 , inverter circuit 220 , and sense (SNS) logic circuit 224 .

[0043] like Figure 2B As shown, the core ramp detection circuit 212 may include a core ramp logic circuit 216, which is Figure 2A The core detection circuit 210 receives the core detection signal (Core_P1_DET), receives the hold signal (RET:RETON / RETOFF), and provides the core ramp signal (CORE_RAMP) to the sense (SNS) logic circuit 224. In addition, the core ramp detection circuit 212 may include an inverter circuit 220, which receives the core detection signal (Core_P1_DET), receives the hold signal (RET:RETON / RETOFF), and provides the core ramp signal (CORE_RAMP) to the sense (SNS) logic circuit 224. Figure 2AThe core detection circuit 210 receives the core detection signal (Core_P1_DET) and provides an inverted core detection signal (Core_P1_DETB). In addition, the core ramp detection circuit 212 may include a sense (SNS) logic circuit 224 that receives the core ramp signal (CORE_RAMP) from the core ramp logic circuit 216, receives the inverted core detection signal (Core_P1_DETB) from the inverter circuit 220, and provides an inverted core detection signal (Core_P1_DETB). Figure 2A The output logic circuit 228 provides a core ramp sense signal (SNS).

[0044] refer to Figure 2C , the output logic circuit 200C refers to Figure 2C The output logic circuit 228. Figure 2C As shown, output logic circuit 228 may include various components, including a NOR logic circuit 230 and a switch 232 .

[0045] like Figure 2C As shown, the output logic circuit 228 can be implemented as a weak pull-down circuit having a logic gate (eg, NOR logic circuit 230) that is connected from ( Figure 2A The core ramp detection circuit 212 receives the core ramp sensing signal (SNS) from ( Figure 2A Retention logic circuit 214 receives the output hold signal (RTO) and provides an activation signal (OUT). In some cases, after receiving the core ramp sense signal (SNS) at a first logic state (e.g., a logic-0 state) and after receiving the output hold signal (RTO) at a second logic state (e.g., a logic-0 state), the activation signal (OUT) can be used to activate switch 232, which couples output pad structure 118A to ground (Gnd or Vss).

[0046] Switch 232 can be coupled between output pad structure 118A and ground (Gnd or Vss) at node (out1). In some cases, output pad structure 118A can have a weak pull-down resistor (Rwk_pd) that is at least greater than 10 kΩ (i.e., Rwk_pd>10 kΩ). Furthermore, output pad structure 118A can be used to provide an output IO signal.

[0047] In some embodiments, the activation signal (OUT) may be referred to as a weak_pull_enable signal, which may provide a logic 1 state (logic 1) or a logic 0 state (logic 0) to the switch 232. For example, a weak_pull_enable signal having a logic 1 state (OUT=1) may be provided to a closed switch 232 with reference to an active weak pull-down in an ON state. Furthermore, in this case, a weak_pull_enable signal having a logic 0 state (OUT=0) may be provided to an open switch 232 with reference to an active weak pull-down in an OFF state.

[0048] refer to Figure 2D The output logic circuit 200D refers to the output pad structure 118A that can be coupled to the Figure 2C The output of the logic circuit 228 is weakly pulled to the output of the logic circuit 248. Figure 2D As shown, output logic circuit 248 may include various components, including transistors ( M1 , M2 ), pre-driver circuit 250 , and core logic and level shifter circuit 252 .

[0049] like Figure 2D As shown, transistors (M1, M2) can be coupled between the IO voltage (IO_P1) and ground (Vss). Output pad structure 118A can be coupled between node (out1) and transistors (M1, M2). In some cases, transistor (M1) can be a PMOS transistor and transistor (M2) can be an NMOS transistor. In addition, pre-driver circuit 250 can be coupled between the IO voltage (IO_P1) and ground (Vss), and pre-driver circuit 250 can be coupled to the gates of transistors (M1, M2). In addition, core logic and level shifter circuit 252 can be coupled between the IO voltage (IO_P1) and ground (Vss), and core logic and level shifter circuit 252 can be coupled to pre-driver circuit 250. In addition, core logic and level shifter circuit 252 can be coupled between the core voltage (Core_P1) and ground (Vss). The core logic and level shifter circuit 252 may receive a data input signal (DATA_IN) and provide a level-shifted data input signal to the pre-driver circuit 250 .

[0050] Figure 3 A diagram of a nuclear detection circuit 300 is shown, in accordance with various embodiments described herein.

[0051] like Figure 3As shown, the core detection circuit 300 may include one or more transistors (T1, T2, ..., T10) and one or more resistors (R1, R2) arranged and coupled together to receive input signals (Core_P1, IO_P1_DET) and provide output signals (Core_P1_DET, Core_P1_DETB).

[0052] exist Figure 3 In the embodiment of the present invention, a resistor (R1) may be coupled between an input node (Core_P1) and the gate of a transistor (T2) at a node (n1), and the transistor (T1) may be coupled between the gate of the transistor (T2) at the node (n1) and ground (Gnd or Vss). The transistor (T1) may be coupled as an NMOS transistor with a grounded gate. In addition, a resistor (R2) may be coupled between a power supply (Vdd) and the transistor (T2) at the node (n2), and the transistor (T2) may be coupled between the resistor (R2) at the node (n2) and ground (Gnd or Vss). The transistor (T3) may be coupled between the power supply (Vdd) and the node (n2), and the input signal (IO_P1) may be coupled to the gate of the transistor (T3). The transistor (T4) may have a source and a drain coupled together to the power supply (Vdd), and the node (n2) may be coupled to the gate of the transistor (T4). Transistors (T5, T6) may be coupled as inverters between a power supply (Vdd) and ground (Gnd or Vss). Furthermore, node (n2) may be coupled to the gates of transistors (T5, T6), and node (n3) may be coupled between transistors (T5, T6). In some cases, node (n3) may have a node voltage (Core_P1_DETB), which may be referred to as an inverted core detection signal for core voltage (Core_P1). Transistor (T7) may have a source and a drain coupled together to ground (Gnd or Vss), and node (n3) may be coupled to the gate of transistor (T7). Transistor (T8) may be coupled between node (n3) and ground (Gnd or Vss), and transistor (T8) may be coupled as an NMOS transistor with a grounded gate. Transistors (T9, T10) may be coupled as inverters between IO voltage (IO_P1) and ground (Gnd or Vss). Additionally, node (n3) may be coupled to the gates of transistors (T9, T10), and node (n4) may be coupled between transistors (T9, T10). In some cases, node (n4) may have a node voltage (Core_P1_DET), which may be referred to as a core detect signal for core voltage (Core_P1).

[0053] In some embodiments, one or more transistors (T1, T2, ..., T10) may include complementary metal oxide semiconductor (CMOS) transistors. For example, some transistors (T1, T2, T5, T7, T8, T9) may include NMOS transistors, while some transistors (T3, T4, T6, T10) may include PMOS transistors. However, various other embodiments may be used.

[0054] Figures 4A to 4B FIG2 shows a diagram of a core ramp detection circuit according to various embodiments described herein. In particular, Figure 4A Shown ( Figure 2A ) schematic diagram 400A of the first portion 212A of the core ramp detection circuit 212, and Figure 4B Shown ( Figure 2A Schematic diagram 400B of the second portion 212B of the core ramp detection circuit 212 (coupled to the first portion 212A at the circled element A).

[0055] like Figure 4A As shown, the core detection circuit 212A may include one or more transistors (T11, T12, ..., T27) and one or more resistors (R3), which are arranged and coupled together to receive input signals (Core_P1_DET, IO_P1_DET, RETON) and provide an output signal at a node (n7), which node (n7) refers to the circled element A.

[0056] exist Figure 4AIn the embodiment, transistor (T11) may be coupled between node (n5) and ground (Gnd or Vss), and transistor (T11) may be coupled as an NMOS transistor with a grounded gate. Transistor (T15) may be coupled between node (n5) and node (n6), and resistor (R3) may be coupled between a power supply (Vdd) and the gate of transistor (T15). Transistor (T12) may be coupled between the gate of transistor (T13) and ground (Gnd or Vss), and transistor (T12) may be coupled as an NMOS transistor with a grounded gate. Furthermore, a RETOFF signal may be coupled to the gate of transistor (T13). Transistors (T13, T14) may be coupled in series between node (n5) and ground (Gnd or Vss). Furthermore, an input signal (Core_P1_DET) may be coupled to the gate of transistor (T14). Transistors (T16, T17) may be coupled as inverters between a power supply (Vdd) and a ground (Gnd or Vss). Furthermore, node (n7) may be coupled to the gates of transistors (T16, T17), and node (n6) may be coupled between transistors (T16, T17). Transistor (T18) may have a source and a drain coupled together to ground (Gnd or Vss), and node (n6) may be coupled to the gate of transistor (T18). Transistor (T19) may be coupled between node (n6) and ground (Gnd or Vss), and transistor (T19) may be coupled as an NMOS transistor with a grounded gate. Transistors (T20, T21) may be coupled as inverters between a power supply (Vdd) and a ground (Gnd or Vss). Furthermore, a node (n6) may be coupled to gates of transistors (T20, T21), and a node (n7) may be coupled between transistors (T20, T21).

[0057] In addition, Figure 4AIn the embodiment of the present invention, transistor (T22) may be coupled between node (n7) and node (n8), and input signal (IO_P1_DET) may be coupled to the gate of transistor (T22). Transistor (T25) may be coupled between the gate of transistor (T23) and ground (Gnd or Vss), and transistor (T25) may be coupled as an NMOS transistor with its gate connected to ground. In addition, in some cases, input signal (RETON) may be coupled to the gate of transistor (T23). Transistors (T23, T24) may be coupled in series between node (n8) and ground (Gnd or Vss), and input signal (Core_P1_DET) may be coupled to the gate of transistor (T24). Transistor (T27) may be coupled between node (n8) and ground (Gnd or Vss), and transistor (T27) may be coupled as an NMOS transistor with its gate connected to ground. The transistor (T26) may be coupled between the power supply (Vdd) and the node (n7), and the input signal (IO_P1_DET) may be coupled to the gate of the transistor (T26). The transistor (T28) may have a source and a drain coupled together to the power supply (Vdd), and the node (n7) may be coupled to the gate of the transistor (T28). In addition, the core ramp detection circuit 212 (e.g. Figure 2A The first portion 212A of the circuit 212 (shown in FIG. 1 ) may be coupled to the core ramp detection circuit 212 (shown in FIG. 1 ) at the circled element A (referring to node (n7)). Figure 2B The second portion 212B is shown).

[0058] In some embodiments, one or more transistors (T11, T12, ..., T28) may include CMOS transistors. For example, some transistors (T11, T12, T13, T14, T15, T16, T18, T19, T20, T22, T23, T24, T25, T27) may include NMOS transistors, while some transistors (T17, T21, T26, T28) may include PMOS transistors. However, various other embodiments may be used.

[0059] exist Figure 4BIn the embodiment of the present invention, transistor (T29) may be coupled between node (n7) and ground (Gnd or Vss), and transistor (T29) may be coupled as an NMOS transistor with its gate grounded. Transistors (T30, T31) may be coupled as inverters between a power supply (Vdd) and ground (Gnd or Vss). Furthermore, node (n7) may be coupled to the gates of transistors (T30, T31), and node (n9) may be coupled between transistors (T30, T31). Transistor (T32) may have a source and a drain coupled together to ground (Gnd or Vss), and node (n9) may be coupled to the gate of transistor (T32). Transistors (T33, T34) may be coupled as inverters between a power supply (Vdd) and ground (Gnd or Vss). Additionally, node (n9) may be coupled to the gates of transistors (T33, T34), and node (n10) may be coupled between transistors (T33, T34). In some cases, node (n10) may have a node voltage (CORE_RAMP), which may be referred to as a core ramp signal for the core voltage (Core_P1). Additionally, in some cases, logic gate 404 (e.g., a NAND gate) may be coupled between an IO voltage (IO_P1) as a power supply input and ground (Gnd or Vss). Logic gate 404 (e.g., a NAND gate) may have multiple inputs, including a first input coupled to an input voltage (Core_P1_DETB) and a second input coupled to node (n10). Logic gate 404 (e.g., a NAND gate) may provide a core ramp sense signal (SNS) as an output. In some cases, reference Figure 4B , the logic gate 404 (eg, NAND gate) may refer to Figure 2B The sensing (SNS) logic circuit 224 in the.

[0060] In some embodiments, one or more transistors (T29, T30, ..., T34) may include CMOS transistors. For example, some transistors (T29, T30, T32, T33) may include NMOS transistors, while some transistors (T31, T34) may include PMOS transistors. However, various other embodiments may be used.

[0061] Figures 5A to 5B A diagram of a retention logic circuit according to various embodiments described herein is shown. In particular, Figure 5A Shown ( Figure 2A ) maintains the schematic diagram 500A of the first portion 214A of the logic circuit 214, and Figure 5B Shown ( Figure 2A Schematic diagram 500B of the second portion 214B of the retention logic circuit 214 (coupled to the first portion 214A at the circled element B).

[0062] like Figure 5A As shown, the core ramp detection circuit 214A may include one or more transistors (T40, T41, ..., T54) and one or more resistors (R4), which are arranged and coupled together to receive input signals (Core_P1_DET, IO_P1_DET, RETON, RETOFF) and provide at least one output signal at a node (n13), which may refer to the circled element B.

[0063] exist Figure 5A In the embodiment, transistor (T40) may be coupled between the gate of transistor (T41) at node (n11) and ground (Gnd or Vss), and transistor (T40) may be coupled as an NMOS transistor with its gate grounded. Transistors (T41, T42) may be coupled in series between node (n12) and ground (Gnd or Vss). Furthermore, an input signal (Core_P1_DET) may be coupled to the gate of transistor (T42), and an input signal (RETOFF) may be coupled to the gate of transistor (T41). Transistor (T43) may be coupled between a power supply (Vdd) and node (n12), and an input signal (IO_P1_DET) may be coupled to the gate of transistor (T43). Transistor (T44) may have a source and a drain coupled together to the power supply (Vdd), and node (n12) may be coupled to the gate of transistor (T44). Transistors (T45, T46) may be coupled as inverters between a power supply (Vdd) and a ground (Gnd or Vss). Furthermore, node (n13) may be coupled to the gates of transistors (T45, T46), and node (n12) may be coupled between transistors (T45, T46). Transistor (T47) may have a source and a drain coupled together to ground (Gnd or Vss), and node (n13) may be coupled to the gate of transistor (T47). Transistor (T48) may be coupled between node (n13) and ground (Gnd or Vss), and transistor (T48) may be coupled as an NMOS transistor with a grounded gate. Transistors (T49, T50) may be coupled as inverters between a power supply (Vdd) and a ground (Gnd or Vss). Furthermore, a node (n12) may be coupled to gates of transistors (T49, T50), and a node (n13) may be coupled between transistors (T49, T50).

[0064] In addition, Figure 5A, transistor (T51) can be coupled between node (n13) and node (n14), and the input signal (RETON) can be coupled to the gate of transistor (T51) via resistor (R4). Transistor (T54) can be coupled between the gate of transistor (T52) and ground (Gnd or Vss), and transistor (T54) can be coupled as an NMOS transistor with its gate grounded. In addition, in some cases, the input signal (RETON) can be coupled to the gate of transistor (T52). Transistors (T52, T53) can be coupled in series between node (n14) and ground (Gnd or Vss), and the input signal (Core_P1_DET) can be coupled to the gate of transistor (T53). Transistor (T55) can be coupled between node (n14) and ground (Gnd or Vss), and transistor (T55) can be coupled as an NMOS transistor with its gate grounded. In addition, core ramp detection circuit 214 (such as Figure 2A The first portion 214A of the circuit 214 may be coupled to the core ramp detection circuit 214 (as shown) at the circled element B (referring to the node (n13)). Figure 2B The second portion 214B is shown).

[0065] In some embodiments, one or more transistors (T40, T41, ..., T55) may include CMOS transistors. For example, some transistors (T40, T41, T42, T45, T47, T48, T49, T51, T52, T53, T54, T55) may include NMOS transistors, while some transistors (T43, T44, T46, T50) may include PMOS transistors. However, various other embodiments may be used.

[0066] exist Figure 5BIn the embodiment, transistor (T56) may be coupled between node (n13) and ground (Gnd or Vss), and transistor (T56) may be coupled as an NMOS transistor with a grounded gate. Transistors (T57, T58) may be coupled as inverters between a power supply (Vdd) and ground (Gnd or Vss). Furthermore, node (n13) may be coupled to the gates of transistors (T57, T58), and node (n15) may be coupled between transistors (T57, T58). Transistor (T59) may have a source and a drain coupled together to ground (Gnd or Vss), and node (n15) may be coupled to the gate of transistor (T59). Transistors (T60, T61) may be coupled as inverters between a power supply (Vdd) and ground (Gnd or Vss). Additionally, node (n15) may be coupled to the gates of transistors (T60, T61), and node (n16) may be coupled between transistors (T60, T61). Transistor (T62) may have a source and a drain coupled together to a power supply (Vdd), and node (n16) may be coupled to the gate of transistor (T62). In some cases, node (n15) provides an inverted output hold signal (RTO_INV), and node (n16) provides an output hold signal (RTO).

[0067] In some embodiments, one or more transistors (T56, T57, ..., T62) may include CMOS transistors. For example, some transistors (T56, T57, T59, T60) may include NMOS transistors, while some transistors (T58, T61, T62) may include PMOS transistors. However, various other embodiments may be used.

[0068] In some embodiments, the PVSense unit 108 can be used in conjunction with Figure 3 Nuclear detection circuit 210, Figures 2A to 2B The core slope detection circuits 212A, 212B and Figures 5A to 5B Therefore, the reference Figures 3 to 5B , the PVSense unit 108 may incorporate operational characteristics and behaviors associated with the combination of circuits 210 , 212A, 212B, 214A, 214B, which may operate as follows.

[0069] During the first core power supply ramp, Core_P1 = 0, therefore, Core_P1_DET = 0 and Core_P1_DETB = 1. Therefore, SNS can be determined by the output of the first core ramp detection blocks 212A and 212B. Since Core_P1_DET is "0," NMOS transistors T14 and T24 are in the off state. Consequently, inputs RETON and RETOFF are disabled, and there is no control over output CORE_RAMP. In this case, when IO_P1 begins to ramp, PMOS transistor T28 couples charge to the right side of the latch provided in the first core ramp detection blocks 212A and 212B. Simultaneously, NMOS transistor T11 (a grounded-gate NMOS device operating as a leakage device) begins discharging the left node of the latch. This action turns the right branch of the latch to "1" and grounds the left side of the latch to "0." Furthermore, CORE_RAMP is set to "1," and SNS is set to "0."

[0070] Holding blocks 214A and 214B can operate in a similar manner, although some connections are different. For example, since Core_P1_DET is "0," NMOS transistors T42 and T53 are disabled. When IO_P1 begins to ramp up, the excess charge can be coupled to the left side of the latch in holding blocks 214A and 214B through PMOS transistor T44, and the right side can be discharged through leakage device T55. As a result, the left side of the latch can be turned to "1," and the right side of the latch can be turned to "0." Furthermore, RTO eventually becomes "0."

[0071] In this case, SNS = 0 and RTO = 0 can be transmitted to the first IO unit 112 to enable the weak pull-down logic in the first IO unit 112, which causes PAD = 0. In normal operation, Core_P1 = 1, so Core_P1_DET becomes "1," and then SNS eventually becomes "1." In this case, or when Core_P1 is stable and "1," SNS may not depend on the first core ramp logic, and the first core ramp detection blocks 212A and 212B may be disabled. In the hold blocks 214A and 214B, when Core_P1_DET is "1," NMOS transistors T52 and T41 may be enabled. Thus, the branch accepts the inputs RETON and RETOFF and operates according to the values of RETON and RETOFF.

[0072] In some embodiments, the various schemes and techniques described herein provide for substantial power savings in the reference IO voltage loop during core power-down mode. The various schemes and techniques described herein can be used in many IoT-specific applications (e.g., wearables, always-on devices, etc.) that typically require power savings. The various schemes and techniques described herein utilize pad operating conditions based on the application allowing the core reference to maintain or tri-state logic states. Additionally, the various schemes and techniques described herein address the first core ramp hold issue by utilizing additional detection circuitry, wherein the additional detection circuitry is disabled for other core power-down modes and becomes active with reference to the first core ramp instance. Consequently, these schemes and techniques may not require the use of additional current, which can maintain pad operating conditions for their use.

[0073] Various embodiments of a device are described herein. The device may include an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include a core ramp detection circuit that detects a first ramp of a core voltage from the core power supply and provides a core ramp sense signal. The device may include an output logic circuit that, upon receiving the core ramp sense signal, couples the output pad to ground to reduce leakage from the IO power supply.

[0074] Various embodiments of a system are described herein. The system may include a first chip having a sensing circuit and a first input / output (IO) cell having a first output pad that provides at least one of an input / output voltage from an IO power supply and a core voltage from a core power supply. The system may include a second chip having a second IO cell having a second output pad that receives at least one of the IO voltage and the core voltage from the first output pad. The sensing circuit may detect a first ramp of the core voltage and couple the first output pad to ground until the core power supply begins to ramp up for the first time, thereby reducing leakage of at least one of the IO voltage and the core voltage to the second output pad.

[0075] Various embodiments of a method are described herein. The method may include providing an input-output (IO) voltage via an output pad. The method may include detecting a first ramp of a core voltage. The method may include generating a ramp sense signal during the detection of the first ramp of the core voltage. The method may include coupling the output pad to ground after receiving the ramp sense signal to reduce leakage of at least one of the IO voltage and the core voltage.

[0076] It is intended that the subject matter of the claims is not limited to the embodiments and descriptions provided herein, but rather includes modifications of those embodiments, including portions of the claimed embodiments and combinations of elements of different embodiments. It should be understood that in the development of any such embodiment, as in any engineering or design project, many implementation-specific decisions should be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from one embodiment to another. Furthermore, it should be understood that such development efforts may be complex and time-consuming, but are nevertheless routine for design, fabrication, and manufacture by those of ordinary skill in the art having the benefit of this disclosure.

[0077] Reference has been made in detail to various embodiments, examples of which are illustrated in the accompanying drawings and figures. In the detailed description that follows, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein can be practiced without these specific details. In some other cases, well-known methods, processes, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring the details of the embodiments.

[0078] It should also be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish elements from each other. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The first element and the second element are both elements, but they are not considered to be the same element.

[0079] The terms used in the description of the present disclosure provided herein are for describing specific embodiments and are not intended to limit the disclosure provided herein. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" used in the description of the disclosure provided herein and the appended claims are also intended to include plural forms. The term "and / or" as used herein refers to and includes any and all possible combinations of one or more associated listed items. When used in this specification, the terms "comprises", "comprising", "containing" and / or "having" specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0080] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [the stated condition or event] is detected" may be interpreted to mean "upon determination" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]," depending on the context. The terms "up" and "down"; "higher" and "lower"; "upward" and "downward"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in conjunction with some embodiments of the various techniques described herein.

[0081] While the foregoing is directed to various embodiments of the techniques described herein, other and further embodiments may be devised from the disclosure herein, which may be determined by the claims that follow.

[0082] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A nuclear slope detection device comprising: Output pad, providing IO voltage from input and output IO power supply; a nuclear detection circuit, sensing a nuclear voltage from a nuclear power supply and providing a nuclear detection signal; a core ramp detection circuit that detects a first ramp of the core voltage from the core power supply and provides a core ramp sense signal based on the core detection signal; as well as The output logic circuit directly couples the output pad to the ground after receiving the core ramp sensing signal, so as to reduce leakage of the IO power supply.

2. The nuclear slope detection device according to claim 1, wherein: The core detection circuit provides the core detection signal to the core ramp detection circuit, and The core ramp detection circuit receives the core detection signal from the core detection circuit, receives a hold signal, and provides the core ramp sensing signal to the output logic circuit based on the core detection signal and the hold signal.

3. The nuclear slope detection device according to claim 2, wherein: The core ramp detection circuit includes: a core ramp logic circuit that receives the core detection signal from the core detection circuit, receives the hold signal, and provides a core ramp signal; an inverter, receiving the nuclear detection signal from the nuclear detection circuit and providing an inverted nuclear detection signal; and A sense logic circuit receives the core ramp signal from the core ramp logic circuit, receives the inverted core detection signal from the inverter, and provides the core ramp sense signal to the output logic circuit.

4. The nuclear slope detection device according to claim 2, further comprising: a hold logic circuit that receives the core detection signal from the core detection circuit, receives the hold signal, and provides an output hold signal to the output logic circuit, The output logic circuit receives the core ramp sensing signal from the core ramp detection circuit, receives the output hold signal from the hold logic circuit, and couples the output pad to ground after receiving the core ramp sensing signal and after receiving the output hold signal, thereby reducing leakage of at least one of the core power supply and the IO power supply.

5. The nuclear slope detection device according to claim 4, wherein: During ramping of the core power supply, the output logic circuit couples the output pad to ground after receiving the core ramp sense signal at a first logic state and after receiving the output hold signal at a second logic state, thereby reducing leakage of at least one of the core power supply and the IO power supply.

6. The nuclear slope detection device according to claim 5, wherein: The output logic circuit includes a weak pull-down circuit having a logic gate that receives the core ramp sense signal from the core ramp detection circuit, receives the output hold signal from the hold logic circuit, and provides an activation signal to activate a switch coupling the output pad to ground after receiving the core ramp sense signal in the first logic state and after receiving the output hold signal in the second logic state.

7. The nuclear slope detection device according to claim 6, wherein: The first logic state refers to a 0 logic state, and wherein the second logic state refers to the 0 logic state.

8. The nuclear slope detection device according to claim 1, wherein: The output pads include a shared structure shared by a plurality of devices.

9. The nuclear slope detection device according to claim 1, further comprising: A core power supply provides the core voltage in a core voltage domain.

10. The nuclear slope detection device according to claim 9, further comprising: Input / output IO power supply, providing IO voltage in an IO voltage domain different from the core voltage domain, Wherein, the output logic circuit is coupled to the IO power supply.

11. The nuclear slope detection device according to claim 10, wherein: The core ramp detection device suppresses leakage of the core voltage and the IO voltage due to independent power sequencing of the core voltage and the IO voltage in low power applications.

12. A nuclear slope detection system comprising: A first chip has a sensing circuit and a first input / output IO unit with a first output pad, wherein the first output pad provides at least one of an input / output IO voltage from an IO power supply and a core voltage from a core power supply; as well as A second chip has a second IO unit with a second output pad, wherein the second output pad receives at least one of the IO voltage and the core voltage from the first output pad. The sensing circuit includes a core slope detection circuit, which detects the first slope of the core voltage and provides a core slope sensing signal, and The first input / output IO unit has an output logic circuit, which directly couples the first output pad to the ground after receiving the core ramp sense signal until the core voltage starts to ramp up for the first time, so as to reduce leakage of at least one of the IO voltage and the core voltage to the second output pad.

13. The nuclear slope detection system according to claim 12, wherein: The sensing circuit comprises: a core detection circuit, sensing the core voltage and providing a core detection signal to the core ramp detection circuit, The core ramp detection circuit receives the core detection signal and the hold signal from the core ramp detection circuit, and provides the core ramp sensing signal to the output logic circuit based on the core detection signal and the hold signal.

14. The nuclear slope detection system according to claim 13, wherein: The sensing circuit comprises: a hold logic circuit that receives the core detection signal from the core detection circuit, receives the hold signal, and provides an output hold signal to the output logic circuit, The output logic circuit receives the core ramp sensing signal from the core ramp detection circuit, receives the output hold signal from the hold logic circuit, and couples the output pad to ground after receiving the core ramp sensing signal and after receiving the output hold signal, thereby reducing leakage of at least one of the IO voltage and the core voltage.

15. The nuclear slope detection system according to claim 14, wherein: The output logic circuit includes: a weak pull-down circuit having a logic gate that receives the core ramp sense signal from the core ramp detection circuit, receives the output hold signal from the hold logic circuit, and provides an activation signal to activate a switch coupling the first output pad to ground after receiving the core ramp sense signal at a first logic state and after receiving the output hold signal at a second logic state.

16. The nuclear slope detection system according to claim 15, wherein: The first logic state refers to a 0 logic state, and wherein the second logic state refers to the 0 logic state.

17. The nuclear slope detection system according to claim 12, wherein: Each of the first chip and the second chip includes: a core power supply, providing the core voltage in a core voltage domain; and an IO power supply, providing an IO voltage in an IO voltage domain different from the core voltage domain, The core ramp detection system suppresses leakage of the core voltage and the IO voltage due to independent power sequencing of the core voltage and the IO voltage in low power applications.

18. A method for detecting a nuclear slope, comprising: Provide input and output IO voltages through output pads; Receive hold signal; detecting a first slope of the core voltage; generating a ramp sense signal during detection of the first ramp of the core voltage; as well as After receiving the hold signal and after receiving the ramp sense signal, the output pad is coupled directly to ground, thereby reducing leakage of at least one of the IO voltage and the core voltage.

19. The method according to claim 18, further comprising: After receiving the ramp sense signal at a first logic state and after receiving the output hold signal at a second logic state, coupling the output pad to ground reduces leakage of at least one of the IO voltage and the core voltage.

20. The method according to claim 19, wherein The first logic state refers to a 0 logic state, and wherein the second logic state refers to the 0 logic state.

21. The method of claim 19, further comprising: After receiving the ramp sense signal at a 0 logic state and after receiving the output hold signal at the 0 logic state, an activation signal is generated to activate a switch for coupling the output pad to ground.

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